Display device

Abstract

A display device includes: a substrate; a circuit layer on the substrate; and an element layer on the circuit layer, in which the substrate includes a main region and a hole region, the main region including a display region in which the emission regions are arranged and a non-display region around the display region, the main region being around the hole region, the element layer including light emitting elements in the emission regions, respectively, and the circuit layer including: an emission pixel driver, a plurality of light emitting elements arranged side by side along a first direction and a second direction crossing the first direction and electrically connected to the light emitting elements, respectively; a data line extending in a second direction and configured to supply a data signal to the emission pixel driver; a bridging line extending in the first direction; and an additional line extending in the second direction and adjacent to the data line, the bridging line including a first dummy bridging line facing the hole area.

Description

[0001] Cross - reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0188046, filed with the Korean Intellectual Property Office on December 21, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and / or smart TVs.

[0005] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and / or a light - emitting display device. Here, the light - emitting display device may include an organic light - emitting display device including organic light - emitting elements, an inorganic light - emitting display device including inorganic light - emitting elements such as inorganic semiconductors, and a micro - light - emitting display device including micro - light - emitting elements.

[0006] The organic light - emitting display device uses light - emitting elements each including a light - emitting layer made of an organic light - emitting material to display an image. Therefore, the organic light - emitting display device uses self - light - emitting elements to implement image display, and accordingly, may have relatively excellent performance in terms of power consumption, response speed, luminous efficiency, brightness, and / or wide viewing angle compared to other display devices.

[0007] One surface of the display device may be a display surface including a display area for displaying an image. Emission areas emitting light of each brightness and color may be arranged in the display area. Summary of the Invention

[0008] In one or more embodiments, a display device includes: a substrate; a circuit layer on the substrate; and an element layer on the circuit layer, wherein the substrate includes a main region and a hole region, the main region includes a display region where an emission region is arranged and a non-display region around the display region, the main region surrounds the hole region, the element layer includes light-emitting elements respectively in the emission region, and the circuit layer includes: emission pixel drivers arranged side by side along a first direction and a second direction intersecting the first direction and respectively electrically connected to the light-emitting elements; data lines extending in the second direction and configured to supply data signals to the emission pixel drivers; bridge lines extending in the first direction; and additional lines extending in the second direction and adjacent to the data lines, the bridge lines include one or more first dummy bridge lines facing the hole region on one side in the second direction and one or more second dummy bridge lines facing the hole region on the other side in the second direction, and the additional lines include one or more first dummy additional lines facing the hole region on one side in the first direction and electrically connected to the one or more first dummy bridge lines and the one or more second dummy bridge lines.

[0009] In one or more embodiments, the additional lines further include one or more second dummy additional lines facing the hole region on the other side in the first direction and electrically connected to the one or more first dummy bridge lines and the one or more second dummy bridge lines.

[0010] In one or more embodiments, the light-transmitting holes passing through the circuit layer and the element layer are in at least a part of the middle of the hole region, wherein the substrate further includes a sub-region protruding from one side of the main region, wherein the main region further includes a hole bypass region around the hole region, wherein the hole bypass region includes a first hole bypass separation region and a second hole bypass separation region adjacent to each other based on a first hole center point extension line that intersects the center point of the hole region and extends in a first direction, and a third hole bypass separation region and a fourth hole bypass separation region respectively adjacent to the first hole bypass separation region and the second hole bypass separation region based on a second hole center point extension line that intersects the center point of the hole region and extends in a second direction, wherein the edge of the display region includes a first side extending in the first direction and facing the sub-region in the second direction, and a second side extending in the first direction, opposite to the first side in the second direction and spaced farther from the sub-region than the first side is from the sub-region, wherein the data line includes a hole-crossing data line that crosses the hole region, wherein each of the hole-crossing data lines includes a first dividing line portion between the first side and the hole region and a second dividing line portion between the hole region and the second side, wherein the hole-crossing data line includes a first hole-crossing data line facing the second hole center point extension line on this side in the first direction, wherein the bridge line further includes a first hole bypass bridge line in the first hole bypass separation region and electrically connected to the first dividing line portion of the first hole-crossing data line, and a second hole bypass bridge line in the second hole bypass separation region and electrically connected to the second dividing line portion of the first hole-crossing data line, wherein the additional line further includes a first hole bypass additional line in the first hole bypass separation region and the second hole bypass separation region and electrically connected between the first hole bypass bridge line and the second hole bypass bridge line, and wherein one or more first dummy additional lines are between the first hole bypass additional line and the hole region in the first direction.

[0011] In one or more embodiments, the hole-crossing data line further includes a second hole-crossing data line facing the second hole center point extension line on the other side in the first direction, wherein the bridge line further includes a third hole bypass bridge line in the third hole bypass separation region and electrically connected to the first dividing line portion of the second hole-crossing data line, and a fourth hole bypass bridge line in the fourth hole bypass separation region and electrically connected to the second dividing line portion of the second hole-crossing data line, wherein the additional line further includes a second hole bypass additional line in the third hole bypass separation region and the fourth hole bypass separation region and electrically connected between the third hole bypass bridge line and the fourth hole bypass bridge line, and wherein one or more second dummy additional lines are between the hole region and the second hole bypass additional line in the first direction.

[0012] In one or more embodiments, the additional lines further include: one or more third dummy additional lines between the first side and the hole region in the second direction and between one or more first dummy additional lines and one or more second dummy additional lines in the first direction; and one or more fourth dummy additional lines between the hole region and the second side in the second direction and between one or more first dummy additional lines and one or more second dummy additional lines in the first direction, wherein the one or more third dummy additional lines are electrically connected to the one or more first dummy additional lines and the one or more second dummy additional lines through one or more first dummy bridging lines, and wherein the one or more fourth dummy additional lines are electrically connected to the one or more first dummy additional lines and the one or more second dummy additional lines through one or more second dummy bridging lines.

[0013] In one or more embodiments, the bridging lines further include: two or more third dummy bridging lines between the first via-side bridging line and the third via-side bridging line in the first direction and between the second via-side bridging line and the fourth via-side bridging line in the first direction; and one or more fourth dummy bridging lines between one or more first dummy bridging lines and one or more second dummy bridging lines in the second direction and intersecting the hole region, wherein the two or more third dummy bridging lines are electrically connected to the one or more first dummy bridging lines and the one or more second dummy bridging lines respectively through one or more third dummy additional lines and one or more fourth dummy additional lines, and wherein the one or more fourth dummy bridging lines are electrically connected to the one or more first dummy additional lines or the one or more second dummy additional lines.

[0014] In one or more embodiments, a part of the second via bypass separation region overlaps with the display region and other parts of the second via bypass separation region overlap with the non-display region, and wherein the circuit layer further includes a first bridging auxiliary line extending in the first direction in the non-display region and electrically connecting between the first via bypass additional line and the second divided line portion of the first via crossing data line.

[0015] In one or more embodiments, a part of the fourth via bypass separation region overlaps with the display region and other parts of the fourth via bypass separation region overlap with the non-display region, and wherein the circuit layer further includes a second bridging auxiliary line extending in the first direction in the non-display region and electrically connecting between the second via bypass additional line and the second divided line portion of the second via crossing data line.

[0016] In one or more embodiments, the circuit layer further includes a first power supply line and a second power supply line. The first power supply line and the second power supply line are in a non-display area and are respectively configured to supply a first power supply and a second power supply to drive the light-emitting elements. Wherein, a part of the second power supply line extends parallel to the second side, and one or more first dummy additional lines and one or more second dummy additional lines are electrically connected to the second power supply line.

[0017] In one or more embodiments, the circuit layer further includes a first power supply line and a second power supply line. The first power supply line and the second power supply line are in a non-display area and are respectively configured to supply a first power supply and a second power supply to drive the light-emitting elements. Wherein, a part of the first power supply line extends parallel to the second side, and one or more first dummy additional lines and one or more second dummy additional lines are electrically connected to the first power supply line.

[0018] In one or more embodiments, the circuit layer further includes: a first power supply line and a second power supply line, the first power supply line and the second power supply line are in a non-display area and are respectively configured to supply a first power supply and a second power supply to drive the light-emitting elements; and a constant voltage supply line configured to supply a constant voltage having a voltage level different from the voltage levels of the first power supply and the second power supply in the non-display area. Wherein, a part of the constant voltage supply line extends parallel to the second side, and one or more first dummy additional lines and one or more second dummy additional lines are electrically connected to the constant voltage supply line.

[0019] In one or more embodiments, one of the light-emitting elements is electrically connected between one of the emission pixel drivers and the second power supply. Wherein, the emission pixel driver includes: a first transistor configured to generate a driving current for driving the light-emitting element; a second transistor electrically connected between one of the data lines and a first electrode of the first transistor; a third transistor electrically connected between a gate electrode of the first transistor and a second electrode of the first transistor; a fourth transistor electrically connected between a first initialization voltage line configured to supply a first initialization voltage and the gate electrode of the first transistor; a fifth transistor electrically connected between a first power supply line configured to supply a first power supply and the first electrode of the first transistor; a sixth transistor electrically connected between the second electrode of the first transistor and the light-emitting element; a seventh transistor electrically connected between a second initialization voltage line configured to supply a second initialization voltage and the light-emitting element; and an eighth transistor electrically connected between a bias voltage line configured to supply a bias voltage and the first electrode of the first transistor, and wherein the constant voltage supply line is configured to supply one of the first initialization voltage, the second initialization voltage, and the bias voltage.

[0020] In one or more embodiments, the data line further includes a first data line and a second data line that is spaced farther from the sub-region than the first data line is from the sub-region, wherein the bridge line further includes a data bypass bridge line electrically connected to the second data line, and wherein the additional line further includes a data bypass additional line adjacent to the first data line and electrically connected to the data bypass bridge line.

[0021] In one or more embodiments, the circuit layer further includes a data supply line electrically connected between the display driving circuit in the sub-region and the data line. The first data supply line among the data supply lines configured to supply the data signal of the first data line extends to the first data line and is directly electrically connected to the first data line, and the second data supply line among the data supply lines configured to supply the data signal of the second data line extends to the data bypass additional line and is electrically connected to the second data line through the data bypass additional line and the data bypass bridge line.

[0022] In one or more embodiments, the edge of the display region further includes a third side and a fourth side that extend in a second direction and face each other in a first direction, wherein the data bypass bridge line is spaced apart from the third side and the fourth side, wherein the bridge line further includes a power supply auxiliary bridge line between one end of the data bypass bridge line and the third side and between the other end of the data bypass bridge line and the fourth side, and wherein the additional line further includes a power supply auxiliary additional line between one end of the data bypass additional line and the second side.

[0023] In one or more embodiments, a display device includes: a substrate; a circuit layer on the substrate; and an element layer on the circuit layer. The substrate includes a main region, a hole region, and a sub-region protruding from one side of the main region. The main region includes a display region where an emission region is arranged and a non-display region surrounding the display region. The main region surrounds the hole region. The element layer includes light-emitting elements respectively located in the emission regions. The circuit layer includes: emission pixel drivers arranged side by side along a first direction and a second direction intersecting the first direction and respectively electrically connected to the light-emitting elements; data lines extending in the second direction and configured to supply data signals to the emission pixel drivers; bridge lines extending in the first direction; and additional lines extending in the second direction and adjacent to the data lines. The main region further includes a hole bypass region surrounding the hole region. The data lines include hole-crossing data lines crossing the hole region. Based on a first hole center point extension line crossing the center point of the hole region and extending in the first direction, each of the hole-crossing data lines includes a first divided line portion on one side in the second direction and a second divided line portion on the other side in the second direction. Based on a second hole center point extension line crossing the center point of the hole region and extending in the second direction, the hole-crossing data lines include a first hole-crossing data line on one side in the first direction and a second hole-crossing data line on the other side in the first direction. The bridge lines include: a first hole bypass bridge line electrically connected to the first divided line portion of the first hole-crossing data line; a second hole bypass bridge line electrically connected to the second divided line portion of the first hole-crossing data line; a third hole bypass bridge line electrically connected to the first divided line portion of the second hole-crossing data line; a fourth hole bypass bridge line electrically connected to the second divided line portion of the second hole-crossing data line; one or more first dummy bridge lines facing the hole region on this side in the second direction; and one or more second dummy bridge lines facing the hole region on the other side in the second direction. The additional lines include: a first hole bypass additional line electrically connected between the first hole bypass bridge line and the second hole bypass bridge line; a second hole bypass additional line electrically connected between the third hole bypass bridge line and the fourth hole bypass bridge line; one or more first dummy additional lines facing the hole region on this side in the first direction and electrically connected to the one or more first dummy bridge lines and the one or more second dummy bridge lines; and one or more second dummy additional lines facing the hole region on the other side in the first direction and electrically connected to the one or more first dummy bridge lines and the one or more second dummy bridge lines, and the one or more first dummy bridge lines, the one or more second dummy bridge lines, the one or more first dummy additional lines, and the one or more second dummy additional lines are electrically connected to each other.

[0024] In one or more embodiments, the bridge connection line further includes: two or more third dummy bridge connection lines between the first hole bypass connection line and the third hole bypass connection line and between the second hole bypass connection line and the fourth hole bypass connection line in a first direction; and one or more fourth dummy bridge connection lines between one or more first dummy bridge connection lines and one or more second dummy bridge connection lines in a second direction and intersecting the hole region, wherein the additional line further includes: one or more third dummy additional lines adjacent to one side of the hole region in the second direction and between one or more first dummy additional lines and one or more second dummy additional lines in the first direction; and one or more fourth dummy additional lines adjacent to the other side of the hole region in the second direction and between one or more first dummy additional lines and one or more second dummy additional lines in the first direction, and the two or more third dummy bridge connection lines, the one or more fourth dummy bridge connection lines, the one or more third dummy additional lines, and the one or more fourth dummy additional lines are electrically connected to the one or more first dummy bridge connection lines, the one or more second dummy bridge connection lines, the one or more first dummy additional lines, and the one or more second dummy additional lines.

[0025] In one or more embodiments, the circuit layer further includes a first power supply line and a second power supply line, the first power supply line and the second power supply line being in a non-display region and being configured to supply a first power supply and a second power supply respectively to drive the light-emitting elements, and wherein the one or more first dummy additional lines and the one or more second dummy additional lines are electrically connected to one of the first power supply line and the second power supply line.

[0026] In one or more embodiments, the circuit layer further includes: a first initialization voltage line configured to supply a first initialization voltage to the emission pixel driver; a second initialization voltage line configured to supply a second initialization voltage to the emission pixel driver; a bias voltage line for transmitting a bias voltage to the emission pixel driver; and a constant voltage supply line in the non-display region, wherein the constant voltage supply line is configured to supply one of the first initialization voltage, the second initialization voltage, and the bias voltage, and wherein the one or more first dummy additional lines and the one or more second dummy additional lines are electrically connected to the constant voltage supply line.

[0027] In one or more embodiments, a part of the hole bypass region overlaps with the display region and other parts of the hole bypass region overlap with the non-display region, and wherein the circuit layer further includes: a first bridge assist line extending in the first direction in the non-display region and electrically connecting between the first hole bypass additional line and a second divided line portion of the first hole crossing data line; and a second bridge assist line extending in the first direction in the non-display region and electrically connecting between the second hole bypass additional line and a second divided line portion of the second hole crossing data line.

[0028] According to one or more embodiments, one or more first dummy bridge lines, one or more second dummy bridge lines, one or more first dummy additional lines, and one or more second dummy additional lines may be electrically connected to each other.

[0029] In this way, one or more first dummy bridge lines and one or more second dummy bridge lines adjacent to the hole region in a first direction, and one or more first dummy additional lines and one or more second dummy additional lines adjacent to the hole region in a second direction may be maintained at the same potential, and thus, the deviation between the luminance characteristics of the emission regions adjacent to the hole region may be reduced.

[0030] Accordingly, the degradation of the image quality caused by one or more first dummy bridge lines, one or more second dummy bridge lines, one or more first dummy additional lines, and one or more second dummy additional lines may be alleviated.

[0031] In addition, according to one or more embodiments, the additional lines may further include one or more third dummy additional lines and one or more fourth dummy additional lines disposed between one or more first dummy additional lines and one or more second dummy additional lines in a first direction. One or more third dummy additional lines may be disposed adjacent to one side of the hole region in a second direction. One or more fourth dummy additional lines may be disposed adjacent to the other side of the hole region in a second direction.

[0032] In addition, the bridge lines may further include two or more third dummy bridge lines disposed between the first hole-side bridge line and the third hole-side bridge line and between the second hole-side bridge line and the fourth hole-side bridge line, and one or more fourth dummy bridge lines disposed between one or more first dummy bridge lines and one or more second dummy bridge lines in a second direction and crossing the hole region.

[0033] According to one or more embodiments, two or more third dummy bridge lines, one or more fourth dummy bridge lines, one or more third dummy additional lines, and one or more fourth dummy additional lines may be electrically connected to one or more first dummy bridge lines, one or more second dummy bridge lines, one or more first dummy additional lines, and one or more second dummy additional lines.

[0034] In other words, some of the bridge lines disposed around the hole region and some of the additional lines disposed around the hole region may be bypass lines for the hole-crossing data lines bypassing the hole region, and the other bridge lines disposed around the hole region and the other additional lines disposed around the hole region may be dummy lines maintained at the same potential.

[0035] In this way, the dummy lines provided around the hole region are maintained at the same potential, so that the deviation of the electrical influence of the dummy lines can be eliminated, and thus, the degradation of the image quality around the hole region can be further alleviated.

[0036] Accordingly, even if the display device according to one or more embodiments includes a through hole provided in the hole region, the image quality of certain regions adjacent to the hole region in the display region can become similar to the image quality of other regions, and thus, the display quality of the display device can be improved.

[0037] The effects, aspects, and features of the present disclosure are not limited to the foregoing effects, aspects, and features, and various other effects, aspects, and features are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other aspects and features of the embodiments of the present disclosure will become more apparent by describing the embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0039] Figure 1 is a perspective view illustrating a display device according to one or more embodiments;

[0040] Figure 2 is illustrated Figure 1 a plan view of the display device;

[0041] Figure 3 is a cross-sectional view taken along line A-A' of Figure 2 ;

[0042] Figure 4 is illustrated Figure 2 a layout view of part B;

[0043] Figure 5 is illustrated Figure 4 an equivalent circuit diagram of the emission pixel driver;

[0044] Figure 6 is illustrated Figure 5 a cross-sectional view of the first transistor, the second transistor, the fourth transistor, the sixth transistor, and the light-emitting element;

[0045] Figure 7 is illustrated Figure 3 a plan view of the substrate;

[0046] Figure 8 is illustrated Figure 7 a layout view of part C;

[0047] Figure 9 is a cross-sectional view taken along line E-E' of Figure 8 ;

[0048] Figure 10 is a layout diagram of part D according to one or more embodiments Figure 7 ;

[0049] Figure 11 is a layout diagram of part D according to one or more embodiments Figure 7 ;

[0050] Figure 12 is a cross-sectional view taken along line F-F’ of Figure 11 ;

[0051] Figure 13 is a layout diagram of part D according to one or more embodiments Figure 7 ;

[0052] Figure 14 is a layout diagram of part D according to one or more embodiments Figure 7 ;

[0053] Figure 15 is a layout diagram of part D according to one or more embodiments Figure 7 ; and

[0054] Figure 16 is a layout diagram of part D according to one or more embodiments Figure 7 ; DETAILED DESCRIPTION

[0055] Aspects and features of embodiments of the present disclosure and methods for implementing the same can be more easily understood by reference to the following detailed description of the embodiments and the accompanying drawings. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art, and the present disclosure will be defined by the claims and their equivalents.

[0056] It will be understood that when an element or layer is referred to as being “on” another element or layer, the element or layer can be directly on the other element or layer, or there may also be intervening elements or layers therebetween. The same reference numerals throughout the present disclosure refer to the same elements. The shapes, dimensions, ratios, angles, quantities, etc. disclosed in the drawings for describing the embodiments are merely examples, and the present disclosure is not limited to the details illustrated.

[0057] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure.

[0058] The features of various embodiments of the present disclosure may be coupled or combined with each other partially or entirely, and may interoperate and drive in various technical ways. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0059] In view of the present disclosure as a whole, those of ordinary skill in the art will understand that each suitable feature of the various embodiments of the present disclosure may be combined or combined with each other partially or entirely and may be linked and operated technically in various suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or implemented in combination with each other in any suitable way.

[0060] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0061] Figure 1 is a perspective view illustrating a display device according to one or more embodiments. Figure 2 is an illustration Figure 1 of a plan view of the display device. Figure 3 is a cross-sectional view taken along line A-A’ of Figure 2 the display device.

[0062] Referring to Figure 1 and Figure 2 , the display device 100 is a device for displaying moving images and / or still images, and may be used as a display screen for various products such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and / or ultra-mobile personal computers (UMPCs).

[0063] The display device 100 may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode (OLED), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro light-emitting diode or a nano light-emitting diode (micro LED or nano LED). Hereinafter, the display device 100 being an organic light-emitting display device will be mainly described. However, the present disclosure is not limited thereto, and may be applied to a display device including an organic insulating material, an organic light-emitting material, and / or a metal material.

[0064] The display device 100 may be formed to be flat, but is not limited thereto. For example, the display device 100 may include curved surface portions formed at its left and right ends and having a constant curvature or a variable curvature. Additionally, the display device 100 may be formed flexibly to be bent, folded, and / or curled.

[0065] As Figures 1 to 3 illustrated in, the display device 100 includes a substrate 110.

[0066] The substrate 110 may include a main region MA corresponding to the display surface of the display device 100 and a sub-region SBA protruding from one side of the main region MA.

[0067] As Figure 2 illustrated in, the main region MA may include a display region DA provided at most of its center and a non-display region NDA provided around the display region DA.

[0068] In a plan view, the display region DA may be formed in a rectangular shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded with a suitable curvature (e.g., a predetermined curvature) or may be right angles. The shape of the display region DA in the plan view is not limited to a rectangular shape and may be other polygonal shapes, circular shapes, and / or elliptical shapes.

[0069] The non-display region NDA may be provided at the edge or periphery of the main region MA so as to surround (e.g., around) the display region DA.

[0070] The sub-region SBA may be a region protruding from the non-display region NDA of the main region MA toward one side in the second direction DR2.

[0071] Figure 2 and Figure 3 illustrates the display device 100 in a state where a part of the sub-region SBA is bent.

[0072] As Figure 2 and Figure 3 illustrated in, a part of the sub-region SBA is transformed into a bent shape so that another part of the sub-region SBA can be provided on the rear surface of the display device 100. In one or more embodiments, the substrate 110 of the display device 100 may include a hole region HLA, and the main region MA of the substrate 110 may include a hole bypass region HBA provided around the hole region HLA. In one or more embodiments, the display driving circuit 200 may be provided in the sub-region SBA, and the circuit board 300 may be provided at an edge on one side of the sub-region SBA.

[0073] In one or more embodiments, as regarding Figures 1 to 7As shown, the sub-region SBA may include a bent region BA that is transformed into a bent shape, a first sub-region SB1 disposed between one side of the bent region BA and the main region MA, and a second sub-region SB2 connected to the other side of the bent region BA.

[0074] Reference Figure 3 , according to one or more embodiments, the display device 100 includes a substrate 110, a circuit layer 120 disposed on the substrate 110, and an element layer 130 disposed on the circuit layer 120.

[0075] According to one or more embodiments, the display device 100 may further include a sealing layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the sealing layer 140.

[0076] In addition, in order to reduce external light reflection, according to one or more embodiments, the display device 100 may further include a polarization layer 160 disposed on the touch sensor layer 150.

[0077] The substrate 110 may be made of an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide. The substrate 110 may be a flexible substrate that can be bent, folded, and / or curled.

[0078] Alternatively, the substrate 110 may be made of an insulating material such as glass.

[0079] The substrate 110 may include a main region MA and a sub-region SBA. The main region MA may include a display region DA and a non-display region NDA.

[0080] The circuit layer 120 may include an insulating layer, a conductive layer, and one or more semiconductor layers. One or more insulating layers may be interposed between the conductive layer and one or more semiconductor layers. The circuit layer 120 may include transistors provided as one or more semiconductor layers and one or more conductive layers, and signal lines each provided as at least one of the conductive layers.

[0081] The element layer 130 may include light-emitting elements.

[0082] The sealing layer 140 may cover the circuit layer 120 and the element layer 130, and may block oxygen and / or moisture from penetrating into the element layer 130.

[0083] The touch sensor layer 150 may include touch electrodes and touch lines connected to the touch electrodes.

[0084] In one or more embodiments, a light-transmitting hole TRH passing through the circuit layer 120, the element layer 130, and the sealing layer 140 is disposed in at least a part of the middle of the hole region HLA.

[0085] Figure 4 is a layout diagram of part B of the illustration Figure 2 .

[0086] Referring to Figure 4 , the display area DA of the display device 100 according to one or more embodiments may include emission areas EA (e.g., EA1, EA2, EA3). Additionally, the display area DA may further include non-emission areas disposed in the interval portions between the emission areas EA.

[0087] The element layer 130 (refer to Figure 3 ) may include light-emitting elements LE (refer to Figure 5 ) respectively disposed in the emission areas EA.

[0088] The circuit layer 120 (refer to Figure 3 ) may include emission pixel drivers EPD arranged side by side along a first direction DR1 and a second direction DR2 in a main area MA. The emission pixel drivers EPD may be electrically connected to the light-emitting elements LE of the element layer 130 respectively (refer to Figure 5 ).

[0089] The emission area EA may have a rhombus shape in a plan view, or may have a rectangular shape in a plan view. However, this is merely an example, and the shape of the emission area EA according to one or more embodiments in the plan view is not limited to Figure 4 the shape illustrated in. That is, the emission area EA may have a polygon shape such as a quadrilateral shape, a pentagon shape, or a hexagon shape in a plan view, or may have a circular shape or an oval shape including curved edges in a plan view.

[0090] The emission area EA may include a first emission area EA1 that emits light of a first color in a suitable wavelength band (e.g., a predetermined wavelength band), a second emission area EA2 that emits light of a second color in a wavelength band lower than the wavelength band of the first color, and a third emission area EA3 that emits light of a third color in a wavelength band lower than the wavelength band of the second color.

[0091] As an example, the first color may be red corresponding to a wavelength band of about 600 nm to 750 nm. The second color may be green corresponding to a wavelength band of about 480 nm to 560 nm. The third color may be blue corresponding to a wavelength band of about 370 nm to 460 nm.

[0092] The first emission area EA1 and the third emission area EA3 may be alternately disposed along at least one of the first direction DR1 or the second direction DR2.

[0093] The second emission region EA2 can be arranged side by side in at least one of the first direction DR1 or the second direction DR2.

[0094] In addition, the second emission region EA2 can be adjacent to the first emission region EA1 and the third emission region EA3 in diagonal directions DR4 and DR5 that intersect the first direction DR1 and the second direction DR2.

[0095] Pixels PX that display each brightness and color can be provided by the first emission region EA1, the second emission region EA2, and the third emission region EA3 that are adjacent to each other among these emission regions EA.

[0096] In other words, the pixel PX can be a basic unit that displays various colors including white at a suitable brightness (e.g., a predetermined brightness).

[0097] Each of the pixels PX can include at least one first emission region EA1, at least one second emission region EA2, and at least one third emission region EA3 that are adjacent to each other. Accordingly, each of the pixels PX can display various colors by mixing the light emitted from the first emission region EA1, the second emission region EA2, and the third emission region EA3 that are adjacent to each other.

[0098] Figure 5 is a schematic diagram Figure 4 of an equivalent circuit of the emission pixel driver.

[0099] Refer to Figure 5 , one light-emitting element LE of the light-emitting elements LE in the element layer 130 can be electrically connected between one emission pixel driver EPD in the emission pixel driver EPD of the circuit layer 120 and the second power supply ELVSS.

[0100] That is, the anode electrode of the light-emitting element LE can be electrically connected to the emission pixel driver EPD, and the second power supply ELVSS having a voltage level lower than the voltage level of the first power supply ELVDD can be applied to the cathode electrode of the light-emitting element LE.

[0101] A capacitor Cel connected in parallel between the anode electrode and the cathode electrode to the light-emitting element LE indicates the parasitic capacitance between the anode electrode and the cathode electrode.

[0102] The circuit layer 120 can further include a first power supply line VDL that transmits the first power supply ELVDD, a first initialization voltage line VIL that transmits the first initialization voltage VINT, a second initialization voltage line VAIL that transmits the second initialization voltage VAINT, and a bias voltage line VBL that transmits the bias voltage VBS.

[0103] The circuit layer 120 may further include a data line DL for transmitting a data signal Vdata, a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, a transmission control line ECL for transmitting a transmission control signal EC, a gate control line GCL for transmitting a gate control signal GC, and a bias control line GBL for transmitting a bias control signal GB.

[0104] One emission pixel driver EPD of the circuit layer 120 may include a first transistor T1 that generates a drive current for driving a light-emitting element LE, two or more transistors T2 to T8 electrically connected to the first transistor T1, and at least one capacitor PC1.

[0105] The first transistor T1 may generate a drive current for driving the light-emitting element LE.

[0106] A first electrode (e.g., a source electrode) of the first transistor T1 may be electrically connected to a first power line VDL through a fifth transistor T5.

[0107] A second electrode (e.g., a drain electrode) of the first transistor T1 may be electrically connected to an anode electrode of the light-emitting element LE through a sixth transistor T6.

[0108] The first electrode of the first transistor T1 may be electrically connected to the data line DL through a second transistor T2.

[0109] A gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through a first capacitor PC1.

[0110] That is to say, the first capacitor PC1 may be electrically connected between the gate electrode of the first transistor T1 and the first power line VDL.

[0111] Accordingly, the potential of the gate electrode of the first transistor T1 may be maintained as the voltage charged in the first capacitor PC1.

[0112] In addition, when the data signal Vdata on the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2, the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 may be the voltage difference between the first power supply ELVDD and the data signal Vdata.

[0113] In this case, when the voltage difference (i.e., the gate-source voltage difference) between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 is greater than or equal to the threshold voltage, the first transistor T1 is turned on, so that a drain-source current of the first transistor T1 corresponding to the data signal Vdata can be generated.

[0114] Subsequently, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be connected in series between the first power supply ELVDD and the second power supply ELVSS to the light-emitting element LE. Accordingly, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as the drive current for the light-emitting element LE.

[0115] Accordingly, the light-emitting element LE can emit light with a brightness corresponding to the data signal Vdata.

[0116] The second transistor T2 can be electrically connected between the first electrode of the first transistor T1 and the data line DL. The second transistor T2 can be turned on by the write scan line signal GW of the write scan line GWL.

[0117] The third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The third transistor T3 can be turned on by the gate control signal GC of the gate control line GCL.

[0118] The fourth transistor T4 can be connected between the gate electrode of the first transistor T1 and the first initialization voltage line VIL. The fourth transistor T4 can be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0119] The third transistor T3 and the fourth transistor T4 can be provided as N-type metal-oxide-semiconductor field-effect transistors (N-type MOSFETs).

[0120] The fifth transistor T5 can be electrically connected between the first electrode of the first transistor T1 and the first power supply line VDL.

[0121] The sixth transistor T6 can be electrically connected between the second electrode of the first transistor T1 and the anode electrode of the light-emitting element LE.

[0122] The fifth transistor T5 and the sixth transistor T6 can be turned on by the emission control signal EC of the emission control line ECL.

[0123] The seventh transistor T7 can be electrically connected between the anode electrode of the light-emitting element LE and the second initialization voltage line VAIL. The seventh transistor T7 can be turned on by the bias control signal GB of the bias control line GBL.

[0124] The eighth transistor T8 can be electrically connected between the first electrode of the first transistor T1 and the bias voltage line VBL.

[0125] The eighth transistor T8 can be turned on by the bias control signal GB of the bias control line GBL.

[0126] According to one or more embodiments, the third transistor T3 and the fourth transistor T4 among the first transistor T1 to the eighth transistor T8 may be provided as N-type MOSFETs, and the transistors T1, T2, and T5 to T8 other than the third transistor T3 and the fourth transistor T4 may be provided as P-type MOSFETs.

[0127] Accordingly, each of the third transistor T3 and the fourth transistor T4 may include a channel portion, a source portion, and a drain portion disposed at a different semiconductor layer from the other transistors T1, T2, and T5 to T8.

[0128] Figure 6 is a diagram Figure 5 cross-sectional view of the first transistor, the second transistor, the fourth transistor, the sixth transistor, and the light-emitting element.

[0129] Reference Figure 6 , according to one or more embodiments, the circuit layer 120 of the display device 100 may include: a buffer layer 121 covering the first light-shielding layer LB1 disposed on the substrate 110; first semiconductor layers CH1, S1, D1, CH2, S2, D2, CH6, S6, and D6 disposed on the buffer layer 121; a first gate insulating layer 122 covering the first semiconductor layers CH1, S1, D1, CH2, S2, D2, CH6, S6, and D6 and the buffer layer 121; first gate conductive layers G1, G2, and G6 disposed on the first gate insulating layer 122; a second gate insulating layer 123 covering the first gate conductive layers G1, G2, and G6 and the first gate insulating layer 122; second gate conductive layers CPE and LB2 disposed on the second gate insulating layer 123; a first interlayer insulating layer 124 covering the second gate conductive layers CPE and LB2 and the second gate insulating layer 123; second semiconductor layers CH4, S4, and D4 disposed on the first interlayer insulating layer 124; a third gate insulating layer 125 covering the second semiconductor layers CH4, S4, and D4 and the first interlayer insulating layer 124; a third gate conductive layer G4 disposed on the third gate insulating layer 125; a second interlayer insulating layer 126 covering the third gate conductive layer G4 and the third gate insulating layer 125; first source / drain conductive layers ANCE1, DCE, GCNE, and VIL disposed on the second interlayer insulating layer 126; a first planarization layer 127 covering the first source / drain conductive layers ANCE1, DCE, GCNE, and VIL and the second interlayer insulating layer 126; second source / drain conductive layers ANCE2 and DL disposed on the first planarization layer 127; and a second planarization layer 128 covering the second source / drain conductive layers ANCE2 and DL and the first planarization layer 127.

[0130] The first transistor T1 may include a channel portion CH1, a source portion S1, and a drain portion D1 of a first semiconductor layer formed to be disposed on the buffer layer 121, and a gate electrode G1 disposed at a first gate conductive layer (the first gate conductive layer is disposed on the first gate insulating layer 122) and overlapping the channel portion CH1 in a third direction DR3 (e.g., the thickness direction of the substrate 110).

[0131] The channel portion CH1 of the first transistor T1 may overlap a first light-shielding layer LB1 disposed on the substrate 110 in the third direction DR3.

[0132] The second transistor T2 may include a channel portion CH2, a source portion S2, and a drain portion D2 of a first semiconductor layer formed to be disposed on the buffer layer 121, and a gate electrode G2 disposed at a first gate conductive layer (the first gate conductive layer is disposed on the first gate insulating layer 122) and overlapping the channel portion CH2 in a third direction DR3.

[0133] The sixth transistor T6 may include a channel portion CH6, a source portion S6, and a drain portion D6 of a first semiconductor layer formed to be disposed on the buffer layer 121, and a gate electrode G6 disposed at a first gate conductive layer (the first gate conductive layer is disposed on the first gate insulating layer 122) and overlapping the channel portion CH6 in a third direction DR3.

[0134] The source portion S2 of the second transistor T2 may be electrically connected to the data line DL through a data connection electrode DCE.

[0135] The data connection electrode DCE may be disposed at a first source / drain conductive layer (the first source / drain conductive layer is disposed on the second interlayer insulating layer 126), and may be electrically connected to the source portion S2 of the second transistor T2 through a data connection auxiliary hole DCAH passing through the second interlayer insulating layer 126, the third gate insulating layer 125, the first interlayer insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0136] The data line DL may be disposed at a second source / drain conductive layer (the second source / drain conductive layer is disposed on the first planarization layer 127), and may be electrically connected to the data connection electrode DCE through a data connection hole DCH passing through the first planarization layer 127.

[0137] The drain portion D2 of the second transistor T2 may be connected to the source portion S1 of the first transistor T1.

[0138] The drain portion D1 of the first transistor T1 may be connected to the source portion S6 of the sixth transistor T6.

[0139] The drain portion D6 of the sixth transistor T6 can be electrically connected to the anode electrode 131 through the first anode connection electrode ANCE1 and the second anode connection electrode ANCE2.

[0140] The first anode connection electrode ANCE1 can be disposed at the first source / drain conductive layer (the first source / drain conductive layer is disposed on the second interlayer insulating layer 126), and can be electrically connected to the drain portion D6 of the sixth transistor T6 through the first anode connection hole ANCH1 that penetrates through the second interlayer insulating layer 126, the third gate insulating layer 125, the first interlayer insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0141] The second anode connection electrode ANCE2 can be disposed at the second source / drain conductive layer (the second source / drain conductive layer is disposed on the first planarization layer 127), and can be electrically connected to the first anode connection electrode ANCE1 through the second anode connection hole ANCH2 that penetrates through the first planarization layer 127.

[0142] The anode electrode 131 can be disposed on the second planarization layer 128, and can be electrically connected to the second anode connection electrode ANCE2 through the third anode connection hole ANCH3 that penetrates through the second planarization layer 128.

[0143] The first capacitor PC1 can be provided by an overlapping region between a capacitor electrode CPE disposed at the second gate conductive layer (the second gate conductive layer is disposed on the second gate insulating layer 123) and the gate electrode G1 of the first transistor T1.

[0144] The fourth transistor T4 can include a channel portion CH4, a source portion S4, and a drain portion D4 formed of a second semiconductor layer disposed on the first interlayer insulating layer 124, a gate electrode G4 disposed at the third gate conductive layer (the third gate conductive layer is disposed on the third gate insulating layer 125), and a gate auxiliary electrode LB2 disposed at the second gate conductive layer (the second gate conductive layer is disposed on the second gate insulating layer 123).

[0145] Each of the gate electrode G4 and the gate auxiliary electrode LB2 can overlap with the channel portion CH4 of the fourth transistor T4 in the third direction DR3.

[0146] The source portion S4 of the fourth transistor T4 can be electrically connected to the first initialization voltage line VIL disposed on the second interlayer insulating layer 126 through the initialization voltage connection hole VICH that penetrates through the second interlayer insulating layer 126 and the third gate insulating layer 125.

[0147] The drain portion D4 of the fourth transistor T4 can be electrically connected to the gate electrode G1 of the first transistor T1 through a gate connection electrode GCNE disposed at the first source / drain conductive layer (the first source / drain conductive layer is disposed on the second interlayer insulating layer 126).

[0148] The gate connection electrode GCNE can be electrically connected to the drain portion D4 of the fourth transistor T4 through a first gate connection hole GCH1 that penetrates the second interlayer insulating layer 126 and the third gate insulating layer 125.

[0149] The gate connection electrode GCNE can be electrically connected to the gate electrode G1 of the first transistor T1 through a second gate connection hole GCH2 that penetrates the second interlayer insulating layer 126, the third gate insulating layer 125, the first interlayer insulating layer 124, and the second gate insulating layer 123.

[0150] In one or more embodiments, the third transistor T3 has a similar structure to the fourth transistor T4, and the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 each have a similar structure to the second transistor T2 and the sixth transistor T6. Therefore, the repeated descriptions will be omitted hereinafter.

[0151] The element layer 130 can be disposed on the circuit layer 120 and can include light-emitting elements LE respectively corresponding to the emission regions EA.

[0152] Each of the light-emitting elements LE can include an anode electrode 131 and a cathode electrode 134 facing each other, and a light-emitting layer 133 is disposed between the anode electrode 131 and the cathode electrode 134.

[0153] That is, the element layer 130 can include an anode electrode 131 respectively corresponding to the emission region EA, a pixel defining layer 132 corresponding to the non-emission region NEA and covering the edge of the anode electrode 131, a light-emitting layer 133 respectively disposed on the anode electrode 131, and a cathode electrode 134 disposed on the light-emitting layer 133 and the pixel defining layer 132.

[0154] In an embodiment, each of the light-emitting elements LE can further include a first common layer disposed between the anode electrode 131 and the light-emitting layer 133 and a second common layer disposed between the light-emitting layer 133 and the cathode electrode 134.

[0155] The anode electrode 131 can be disposed in each of the emission regions EA and can be electrically connected to an emission pixel driver EPD of the circuit layer 120. The anode electrode 131 can be referred to as a pixel electrode.

[0156] The anode electrode 131 can be electrically connected to the second anode connection electrode ANCE2 through a third anode connection hole ANCH3 that penetrates the second planarization layer 128.

[0157] The light-emitting layer 133 can include an organic light-emitting material that converts electron-hole pairs into light.

[0158] The cathode electrode 134 may be disposed in the display area DA including the emission area EA. The second power supply ELVSS may be commonly applied to the cathode electrode 134. The cathode electrode 134 may be referred to as a common electrode.

[0159] The sealing layer 140 may be disposed on the circuit layer 120 and cover the element layer 130.

[0160] As an example, the sealing layer 140 may include a first encapsulation layer disposed on the element layer 130 and made of an inorganic insulating material, a second encapsulation layer disposed on the first encapsulation layer, covering the element layer 130 and made of an organic insulating material, and a third encapsulation layer disposed on the first encapsulation layer, covering the second encapsulation layer and made of an inorganic insulating material.

[0161] In one or more embodiments, in order to reduce the width of the non-display area NDA, the circuit layer 120 of the display device 100 may include a bridge wire BRL (see Figure 8 ) and an additional wire ADL (see Figure 8 ).

[0162] Figure 7 is a plan view of the substrate shown Figure 3 of.

[0163] Referring to Figure 7 , the substrate 110 of the display device 100 according to one or more embodiments includes a main area MA corresponding to the display surface and a sub-area SBA protruding from one side of the main area MA.

[0164] The main area MA includes a display area DA disposed at most of its center and a non-display area NDA disposed at its edge or periphery and around the display area DA (e.g., surrounding the display area DA).

[0165] The edge of the display area DA may include a first side SD1 extending in a first direction DR1 and facing the sub-area SBA in a second direction DR2, and a second side SD2 extending in the first direction DR1, opposite to the first side SD1 in the second direction DR2 and spaced farther from the sub-area SBA than the first side SD1 is from the sub-area SBA.

[0166] In addition, the edge of the display area DA may further include a third side SD3 and a fourth side SD4 extending in the second direction DR2 and opposite to each other in the first direction DR1.

[0167] That is, the display area DA may have a rectangular shape including four sides SD1, SD2, SD3, and SD4.

[0168] The display area DA may include a bypass area BYA disposed on a side adjacent to the sub-area SBA in the second direction DR2 and a general area GA disposed in an area other than the bypass area BYA.

[0169] The bypass area BYA may include a bypass middle area BMA disposed in the middle, a first bypass side area BSA1 in contact with one side of the bypass middle area BMA, and a second bypass side area BSA2 disposed between the non-display area NDA and the first bypass side area BSA1 in the first direction DR1.

[0170] The second bypass side area BSA2 may be disposed closer to the bent corner of the substrate 110 than the bypass middle area BMA and the first bypass side area BSA1.

[0171] One first bypass side area BSA1 and one second bypass side area BSA2 may be disposed on each of the two sides of the bypass middle area BMA in the first direction DR1.

[0172] The general area GA may include a general middle area GMA connected to the bypass middle area BMA in the second direction DR2, a first general side area GSA1 connected to the first bypass side area BSA1 in the second direction DR2, and a second general side area GSA2 connected to the second bypass side area BSA2 in the second direction DR2.

[0173] The non-display area NDA may include a gate driving circuit area GDRA where a gate driving circuit is disposed.

[0174] The gate driving circuit area GDRA may be disposed in a part of the non-display area NDA facing the third side SD3 and / or the fourth side SD4 of the display area DA.

[0175] The gate driving circuit in the gate driving circuit area GDRA may sequentially transmit gate signals to the gate lines. Here, the gate lines may include a scan write-in line GWL (see Figure 5 ) for transmitting a scan write-in signal GW (see Figure 5 ), a scan initialization line GIL (see Figure 5 ) for transmitting a scan initialization signal GI (see Figure 5 ), a gate control line GCL (see Figure 5 ) for transmitting a gate control signal GC (see Figure 5 ), a bias control line GBL (see Figure 5 ) for transmitting a bias control signal GB (see Figure 5 ), and an emission control line ECL (see Figure 5 ) for transmitting an emission control signal EC.

[0176] The sub-region SBA may include a bent region BA that is transformed into a bent shape, a first sub-region SB1 disposed between one side of the bent region BA and the main region MA, and a second sub-region SB2 connected to the other side of the bent region BA.

[0177] When the bent region BA is transformed into a bent shape, the second sub-region SB2 is disposed under the substrate 110 and overlaps the main region MA in the third direction DR3.

[0178] The display driving circuit 200 may be disposed in the second sub-region SB2.

[0179] The signal pad SPD to which the circuit board 300 is connected may be disposed at an edge on one side of the second sub-region SB2.

[0180] Figure 8 is a layout diagram of part C of the illustration Figure 7 of the illustration. Figure 9 is along Figure 8 of the illustration taken along line E-E'.

[0181] Refer to Figure 8 , according to one or more embodiments, the circuit layer 120 of the display device 100 may include emission pixel drivers EPD arranged along a first direction DR1 and a second direction DR2, data lines DL extending in the second direction DR2 and transmitting data signals Vdata to the emission pixel drivers EPD, bridge lines BRL extending in the first direction DR1, and additional lines ADL extending in the second direction DR2 and adjacent to the data lines DL.

[0182] The circuit layer 120 may further include a first power sub-line VDSBL extending in the second direction DR2 and transmitting a first power supply ELVDD (see Figure 5 ), and a first power main line VDMNL extending in the first direction DR1 and transmitting the first power supply ELVDD (see Figure 5 ). The first power main line VDMNL and the first power sub-line VDSBL are electrically connected to each other, and accordingly, the first power supply ELVDD may be supplied by lines having a grid shape.

[0183] According to one or more embodiments, each of the emission pixel drivers EPD may overlap with one data line DL, one additional line ADL paired with the one data line DL, and one first power sub-line VDSBL adjacent to one of the one data line DL and the one additional line ADL.

[0184] In the first direction DR1, one additional line ADL may be disposed between one data line DL and one first power sub-line VDSBL.

[0185] That is, in the first direction DR1, two data lines DL facing each other can be disposed between additional lines ADL respectively paired with these two data lines DL.

[0186] In addition, in the first direction DR1, two first power sub-lines VDSBL facing each other can be disposed between additional lines ADL adjacent to these two first power sub-lines VDSBL respectively.

[0187] According to one or more embodiments, each of the emission pixel drivers EPD can overlap with a bridge line BRL and a first power main line VDMNL adjacent to the bridge line BRL.

[0188] That is, in the second direction DR2, the bridge line BRL and the first power main line VDMNL can be alternately arranged one by one.

[0189] According to one or more embodiments, the circuit layer 120 can further include a data supply line DSPL disposed in the non-display area NDA and electrically connected between the display driving circuit 200 and the data line DL.

[0190] The data line DL can include a first data line DL1 disposed in the first bypass side area BSA1 and a second data line DL2 disposed in the second bypass side area BSA2.

[0191] That is, the second data line DL2 is farther from the sub-area SBA than the first data line DL1 is from the sub-area SBA.

[0192] The bridge line BRL can include a data bypass bridge line DBBRL electrically connected to the second data line DL2 in the second bypass side area BSA2.

[0193] The additional line ADL can include a data bypass additional line DBADL disposed in the first bypass side area BSA1, adjacent to the first data line DL1, and electrically connected to the data bypass bridge line DBBRL.

[0194] The data supply line DSPL can include a first data supply line DSPL1 for transmitting the data signal of the first data line DL1 and a second data supply line DSPL2 for transmitting the data signal of the second data line DL2.

[0195] According to one or more embodiments, the data supply line DSPL can extend to areas other than the second bypass side area BSA2 that is relatively far from the sub-area SBA. That is, the data supply line DSPL can extend to the first bypass side area BSA1 and the bypass middle area BMA.

[0196] Accordingly, the first data supply line DSPL1 can extend to the first data line DL1 in the first bypass side area BSA1 and can be directly electrically connected to the first data line DL1.

[0197] On the other hand, the second data supply line DSPL2 can extend to the data bypass additional line DBADL in the first bypass side area BSA1 and can be electrically connected to the second data line DL2 through the data bypass additional line DBADL and the data bypass bridge connection line DBBRL.

[0198] In this way, the second data supply line DSPL2 extends to the data bypass additional line DBADL in the first bypass side area BSA1 instead of extending to the second data line DL2 in the second bypass side area BSA2, and thus, the extension length of the second data supply line DSPL2 can be reduced. For this purpose, the width of the area required to set the data supply line DSPL can be reduced, and thus, the width of the non-display area NDA can be reduced.

[0199] In addition, the data supply line DSPL is not arranged in the second bypass side area BSA2 adjacent to the bent corner in the non-display area NDA of the substrate 110, and thus, the width of the non-display area NDA can be further reduced.

[0200] The data line DL can further include a third data line DL3 provided in the bypass middle area BMA.

[0201] In addition, the data supply line DSPL can further include a third data supply line DSPL3 that transmits the data signal of the third data line DL3.

[0202] The third data supply line DSPL3 can extend to the third data line DL3 in the bypass middle area BMA and can be directly electrically connected to the third data line DL3.

[0203] The data bypass bridge connection line DBBRL can be provided between the data bypass additional line DBADL and the second data line DL2.

[0204] The data bypass additional line DBADL can be provided between the first side SD1 and the data bypass bridge connection line DBBRL.

[0205] In this way, the data bypass bridge connection line DBBRL and the data bypass additional line DBADL are limitedly provided in the bypass area BYA, and accordingly, the presence or absence of the data bypass bridge connection line DBBRL and the data bypass additional line DBADL can be observed.

[0206] In addition, both ends of the data bypass bridge wiring DBBRL and one end of the data bypass additional wiring DBADL are provided in the display area DA, and thus, the visibility of both ends of the data bypass bridge wiring DBBRL and one end of the data bypass additional wiring DBADL can be improved.

[0207] To prevent this, the bridge wiring BRL may further include a power supply auxiliary bridge wiring VABRL. In addition, the additional wiring ADL may further include a power supply auxiliary additional wiring VAADL.

[0208] One power supply auxiliary bridge wiring VABRL in the power supply auxiliary bridge wiring VABRL may be provided between one end of the data bypass bridge wiring DBBRL and the third side SD3, and the other power supply auxiliary bridge wiring VABRL in the power supply auxiliary bridge wiring VABRL may be provided between the other end of the data bypass bridge wiring DBBRL and the fourth side SD4.

[0209] One power supply auxiliary additional wiring VAADL in the power supply auxiliary additional wiring VAADL may be provided between one end of the data bypass additional wiring DBADL and the second side SD2.

[0210] Accordingly, some of the first data lines DL1 in the first data line DL1 may be adjacent to the data bypass additional wiring DBADL, and the other first data lines DL1 in the first data line DL1 may be adjacent to the power supply auxiliary additional wiring VAADL.

[0211] Since the data bypass additional wiring DBADL is only provided in the first bypass side area BSA1, each of the second data lines DL2 in the second bypass side area BSA2 and the third data lines DL3 in the bypass middle area BMA may be adjacent to the power supply auxiliary additional wiring VAADL as a whole.

[0212] The power supply auxiliary bridge wiring VABRL and the power supply auxiliary additional wiring VAADL may be electrically connected to each other through the power supply auxiliary connection hole VACH.

[0213] The power supply auxiliary connection hole VACH may be provided in an area in the display area DA other than the first bypass side area BSA1 and the second bypass side area BSA2.

[0214] As Figure 8 illustrated, the circuit layer 120 may further include a first power supply line VDSPL and a second power supply line VSSPL that are provided in the non-display area NDA and respectively transmit a first power supply ELVDD and a second power supply ELVSS for driving the light emitting element LE.

[0215] The second power supply line VSSPL can be formed to extend from one side of the first side SD1 of the edge of the display area DA via the third side SD3, the second side SD2, and the fourth side SD4 to the other side of the first side SD1.

[0216] The first power supply line VDSPL can be formed to face the first side SD1 of the edge of the display area DA.

[0217] Alternatively, like the second power supply line VSSPL, the first power supply line VDSPL can be formed to extend from one side of the first side SD1 of the edge of the display area DA via the third side SD3, the second side SD2, and the fourth side SD4 to the other side of the first side SD1, and can be disposed between the second power supply line VSSPL and the display area DA.

[0218] The first power supply line VDSPL and the second power supply line VSSPL can extend from the sub-region SBA.

[0219] The first power supply line VDSPL can be electrically connected to the first power supply pad for transmitting the first power supply ELVDD among the signal pads SPD disposed in the second sub-region SB2.

[0220] The second power supply line VSSPL can be electrically connected to the second power supply pad for transmitting the second power supply ELVSS among the signal pads SPD disposed in the second sub-region SB2.

[0221] According to one or more embodiments, the power supply auxiliary bridge wiring VABRL can be electrically connected to the second power supply line VSSPL.

[0222] The power supply auxiliary additional wiring VAADL can be electrically connected to the power supply auxiliary bridge wiring VABRL and the second power supply line VSSPL.

[0223] Alternatively, some of the power supply auxiliary bridge wiring VABRL and some of the power supply auxiliary additional wiring VAADL can be electrically connected to the second power supply line VSSPL, and the other power supply auxiliary bridge wiring VABRL and the other power supply auxiliary additional wiring VAADL can be electrically connected to the constant voltage supply line CVSPL (see Figure 13 and Figure 14 ).

[0224] The constant voltage supply line CVSPL (see Figure 13 and Figure 14 ) can transmit the first initialization voltage VINT (see Figure 5 ), the second initialization voltage VAINT (see Figure 5 ) and the bias voltage VBS (seeFigure 5 one of the following

[0225] The first power main line VDMNL and the first power sub-line VDSBL can be electrically connected to the first power supply line VDSPL.

[0226] Reference Figure 9 , the data line DL, the additional line ADL, and the first power sub-line VDSBL can be disposed on at least one insulating layer (i.e., the first planarization layer 127) covering the bridge connection line BRL and the first power main line VDMNL.

[0227] That is to say, the bridge connection line BRL and the first power main line VDMNL can be disposed at the first source / drain conductive layer (the first source / drain conductive layer is disposed on the second interlayer insulating layer 126).

[0228] The data line DL, the additional line ADL, and the first power sub-line VDSBL can be disposed at the second source / drain conductive layer (the second source / drain conductive layer is disposed on the first planarization layer 127).

[0229] The second data line DL2 can be electrically connected to the data bypass bridge connection line DBBRL through the first data bypass connection hole DBCH1 penetrating the first planarization layer 127.

[0230] The data bypass additional line DBADL can be electrically connected to the data bypass bridge connection line DBBRL through the second data bypass connection hole DBCH2 penetrating the first planarization layer 127.

[0231] Accordingly, the second data line DL2 can be electrically connected to the data bypass additional line DBADL through the data bypass bridge connection line DBBRL.

[0232] In addition, the data bypass additional line DBADL is electrically connected to the second data supply line DSPL2, and thus, the second data supply line DSPL2 can be electrically connected to the second data line DL2 through the data bypass additional line DBADL and the data bypass bridge connection line DBBRL.

[0233] As described above, according to one or more embodiments, the circuit layer 120 includes the data bypass additional line DBADL and the data bypass bridge connection line DBBRL disposed in the display area DA, and accordingly, even if the second data supply line DSPL2 does not extend to the second data line DL2, it can be electrically connected to the second data line DL2. Accordingly, the extension length of the data supply line DSPL2 can be reduced, and thus, the width of the non-display area NDA can be reduced.

[0234] As Figure 7As shown, the substrate 110 of the display device 100 according to one or more embodiments may include a hole region HLA, and a main region MA of the substrate 110 may include a hole bypass region HBA disposed around the hole region HLA.

[0235] The light-transmitting holes TRH (see Figure 3 ) passing through the circuit layer 120, the element layer 130, and the sealing layer 140 are disposed in at least a part of the middle of the hole region HLA, and accordingly, some hole-crossing data lines HCRDL (see Figure 10 ) among the data lines DL of the circuit layer 120 that cross the hole region HLA are separated by the hole region HLA.

[0236] Accordingly, according to an embodiment, the separated portions of each of the hole-crossing data lines HCRDL (see Figure 10 ) may be electrically connected to each other using some bridge lines BRL and some additional lines ADL disposed in the hole bypass region HBA.

[0237] Figure 10 is a layout diagram of part D of Figure 7 according to one or more embodiments.

[0238] Referring to Figure 10 , the substrate 110 of the display device 100 according to one or more embodiments may include a hole region HLA surrounded by the main region MA.

[0239] The hole region HLA may include a hole main region HMA disposed in the middle and a hole sub-region HSA disposed between the hole main region HMA and the hole bypass region HBA.

[0240] The light-transmitting holes TRH passing through the circuit layer 120 and the element layer 130 may be disposed in the hole main region HMA. The light-transmitting holes TRH may further pass through at least one of the substrate 110, the sealing layer 140, and the touch sensor layer 150.

[0241] A bonding structure of an inorganic insulating material for blocking the penetration of oxygen or moisture through the light-transmitting holes TRH may be disposed in the hole sub-region HSA.

[0242] The main region MA may include a display region DA in which an emission region EA is arranged, a non-display region NDA disposed around the display region DA, and a hole bypass region HBA disposed around the hole region HLA.

[0243] According to one or more embodiments, the circuit layer 120 may include an emission pixel driver EPD arranged side by side along a first direction DR1 and a second direction DR2, a data line DL extending in the second direction DR2, a bridge wiring BRL extending in the first direction DR1, and an additional line ADL extending in the second direction DR2 and adjacent to the data line DL.

[0244] According to one or more embodiments, the bridge wiring BRL may include one or more first dummy bridge wirings DMBRL1 facing a hole region HLA on one side in the second direction DR2 and one or more second dummy bridge wirings DMBRL2 facing the hole region HLA on the other side in the second direction DR2.

[0245] Each of the one or more first dummy bridge wirings DMBRL1 and the one or more second dummy bridge wirings DMBRL2 may not cross the hole region HLA, and may extend between a third side SD3 (see Figure 7 ) and a fourth side SD4 (see Figure 7 ).

[0246] The one or more first dummy bridge wirings DMBRL1 may be one or more bridge wirings BRL selected in an order adjacent to the hole region HLA on one side in the second direction DR2 ( Figure 10 the lower side) that do not cross the hole region HLA.

[0247] The one or more second dummy bridge wirings DMBRL2 may be one or more bridge wirings BRL selected in an order adjacent to the hole region HLA on the other side in the second direction DR2 ( Figure 10 the upper side) that do not cross the hole region HLA.

[0248] According to one or more embodiments, the additional line ADL may include one or more first dummy additional lines DMADL1 facing the hole region HLA on one side in the first direction DR1.

[0249] The one or more first dummy additional lines DMADL1 may be one or more additional lines ADL selected in an order adjacent to the hole region HLA on one side in the first direction DR1 ( Figure 10 the left side) that do not cross the hole region HLA.

[0250] According to one or more embodiments, the one or more first dummy additional lines DMADL1 may be electrically connected to the one or more first dummy bridge wirings DMBRL1 and the one or more second dummy bridge wirings DMBRL2.

[0251] In this way, one or more first dummy bridge wiring lines DMBRL1 and one or more second dummy bridge wiring lines DMBRL2 are electrically connected to each other through one or more first dummy additional lines DMADL1, and accordingly, may have the same potential.

[0252] In addition, according to one or more embodiments, the additional line ADL may include one or more second dummy additional lines DMADL2 that face the hole region HLA on the other side in the first direction DR1.

[0253] One or more second dummy additional lines DMADL2 may be one or more additional lines ADL among the additional lines ADL that do not cross the hole region HLA and are selected in the order adjacent to the hole region HLA on the other side ( Figure 10 the right side) in the first direction DR1.

[0254] One or more second dummy additional lines DMADL2 may be electrically connected to one or more first dummy bridge wiring lines DMBRL1 and one or more second dummy bridge wiring lines DMBRL2.

[0255] In this way, one or more first dummy bridge wiring lines DMBRL1, one or more second dummy bridge wiring lines DMBRL2, one or more first dummy additional lines DMADL1, and one or more second dummy additional lines DMADL2 are electrically connected to each other, and accordingly, may have the same potential.

[0256] Therefore, the potential difference between one or more first dummy bridge wiring lines DMBRL1 and one or more second dummy bridge wiring lines DMBRL2 and one or more first dummy additional lines DMADL1 and one or more second dummy additional lines DMADL2 disposed closest to the hole region HLA is eliminated, and thus, the electrical effects of one or more first dummy bridge wiring lines DMBRL1, one or more second dummy bridge wiring lines DMBRL2, one or more first dummy additional lines DMADL1, and one or more second dummy additional lines DMADL2 may become similar to each other. Accordingly, the difference in image quality between the emission regions EA adjacent to the hole region HLA can be reduced.

[0257] According to one or more embodiments, the hole bypass area HBA may include a first hole bypass separation area HBPA1 and a second hole bypass separation area HBPA2 that are adjacent to each other based on a first hole center point extension line EXT1 that intersects the center point HCP of the hole area HLA and extends in a first direction DR1, and a third hole bypass separation area HBPA3 and a fourth hole bypass separation area HBPA4 that are adjacent to the first hole bypass separation area HBPA1 and the second hole bypass separation area HBPA2 respectively based on a second hole center point extension line EXT2 that intersects the center point HCP of the hole area HLA and extends in a second direction DR2.

[0258] As an example, as Figure 10 illustrated, the first hole bypass separation area HBPA1 may be disposed on the lower left side of the hole area HLA, the second hole bypass separation area HBPA2 may be disposed on the upper left side of the hole area HLA, the third hole bypass separation area HBPA3 may be disposed on the lower right side of the hole area HLA, and the fourth hole bypass separation area HBPA4 may be disposed on the upper right side of the hole area HLA.

[0259] The data line DL may include a hole-crossing data line HCRDL that crosses the hole area HLA.

[0260] Each of the hole-crossing data lines HCRDL is separated by the hole area HLA passing through the circuit layer 120, and thus, may include a first divided line portion DVL1 disposed on one side of the hole area HLA and a second divided line portion DVL2 disposed on the other side of the hole area HLA.

[0261] That is, the first divided line portion DVL1 (DVL1_HCRDL1 and DVL1_HCRDL2) of each of the hole-crossing data lines HCRDL may be disposed between the first side SD1 (see Figure 7 ) and the hole area HLA. In addition, the second divided line portion DVL2 (DVL2_HCRDL1 and DVL2_HCRDL2) of each of the hole-crossing data lines HCRDL may be disposed between the hole area HLA and the second side SD2.

[0262] In other words, the first divided line portion DVL1 (DVL1_HCRDL1 and DVL1_HCRDL2) of each of the hole-crossing data lines HCRDL may be disposed on one side of the second direction DR2 based on the first hole center point extension line EXT1. In addition, the second divided line portion DVL2 (DVL2_HCRDL1 and DVL2_HCRDL2) of each of the hole-crossing data lines HCRDL may be disposed on the other side of the second direction DR2 based on the first hole center point extension line EXT1.

[0263] The hole-crossing data line HCRDL may include a first hole-crossing data line HCRDL1 (DVL1_HCRDL1 and DVL2_HCRDL1) on one side in the first direction DR1 (e.g., the left side of Figure 10 ) facing the extension line EXT2 of the center point of the second hole.

[0264] According to one or more embodiments, the bridge line BRL may further include a first hole-bypass bridge line HBBRL1 disposed in the first hole-bypass separation region HBPA1 and electrically connected to the first split line portion DVL1_HCRDL1 of the first hole-crossing data line HCRDL1, and a second hole-bypass bridge line HBBRL2 disposed in the second hole-bypass separation region HBPA2 and electrically connected to the second split line portion DVL2_HCRDL1 of the first hole-crossing data line HCRDL1.

[0265] The additional line ADL may further include a first hole-bypass additional line HBADL1 disposed in the first hole-bypass separation region HBPA1 and the second hole-bypass separation region HBPA2 and electrically connected between the first hole-bypass bridge line HBBRL1 and the second hole-bypass bridge line HBBRL2.

[0266] Accordingly, the first split line portion DVL1_HCRDL1 of the first hole-crossing data line HCRDL1 and the second split line portion DVL2_HCRDL1 of the first hole-crossing data line HCRDL1 may be electrically connected to each other while bypassing the hole region HLA through the first hole-bypass bridge line HBBRL1, the first hole-bypass additional line HBADL1, and the second hole-bypass bridge line HBBRL2.

[0267] One or more first dummy additional lines DMADL1 are closest to the hole region HLA on one side in the first direction DR1, and thus, may be disposed between the first hole-bypass additional line HBADL1 and the hole region HLA in the first direction DR1.

[0268] In addition, the hole-crossing data line HCRDL may further include a second hole-crossing data line HCRDL2 (DVL1_HCRDL2 and DVL2_HCRDL2) on the other side in the first direction DR1 (e.g., the right side of Figure 10 ) facing the extension line EXT2 of the center point of the second hole.

[0269] According to one or more embodiments, the bridge wiring BRL may further include a third-hole bypass bridge wiring HBBRL3 disposed in the third-hole bypass partition area HBPA3 and electrically connected to the second-hole cross data line HCRDL2, and a fourth-hole bypass bridge wiring HBBRL4 disposed in the fourth-hole bypass partition area HBPA4 and electrically connected to the second-hole cross data line HCRDL2.

[0270] The additional wiring ADL may further include a second-hole bypass additional wiring HBADL2 disposed in the third-hole bypass partition area HBPA3 and the fourth-hole bypass partition area HBPA4 and electrically connected between the third-hole bypass bridge wiring HBBRL3 and the fourth-hole bypass bridge wiring HBBRL4.

[0271] Accordingly, the first split line portion DVL1_HCRDL2 of the second-hole cross data line HCRDL2 and the second split line portion DVL2_HCRDL2 of the second-hole cross data line HCRDL2 may be electrically connected to each other while bypassing the hole area HLA through the third-hole bypass bridge wiring HBBRL3, the second-hole bypass additional wiring HBADL2, and the fourth-hole bypass bridge wiring HBBRL4.

[0272] One or more second dummy additional wirings DMADL2 are closest to the hole area HLA on the other side in the first direction DR1, and thus, may be disposed between the second-hole bypass additional wiring HBADL2 and the hole area HLA in the first direction DR1.

[0273] According to one or more embodiments, the additional wiring ADL may further include one or more third dummy additional wirings DMADL3 and one or more fourth dummy additional wirings DMADL4 disposed between one or more first dummy additional wirings DMADL1 and one or more second dummy additional wirings DMADL2 in the first direction DR1.

[0274] One or more third dummy additional wirings DMADL3 may be adjacent to one side of the hole area HLA in the second direction DR2 and may be disposed between the first side SD1 and the hole area HLA. That is, one or more third dummy additional wirings DMADL3 may be disposed in the first-hole bypass partition area HBPA1 and the third-hole bypass partition area HBPA3.

[0275] One or more third dummy additional wirings DMADL3 may be electrically connected to one or more first dummy additional wirings DMADL1 and one or more second dummy additional wirings DMADL2 through one or more first dummy bridge wirings DMBRL1.

[0276] One or more fourth dummy additional lines DMADL4 may be adjacent to the other side of the hole region HLA in the second direction DR2 and may be disposed between the second side SD2 and the hole region HLA. That is, one or more fourth dummy additional lines DMADL4 may be disposed in the second hole bypass partition region HBPA2 and the fourth hole bypass partition region HBPA4.

[0277] One or more fourth dummy additional lines DMADL4 may be electrically connected to one or more first dummy additional lines DMADL1 and one or more second dummy additional lines DMADL2 by one or more second dummy bridge lines DMBRL2.

[0278] According to one or more embodiments, the bridge line BRL may further include two or more third dummy bridge lines DMBRL3 disposed between the first hole bypass bridge line HBBRL1 and the third hole bypass bridge line HBBRL3 in the first direction DR1 and between the second hole bypass bridge line HBBRL2 and the fourth hole bypass bridge line HBBRL4, and one or more fourth dummy bridge lines DMBRL4 disposed between one or more first dummy bridge lines DMBRL1 and one or more second dummy bridge lines DMBRL2 in the second direction DR2.

[0279] One or more fourth dummy bridge lines DMBRL4 may cross the hole region HLA. Accordingly, in the first direction DR1, one or more fourth dummy bridge lines DMBRL4 may be disposed between one side of the hole region HLA and the third side SD3 (see Figure 7 ) and between the other side of the hole region HLA and the fourth side SD4 (see Figure 7 ).

[0280] Some of the two or more third dummy bridge lines DMBRL3 disposed between the first hole bypass bridge line HBBRL1 and the third hole bypass bridge line HBBRL3 may be electrically connected to one or more first dummy bridge lines DMBRL1 by one or more third dummy additional lines DMADL3.

[0281] Some other third dummy bridge lines DMBRL3 of the two or more third dummy bridge lines DMBRL3 disposed between the second hole bypass bridge line HBBRL2 and the fourth hole bypass bridge line HBBRL4 may be electrically connected to one or more second dummy bridge lines DMBRL2 by one or more fourth dummy additional lines DMADL4.

[0282] Some of the one or more fourth dummy bridge connection lines DMBRL4 disposed in the first hole bypass partition region HBPA1 and the second hole bypass partition region HBPA2 among the one or more fourth dummy bridge connection lines DMBRL4 may be electrically connected to one or more first dummy additional lines DMADL1.

[0283] Some of the other fourth dummy bridge connection lines DMBRL4 disposed in the third hole bypass partition region HBPA3 and the fourth hole bypass partition region HBPA4 among the one or more fourth dummy bridge connection lines DMBRL4 may be electrically connected to one or more second dummy additional lines DMADL2.

[0284] Accordingly, two or more third dummy bridge connection lines DMBRL3, one or more fourth dummy bridge connection lines DMBRL4, one or more third dummy additional lines DMADL3, and one or more fourth dummy additional lines DMADL4 may be electrically connected to one or more first dummy bridge connection lines DMBRL1, one or more second dummy bridge connection lines DMBRL2, one or more first dummy additional lines DMADL1, and one or more second dummy additional lines DMADL2.

[0285] In this way, the first dummy bridge connection lines DMBRL1, second dummy bridge connection lines DMBRL2, third dummy bridge connection lines DMBRL3, and fourth dummy bridge connection lines DMBRL4, and the first dummy additional lines DMADL1, second dummy additional lines DMADL2, third dummy additional lines DMADL3, and fourth dummy additional lines DMADL4 among the bridge connection lines BRL and additional lines ADL disposed in the hole bypass region HBA and not electrically connected to the hole cross data lines HCRDL have the same potential. Therefore, the electrical effects of the first dummy bridge connection lines DMBRL1, second dummy bridge connection lines DMBRL2, third dummy bridge connection lines DMBRL3, and fourth dummy bridge connection lines DMBRL4, and the first dummy additional lines DMADL1, second dummy additional lines DMADL2, third dummy additional lines DMADL3, and fourth dummy additional lines DMADL4 on the surrounding environment can become equal to each other. Accordingly, the difference in image quality between the emission regions EA adjacent to the hole region HLA can be reduced.

[0286] According to one or more embodiments, one or more first dummy bridge connection lines DMBRL1, one or more second dummy bridge connection lines DMBRL2, two or more third dummy bridge connection lines DMBRL3, and one or more fourth dummy bridge connection lines DMBRL4 may be electrically connected to one or more first dummy additional lines DMADL1, one or more second dummy additional lines DMADL2, one or more third dummy additional lines DMADL3, and one or more fourth dummy additional lines DMADL4 through the dummy connection holes DMCH.

[0287] According to one or more embodiments, dummy connection holes DMCH may be arranged around the hole region HLA (e.g., surrounding the hole region HLA) such that a first dummy bridge line DMBRL1, a second dummy bridge line DMBRL2, a third dummy bridge line DMBRL3, and a fourth dummy bridge line DMBRL4 are electrically connected to a first dummy additional line DMADL1, a second dummy additional line DMADL2, a third dummy additional line DMADL3, and a fourth dummy additional line DMADL4 to each other.

[0288] According to one or more embodiments, the emission pixel driver EPD may be arranged in the hole bypass region HBA like the display region DA.

[0289] The emission pixel driver EPD in the hole bypass region HBA may include a dummy emission pixel driver DMPD in contact with the hole region HLA. The dummy emission pixel driver DMPD may have the same structure as the emission pixel driver EPD, but may not be used to supply driving current.

[0290] As an example, the dummy emission pixel driver DMPD may not be electrically connected to the data line DL and / or may not be electrically connected to the light-emitting element LE.

[0291] In this way, even in a process of setting the transmissive hole TRH (see Figure 3 ) in the hole region HLA where some of the emission pixel drivers EPD adjacent to the hole region HLA are damaged, deterioration of the image quality around the hole region HLA can be prevented.

[0292] Figure 11 is a layout diagram of part D according to one or more embodiments of Figure 7 . Figure 12 is a cross-sectional view taken along line F-F’ of Figure 11 .

[0293] Except that one or more first dummy additional lines DMADL1 and one or more second dummy additional lines DMADL2 are electrically connected to a second power supply line VSSPL, the display device 100 according to one or more embodiments illustrated in Figure 11 is substantially the same as the display device 100 according to one or more embodiments illustrated in Figure 10 , and thus, repeated descriptions will be omitted below.

[0294] According to one or more embodiments, the circuit layer 120 may further include a first power supply ELVDD (see Figure 5 ) and a second power supply ELVSS (see Figure 5 ) that are provided in the non-display region NDA and respectively transmit power for driving the light-emitting element LE (seeFigure 5 ) the first power supply line VDSPL and the second power supply line VSSPL.

[0295] A portion of the second power supply line VSSPL may extend parallel to the second side SD2 of the relatively adjacent hole region HLA.

[0296] According to Figure 11 one or more embodiments, one or more first dummy additional lines DMADL1 and one or more second dummy additional lines DMADL2 may be electrically connected to the second power supply line VSSPL.

[0297] Additionally, according to Figure 11 an embodiment, one or more fourth dummy additional lines DMADL4 may also be electrically connected to the second power supply line VSSPL.

[0298] As an example, when the first power supply line VDSPL is disposed between the display region DA and the second power supply line VSSPL and the first power supply line VDSPL and the second power supply line VSSPL are disposed at the same conductive layer, as Figure 11 and Figure 12 illustrated, each of one or more first dummy additional lines DMADL1, one or more second dummy additional lines DMADL2, and one or more fourth dummy additional lines DMADL4 may be electrically connected to the second power supply line VSSPL through a power supply auxiliary connection line VACL.

[0299] As Figure 12 illustrated, the power supply auxiliary connection line VACL may be disposed at a third gate conductive layer (the third gate conductive layer is disposed on the third gate insulating layer 125).

[0300] However, this is only an example, and the power supply auxiliary connection line VACL may be disposed at at least one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer.

[0301] Each of the fourth dummy additional line DMADL4 and the second power supply line VSSPL may be electrically connected to the power supply auxiliary connection line VACL through a connection hole penetrating the first planarization layer 127 and the second interlayer insulating layer 126.

[0302] The fourth dummy additional line DMADL4 may be electrically connected to each of the second dummy bridge line DMBRL2 and the fourth dummy bridge line DMBRL4 intersecting the fourth dummy additional line DMADL4 through a dummy connection hole DMCH penetrating the first planarization layer 127.

[0303] The first dummy additional line DMADL1 can also be electrically connected to each of the first dummy bridging line DMBRL1 and the fourth dummy bridging line DMBRL4 that cross the first dummy additional line DMADL1 through a dummy connection hole DMCH.

[0304] The third dummy additional line DMADL3 can be electrically connected to the first dummy additional line DMADL1 through the first dummy bridging line DMBRL1.

[0305] In one or more embodiments, when another line is different from Figure 11 and Figure 12 and is not disposed between the display area DA and the second power supply line VSSPL as illustrated, one or more first dummy additional lines DMADL1 and one or more second dummy additional lines DMADL2 can extend to the non-display area NDA and can be directly electrically connected to the second power supply line VSSPL.

[0306] Figure 13 is a layout diagram of part D of Figure 7 illustrated according to one or more embodiments.

[0307] Except that one or more first dummy additional lines DMADL1 and one or more second dummy additional lines DMADL2 are electrically connected to the first power supply line VDSPL, the display device 100 according to one or more embodiments illustrated in Figure 13 is substantially the same as the display device 100 according to one or more embodiments illustrated in Figure 10 and thus, repeated descriptions will be omitted hereinafter.

[0308] According to Figure 13 one or more embodiments, a part of the first power supply line VDSPL can extend in parallel with the second side SD2 of the relatively adjacent hole area HLA.

[0309] According to Figure 13 one or more embodiments, one or more first dummy additional lines DMADL1 and one or more second dummy additional lines DMADL2 can extend to the non-display area NDA and can be electrically connected to the first power supply line VDSPL.

[0310] In addition, according to Figure 13 one or more embodiments, one or more fourth dummy additional lines DMADL4 can also extend to the non-display area NDA and be electrically connected to the first power supply line VDSPL.

[0311] Figure 14 is a layout diagram of part D of Figure 7 illustrated according to one or more embodiments.

[0312] Except that one or more first dummy additional lines DMADL1 and one or more second dummy additional lines DMADL2 are electrically connected to a constant voltage supply line CVSPL, the display device 100 according to Figure 14 one or more embodiments illustrated therein is substantially the same as the display device 100 according to Figure 10 one or more embodiments illustrated therein, and thus, a repetitive description will be omitted hereinafter.

[0313] According to Figure 14 an embodiment of, a circuit layer 120 may further include a first power supply line VDSPL and a second power supply line VSSPL that are disposed in a non-display area NDA and respectively transmit a first power supply ELVDD (see Figure 5 ) for driving a light-emitting element LE (see Figure 5 ) and a second power supply ELVSS (see Figure 5 ), and a constant voltage supply line CVSPL that transmits a constant voltage having a voltage level different from the voltage levels of the first power supply ELVDD and the second power supply ELVSS.

[0314] The constant voltage supply line CVSPL may transmit one of a first initialization voltage VINT (see Figure 5 ), a second initialization voltage VAINT (see Figure 5 ), and a bias voltage VBS (see Figure 5 ).

[0315] However, this is only an example, and the constant voltage supply line CVSPL may also transmit a constant voltage having a voltage level different from the voltage levels of the first initialization voltage VINT (see Figure 5 ), the second initialization voltage VAINT (see Figure 5 ), the bias voltage VBS (see Figure 5 ), and the first power supply ELVDD and the second power supply ELVSS.

[0316] As an example, when the first power supply line VDSPL is disposed between a display area DA and the constant voltage supply line CVSPL and the first power supply line VDSPL and the constant voltage supply line CVSPL are disposed in the same conductive layer, as illustrated in Figure 14 , each of one or more first dummy additional lines DMADL1, one or more second dummy additional lines DMADL2, and one or more fourth dummy additional lines DMADL4 may be electrically connected to the constant voltage supply line CVSPL through a constant voltage auxiliary connection line CACL.

[0317] Alternatively, when another line is different from Figure 14When not disposed between the display area DA and the constant voltage supply line CVSPL as illustrated, one or more first dummy additional lines DMADL1 and one or more second dummy additional lines DMADL2 may extend into the non-display area NDA and may be directly electrically connected to the constant voltage supply line CVSPL.

[0318] Figure 15 is a layout diagram of part D of Figure 7 illustrated according to one or more embodiments.

[0319] Except that some of the power supply auxiliary additional lines VAADL among the power supply auxiliary additional lines VAADL are electrically connected to the second power supply line VSSPL and other power supply auxiliary additional lines VAADL among the power supply auxiliary additional lines VAADL are electrically connected to the constant voltage supply line CVSPL, the display device 100 according to Figure 15 the one or more embodiments illustrated in Figure 14 is substantially the same as the display device 100 according to

[0320] the one or more embodiments illustrated in Figure 15 According to one or more embodiments of Figure 7 ), some of the additional lines ADL disposed between one or more first dummy additional lines DMADL1 and the third side SD3 (see Figure 7 ) may be electrically connected to the second power supply line VSSPL, and other additional lines ADL disposed between one or more first dummy additional lines DMADL1 and the third side SD3 (see Figure 7 ) may be electrically connected to the constant voltage supply line CVSPL.

[0321] In addition, some of the additional lines ADL disposed between one or more second dummy additional lines DMADL2 and the fourth side SD4 (see Figure 7 ) may be electrically connected to the second power supply line VSSPL, and other additional lines ADL disposed between one or more second dummy additional lines DMADL2 and the fourth side SD4 (see Figure 7 ) may be electrically connected to the constant voltage supply line CVSPL.

[0322] In this way, the constant voltage of the constant voltage supply line CVSPL can be supplied to the display area DA by other power supply auxiliary additional lines VAADL among the power supply auxiliary additional lines VAADL, except for some power supply auxiliary additional lines VAADL that transmit the second power supply ELVSS, through lines having a grid shape.

[0323] Figure 16is a layout diagram of part D according to one or more embodiments Figure 7 of the display device 100.

[0324] Except that a part of the hole bypass area HBA overlaps with the display area DA and other parts of the hole bypass area HBA overlap with the non-display area NDA, the first bridging auxiliary line BRAL1, rather than at least one second hole bypass bridging line HBBRL2, is electrically connected between the first hole bypass additional line HBADL1 and the second divided line part DVL2_HCRDL1 of the first hole cross data line HCRDL1, and the second bridging auxiliary line BRAL2, rather than at least one fourth hole bypass bridging line HBBRL4, is electrically connected between the second hole bypass additional line HBADL2 and the second divided line part DVL2_HCRDL2 of the second hole cross data line HCRDL2, the display device 100 according to one or more embodiments illustrated in Figure 16 is substantially the same as the display device 100 according to one or more embodiments illustrated in Figure 11 and thus, the repeated description will be omitted hereinafter.

[0325] According to Figure 16 the embodiment, the circuit layer 120 may further include a first bridging auxiliary line BRAL1 and a second bridging auxiliary line BRAL2 that are disposed in the non-display area NDA and extend in the first direction DR1.

[0326] The first auxiliary bridging line BRAL1 and the second auxiliary bridging line BRAL2 may be disposed between the second power supply line VSSPL and the edge of the substrate 110. However, this is only an example, and the first auxiliary bridging line BRAL1 and the second auxiliary bridging line BRAL2 may also be disposed adjacent to the second side SD2 of the display area DA.

[0327] According to Figure 16 one or more embodiments, the circuit layer 120 may further include a first bypass auxiliary line BASL1 electrically connected between the first bridging auxiliary line BRAL1 and the first hole bypass additional line HBADL1, a second bypass auxiliary line BASL2 electrically connected between the first bridging auxiliary line BRAL1 and the second divided line part DVL2_HCRDL1 of the first hole cross data line HCRDL1, a third bypass auxiliary line BASL3 electrically connected between the second bridging auxiliary line BRAL2 and the second hole bypass additional line HBADL2, and a fourth bypass auxiliary line BASL4 electrically connected between the second bridging auxiliary line BRAL2 and the second divided line part DVL2_HCRDL2 of the second hole cross data line HCRDL2.

[0328] Each of the first bypass auxiliary line BASL1, the second bypass auxiliary line BASL2, the third bypass auxiliary line BASL3, and the fourth bypass auxiliary line BASL4 may extend in the second direction DR2.

[0329] As Figure 16 As illustrated therein, when the first power supply line VDSPL and the second power supply line VSSPL are sequentially arranged in parallel with the second side SD2, each of the first bypass auxiliary line BASL1, the second bypass auxiliary line BASL2, the third bypass auxiliary line BASL3, and the fourth bypass auxiliary line BASL4 may cross the first power supply line VDSPL and the second power supply line VSSPL.

[0330] The bridge connection lines BRL may be spaced apart from each other at a suitable interval (e.g., a predetermined interval) so that they are arranged one by one at respective emission pixel drivers EPD and DMPD, while the first bridge connection auxiliary line BRAL1 and the second bridge connection auxiliary line BRAL2 provided in the non-display area NDA may be arranged at an interval smaller than the interval of the bridge connection lines BRL. Accordingly, the width of the hole bypass area HBA may be reduced. In addition, in the non-display area NDA, the second hole bypass bridge connection line HBBRL2 and the fourth hole bypass bridge connection line HBBRL4 may be replaced by the first bridge connection auxiliary line BRAL1 and the second bridge connection auxiliary line BRAL2, and thus, an increase in the interval between the second side SD2 and the hole area HLA due to the arrangement of the second hole bypass bridge connection line HBBRL2 and the fourth hole bypass bridge connection line HBBRL4 may be prevented.

[0331] However, the effects, aspects, and features of the present disclosure are not limited to the effects, aspects, and features set forth herein. By referring to the claims, the above and other effects, aspects, and features of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

Claims

1. A display device, comprising: substrate; a circuit layer, on the substrate; as well as A component layer, on the circuit layer, The substrate includes a main area and a hole area, the main area includes a display area where an emission area is arranged and a non-display area around the display area, and the main area is around the hole area. The element layer includes light emitting elements respectively in the emission regions, and The circuit layer comprises: Emission pixel drivers, arranged side by side along a first direction and a second direction crossing the first direction and electrically connected to the light emitting elements respectively; a data line extending in the second direction and configured to supply a data signal to the emission pixel driver; a bridging line extending in the first direction; and an additional line extending in the second direction and adjacent to the data line, The bridge line includes one or more first dummy bridge lines facing the hole area on one side in the second direction and one or more second dummy bridge lines facing the hole area on the other side in the second direction, and The additional lines include one or more first dummy additional lines facing the hole area at one side in the first direction and electrically connected to the one or more first dummy bridge lines and the one or more second dummy bridge lines.

2. The display device according to claim 1, wherein: The additional lines further include one or more second dummy additional lines facing the hole area at the other side in the first direction and electrically connected to the one or more first dummy bridge lines and the one or more second dummy bridge lines.

3. The display device according to claim 2, wherein: A light-transmitting hole passing through the circuit layer and the component layer is in at least a portion in the middle of the hole area, wherein the substrate further comprises a secondary region protruding from one side of the primary region, wherein the main region further includes a hole bypass region around the hole region, wherein the hole bypass region includes a first hole bypass separation region and a second hole bypass separation region adjacent to each other based on a first hole center point extension line intersecting the center point of the hole region and extending in the first direction, and a third hole bypass separation region and a fourth hole bypass separation region adjacent to the first hole bypass separation region and the second hole bypass separation region, respectively, based on a second hole center point extension line intersecting the center point of the hole region and extending in the second direction, The edge of the display area includes a first side extending in the first direction and facing the sub-area in the second direction, and a second side extending in the first direction, opposite to the first side in the second direction and spaced farther from the sub-area than the first side. wherein the data line comprises a hole-crossing data line intersecting the hole area, Each of the hole-crossing data lines includes a first dividing line portion between the first side and the hole area and a second dividing line portion between the hole area and the second side. The hole crossing data line includes a first hole crossing data line facing the extension line of the center point of the second hole on the one side in the first direction, wherein the bridge line further includes a first hole bypass bridge line in the first hole bypass separation region and electrically connected to the first splitting line portion of the first hole crossing data line, and a second hole bypass bridge line in the second hole bypass separation region and electrically connected to the second splitting line portion of the first hole crossing data line, wherein the additional line further includes a first hole bypass additional line in the first hole bypass separation region and the second hole bypass separation region and electrically connected between the first hole bypass bridge line and the second hole bypass bridge line, and The one or more first dummy additional lines are between the first hole bypass additional line and the hole area in the first direction.

4. The display device according to claim 3, wherein: The hole-crossing data line further includes a second hole-crossing data line facing the extension line of the second hole center point on the other side in the first direction, The bridge line further includes a third hole bypass bridge line in the third hole bypass separation area and electrically connected to the first splitting line portion of the second hole crossing data line, and a fourth hole bypass bridge line in the fourth hole bypass separation area and electrically connected to the second splitting line portion of the second hole crossing data line. wherein the additional line further includes a second hole bypass additional line in the third hole bypass separation region and the fourth hole bypass separation region and electrically connected between the third hole bypass bridge line and the fourth hole bypass bridge line, and The one or more second dummy additional lines are between the hole area and the second hole bypass additional line in the first direction.

5. The display device according to claim 4, wherein: The additional lines further include: one or more third dummy additional lines between the first side and the hole area in the second direction and between the one or more first dummy additional lines and the one or more second dummy additional lines in the first direction; and one or more fourth dummy additional lines between the hole area and the second side in the second direction and between the one or more first dummy additional lines and the one or more second dummy additional lines in the first direction, wherein the one or more third dummy additional lines are electrically connected to the one or more first dummy additional lines and the one or more second dummy additional lines through the one or more first dummy bridge lines, and The one or more fourth dummy additional lines are electrically connected to the one or more first dummy additional lines and the one or more second dummy additional lines through the one or more second dummy bridge lines.

6. The display device according to claim 5, wherein: The bridge line further comprises: two or more third dummy bridge lines between the first hole bypass bridge line and the third hole bypass bridge line and between the second hole bypass bridge line and the fourth hole bypass bridge line in the first direction; and one or more fourth dummy bridge lines, between the one or more first dummy bridge lines and the one or more second dummy bridge lines in the second direction and crossing the hole area, wherein the two or more third dummy bridge lines are electrically connected to the one or more first dummy bridge lines and the one or more second dummy bridge lines through the one or more third dummy additional lines and the one or more fourth dummy additional lines, respectively, and The one or more fourth dummy bridge lines are electrically connected to the one or more first dummy additional lines or the one or more second dummy additional lines.

7. The display device according to claim 6, wherein: A portion of the second hole bypass partition area overlaps the display area and the other portion of the second hole bypass partition area overlaps the non-display area, and The circuit layer further includes: a first bridge auxiliary line extending in the first direction in the non-display area and electrically connected between the first hole bypass additional line and the second dividing line portion of the first hole crossing data line.

8. The display device according to claim 7, wherein: A portion of the fourth hole bypass partition area overlaps the display area and the other portion of the fourth hole bypass partition area overlaps the non-display area, and The circuit layer further includes: a second bridge auxiliary line extending in the first direction in the non-display area and electrically connected between the second hole bypass additional line and the second dividing line portion of the second hole crossing data line.

9. The display device according to claim 6, wherein: The circuit layer further includes: a first power line and a second power line, the first power line and the second power line are in the non-display area and are respectively configured to supply a first power source and a second power source to drive the light emitting element, wherein a portion of the second power line extends parallel to the second side, and The one or more first dummy additional lines and the one or more second dummy additional lines are electrically connected to the second power line.

10. The display device according to claim 6, wherein: The circuit layer further includes a first power line and a second power line, the first power line and the second power line are in the non-display area and are respectively configured to supply a first power source and a second power source to drive the light emitting element, Wherein, a portion of the first power line extends parallel to the second side, and The one or more first dummy additional lines and the one or more second dummy additional lines are electrically connected to the first power line.

11. The display device according to claim 6, wherein: The circuit layer further comprises: a first power line and a second power line, the first power line and the second power line being in the non-display area and respectively configured to supply a first power source and a second power source to drive the light emitting element; and a constant voltage supply line configured to supply a constant voltage having a voltage level different from voltage levels of the first power source and the second power source in the non-display area, wherein a portion of the constant voltage supply line extends parallel to the second side, and Wherein, the one or more first dummy additional lines and the one or more second dummy additional lines are electrically connected to the constant voltage supply line.

12. The display device according to claim 11, wherein: One of the light emitting elements is electrically connected between one of the emission pixel drivers and the second power supply, Wherein, the emission pixel driver comprises: a first transistor configured to generate a driving current for driving the light emitting element; a second transistor electrically connected between one of the data lines and the first electrode of the first transistor; a third transistor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; a fourth transistor electrically connected between a first initialization voltage line configured to supply a first initialization voltage and the gate electrode of the first transistor; a fifth transistor electrically connected between a first power line configured to supply the first power source and the first electrode of the first transistor; a sixth transistor electrically connected between the second electrode of the first transistor and the light emitting element; a seventh transistor electrically connected between a second initialization voltage line configured to supply a second initialization voltage and the light emitting element; and an eighth transistor electrically connected between a bias voltage line configured to supply a bias voltage and the first electrode of the first transistor, and The constant voltage supply line is configured to supply one of the first initialization voltage, the second initialization voltage, and the bias voltage.

13. The display device according to claim 6, wherein: The data line further includes a first data line and a second data line spaced farther from the sub-region than the first data line and the sub-region. The bridge line further includes a data bypass bridge line electrically connected to the second data line, and The additional lines further include a data bypass additional line adjacent to the first data line and electrically connected to the data bypass bridge line.

14. The display device according to claim 13, wherein: The circuit layer further includes a data supply line electrically connected between the display driving circuit in the sub-region and the data line, A first data supply line configured to supply a data signal of the first data line among the data supply lines extends to the first data line and is directly electrically connected to the first data line, and A second data supply line configured to supply a data signal of the second data line among the data supply lines extends to the data bypass additional line and is electrically connected to the second data line through the data bypass additional line and the data bypass bridge line.

15. The display device according to claim 13, wherein: The edge of the display area further includes a third side and a fourth side extending in the second direction and opposite to each other in the first direction, wherein the data bypass bridge line is separated from the third side and the fourth side, The bridge line further includes a power auxiliary bridge line between one end of the data bypass bridge line and the third side and between the other end of the data bypass bridge line and the fourth side, and The additional line further includes a power auxiliary additional line between one end of the data bypass additional line and the second side.

16. A display device, comprising: substrate; a circuit layer, on the substrate; as well as A component layer, on the circuit layer, The substrate includes a main area, a hole area, and a sub-area protruding from one side of the main area, the main area includes a display area where an emission area is arranged and a non-display area around the display area, and the main area is around the hole area. The element layer includes light emitting elements respectively located in the emission regions, The circuit layer comprises: Emission pixel drivers, arranged side by side along a first direction and a second direction crossing the first direction and electrically connected to the light emitting elements respectively; a data line extending in the second direction and configured to supply a data signal to the emission pixel driver; a bridging line extending in the first direction; and an additional line extending in the second direction and adjacent to the data line, The main region further includes an aperture bypass region surrounding the aperture region, The data lines include hole-crossing data lines crossing the hole area, Based on a first hole center point extension line that intersects the center point of the hole area and extends in the first direction, each of the hole crossing data lines includes a first segmentation line portion on one side in the second direction and a second segmentation line portion on the other side in the second direction, Based on a second hole center point extension line that intersects the center point of the hole area and extends in the second direction, the hole intersection data line includes a first hole intersection data line on one side of the first direction and a second hole intersection data line on the other side of the first direction, The bridge line comprises: a first hole bypass bridge wire electrically connected to the first split line portion of the first hole crossing data line; a second hole bypass bridge wire electrically connected to the second split line portion of the first hole crossing data line; a third hole bypass bridge wire electrically connected to the first split line portion of the second hole crossing data line; a fourth hole bypass bridge wire electrically connected to the second splitting line portion of the second hole crossing data line; one or more first dummy bridge lines, the one side in the second direction facing the hole area; and one or more second dummy bridge lines, the other side in the second direction facing the hole area, The additional lines include: a first hole bypass additional line electrically connected between the first hole bypass bridge line and the second hole bypass bridge line; a second hole bypass additional line electrically connected between the third hole bypass bridge line and the fourth hole bypass bridge line; one or more first dummy additional lines facing the hole area on the one side in the first direction and electrically connected to the one or more first dummy bridge lines and the one or more second dummy bridge lines; and one or more second dummy additional lines facing the hole area on the other side in the first direction and electrically connected to the one or more first dummy bridge lines and the one or more second dummy bridge lines, and The one or more first dummy bridge lines, the one or more second dummy bridge lines, the one or more first dummy additional lines, and the one or more second dummy additional lines are electrically connected to one another.

17. The display device according to claim 16, wherein: The bridge line further comprises: two or more third dummy bridge lines between the first hole bypass bridge line and the third hole bypass bridge line and between the second hole bypass bridge line and the fourth hole bypass bridge line in the first direction; and one or more fourth dummy bridge lines, between the one or more first dummy bridge lines and the one or more second dummy bridge lines in the second direction and crossing the hole area, Wherein, the additional line further comprises: one or more third dummy additional lines adjacent to one side of the hole area in the second direction and between the one or more first dummy additional lines and the one or more second dummy additional lines in the first direction; and one or more fourth dummy additional lines adjacent to the other side of the hole area in the second direction and between the one or more first dummy additional lines and the one or more second dummy additional lines in the first direction, and The two or more third dummy bridge lines, the one or more fourth dummy bridge lines, the one or more third dummy additional lines and the one or more fourth dummy additional lines are electrically connected to the one or more first dummy bridge lines, the one or more second dummy bridge lines, the one or more first dummy additional lines and the one or more second dummy additional lines.

18. The display device according to claim 17, wherein: The circuit layer further includes a first power line and a second power line, the first power line and the second power line are in the non-display area and are respectively configured to supply a first power source and a second power source to drive the light emitting element, and The one or more first dummy additional lines and the one or more second dummy additional lines are electrically connected to one of the first power line and the second power line.

19. The display device according to claim 17, wherein: The circuit layer further comprises: a first initialization voltage line configured to supply a first initialization voltage to the emission pixel driver; a second initialization voltage line configured to supply a second initialization voltage to the emission pixel driver; a bias voltage line to transmit a bias voltage to the emission pixel driver; and A constant voltage supply line, in the non-display area, wherein the constant voltage supply line is configured to supply one of the first initialization voltage, the second initialization voltage, and the bias voltage, and Wherein, the one or more first dummy additional lines and the one or more second dummy additional lines are electrically connected to the constant voltage supply line.

20. The display device according to claim 17, wherein: A portion of the hole bypass area overlaps the display area and another portion of the hole bypass area overlaps the non-display area, and Wherein, the circuit layer further comprises: a first bridging auxiliary line extending in the first direction in the non-display area and electrically connected between the first hole bypass additional line and the second dividing line portion of the first hole crossing data line; and A second bridging auxiliary line extends in the first direction in the non-display area and is electrically connected between the second hole bypass additional line and the second dividing line portion of the second hole crossing data line.

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