Display panel, preparation method thereof and display device

Abstract

The invention provides a display panel, a preparation method thereof and a display device, and belongs to the technical field of display. The display panel comprises a substrate, a driving layer and a pixel layer which are sequentially stacked, wherein the driving layer comprises a top planarization layer, and the pixel layer comprises a pixel electrode layer and a pixel definition layer which are sequentially stacked on the surface of the top planarization layer; the display panel comprises a plurality of reflection structures, and any reflection structure comprises a reflection substrate which is located on a top planarization layer and is provided with a reflection groove; the electrode unit is arranged on the pixel electrode layer; the electrode unit comprises a climbing part covering the side wall of the reflecting groove and a flat part covering the groove bottom of the reflecting groove; the pixel definition unit is arranged on the pixel definition layer; the pixel defining unit covers the climbing part and exposes at least partial area of the flat part; the thickness of at least one part of the pixel defining unit is gradually reduced in the direction away from the center of the reflecting groove. The display panel can improve the light extraction rate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display panel, a method for manufacturing the same, and a display device. Background Art

[0002] In the field of OLED display technologies, providing a reflective cup can effectively improve the light extraction rate of a display panel.

[0003] It should be noted that the information disclosed in the above Background Art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] The purpose of the present disclosure is to overcome the deficiencies of the above prior art, and to provide a display panel, a method for manufacturing the same, and a display device, so as to improve the light extraction rate of the display panel.

[0005] According to a first aspect of the present disclosure, there is provided a display panel, including a substrate, a driving layer, and a pixel layer stacked in sequence; wherein, the driving layer includes a top planarization layer, and the pixel layer includes a pixel electrode layer and a pixel definition layer stacked in sequence on the surface of the top planarization layer; the display panel includes a plurality of reflection structures, and any one of the reflection structures includes:

[0006] A reflection matrix, located on the top planarization layer and having a reflection groove;

[0007] An electrode unit, disposed on the pixel electrode layer; the electrode unit includes a ramp portion covering the sidewall of the reflection groove and a flat portion covering the bottom of the reflection groove;

[0008] A pixel definition unit, disposed on the pixel definition layer; the pixel definition unit covers the ramp portion and exposes at least a part of the flat portion;

[0009] In a direction away from the center of the reflection groove, the thickness of at least a part of the pixel definition unit gradually decreases.

[0010] According to an embodiment of the present disclosure, the pixel definition unit has a gradient portion on a side of a critical reference plane closer to the substrate; in a direction away from the substrate, the lateral width of the gradient portion gradually decreases;

[0011] The lateral width of the gradient portion refers to the distance between the inner edge and the outer edge of the gradient portion on a first reference plane; both the first reference plane and the critical reference plane are parallel to the substrate; the first reference plane is located between the critical reference plane and the flat portion.

[0012] According to an embodiment of the present disclosure, the distance between the inner edge of the upper surface of the pixel defining unit and the inner edge of the lower surface of the pixel defining unit is a first dimension, and the first dimension is between 1.5 and 2.4 micrometers.

[0013] According to an embodiment of the present disclosure, the thickness of the pixel defining unit at the outer edge P1 is a second dimension, and the second dimension is between 0.8 and 1.2 micrometers;

[0014] The orthographic projection of the outer edge of the pixel defining unit on the substrate coincides with the orthographic projection of the opening edge of the reflection groove on the substrate.

[0015] According to an embodiment of the present disclosure, the distance between the inner edge of the upper surface of the pixel defining unit and the inner edge of the lower surface of the pixel defining unit is a first dimension, and the thickness of the pixel defining unit at the outer edge is a second dimension; the orthographic projection of the outer edge of the pixel defining unit on the substrate coincides with the orthographic projection of the opening edge of the reflection groove on the substrate;

[0016] The first dimension is 1.5 to 2.5 times the second dimension.

[0017] According to an embodiment of the present disclosure, the depth of the reflection groove is between 2.0 and 3.0 micrometers; the component of the distance between the inner edge and the outer edge of the ramp portion in the direction parallel to the substrate is 1.8 to 2.4 times the depth of the reflection groove.

[0018] According to an embodiment of the present disclosure, the thickness of the pixel defining unit at the inner edge of the lower surface is 1.3 to 1.8 times the thickness of the pixel defining unit at the outer edge of the lower surface.

[0019] According to an embodiment of the present disclosure, the slope angle of the upper surface of the pixel defining unit at the inner edge is smaller than the slope angle of the lower surface of the pixel defining unit at the inner edge.

[0020] According to an embodiment of the present disclosure, the slope angle of the upper surface of the pixel defining unit at the inner edge is between 40 and 55°;

[0021] The slope angle of the lower surface of the pixel defining unit at the inner edge is between 55° and 65°;

[0022] The slope angle of the upper surface of the pixel defining unit at the inner edge is at least 5° smaller than the slope angle of the lower surface of the pixel defining unit at the inner edge.

[0023] According to an embodiment of the present disclosure, along the direction away from the center of the reflection groove, the slope angle of the upper surface of the pixel defining unit gradually decreases.

[0024] According to an embodiment of the present disclosure, the pixel defining unit has a gradient portion located on the side of the critical reference plane closer to the substrate;

[0025] The slope angle formed by the lower surface of the gradient portion and the first reference plane is greater than the slope angle formed by the upper surface of the gradient portion and the first reference plane; both the first reference plane and the critical reference plane are parallel to the substrate; the first reference plane is located between the critical reference plane and the flat portion.

[0026] According to a second aspect of the present disclosure, there is provided a display device including the above-mentioned display panel.

[0027] According to a third aspect of the present disclosure, there is provided a method for manufacturing a display panel, including: sequentially forming a driving layer and a pixel layer on one side of a substrate; wherein, the driving layer includes a top planarization layer, and the pixel layer includes a pixel electrode layer and a pixel defining layer sequentially stacked on the surface of the top planarization layer;

[0028] Forming the top planarization layer of the driving layer includes:

[0029] Forming a top planarization layer such that the top planarization layer has a plurality of reflection grooves;

[0030] Forming the pixel electrode layer includes:

[0031] Forming a pixel electrode layer such that the pixel electrode layer includes a plurality of electrode units corresponding to the plurality of reflection grooves one by one, and the electrode unit includes a ramp portion covering the side wall of the corresponding reflection groove and a flat portion covering the bottom of the corresponding reflection groove;

[0032] Forming the pixel defining layer includes:

[0033] Forming the pixel defining layer such that the pixel defining layer includes a plurality of pixel defining units corresponding to the plurality of electrode units one by one, the pixel defining unit covers the ramp portion of the corresponding electrode unit and exposes at least a partial area of the flat portion of the corresponding electrode unit; along the direction away from the center of the corresponding reflection groove, the thickness of at least a part of the pixel defining unit gradually decreases.

[0034] According to an embodiment of the present disclosure, forming the pixel defining layer includes:

[0035] Forming a pixel defining material layer, the pixel defining material layer covering the pixel electrode layer;

[0036] Pattern the pixel defining material layer to form pixel defining precursor units corresponding one-to-one with a plurality of the electrode units, where the pixel defining precursor units cover the ramp portions and partial flat portions of the corresponding electrode units;

[0037] Liquefy at least part of the pixel defining precursor units, and at least part of the material of the pixel defining precursor units deforms into the reflection grooves;

[0038] Cure the deformed pixel defining precursor units to form the pixel defining units.

[0039] According to an embodiment of the present disclosure, the material of the pixel defining precursor units is a positive photoresist;

[0040] Liquefying at least part of the pixel defining precursor units includes: irradiating the pixel defining precursor units with ultraviolet light.

[0041] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Description of the Drawings

[0042] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0043] Figure 1 It is a schematic plan view of a display panel in an embodiment of the present disclosure.

[0044] Figure 2 It is a schematic partial cross-sectional view of a display panel in an embodiment of the present disclosure.

[0045] Figure 3 It is a schematic partial cross-sectional view of a reflection structure in an embodiment of the present disclosure.

[0046] Figure 4 It is a schematic diagram of a principle of increasing the light extraction efficiency of a reflection structure in an embodiment of the present disclosure.

[0047] Figure 5 It is a schematic diagram of a principle of increasing the light extraction efficiency of a reflection structure in an embodiment of the present disclosure.

[0048] Figure 6 It is a schematic diagram of the morphological difference before and after the improvement of the reflection structure.

[0049] Figure 7In an embodiment of the present disclosure, it is a partial cross-sectional view schematic diagram of a reflection structure.

[0050] Figure 8 In an embodiment of the present disclosure, it is a partial cross-sectional view schematic diagram of a reflection structure.

[0051] Figure 9 In an embodiment of the present disclosure, it is a partial cross-sectional view schematic diagram of a reflection structure.

[0052] Figure 10 In an embodiment of the present disclosure, it is a partial cross-sectional view schematic diagram of a pixel definition unit.

[0053] Figure 11 In an embodiment of the present disclosure, it is a schematic diagram of the structure of the first sub-layer forming the top planarization layer.

[0054] Figure 12 In an embodiment of the present disclosure, it is a schematic diagram of the structure of the second sub-layer forming the top planarization layer.

[0055] Figure 13 In an embodiment of the present disclosure, it is a schematic diagram of the structure of forming a pixel electrode layer and a pixel definition material layer.

[0056] Figure 14 In an embodiment of the present disclosure, it is a schematic diagram of the structure of forming a pixel definition unit.

[0057] Figure 15 In an embodiment of the present disclosure, it is a schematic diagram of the structure of forming a support pillar layer. Detailed implementation manners

[0058] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0059] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the accompanying drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0060] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0061] The structure layer A is located on the side of the structure layer B away from the substrate. It can be understood that the structure layer A is formed on the side of the structure layer B away from the substrate. When the structure layer B is a patterned structure, a part of the structure layer A can also be located at the same physical height as the structure layer B or lower than the physical height of the structure layer B, where the substrate is the height reference.

[0062] The present disclosure provides a display panel and a display device applying the display panel. Figure 1 In an embodiment of the present disclosure, it is a schematic plan view of the display panel PNL. Refer to Figure 1 , the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. In the display area AA, the display panel PNL is provided with display units DU arranged in an array, and the display unit DU includes sub-pixels PX and a pixel driving circuit PDC for driving the sub-pixels PX. The display panel PNL does not provide display units DU in the peripheral area BB, or the provided display units DU are not used for displaying images. In Figure 1In the example, the display panel PNL is provided with a plurality of scan lines GL extending in the row direction DH in the display area AA, and each scan line GL is arranged corresponding to each display unit row one by one. The pixel driving circuits PDC of each display unit DU in the display unit row are all electrically connected to the corresponding scan line GL. The display panel PNL is further provided with a plurality of data lines DL extending in the column direction DV in the display area AA, and each data line DL is arranged corresponding to each display unit column one by one. The pixel driving circuits PDC of each display unit DU in the display unit column are all electrically connected to the corresponding data line DL. Thus, the pixel driving circuit PDC of each display unit DU is connected to one scan line GL and one data line DL. When a scan signal is loaded on the scan line GL, the driving voltage loaded on the data line DL can be written into the pixel driving circuit PDC, and then the pixel driving circuit PDC can control the brightness of the sub-pixel PX according to the written driving voltage. It can be understood that in other embodiments of the present disclosure, the arrangement manner of the display unit DU and the connection manner with the data line DL, the scan line GL, etc. can also be different from Figure 1 the example.

[0063] Figure 2 In an embodiment of the present disclosure, it is a partial cross-sectional schematic diagram of the display panel PNL. In Figure 2 the example, the display panel PNL may include a substrate SBT, a driving layer DRL, and a pixel layer PXL stacked in sequence; wherein, sub-pixels PX for display are arranged in the pixel layer PXL, and pixel driving circuits PDC for driving the sub-pixels PX are arranged in the driving layer DRL. Each sub-pixel PX can emit light under the drive of the pixel driving circuit PDC to display an image.

[0064] Optionally, the substrate SBT may be a substrate made of inorganic materials, or may be a substrate made of organic materials; of course, it may also be a composite substrate formed by laminating an inorganic material substrate and an organic material substrate. For example, in some embodiments of the present disclosure, the material of the substrate SBT may be glass materials such as soda-lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the material of the substrate SBT may be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT may also be a flexible substrate, for example, the material of the substrate SBT may be polyimide.

[0065] Optionally, in the driving layer DRL, any pixel driving circuit PDC may include a transistor (such as a thin film transistor) and a storage capacitor. Further, the transistor may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor or a double-gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0066] It is understandable that, among the transistors in the pixel driving circuit, the types of any two transistors may be the same or different. Exemplarily, in some embodiments, in a pixel driving circuit, some transistors may be N-type transistors and some transistors may be P-type transistors. Again exemplarily, in other embodiments, in a pixel driving circuit, the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.

[0067] Optionally, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, a planarization layer PLN, etc., which are stacked between the substrate SBT and the pixel layer PXL. Each thin-film transistor and storage capacitor may be formed by film layers such as the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, and the source-drain metal layer SD. Among them, the positional relationship of each film layer may be determined according to the film layer structure of the thin-film transistor. Further, the semiconductor layer SCL may be used to form the channel region of the transistor, and in necessary cases, partial traces or conductive structures may also be formed by conductorization. The gate layer may be used to form one or more of the gate layer traces such as the scan trace, the reset control trace, and the light-emitting control trace, may also be used to form the gate of the transistor, and may also be used to form part or all of the electrode plates of the storage capacitor. The source-drain metal layer may be used to form the source-drain metal layer traces such as the data trace and the driving power supply voltage trace, and may also be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL may further include other film layers according to needs, for example, may further include a light-shielding layer located between the semiconductor layer SCL and the substrate SBT. According to needs, any one of the above film layers such as the semiconductor layer SCL, the gate layer GT, and the source-drain metal layer SD may also be a multi-layer. For example, the driving layer DRL may include two different semiconductor layers SCL, or include two or three source-drain metal layers SD, or include two or three gate layers GT; correspondingly, the insulating film layers (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) in the driving layer DRL may be adaptively increased or decreased, or new insulating film layers may be added according to needs. Optionally, the driving layer DRL may further include a passivation layer, and the passivation layer may be disposed on the surface of the source-drain metal layer SD away from the substrate SBT to protect the source-drain metal layer SD.

[0068] In one embodiment of the present disclosure, the film layer between the substrate SBT and the first source-drain metal layer SD1 may be regarded as a whole and referred to as the transistor layer TFTL, and the transistor layer TFTL has the semiconductor layer SCL, the gate insulating layer GI, and the gate layer GT required for forming the thin-film transistor. For example, in Figure 2 the example, the transistor layer TFTL includes a first inorganic buffer layer BUFA, a polysilicon semiconductor layer PSCL, a first gate insulating layer GI1, a first gate layer GT1, a second inorganic buffer layer BUFB, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer OSCL, a third gate insulating layer GI3, a third gate layer GT3, and an interlayer dielectric layer ILD, which are sequentially stacked on one side of the substrate SBT. In Figure 2In the example of , the driving layer DRL includes two semiconductor layers SCL (polycrystalline silicon semiconductor layer PSCL and metal oxide semiconductor layer OSCL), three gate insulating layers GI (first gate insulating layer GI1, second gate insulating layer GI2, and third gate insulating layer GI3), three gate layers GT (first gate layer GT1, second gate layer GT2, and third gate layer GT3), two source-drain metal layers SD (first source-drain metal layer SD1 and second source-drain metal layer SD2), and two planarization layers PLN (first planarization layer PLN1 and second planarization layer PLN2). Among them, the polycrystalline silicon semiconductor layer PSCL, the first gate insulating layer GI1, and the first gate layer GT1 can form a low-temperature polycrystalline silicon thin-film transistor, and the second gate layer GT2, the second gate insulating layer GI2, the metal oxide semiconductor layer OSCL, the third gate insulating layer GI3, and the third gate layer GT3 can form a metal oxide thin-film transistor. Thus, the display panel PNL is a display panel adopting LTPO technology. It can be understood that the transistor layer TFTL of the embodiments of the present disclosure is not limited to Figure 2 the structure shown in the example; in some other embodiments of the present disclosure, a transistor layer TFTL with other structures can also be adopted.

[0069] In an embodiment of the present disclosure, the structure between the transistor layer TFTL and the pixel layer PXL can be referred to as a wiring layer MRL. One important function of this wiring layer MRL is to achieve electrical connection between different devices, such as achieving electrical connection between thin-film transistors, storage capacitors, and sub-pixels PX. Optionally, the wiring layer MRL can include one or more wiring unit layers, and each wiring unit layer can include a source-drain metal layer SD and a planarization layer PLN located on the side of the source-drain metal layer SD away from the substrate SBT. It can be understood that in some examples, the wiring unit layer can further include a passivation layer, and the passivation layer can be disposed between the source-drain metal layer SD and the planarization layer PLN to protect the source-drain metal layer SD.

[0070] For example, in Figure 2In the example, the wiring layer MRL includes a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, and a second planarization layer PLN2 that are sequentially stacked on the side of the transistor layer TFTL away from the substrate SBT. Thus, the wiring layer MRL includes two wiring unit layers such as a first wiring unit layer (including the first source-drain metal layer SD1 and the first planarization layer PLN1) and a second wiring unit layer (including the second source-drain metal layer SD2 and the second planarization layer PLN2). When the display panel PNL requires more source-drain metal layers SD, the number of wiring unit layers can be adaptively increased (i.e., the source-drain metal layer SD and the planarization layer PLN are increased synchronously). For example, when the display panel PNL is provided with three source-drain metal layers SD, the wiring layer MRL includes a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, a second planarization layer PLN2, a third source-drain metal layer, and a third planarization layer (the third source-drain metal layer and the third planarization layer serve as the third wiring unit layer) that are sequentially stacked.

[0071] It can be understood that the wiring layer MRL of the embodiment of the present disclosure is not limited to Figure 2 the structure shown in the example; in some other embodiments of the present disclosure, a wiring layer MRL with other structures can also be adopted, such as a wiring layer MRL with one wiring unit layer, a wiring layer MRL with three wiring unit layers, a wiring layer MRL with four wiring unit layers, or a wiring layer MRL with five wiring unit layers.

[0072] In Figure 2 the example, a transistor layer TFTL is provided in the driving layer DRL, so the display panel PNL can be an active-driven display panel. It can be understood that in some other embodiments of the present disclosure, the display panel PNL can also adopt a passive driving technology. For example, only a wiring layer MRL can be provided in the driving layer DRL of the display panel PNL without providing a transistor layer TFTL.

[0073] In the embodiment of the present disclosure, the wiring unit layer in the wiring layer MRL that is farthest from the substrate SBT can be called the top wiring unit layer, the source-drain metal layer SD included in the top wiring unit layer can be called the top source-drain metal layer TSD, and the planarization layer PLN included in the top wiring unit layer can be called the top planarization layer TPLN. Thus, the top source-drain metal layer TSD is the source-drain metal layer SD that is farthest from the substrate SBT among the source-drain metal layers SD of the driving layer DRL; for example, in Figure 2 the example, the top source-drain metal layer TSD is the second source-drain metal layer SD2. The top planarization layer TPLN is the planarization layer PLN that is farthest from the substrate SBT among the planarization layers PLN of the driving layer DRL; for example, in Figure 2In the example, the top planarization layer TPLN is the second planarization layer PLN2.

[0074] In an embodiment of the present disclosure, referring to Figure 2 , the sub-pixels in the pixel layer PXL are thin-film light-emitting elements, which may include two electrodes arranged in a stacked manner and a light-emitting functional unit sandwiched between the two electrodes. In Figure 2 's example, the pixel layer PXL may include a pixel electrode layer PEL, a pixel definition layer PDL, a light-emitting functional layer EFL, and a common electrode layer COML arranged in a stacked manner in sequence. Among them, the pixel electrode layer PEL has a plurality of pixel electrodes in the display area of the display panel. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes one by one, and any one pixel opening exposes at least a partial area of the corresponding pixel electrode. For example, the pixel definition layer PDL exposes at least a partial internal area of the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode (the area directly connected to the light-emitting functional layer EFL), and further define the light-emitting area and light-emitting area of the sub-pixel PX. The light-emitting functional layer EFL at least covers the pixel electrode exposed by the pixel definition layer PDL. The common electrode layer COML can cover the light-emitting functional layer EFL in the display area. The pixel electrode and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EFL, so that the light-emitting functional layer EFL emits light. The part of the light-emitting functional layer EFL located between the pixel electrode and the common electrode layer COML can be used as the light-emitting functional unit. The pixel electrode, the common electrode layer COML, and the light-emitting functional unit form the sub-pixel PX. Among them, one of the pixel electrode and the common electrode layer COML serves as the anode of the sub-pixel PX, and the other serves as the cathode of the sub-pixel PX.

[0075] In an embodiment of the present disclosure, the display panel further includes a support pillar layer PSL located on the side of the pixel definition layer PDL away from the substrate, and the support pillar layer PSL is used to form a plurality of support pillars to support the precision metal mask plate in the evaporation process. In one example, the support pillar layer and the pixel definition layer PDL can be made of the same material and prepared in the same process. For example, a grayscale mask process can be used for the same organic material layer to simultaneously form the pixel definition layer and the support pillar layer. In another example, after the pixel definition layer is formed, a new organic material layer can be coated and patterned to form each support pillar of the support pillar layer; the materials of the pixel definition layer and the support pillar layer can be the same or different.

[0076] In one example, the pixel electrode serves as the anode of the sub-pixel PX, and the common electrode layer COML serves as the cathode of the sub-pixel PX.

[0077] In Figure 2In the example, the sub-pixel PX is an organic light-emitting diode (OLED). It can be understood that in other embodiments of the present disclosure, the sub-pixel can also be other types of light-emitting elements, such as current-driven light-emitting elements like QLED, PLED, Micro LED, Mini LED, etc.

[0078] In one embodiment of the present disclosure, the display panel PNL may further include a thin film encapsulation layer TFE located on the side of the pixel layer PXL away from the substrate SBT. In Figure 2 the example, the thin film encapsulation layer TFE may be disposed on the surface of the pixel layer PXL away from the substrate SBT, and it may include an inorganic encapsulation layer and an organic encapsulation layer stacked alternately. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PXL and causing the materials in the pixel layer PXL to age. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2 stacked in sequence on the side of the pixel layer PXL away from the substrate SBT. Of course, in other embodiments of the present disclosure, the thin film encapsulation layer TFE may also adopt other structures, such as a stacked multi-layer inorganic encapsulation layer.

[0079] In one embodiment of the present disclosure, a touch function layer TSL may be further provided on the side of the thin film encapsulation layer TFE away from the substrate SBT of the display panel PNL, so that the display panel PNL has a touch function.

[0080] In one example, the touch function layer TSL may include two metal layers and an insulating layer sandwiched between the two metal layers. It can be understood that in other embodiments of the present disclosure, the touch function layer TSL may also include more metal layers or fewer metal layers.

[0081] In one embodiment of the present disclosure, refer to Figure 2, the display panel PNL may further include a color filter layer CFL located on the side of the touch function layer TSL away from the substrate SBT. The color filter layer CFL has color filter units corresponding to the sub-pixels PX. For example, a red color filter unit is disposed above the red sub-pixel, a green color filter unit is disposed above the green sub-pixel, and a blue color filter unit is disposed above the blue sub-pixel. In this way, the light-emitting color purity of the display panel PNL can be improved, which is beneficial to improving the color gamut of the display panel PNL, and the interference of ambient light on normal display can also be reduced. In one example, the color filter layer CFL further has a black matrix, which can be located between the sub-pixels PX to reduce light-emitting crosstalk and further reduce the reflection of ambient light.

[0082] Due to reasons such as process and materials, the lifespan of the blue sub-pixel is often shorter than that of the red and green sub-pixels. By optimizing the display panel, the embodiments of the present disclosure can improve the light-emitting efficiency of the blue sub-pixel, which is beneficial to improving the lifespan of the blue sub-pixel and the brightness and lifespan of the entire display panel.

[0083] In the embodiments of the present disclosure, refer to Figure 2 and Figure 3 , the display panel PNL is provided with at least one reflection structure RS to improve the light-emitting efficiency of the display panel PNL. Refer to Figure 2 and Figure 3 , the reflection structure RS includes a reflection matrix RB located in the top planarization layer TPLN, an electrode unit PEU located in the pixel electrode layer PEL, and a pixel definition unit PDU located in the pixel definition layer PDL. The reflection matrix RB has a reflection groove GV, the opening direction of the reflection groove GV faces away from the substrate SBT, and the lateral dimension (the dimension along the direction parallel to the substrate SBT) of the notch of the reflection groove GV is larger than the lateral dimension (the dimension along the direction parallel to the substrate SBT) of the bottom of the groove. The electrode unit PEU covers the reflection groove GV, and includes a ramp portion PEB covering the side wall of the reflection groove GV and a flat portion PEA covering the bottom of the reflection groove GV. The pixel definition unit PDU covers the ramp portion PEB and exposes at least a partial area of the flat portion PEA.

[0084] In this embodiment, the electrode unit PEU is a part of the pixel electrode PE. Refer to Figure 3, the pixel electrode PE further includes a connection portion PEC, which is used to be electrically connected to the top source-drain metal layer TSD through a via hole and is electrically connected to the electrode unit PEU. In a further example, the connection portion PEC may include a surrounding portion surrounding the electrode unit PEU and a lead portion electrically connected to the top source-drain metal layer TSD through a via hole, and the surrounding portion is electrically connected to the lead portion. In this way, the pixel driving circuit PDC can load the driving current to the electrode unit PEU of the pixel electrode PE through the connection portion PEC, and then drive the sub-pixel PX to emit light.

[0085] In this embodiment, a part of the flat portion PEA is covered by the pixel defining unit PDU and a part is exposed by the pixel defining unit PDU. For example, refer to Figure 7 , the flat portion PEA includes a covered sub-portion PEA1 covered by the pixel defining unit PDU and an exposed sub-portion PEA2 exposed by the pixel defining unit PDU. The exposed sub-portion PEA2 can be in direct contact with the light-emitting functional layer EFL, and this part of the region can be used as the effective region of the pixel electrode PE. The effective region of the pixel electrode PE is located at the bottom of the reflection groove GV and has high flatness. The part of the pixel electrode PE other than the exposed sub-portion PEA2 can be covered by the pixel defining layer PDL and cannot be in direct contact with the light-emitting functional layer EFL. When the pixel driving circuit PDC loads a driving current to the pixel electrode PE, the driving current can flow through the exposed sub-portion PEA2 through the light-emitting functional layer EFL and flow into the common electrode layer COML, and then the part of the light-emitting functional layer EFL in direct contact with the exposed sub-portion PEA2 emits light. In other words, the sub-pixel PX is located in the reflection groove GV and is disposed at the bottom of the reflection groove GV.

[0086] Refer to Figure 4, when the sub-pixel PX emits light, specifically, when the portion of the light-emitting functional layer EFL that is in direct contact with the exposed sub-portion PEA2 emits light, part of the light of the sub-pixel PX can irradiate the reflection structure RS and be reflected by the reflection structure RS. For example, if the light emitted by the sub-pixel PX irradiates in the direction of the substrate SBT, the light can be reflected by the flat portion PEA to a direction away from the substrate SBT. If the light emitted by the sub-pixel PX is large-angle light (at a large angle with the normal direction of the substrate SBT, for example, at 80° - 90°), part or all of these large-angle lights can irradiate the ramp portion PEB and the pixel defining unit PDU covering the ramp portion PEB, and then be reflected by the ramp portion PEB and the pixel defining unit PDU to form small-angle light. In other words, the top planarization layer TPLN is provided with reflection grooves GV corresponding to the sub-pixels PX one by one. The sub-pixel PX is disposed at the bottom of the reflection groove GV, and the side walls of the reflection groove GV are covered by the pixel electrode PE and the pixel defining layer PDL; the pixel electrode PE and the pixel defining layer PDL covering the reflection groove GV can converge the light emitted by the sub-pixel PX to the light-emitting direction, thereby improving the light extraction rate of the display panel PNL.

[0087] See Figure 4 and Figure 5 , the pixel defining unit PDU has an upper surface TSF and a lower surface DSF that are oppositely arranged; the upper surface TSF of the pixel defining unit PDU is located on the side away from the substrate SBT of the lower surface DSF. In one example, within the reflection structure RS, the lower surface DSF of the pixel defining unit PDU is in contact with the ramp portion PEB, so the lower surface DSF of the pixel defining unit PDU and the upper surface (the surface away from the substrate SBT) of the ramp portion PEB can be substantially coincident. The upper surface TSF of the pixel defining unit PDU can be the side wall of the pixel opening formed by the pixel defining layer PDL at the reflection groove GV.

[0088] In the embodiment of the present disclosure, the thickness of the pixel defining unit PDU can be determined based on the lower surface DSF of the pixel defining unit PDU. For example, the thickness of the pixel defining unit PDU refers to the distance between the first point formed by the thickness reference line intersecting the lower surface DSF of the pixel defining unit PDU and the second point formed by the thickness reference line intersecting the upper surface TSF of the pixel defining unit PDU; wherein, the thickness reference line is the normal line of the lower surface DSF at the first point.

[0089] See Figures 3 to 5, in the display panel PNL provided by the embodiment of the present disclosure, along the direction away from the center of the reflection groove GV, the thickness of at least a part of the pixel definition unit PDU gradually decreases, forming a converging light guide space. For example, the thickness of the pixel definition unit PDU gradually decreases as it moves away from the center of the reflection groove GV. In this way, the light incident on the pixel definition unit PDU will be reflected after irradiating the ramp portion PEB; when the light is reflected to the upper surface TSF of the pixel definition unit PDU, there may be a situation where part of the light is reflected back into the pixel definition unit PDU, that is, part of the light exits from the upper surface TSF and part is reflected back into the pixel definition unit PDU by the upper surface TSF. Since the thickness of the pixel definition unit PDU gradually decreases, the length of the reflection path of the light during multiple reflections in the pixel definition unit PDU decreases in sequence; this enables the light that fails to exit from the pixel definition unit PDU to be directed towards the upper surface TSF of the pixel definition unit PDU more times, thereby increasing the total light extraction rate of the light in the pixel definition unit PDU.

[0090] Figure 6 is a schematic structural diagram of a reflection structure in the related art. In Figure 6 example, the pixel definition layer PDL0 represents the pixel definition layer in the related art; the pixel definition unit PDU0 represents the pixel definition unit in the related art; the upper surface TSF0 represents the upper surface of the pixel definition unit in the related art; the lower surface DSF0 represents the lower surface DSF of the pixel definition unit in the related art. In this Figure 6 example, the upper surface TSF of the pixel definition unit PDU provided by the embodiment of the present disclosure is also represented by a dashed line. Refer to Figure 6 , in the related art, the upper surface TSF0 of the pixel definition unit PDU0 is substantially parallel to the lower surface DSF0, and the pixel definition unit PDU0 is provided with a uniform thickness. Therefore, compared with Figure 5 the same incident light ray in, the total number of reflections that can be performed by the incident light ray in the pixel definition unit PDU0 during reflection is relatively small, and the light extraction rate in the pixel definition unit PDU0 is lower than that of the pixel definition unit PDU of the embodiment of the present disclosure.

[0091] In an embodiment of the present disclosure, the display panel PNL provided by the present disclosure can be prepared by the following preparation method. Refer to Figures 11 to 15 , a driving layer DRL and a pixel layer PXL are sequentially formed on one side of the substrate SBT; wherein, the driving layer DRL includes a top planarization layer TPLN, and the pixel layer PXL includes a pixel electrode layer PEL and a pixel definition layer PDL sequentially stacked on the surface of the top planarization layer TPLN.

[0092] Forming the top planarization layer TPLN of the driving layer DRL includes: Refer to Figure 11 andFigure 12 , a top planarization layer TPLN is formed such that the top planarization layer TPLN has a plurality of reflection grooves GV;

[0093] Forming the pixel electrode layer PEL includes: Refer to Figure 13 , a pixel electrode layer PEL is formed such that the pixel electrode layer PEL includes a plurality of electrode units PEU corresponding one-to-one to the plurality of reflection grooves GV, and the electrode unit PEU includes a ramp portion PEB covering the sidewall of the corresponding reflection groove GV and a flat portion PEA covering the bottom of the corresponding reflection groove GV;

[0094] Forming the pixel definition layer PDL includes: Refer to Figures 13 to 15 , a pixel definition layer PDL is formed such that the pixel definition layer PDL includes a plurality of pixel definition units PDU corresponding one-to-one to the plurality of electrode units PEU, the pixel definition unit PDU covers the ramp portion PEB of the corresponding electrode unit PEU and exposes at least a partial area of the flat portion PEA of the corresponding electrode unit PEU; in a direction away from the center of the corresponding reflection groove GV, the thickness of at least a part of the pixel definition unit PDU gradually decreases.

[0095] As follows, with reference to the accompanying drawings, the structure of the display panel PNL according to the embodiments of the present disclosure and its manufacturing method will be further explained and described.

[0096] Figure 7 In an embodiment of the present disclosure, it is a partial structural schematic diagram of the display panel PNL at the reflection structure RS. In Figure 7In the example, the top planarization layer TPLN includes two sub-layers, namely, the first sub-layer TPLN1 of the top planarization layer and the second sub-layer TPLN2 of the top planarization layer, which are sequentially arranged on the side of the top source-drain metal layer TSD away from the substrate SBT; the top planarization layer TPLN may have a connection via CNT that penetrates the first sub-layer TPLN1 and the second sub-layer TPLN2 of the top planarization layer, and the top source-drain metal layer TSD is provided with a transfer pad, and at least a part of the transfer pad is exposed by the connection via CNT. Thus, when preparing the pixel electrode PE, the pixel electrode PE can be electrically connected to the transfer pad through the connection via CNT. Further, the transfer pad can be used as the output terminal of the pixel driving circuit PDC, which enables the driving current provided by the pixel driving circuit PDC to be loaded onto the pixel electrode PE. The top planarization layer TPLN also has a reflection groove GV, wherein the reflection groove GV penetrates the second sub-layer TPLN2 of the top planarization layer and exposes the first sub-layer TPLN1 of the top planarization layer. Thus, the first sub-layer TPLN1 of the top planarization layer provides a flat groove bottom for the reflection groove GV, thereby ensuring the flatness of the flat portion PEA, and further facilitating the improvement of the light emission uniformity of the display panel PNL. The second sub-layer TPLN2 of the top planarization layer forms the side wall of the reflection groove GV, thereby providing support for the morphology of the ramp portion PEB and the pixel definition unit PDU. In this embodiment, the reflection structure RS may include a first reflection matrix RB1 formed by the first sub-layer TPLN1 of the top planarization layer and a second reflection matrix RB2 formed by the second sub-layer TPLN2 of the top planarization layer.

[0097] In Figure 7 the example, the driving layer DRL includes a first planarization layer PLN1 and a second planarization layer PLN2. The second planarization layer PLN2 serves as the top planarization layer TPLN, and the second source-drain metal layer SD2 serves as the top source-drain metal layer TSD. Among them, the second planarization layer PLN2 includes the first sub-layer PLN21 of the second planarization layer that serves as the first sub-layer TPLN1 of the top planarization layer, and the second sub-layer PLN22 of the second planarization layer that includes the second sub-layer TPLN2 of the top planarization layer.

[0098] Taking Figure 11 and Figure 12 the preparation process shown as an example, when preparing the top planarization layer TPLN, the first sub-layer TPLN1 of the top planarization layer (for example, Figure 11 the first sub-layer PLN21 of the second planarization layer in Figure 11 ) can be formed after forming the top source-drain metal layer TSD (for example, Figure 12, after forming the first sub-layer TPLN1 of the top planarization layer (for example Figure 11 the first sub-layer PLN21 of the second planarization layer in Figure 12 ), the second sub-layer TPLN2 of the top planarization layer can be formed on the side of the first sub-layer TPLN1 of the top planarization layer away from the substrate SBT (for example Figure 12 the second sub-layer PLN22 of the second planarization layer in

[0099] ). The second sub-layer TPLN2 of the top planarization layer exposes the connection via CNT and further exposes the top source-drain metal layer TSD, so that the pixel electrode PE is electrically connected to the top source-drain metal layer TSD through the connection via CNT. The second sub-layer TPLN2 of the top planarization layer is also provided with a reflection groove GV, and the reflection groove GV penetrates through the second sub-layer TPLN2 of the top planarization layer to expose the first sub-layer TPLN1 of the top planarization layer. In this way, the second sub-layer TPLN2 of the top planarization layer and the first sub-layer TPLN1 of the top planarization layer together form the reflection groove GV. The first sub-layer TPLN1 of the top planarization layer provides a flat groove bottom for the reflection groove GV, and the second sub-layer TPLN2 of the top planarization layer provides side walls for the reflection groove GV. Refer to

[0100] In the drawings and exemplary introductions provided by the embodiments of the present disclosure, the display panel PNL is provided with two planarization layers PLN, and the second planarization layer PLN2 is used as the top planarization layer TPLN to exemplarily introduce the reflection structure RS. It can be understood that in some other embodiments of the present disclosure, the number of planarization layers PLN of the display panel PNL is not limited to two, and the top planarization layer TPLN is not necessarily limited to the second planarization layer PLN2.

[0101] In the accompanying drawings and exemplary introductions provided by the embodiments of the present disclosure, the top planarization layer TPLN includes two sub-film layers, namely, the first sub-layer TPLN1 of the top planarization layer and the second sub-layer TPLN2 of the top planarization layer. The first sub-layer TPLN1 of the top planarization layer provides a flat bottom for the reflective groove GV, and the second sub-layer TPLN2 of the top planarization layer provides the required sidewalls for the reflective groove GV. It can be understood that in some other embodiments of the present disclosure, the top planarization layer TPLN is not limited to two sub-film layers. For example, a single-layer planarization layer can also be used to prepare the reflective groove GV. For example, the top source-drain metal layer TSD can be provided with a barrier pad corresponding one-to-one to the reflective groove GV, and the surface of the barrier pad is flat. When forming the top planarization layer TPLN (single-layer organic layer), the top planarization layer TPLN can form a reflective groove GV exposing a partial area of the barrier pad, and form a connection via CNT exposing the transfer pad; the presence of the barrier pad ensures the flatness of the bottom of the formed reflective groove GV.

[0102] In one embodiment of the present disclosure, referring to Figure 3 and Figure 13 , after forming the top planarization layer TPLN and the reflective groove GV on the top planarization layer TPLN, a pixel electrode layer PEL can be formed on the side of the top planarization layer TPLN away from the substrate SBT. Referring to Figure 3 and Figure 13 , the pixel electrode layer PEL includes pixel electrodes PE corresponding one-to-one to the reflection structure RS (correspondingly, also one-to-one to the sub-pixels PX), and the pixel electrodes PE cover the reflective groove GV and the connection via CNT. In the embodiments of the present disclosure, the part of the pixel electrode PE located at the bottom of the reflective groove GV is called the flat part PEA, and the surface of the flat part PEA is flat and is used to connect with the light-emitting functional layer EFL. The part of the pixel electrode PE covering the sidewall of the reflective groove GV is called the ramp part PEB; along the direction away from the center of the reflective groove GV, the ramp part PEB gradually slopes upward. The remaining part of the pixel electrode PE is called the connection part PEC, and the connection part PEC is connected to the ramp part PEB and is connected to the transfer pad of the top source-drain metal layer TSD through the connection via CNT.

[0103] In the embodiments of the present disclosure, the pixel electrode layer PEL can adopt a material capable of reflecting light, such as a metal material or a reflective sub-layer formed at least containing a metal material. For example, the pixel electrode layer PEL can include a reflective sub-layer and an ITO sub-layer stacked in sequence, and the material of the reflective sub-layer is silver. In this way, the part of the light-emitting functional layer EFL in contact with the flat part PEA can emit light under the control of the pixel driving circuit PDC, and the light emitted by the sub-pixel PX is converged toward the light-emitting side of the display panel PNL through the reflection of the flat part PEA and the ramp part PEB, improving the light-emitting efficiency of the sub-pixel PX.

[0104] In an embodiment of the present disclosure, the following method can be used to prepare the pixel definition layer PDL:

[0105] Refer to Figure 13 , to form a pixel definition material layer PDLX, and the pixel definition material layer PDLX covers the pixel electrode layer PEL;

[0106] Refer to Figure 13 , to pattern the pixel definition material layer PDLX to form pixel definition precursor units PDUX corresponding one-to-one to the plurality of electrode units PEU, and the pixel definition precursor units PDUX cover the ramp portions PEB and partial flat portions PEA of the corresponding electrode units PEU;

[0107] Refer to Figure 14 , to at least partially liquefy the pixel definition precursor units PDUX, and at least part of the material of the pixel definition precursor units PDUX deforms into the reflection groove GV, thereby causing the morphology of the pixel definition precursor units PDUX to change;

[0108] Refer to Figure 14 , to cure the liquefied pixel definition material layer PDLX, so that the pixel definition precursor units PDUX are cured to form the pixel definition units PDU.

[0109] Refer to Figure 15 , in an embodiment of the present disclosure, after forming the pixel definition units PDU, a support pillar layer PSL can be formed on the side of the pixel definition layer PDL away from the substrate SBT. The support pillar layer PSL has support pillars for supporting a precision metal mask. In one example, the material of the support pillar layer PSL is the same as the material of the pixel definition layer PDL. Of course, the material of the support pillar layer PSL can also be different from the material of the pixel definition layer PDL.

[0110] In the above preparation method, the pixel definition material layer PDLX can be patterned by an exposure - development technique to form a pixel definition precursor unit PDUX, and then the pixel definition precursor unit PDUX is made to have fluidity and is shaped during the flow process and then cured to prepare a pixel definition unit PDU. When the pixel definition precursor unit PDUX is flowing and shaping, under the action of internal stress and external gravity, it has a tendency to flow towards the bottom of the reflection groove GV. Thus, during the flow process of the pixel definition precursor unit PDUX, the inner edge P1 of its upper surface TSF will move towards the center of the reflection groove GV, and the slope angle of its upper surface TSF will become smaller. Moreover, during the process of part of the liquefied pixel definition precursor unit PDUX flowing into the reflection groove GV, more material will accumulate at the bottom of the reflection groove GV of the pixel definition precursor unit PDUX and the material at the opening of the reflection groove GV will decrease, resulting in at least a part of the formed pixel definition unit PDU having a gradually changing thickness.

[0111] In one example, the material of the pixel definition material layer PDLX is a positive photoresist; the liquefaction treatment of the pixel definition material layer PDLX includes: irradiating the pixel definition material layer PDLX with ultraviolet light. When the pixel definition precursor unit PDUX is irradiated with ultraviolet light, the groups sensitive to ultraviolet light in the pixel definition precursor unit PDUX can break, resulting in partial destruction of the intermolecular cross - linking of the pixel definition precursor unit PDUX, and the pixel definition precursor unit PDUX has a certain fluidity. The pixel definition precursor unit PDUX forms the morphology of the pixel definition unit PDU of the present disclosure after flowing, and then the shaped pixel definition precursor unit PDUX can be cured by a curing process such as baking to form a pixel definition unit PDU.

[0112] In one example, when the pixel definition precursor unit PDUX flows after liquefaction, the inner edge P1 of the upper surface TSF moves 0.8 - 1.5 micrometers towards the center of the reflection groove GV, for example, it moves 0.8μm, 0.9μm, 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm or 1.5μm.

[0113] In one example, the material used for the pixel definition material layer PDLX may be the same as the material used for the top planarization layer TPLN. In particular, the material used for the pixel definition material layer PDLX is the same as the second sub-layer TPLN2 of the top planarization layer. In this way, during the preparation of the reflective groove GV and the preparation of the pixel definition precursor unit PDUX, similar exposure and development conditions can be used; moreover, the upper surface TSF of the pixel definition precursor unit PDUX and the side wall of the reflective groove GV maintain substantially the same slope. After making the pixel definition precursor unit PDUX fluid and allowing the pixel definition precursor unit PDUX to flow into the reflective groove GV, it can be ensured that the slope angle of the upper surface TSF of the pixel definition unit PDU formed after shaping becomes smaller.

[0114] Figure 7 And Figure 8 is a schematic structural diagram of the reflective structure RS; for clearer display, Figure 7 and Figure 8 show the ideal morphologies of organic film layers such as the reflective groove GV and the pixel definition unit PDU. It can be understood that due to the reasons of the preparation process, the actual morphology of the organic film layer is basically consistent with the trend of the ideal morphology, but it is usually difficult to have obvious turning angles as exemplified in Figure 7 and Figure 8 . Figure 9 and Figure 10 is another partial structural schematic diagram of the pixel definition unit PDU, and the pixel definition unit PDU exemplified by Figure 9 and Figure 10 forms a morphology closer to that of the pixel definition unit PDU in the actual process.

[0115] In an embodiment of the present disclosure, referring to Figure 9 and Figure 10 , the pixel definition unit PDU has a gradient portion PDU1 located on the side of the critical reference plane L0 close to the substrate SBT; along the direction away from the substrate SBT, the lateral width D2 of the gradient portion PDU1 gradually decreases;

[0116] The lateral width D2 of the gradient portion PDU1 refers to the distance between the inner edge and the outer edge of the gradient portion PDU1 on the first reference plane; both the first reference plane and the critical reference plane L0 are parallel to the substrate SBT; the first reference plane is located between the critical reference plane L0 and the plane where the flat portion PEA is located.

[0117] In one example, the slope angle formed by the lower surface DSF of the gradient portion PDU1 and the first reference plane is greater than the slope angle formed by the upper surface TSF of the gradient portion PDU1 and the first reference plane; both the first reference plane and the critical reference plane L0 are parallel to the substrate SBT; the first reference plane is located between the critical reference plane L0 and the plane where the flat portion PEA is located.

[0118] In this way, along the direction away from the substrate SBT, the gradient portion PDU1 forms a gradually converging light guiding channel. The lower surface DSF of this light guiding channel is in contact with the climbing portion PEB and has a high reflectivity; the upper surface TSF of this light guiding channel can emit light or reflect a part of the light; the reflected light continues to be reflected back and forth in the light guiding channel, and a part of the light is emitted each time it reaches the upper surface TSF of the light guiding channel.

[0119] In an embodiment of the present disclosure, the distance between the inner edge P1 of the upper surface TSF (the surface away from the substrate SBT, that is, the surface forming the pixel opening) of the pixel definition unit PDU and the inner edge P2 of the lower surface DSF (the surface close to the substrate SBT, that is, the surface in contact with the climbing portion PEB) of the pixel definition unit PDU is a first dimension X1, and the first dimension X1 is between 1.5 and 2.4 micrometers. In this way, on the one hand, it can ensure that the climbing portion PEB is covered by a sufficiently thick pixel definition unit PDU, avoiding short circuit between the climbing portion PEB and the light-emitting functional layer EFL due to insufficient insulation of the pixel definition unit PDU (this will cause changes in the light-emitting area and light-emitting area of the sub-pixel). On the other hand, this can avoid the size of the flat portion PEA being covered too large (that is, avoiding covering too large an area of the sub-portion PEA1), thereby ensuring that the effective area of the flat portion PEA (that is, covering the sub-portion PEA1) is as large as possible and ensuring the light-emitting area of the sub-pixel.

[0120] In one example, the first dimension X1 is 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm, 2.1μm, 2.2μm, 2.3μm or 2.4μm.

[0121] In an embodiment of the present disclosure, the thickness of the pixel definition unit PDU at the outer edge P4 is a second dimension X2, and the second dimension X2 is between 0.8 and 1.2 micrometers; the positive projection of the outer edge P4 of the pixel definition unit PDU on the substrate SBT coincides with the positive projection of the opening edge of the reflection groove GV on the substrate SBT. Obviously, since the pixel definition precursor unit PDUX flows into the reflection groove GV after liquefaction, the amount of material of the pixel definition unit PDU located at the opening of the reflection groove GV is less than the amount of material of the pixel definition unit PDU located at the bottom of the reflection groove GV, resulting in the thinning of the pixel definition unit PDU at the opening of the reflection groove GV.

[0122] In one example, the second dimension X2 is 0.8 μm, 0.85 μm, 0.9 μm, 0.95 μm, 1 μm, 1.05 μm, 1.1 μm, 1.15 μm or 1.2 μm.

[0123] In an embodiment of the present disclosure, the distance between the inner edge P1 of the upper surface TSF of the pixel definition unit PDU and the inner edge P2 of the lower surface DSF of the pixel definition unit PDU is a first dimension X1, the thickness of the pixel definition unit PDU at the outer edge P4 is a second dimension X2, and the positive projection of the outer edge P4 of the pixel definition unit PDU on the substrate SBT coincides with the positive projection of the opening edge of the reflection groove GV on the substrate SBT. The first dimension X1 is 1.5 to 2.5 times the second dimension X2. In particular, the first dimension X1 is 1.6 to 2.0 times the second dimension X2. When the pixel definition precursor unit PDUX flows after liquefaction, the material of the pixel definition precursor unit PDUX located at the notch of the reflection groove GV flows to the bottom of the reflection groove GV, which makes the first dimension X1 increase and the second dimension X2 decrease, and further makes the upper surface TSF of the pixel definition unit PDU have a smaller slope angle. However, it is necessary to control the flow rate of the pixel definition precursor unit PDUX to avoid too large a flow rate resulting in too small a second dimension X2 and too large a first dimension X1. If the flow rate is too large, the ratio of the corresponding first dimension X1 to the second dimension X2 will be larger, which will cause the pixel definition unit PDU to be too thin at the opening of the reflection groove GV and prone to insulation defects, and the coverage area of the pixel definition unit PDU on the flat part PEA is too large, resulting in insufficient effective area of the flat part PEA. If the flow rate is too small, the ratio of the corresponding first dimension X1 to the second dimension X2 will be smaller, which will reduce the difference in the slope angle between the upper surface TSF of the pixel definition unit PDU and the surface of the climbing part PEB. Along the direction away from the center of the reflection groove GV, the effect of the convergence of the light refraction path caused by the thickness change of the pixel definition unit PDU will be weakened, and thus the light output enhancement effect will be weakened.

[0124] In one example, the first dimension X1 is 1.6 times, 1.65 times, 1.7 times, 1.75 times, 1.8 times, 1.85 times, 1.9 times, 1.95 times, or 2 times the second dimension X2.

[0125] As an example, the first dimension X1 is 1.88 microns and the second dimension X2 is 1.02 microns.

[0126] In one embodiment of the present disclosure, the thickness D1 of the pixel definition unit PDU at the inner edge P2 of the lower surface DSF is 1.3 to 1.8 times the thickness (i.e., the second dimension X2) of the pixel definition unit PDU at the outer edge P4 of the lower surface DSF, such as 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.7 times, or 1.8 times.

[0127] In one embodiment of the present disclosure, the groove depth of the reflection groove GV is the fourth dimension X4; the component of the distance between the inner edge P1 and the outer edge P3 of the upper surface TSF of the pixel definition unit PDU in the direction parallel to the substrate SBT is the third dimension X3. The third dimension X3 is 2.5 to 3.5 times the fourth dimension X4, especially 2.3 to 2.7 times. For example, the third dimension X3 is 2.3 times, 2.35 times, 2.4 times, 2.45 times, 2.5 times, 2.55 times, 2.6 times, 2.65 times, or 2.7 times the fourth dimension X4.

[0128] In one embodiment of the present disclosure, the groove depth of the reflection groove GV is the fourth dimension X4; the component of the distance between the inner edge and the outer edge of the ramp portion PEB in the direction parallel to the substrate SBT is the fifth dimension X5, and the fifth dimension X5 is 1.8 to 2.4 times the fourth dimension X4. Thus, the ramp portion PEB itself has an appropriate slope angle and can cooperate with the upper surface TSF of the pixel definition unit PDU to form a converging light guide channel. Further, the fifth dimension X5 is 1.8 to 2.2 times the fourth dimension X4, such as 1.8 times, 1.85 times, 1.9 times, 1.95 times, 2 times, 2.05 times, 2.1 times, 2.15 times, or 2.2 times.

[0129] In one example, the fourth dimension X4 is between 2.0 μm and 3.0 microns, such as 2 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, 2.5 μm, 2.6 μm, 2.7 μm, 2.8 μm, 2.9 μm, or 3 μm.

[0130] In one example, the fifth dimension X5 is between 2.0 and 3.0 micrometers, for example, between 4.2 μm and 6.2 micrometers, and in particular, it can be between 4.7 μm and 5.7 μm, such as 4.7 μm, 4.8 μm, 4.9 μm, 5 μm, 5.1 μm, 5.2 μm, 5.3 μm, 5.4 μm, 5.5 μm, 5.6 μm or 5.7 μm.

[0131] The embodiments of the present disclosure also detect the effects of the reflection structures before and after improvement. Figure 6 It is a schematic diagram of the morphology of a reflector in the related art. The upper surface TSF0 is the upper surface of the pixel definition unit PDU0 in the related art. Figure 6 The upper surface TSF represented by the dashed line in [Figure] is the upper surface of the pixel definition unit PDU of the embodiment of the present disclosure. In this test, the difference between the display panel before improvement (using the reflection structure in the related art) and the display panel after improvement (using the reflection structure provided by the embodiment of the present disclosure) lies only in the different morphologies of the pixel definition units and the subsequent film layer shape differences caused by the different morphologies (which basically do not affect light output), and the actual light-emitting areas of the sub-pixels of the same color are the same. It is found in the test that the reflection structure after improvement improves the light extraction efficiency of all three types of red, green, and blue sub-pixels, and the improvement in the light extraction efficiency of the blue sub-pixels and the improvement in the white light efficiency are significantly stronger than those in the related art. Specifically, through the improvement of the pixel definition unit, the improvement rate of the light extraction efficiency of the blue sub-pixels provided by the reflection structure of the present disclosure increases from 4.9% (related art) to 6.% (present disclosure), and the improvement amplitude reaches 22%; the improvement rate of the white light efficiency of the reflection structure increases from 4.9% (related art) to 5.6.% (present disclosure), and the improvement amplitude reaches 14%. The improvement of the reflection structure after improvement in the red light efficiency can reach 4.7%, and the improvement in the green light efficiency can reach 4.0%. Thus, compared with the related art, the reflection structure RS of the present disclosure can improve the blue light efficiency and the white light efficiency when applied, which is of great significance for improving the lifespan of blue light devices and the lifespan of the display panel PNL.

[0132] The present disclosure's Figure 13 and Figure 14The preparation process of the example adopts a two-step method to prepare the pixel definition layer PDL, that is, first form the pixel definition precursor unit PDUX, and then shape the pixel definition precursor unit PDUX. It can be understood that in some other embodiments of the present disclosure, the pixel definition layer PDL can also be prepared by a one-step method. For example, when forming the pixel definition material layer PDLX, a material different from the top planarization layer TPLN can be selected, especially a material different from the second sub-layer TPLN2 of the top planarization layer. The side wall of the pattern formed after exposure and development of this material has a smaller slope angle; then the pixel definition unit PDU is directly prepared by exposure and development; in this way, the slope angle of the pixel definition unit PDU can be smaller than the slope angle of the reflection groove GV, so that the pixel definition unit PDU has a light guiding channel with a size convergence along the direction away from the center of the reflection groove GV.

[0133] In one embodiment of the present disclosure, referring to Figure 7 , the slope angle θ1 of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 is smaller than the slope angle θ2 of the lower surface DSF of the pixel definition unit PDU at the inner edge P2. On the one hand, this can ensure that the thickness of the pixel definition unit PDU decreases successively near the center of the reflection groove GV. On the other hand, when light refracts back and forth between the upper surface TSF and the lower surface DSF of the pixel definition unit PDU, the incident angle with the lower surface DSF or the upper surface TSF decreases successively, so that the light is more likely to exit during the back-and-forth refraction process, which is beneficial to improving the light extraction efficiency.

[0134] In one embodiment of the present disclosure, the slope angle θ1 of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 is at least 5° smaller than the slope angle θ2 of the lower surface DSF of the pixel definition unit PDU at the inner edge P2, especially 5° - 20° smaller. For example, the slope angle θ1 of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 is at least 5°, 6°, 7°, 8°, 9°, 10°, 11°, 12°, 13°, 14°, 15°, 16°, 17°, 18°, 19° or 20° smaller than the slope angle θ2 of the lower surface DSF of the pixel definition unit PDU at the inner edge P2.

[0135] In one example, the slope angle of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 is between 40° and 55°. In this way, the overall slope angle of the upper surface TSF of the pixel definition unit PDU is more appropriate, which is beneficial to the preparation of the pixel definition unit PDU. For example, the pixel definition precursor unit PDUX can be prepared first, and then the pixel definition precursor unit PDUX is partially liquefied, so that the pixel definition precursor unit PDUX is shaped under the action of stress and external force to change the morphology of the upper surface TSF, and then solidified into the pixel definition unit PDU; during the shaping process, the slope of the upper surface TSF of the pixel definition precursor unit PDUX decreases, so that the slope angle of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 is between 40° and 55°, especially between 40° and 49°. For example, the slope angle of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 is 40.1°, 40.6°, 41.1°, 41.6°, 42.1°, 42.6°, 43.1°, 43.6°, 44.1°, 44.6°, 45.1°, 45.6°, 46.1°, 46.6°, 47.1°, 47.6° or 48.1°.

[0136] In one example, the slope angle of the lower surface DSF of the pixel definition unit PDU at the inner edge P2 is between 55° and 65°. The lower surface DSF of the pixel definition unit PDU substantially coincides with the upper surface of the climbing portion PEB, and the slope angle at its inner edge can ensure the continuity of the pixel electrode PE. Optionally, the pixel definition precursor unit PDUX can be partially liquefied by a light irradiation method (such as ultraviolet irradiation method), and the second reflection matrix RB2 and the first reflection matrix RB1 are protected by the pixel electrode PE and will not be partially liquefied, so that the slope angle of the side wall of the reflection groove GV can be maintained, and finally the slope angle of the lower surface DSF of the pixel definition unit PDU at the inner edge P2 can be maintained. Further, the slope angle of the lower surface DSF of the pixel definition unit PDU at the inner edge P2 is between 55° and 62°, for example, 55.2°, 55.7°, 56.2°, 56.7°, 57.2°, 57.7°, 58.2°, 58.7°, 59.2°, 59.7°, 60.2°, 60.7°, 61.2°, 61.7° or 62°.

[0137] In an embodiment of the present disclosure, the slope angle of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 is between 40° and 49°; the slope angle of the lower surface DSF of the pixel definition unit PDU at the inner edge P2 is between 55° and 62°; the difference between the slope angle of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 and the slope angle of the lower surface DSF of the pixel definition unit PDU at the inner edge P2 is between 10° and 15°, especially a difference of 13° to 14.5°, for example, a difference of 13°, 13.1°, 13.2°, 13.3°, 13.4°, 13.5°, 13.6°, 13.7°, 13.8°, 13.9°, 14°, 14.1°, 14.2°, 14.3°, 14.4° or 14.5°.

[0138] It can be understood that in some other embodiments of the present disclosure, the slope angles of the upper surface of the pixel definition unit PDU may also be kept substantially the same. For example, after forming the pixel definition material layer PDLX, parameters such as the exposure light intensity, the size of the light-transmitting holes on the mask, or the light transmittance of the light-transmitting holes, etc., can be adjusted during the exposure of the pixel definition material layer PDLX, or the material of the pixel definition layer PDL can be adjusted so that the slope angle of the upper surface of the pixel definition unit PDU formed after exposure is less than the sidewall slope angle of the reflection groove GV formed by the top planarization layer TPLN.

[0139] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A display panel, characterized in that: The display panel comprises a base substrate, a driving layer and a pixel layer which are sequentially stacked; wherein the driving layer comprises a top planarization layer, and the pixel layer comprises a pixel electrode layer and a pixel definition layer which are sequentially stacked on the surface of the top planarization layer; the display panel comprises a plurality of reflective structures, and any one of the reflective structures comprises: A reflective substrate, located on the top planarization layer and having a reflective groove; An electrode unit is arranged on the pixel electrode layer; the electrode unit comprises a climbing portion covering the side wall of the reflection groove and a flat portion covering the groove bottom of the reflection groove; A pixel definition unit is provided in the pixel definition layer; the pixel definition unit covers the climbing portion and exposes at least a part of the flat portion; A thickness of at least a portion of the pixel definition unit gradually decreases in a direction away from a center of the reflection groove.

2. The display panel according to claim 1, characterized in that: The pixel definition unit has a gradient portion located on a side of the critical reference plane close to the substrate; the lateral width of the gradient portion decreases in a direction away from the substrate; The lateral width of the gradient portion refers to the distance between the inner edge and the outer edge of the gradient portion on the first reference plane; the first reference plane and the critical reference plane are both parallel to the substrate; the first reference plane is located between the critical reference plane and the flat portion.

3. The display panel according to claim 1, characterized in that: The distance between the inner edge of the upper surface of the pixel definition unit and the inner edge of the lower surface of the pixel definition unit is a first size, and the first size is between 1.5 and 2.4 microns.

4. The display panel according to claim 1, characterized in that: The thickness of the pixel definition unit at the outer edge P1 is a second size, and the second size is between 0.8 and 1.2 microns; The orthographic projection of the outer edge of the pixel definition unit on the base substrate coincides with the orthographic projection of the opening edge of the reflection groove on the base substrate.

5. The display panel according to claim 1, characterized in that: The distance between the inner edge of the upper surface of the pixel definition unit and the inner edge of the lower surface of the pixel definition unit is a first size, and the thickness of the pixel definition unit at the outer edge is a second size; the orthographic projection of the outer edge of the pixel definition unit on the substrate coincides with the orthographic projection of the opening edge of the reflection groove on the substrate; The first size is 1.5 to 2.5 times the second size.

6. The display panel according to claim 1, characterized in that: The groove depth of the reflective groove is between 2.0 and 3.0 microns; the component of the distance between the inner edge of the climbing portion and the outer edge of the climbing portion in the direction parallel to the base substrate is 1.8 to 2.4 times the groove depth of the reflective groove.

7. The display panel according to claim 1, characterized in that: The thickness of the pixel definition unit at the inner edge of the lower surface is 1.3 to 1.8 times the thickness of the pixel definition unit at the outer edge of the lower surface.

8. The display panel according to any one of claims 1 to 7, characterized in that: The slope angle of the upper surface of the pixel definition unit at the inner edge is smaller than the slope angle of the lower surface of the pixel definition unit at the inner edge.

9. The display panel according to claim 8, characterized in that: The slope angle of the upper surface of the pixel definition unit at the inner edge is between 40° and 55°; The slope angle of the lower surface of the pixel definition unit at the inner edge is between 55° and 65°; The slope angle of the upper surface of the pixel definition unit at the inner edge is at least 5° smaller than the slope angle of the lower surface of the pixel definition unit at the inner edge.

10. The display panel according to any one of claims 1 to 7, characterized in that: Along the direction away from the center of the reflection groove, the slope angle of the upper surface of the pixel definition unit gradually decreases.

11. The display panel according to any one of claims 1 to 7, characterized in that: The pixel definition unit has a gradient portion located on a side of the critical reference plane close to the substrate; The slope angle formed by the lower surface of the gradient portion and the first reference plane is greater than the slope angle formed by the upper surface of the gradient portion and the first reference plane; The first reference plane and the critical reference plane are both parallel to the substrate; The first reference plane is located between the critical reference plane and the flat portion.

12. A display device, characterized in that: A display panel comprising any one of claims 1 to 11.

13. A method for preparing a display panel, characterized in that: include: A driving layer and a pixel layer are sequentially formed on one side of the base substrate; wherein the driving layer includes a top planarization layer, and the pixel layer includes a pixel electrode layer and a pixel definition layer sequentially stacked on the surface of the top planarization layer; The top planarization layer of the driving layer is formed including: forming a top planarization layer so that the top planarization layer has a plurality of reflection grooves; Forming the pixel electrode layer includes: forming a pixel electrode layer, so that the pixel electrode layer includes a plurality of electrode units corresponding to the plurality of reflection grooves one by one, and the electrode units include a climbing portion covering the sidewall of the corresponding reflection groove and a flat portion covering the groove bottom of the corresponding reflection groove; Forming the pixel definition layer includes: The pixel definition layer is formed so that the pixel definition layer includes a plurality of pixel definition units corresponding one by one to the plurality of electrode units, the pixel definition units cover the climbing portion of the corresponding electrode unit and expose at least a portion of the flat portion of the corresponding electrode unit; and the thickness of at least a portion of the pixel definition unit gradually decreases in a direction away from the center of the corresponding reflection groove.

14. The method for preparing a display panel according to claim 13, characterized in that: Forming the pixel definition layer includes: forming a pixel definition material layer, wherein the pixel definition material layer covers the pixel electrode layer; Patterning the pixel definition material layer to form pixel definition precursor units corresponding to the plurality of electrode units one by one, wherein the pixel definition precursor units cover the corresponding climbing portions and part of the flat portions of the electrode units; causing the pixel definition precursor unit to at least partially liquefy, and at least a portion of the material of the pixel definition precursor unit to deform into the reflective groove; The deformed pixel definition precursor unit is solidified to form the pixel definition unit.

15. The method for preparing a display panel according to claim 13, characterized in that: The material of the pixel definition precursor unit is a positive photoresist; At least partially liquefying the pixel definition precursor unit includes: irradiating the pixel definition precursor unit with ultraviolet light.

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