Dynamic random instruction generator based on resource pool

Abstract

The invention discloses a dynamic random instruction generator based on a resource pool, and the generator comprises an instruction model module which is used for carrying out the modeling of instructions at an instruction domain level and an instruction level, and carrying out the sorting and numbering of the instructions; the fetch packet structure generator is used for modeling the instruction on the execution packet level and the fetch packet level and is used for generating a buffer area of the instruction; the resource pool is used for integrating each layer of resources required by instruction execution, the generated instruction must meet the constraint of the resource pool, otherwise, the processor resources required for executing the instruction are insufficient, and the instruction cannot be normally executed; the resource manager is used for predicting each level of resources required by execution of the generated instructions, maintaining a resource pool while generating the instructions, and ensuring that no conflict exists among the generated instructions; and the random number generator is used for generating various random numbers under the constraint of the resource pool according to the input parameters. The device has the advantages of simple structure, simplicity and convenience in operation, wide application range, capability of improving verification efficiency and the like.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of processor design and testing, and particularly refers to a dynamic random instruction generator based on a resource pool. Background Art

[0002] After the designer completes the design, the verifier needs to determine whether the register transfer level (RTL) code conforms to the chip design specifications. These RTL codes are usually referred to as the design under test (DUT). The verifier needs to write test cases, apply these test cases to the DUT through a verification platform, and observe whether the output results are consistent with the expectations. In this verification process, the verifier needs to continuously write and modify test cases to cover more function points to meet the actual test needs.

[0003] For complex designs at the processor level, it is difficult for the test programs written by verifiers to cover all function points, and each modified and written test program needs to be recompiled. Especially for very long instruction word (VLIW) processors with the characteristics of multiple issue and variable number of instructions issued per clock cycle, there are strong instruction dependencies and large data dependencies, making it more difficult to write test cases, resulting in problems such as long verification cycles and low verification efficiency. At the same time, the compiler will perform various optimization processes on programs with the VLIW architecture, making it difficult to write test cases to accurately verify function points such as cross-boundary instruction fetching, compressed instructions, and exceptions of the processor. Summary of the Invention

[0004] The technical problem to be solved by the present invention is: aiming at the technical problems existing in the prior art, the present invention provides a dynamic random instruction generator based on a resource pool, which has a simple structure, is easy to operate, has a wide application range, and can improve verification efficiency.

[0005] To solve the above technical problems, the present invention adopts the following technical solutions: A dynamic random instruction generator based on a resource pool, comprising: An instruction model module, used to model instructions at the instruction domain level and the instruction level, and sort and number the instructions; An instruction fetch packet structure generator, used to model instructions at the execution packet level and the instruction fetch packet level, and is also a buffer for generating instructions; A resource pool, used to integrate resources at each level required for instruction execution. The generated instructions must meet the constraints of the resource pool. Otherwise, the processor resources required to execute the instruction are insufficient, and the instruction cannot be executed normally; A resource manager, which is used to predict the resources at all levels required for the execution of the generated instructions, maintain a resource pool while generating instructions, and ensure that there are no conflicts between the generated instructions; A random number generator, which is used to generate various random numbers according to the input parameters under the constraints of the resource pool.

[0006] As a further improvement of the method of the present invention: in the fetch packet structure generator, there are multiple execution packets in the fetch packet, and each execution packet has more than one instruction. The fetch packet structure generator is used to determine the number of execution packets in the fetch packet and the number of instructions in each execution packet.

[0007] As a further improvement of the method of the present invention: the size of the fetch packet is 256 bits, including a full-word instruction packet or a compressed instruction packet.

[0008] As a further improvement of the method of the present invention: the full-word fetch packet is composed of 8 full-word instructions. The last bit of each full-word instruction is a parallel domain. If the parallel domain is 1, the next instruction and this instruction are in the same execution packet.

[0009] As a further improvement of the method of the present invention: the high 224 bits of the compressed instruction packet are instruction codes, and the low 32 bits are packet header information; the packet header information consists of the following parts: the high 4 bits are a specific sequence, which can be used to determine whether it is a packet header; immediately following are 7 bits indicating whether each 32-bit instruction code in the compressed fetch packet is a full-word instruction or two compressed instructions; the low 14 bits indicate whether the compressed instruction codes at each position are parallel to the next instruction; the remaining bits are decoding information required for the compressed instructions.

[0010] As a further improvement of the method of the present invention: the binary instruction code of each instruction in the instruction model module is divided into different regions according to functions, that is, instruction domains; according to the instruction set, the instruction format corresponding to each instruction is obtained. The instruction format includes the bit widths, value ranges of each instruction domain, and the position information of the instruction domain in the instruction code.

[0011] As a further improvement of the method of the present invention: the instructions are numbered according to a standard, and each number maps to an instruction format; the priorities of the standards are, from high to low, function unit, delay slot, function unit delay, instruction type, whether to use a cross path, instruction format, and first letter.

[0012] As a further improvement of the method of the present invention: The instruction domain hierarchical resources in the resource pool include: the bit width of each instruction domain, the value range, the cross path on both sides of A and B, the usage of the A and B register files, the write data path of each functional unit, and the data path of the memory access instruction; the instruction hierarchical resources include: the bit width of the instruction code, the instruction type, etc.; the execution packet hierarchical resources include the number of multi-cycle NOP instructions, the number of instructions in the current execution packet, the usage of each functional unit, and the number of memory access instructions; the fetch packet hierarchical resources include the packet header information and input parameters.

[0013] As a further improvement of the method of the present invention: In the resource manager, when a certain generated instruction has a register write operation, the elements of the corresponding queue are set according to the execution cycle of the instruction, indicating that the register is written in the corresponding clock cycle, and other instructions generated thereafter will not be able to write to this register in this clock cycle; after generating an execution packet, the heads of all queues are popped, and 0 is pushed into the tails, indicating that one clock cycle has passed.

[0014] As a further improvement of the method of the present invention: After obtaining the fetch packet structure, the random number generator needs to fill the corresponding positions in the fetch packet with random instruction codes that meet the resource pool constraints; if the position in the fetch packet is a whole-word instruction, the corresponding number range of the whole-word instruction is queried, and if it is a compressed instruction, the instruction number range corresponding to the compressed instruction is queried, and compilation information is added. First, the instruction number range corresponding to the whole-word instruction in the instruction model is queried, and then the instruction number range of the memory access instruction is queried. A random number is selected from the intersection of the two numbers as the instruction number of the instruction to be generated; after determining the instruction number, the random number generator generates a random instruction domain and passes it to the instruction model, and the instruction model concatenates each instruction domain according to the instruction format to form a whole-word instruction and fills it into the corresponding position of the fetch packet.

[0015] Compared with the prior art, the advantages of the present invention are as follows: 1. The dynamic random instruction generator based on the resource pool of the present invention has a simple structure, is easy to operate, has a wide range of applications, and can improve the verification efficiency. According to the very long instruction word architecture and the format of the compiler-packaged instructions, the present invention models the instructions in a hierarchical form, dynamically manages the resource pool by predicting the resources required for instruction execution, and finally generates binary test instructions.

[0016] 2. The dynamic random instruction generator based on the resource pool of the present invention starts from the multi-issue structure of the VLIW processor and uses the fetch packet as the basic unit. The generated test program is more in line with the VLIW processor architecture, and solves the technical problems brought by the existing instruction generation technologies that mostly use single instructions as the basic unit to form test programs.

[0017] 3. The dynamic random instruction generator based on a resource pool according to the present invention can directly generate the required binary instructions and can accurately cover certain function points. The present invention solves the technical problem that most of the existing instruction generation technologies generate assembly instructions, which need to be compiled before being input into the RTL design, that is, in the VLIW architecture, the compiler will optimize or adjust the assembly program, and may not cover some function points, such as cross-boundary instruction fetching, compressed instructions, and exceptions.

[0018] 4. The dynamic random instruction generator based on a resource pool according to the present invention adopts a dynamic design concept. The smallest basic unit generated can be directly driven to the design under test, and the constraints can be adjusted again according to the operation results, with stronger flexibility. Most of the existing instruction generation technologies are static, that is, a complete test program is directly generated and then driven to the design under test.

[0019] 5. The dynamic random instruction generator based on a resource pool according to the present invention sorts the instructions according to certain criteria during instruction modeling, so that constraints can be batch-written for a certain type of instruction according to functions, reducing the workload of writing constraints.

[0020] 6. The dynamic random instruction generator based on a resource pool according to the present invention adopts the concept of a resource pool, and the modular structure can be well transplanted to other architectures. Many resources of the processor and their maintenance are usually similar, such as general-purpose registers. Even if the instruction sets are completely different, as long as the processor architectures are similar, the original resource pool can still be used when writing constraints. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the hierarchical structure of instruction modeling in a specific application example of the present invention.

[0022] Figure 2 It is a schematic diagram of the topological structure principle in a specific application example of the present invention.

[0023] Figure 3 It is a schematic diagram of the working process in a specific application example of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present invention will be further described in detail below with reference to the accompanying drawings of the specification and specific embodiments.

[0025] In the following introduction, a VLIW processor is taken as an example for illustration. The core of this VLIW processor mainly consists of an instruction fetch unit, a distribution unit, a decoding unit, two general register files A and B, a control register, and two data paths each containing four functional units. Among them, the data path is the execution part of the instruction. Taking the A side as an example, it includes one general register file, four functional units (L, S, M, D), two paths (LD1 and LD2) for reading the data memory, two paths (ST1 and ST2) for writing to the data memory, and a register cross path (2X). The data path on the B side is basically the same as that on the A side. This VLIW processor is multi-issue, and each functional unit can execute one instruction per clock cycle. There are a total of eight functional units on both the A and B sides. Therefore, this VLIW processor can execute at most eight instructions per clock cycle.

[0026] The VLIW processor is multi-issue, and the characteristics are that the instructions operated by the instruction fetch unit, the distribution unit, and the execution unit are at different levels, namely the instruction fetch packet, the execution packet, and the instruction. As Figure 1 shown, the instructions of the VLIW processor in the present invention are divided into the following levels from bottom to top: the instruction domain level, the instruction level, the execution packet level, and the instruction fetch packet level. Among them, the instruction fetch packet is the format in which the compiler packs instructions, and it consists of the execution packet and other information added by the compiler. The instruction fetch component of the VLIW processor sends instructions into the pipeline in units of instruction fetch packets. The distribution unit issues instructions in units of execution packets. There may be one or more instructions in an execution packet, and the instructions in the same execution packet can be executed in parallel. The instruction code of a single instruction can be divided into different instruction domains according to the function, constituting the instruction domain level. The final test program consists of many instruction fetch packets.

[0027] As Figure 2 shown, the resource pool-based dynamic random instruction generator of the present invention includes: An instruction model module, which is used to model instructions at the instruction domain level and the instruction level, and sort and number the instructions; An instruction fetch packet structure generator, which is used to model instructions at the execution packet level and the instruction fetch packet level, and is also a buffer for generating instructions; A resource pool, which is used to integrate the resources at each level required for instruction execution. The generated instructions must meet the constraints of the resource pool. Otherwise, the processor resources required to execute this instruction are insufficient, and this instruction will not be able to execute normally; A resource manager, which is used to predict the resources at each level required for the execution of the generated instructions, and maintain the resource pool while generating instructions to ensure that there are no conflicts between the generated instructions; A random number generator, which is used to generate various random numbers under the constraints of the resource pool according to the input parameters.

[0028] In a specific application example, there are usually multiple execution packets in the fetch packet structure generator. Each execution packet has one or more instructions. The purpose of the fetch packet structure generator is to determine the number of execution packets in the fetch packet and the number of instructions in each execution packet. Taking the above-mentioned processor as an example, the size of the fetch packet is 256 bits, which may be a whole-word instruction packet (all 32-bit whole-word instructions) or a compressed instruction packet (there are 16-bit compressed instructions). It can be understood that in other examples, the size of the fetch packet is not necessarily 256 bits, and the fetch packet consists of whole-word instructions, compressed instructions, and compilation information. An instruction packet with only whole-word instructions is a whole-word instruction packet, and an instruction packet containing compressed instructions and compilation information is a compressed instruction packet.

[0029] Further, as a preferred embodiment, in this example, the whole-word fetch packet consists of 8 whole-word instructions. The last bit of each whole-word instruction is the parallel domain. If the parallel domain is 1, the next instruction and this instruction are in the same execution packet.

[0030] Further, as a preferred embodiment, in this example, the high 224 bits of the compressed instruction packet are the instruction codes, and the low 32 bits are the packet header information. The packet header information consists of the following parts: the high 4 bits are a specific sequence, which can be used to determine whether it is a packet header; the following 7 bits indicate whether each 32-bit instruction code in the compressed fetch packet is a whole-word instruction or two compressed instructions; the low 14 bits indicate whether the compressed instruction codes at each position are parallel to the next instruction; the remaining bits are the decoding information required for the compressed instructions.

[0031] As can be seen from the above, the structure of the whole-word fetch packet is simple. As long as the positions corresponding to the parallel domains of the 8 instructions in the fetch packet are randomized, a random whole-word fetch packet structure can be obtained. For the compressed instruction packet, the processing of the whole-word instruction part remains unchanged, and the processing of the compressed instructions is achieved by randomly generating the packet header. In the test, in order to obtain a fetch packet with a specific structure, it can be controlled by input parameters.

[0032] Taking the above-mentioned processor as an example, the input parameters include the number of execution packets in the fetch packet, the number of compressed instructions, and whether to cross the boundary. The generated instructions cannot be immediately issued, but are cached in the fetch packet structure generator, and then driven to the design under test after a complete fetch packet is generated.

[0033] In a specific application example, the binary instruction code of each instruction in the instruction model module can be divided into different regions according to functions, namely instruction domains. According to the instruction set, information such as the bit widths, value ranges, and positions of each instruction domain in the instruction code corresponding to each instruction can be obtained, and this information is called the instruction format. Taking a 32-bit ADD instruction as an example, from the high bit to the low bit, it is respectively a 4-bit condition field, a 5-bit destination operand register, a 5-bit source operand 2 register, a 5-bit source operand 1 register, a 1-bit cross-path field, a 10-bit operation code, a 1-bit data path field, and a 1-bit parallel field. The instructions of the VLIW instruction set usually have various formats and complex functions.

[0034] In order to accurately obtain a certain instruction format, as a preferred solution, the present invention further numbers the instructions according to a certain standard, and each number maps to an instruction format. Among them, the sorting standard is to be able to quickly find a certain instruction in the instruction model and facilitate writing constraints. Taking the above-mentioned processor as an example, the priorities of the standards are, from high to low, functional unit, delay slot, functional unit delay, instruction type, whether to use the cross path, instruction format, and first letter.

[0035] In a specific application example, the instruction domain-level resources in the resource pool include: the bit widths, value ranges, cross paths on both sides of A and B, the usage of A and B register files, the write data paths of each functional unit, the data paths of memory access instructions, etc.; the instruction-level resources include: the bit width of the instruction code, the instruction type, etc.; the execution packet-level resources include the number of multi-cycle NOP instructions, the number of instructions in the current execution packet, the usage of each functional unit, the number of memory access instructions, etc.; the fetch packet-level resources include the packet header information, input parameters, etc. Taking the A register file resource at the instruction domain level as an example, there are 32 32-bit registers in the A register file memory, and the CPU only allows one write operation to a certain register per clock cycle. After the start of the execution stage, an instruction can complete the register write operation in at most 10 clock cycles. Therefore, 32 queues with a length of 10 are used to record the write situation of the A register file, where 0 means not written and 1 means written.

[0036] In a specific application example, taking the A register file of the above-mentioned processor as an example, in the resource manager, when a generated instruction has a register write operation, the elements of the corresponding queue are set according to the execution cycle of the instruction, representing that the register is written in the corresponding clock cycle, and other instructions generated thereafter will not be able to write to the register in this clock cycle. After generating an execution packet, the heads of all queues are popped, and 0 is pushed into the tails, indicating that one clock cycle has passed.

[0037] In a specific application example, after the random number generator obtains the fetch packet structure, the random number generator needs to fill random instruction codes at corresponding positions in the fetch packet. Taking filling a whole-word memory access instruction as an example, first query the instruction number range corresponding to the whole-word instruction in the instruction model, then query the instruction number range of the memory access instruction, and select a random number from the intersection of the two numbers as the instruction number of the instruction to be generated. After determining the instruction number, the random number generator generates a random instruction field and passes it to the instruction model. The instruction model concatenates each instruction field according to the instruction format to form a whole-word instruction and fills it into the corresponding position of the fetch packet.

[0038] After adopting the above technical solution of the present invention, the execution process is as Figure 3 shown, including: Step S1: Obtain the hardware information, compiler information, and test requirement information of the design under test.

[0039] Among them, the hardware information includes the architecture and instruction set of the design under test. The compiler information includes the format of the compiler-packaged instructions and the instruction scheduling method. The test requirement information includes the functional points of the design under test.

[0040] Step S2: Generate an instruction model according to the information obtained in Step S1.

[0041] Among them, the levels of the instructions of the present invention include, from bottom to top, the instruction field level, the instruction level, the execution packet level, and the fetch packet level. Among them, the fetch packet is the format of the compiler-packaged instructions; the execution packet is composed of instructions that are executed in parallel by the multi-issue processor every clock cycle; the instruction is a command to perform a certain operation and is the smallest unit for the design under test to run; the instruction is composed of instruction fields, and the instruction field information includes the bit width, fetch range, etc. The instruction model models the instructions at the instruction field level and the instruction level. The specific steps are to extract the instruction fields of all instructions from the instruction set and splice them into different instruction formats according to the binary instruction codes of each instruction. Each instruction format maps to an instruction number. The standard of the instruction number is to facilitate the writing of constraints and the precise search of instructions.

[0042] Step S3: Create resources at each level in the resource pool according to the information obtained in Step S1, and the resources used by the generated instructions cannot exceed the limits of the resource pool.

[0043] Specifically, the content of the resource pool includes but is not limited to the following parts: (1) Instruction field level: the bit width of each instruction field, the fetch range of each instruction field, the usage of a certain register, the usage of a certain data path, the usage of a certain storage area.

[0044] (2) Instruction level: instruction type, instruction code bit width.

[0045] (3) Execution package level: maximum execution package size, maximum number of certain types of instructions, and usage of a certain execution unit.

[0046] (4) Instruction fetch package level: instruction fetch package format, other information added by the compiler, and input parameters.

[0047] Step S4: Generate a random instruction fetch package structure based on the input parameters.

[0048] The present invention determines the structural parameters of the instruction fetch package according to the format of the compiler packing instructions obtained in step S1. A random or specified instruction fetch package structure can be obtained through random or input-specified structural parameters. The structural parameters of the instruction fetch package include, but are not limited to, the instruction fetch package size, instruction fetch package format, and header information added by the compiler.

[0049] Step S5: According to the instruction fetch package structure determined in step S4, obtain an instruction that meets the resource pool constraints and fill it into the instruction fetch package; First, obtain a random or specified instruction number that meets the resource pool requirements and map it to the corresponding instruction format. Then, generate each random instruction field that meets the resource pool constraints. Finally, the instruction model concatenates the instruction fields into a complete instruction code according to the instruction format, and the instruction code is cached at the corresponding position of the instruction fetch package.

[0050] Step S6: Update the resource pool according to the generated instruction.

[0051] After detecting the newly generated instruction in the instruction fetch package, occupy or release the resources in the resource pool according to the information obtained in step 1.

[0052] Step S7: Repeat steps S5 - S6 until the instruction fetch package structure generated in step S4 is filled.

[0053] Step S8: Adjust the input parameters, repeat steps S4 - S7, and continue to generate new instruction fetch packages. After the instruction fetch packages meet the specified quantity requirements, they can be directly driven to the design under test.

[0054] The above is only the preferred embodiment of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, several improvements and refinements made without departing from the principle of the present invention should be regarded as within the protection scope of the present invention.

Claims

1. A dynamic random instruction generator based on a resource pool, characterized in that: include: An instruction model module, used to model instructions at the instruction domain level and instruction level, and to sort and number instructions; The instruction fetch packet structure generator is used to model instructions at the execution packet level and the instruction fetch packet level, and is also a buffer for generating instructions; Resource pool is used to integrate resources at all levels required for instruction execution. The generated instructions must meet the constraints of the resource pool, otherwise the processor resources required to execute the instruction are insufficient and the instruction will not be executed normally. Resource manager, used to predict the various levels of resources required for the execution of generated instructions, maintain resource pools while generating instructions, and ensure that there are no conflicts between generated instructions; The random number generator is used to generate various random numbers under the constraints of the resource pool according to the input parameters.

2. The dynamic random instruction generator based on resource pool according to claim 1, characterized in that: The instruction fetch package in the instruction fetch package structure generator has multiple execution packages, each execution package has more than one instruction, and the instruction fetch package structure generator is used to determine the number of execution packages in the instruction fetch package and the number of instructions in each execution package.

3. The dynamic random instruction generator based on resource pool according to claim 2, characterized in that: The size of the instruction fetch packet is 256 bits, including a whole word instruction packet or a compressed instruction packet.

4. The resource pool-based dynamic random instruction generator according to claim 3, characterized in that: The whole word instruction fetch package is composed of 8 whole word instructions. The last bit of each whole word instruction is a parallel domain. If the parallel domain is 1, the next instruction and the instruction are in the same execution package.

5. The resource pool-based dynamic random instruction generator according to claim 3, characterized in that: The upper 224 bits of the compressed instruction packet are the instruction code, and the lower 32 bits are the header information; the header information is composed of the following parts: the upper 4 bits are a specific sequence, which can be used to determine whether it is a header; the following 7 bits indicate whether each 32-bit instruction code in the compressed instruction packet is a whole word instruction or two compressed instructions; the lower 14 bits indicate whether the compressed instruction code at each position is parallel to the next instruction; the remaining bits are the decoding information required for the compressed instruction.

6. The resource pool-based dynamic random instruction generator according to any one of claims 1 to 5, characterized in that: The binary instruction code of each instruction in the instruction model module is divided into different areas, namely instruction domains, according to functions; the instruction format corresponding to each instruction is obtained according to the instruction set, and the instruction format includes the bit width, value range and position information of each instruction domain in the instruction code.

7. The resource pool-based dynamic random instruction generator according to claim 6, characterized in that: Instructions are numbered according to the standard, and each number maps to an instruction format; the priority according to the standard is from high to low: functional unit, delay slot, functional unit delay, instruction type, whether to use cross-path, instruction format, and first letter.

8. The resource pool-based dynamic random instruction generator according to any one of claims 1 to 5, characterized in that: The instruction domain level resources in the resource pool include: the bit width of each instruction domain, the value range, the cross paths on both sides of AB, the usage of the AB register stack, the write data path of each functional unit, and the memory access instruction data path; the instruction level resources include: the instruction code bit width, the instruction type, etc.; the execution package level resources include the number of multi-cycle NOP instructions, the number of instructions in the current execution package, the usage of each functional unit, and the number of memory access instructions; the instruction package level resources include the packet header information and input parameters.

9. The resource pool-based dynamic random instruction generator according to any one of claims 1 to 5, characterized in that: In the resource manager, when a generated instruction has a register write operation, the element of the corresponding queue is set according to the execution cycle of the instruction, indicating that the register is written in the corresponding clock cycle, and other instructions generated thereafter will not be able to write to the register in this clock cycle; after completing the generation of an execution package, the head of all queues is popped out and 0 is pushed into the tail, indicating that a clock cycle has passed.

10. The resource pool-based dynamic random instruction generator according to any one of claims 1 to 5, characterized in that: After obtaining the instruction fetch package structure, the random number generator needs to fill the corresponding position in the instruction fetch package with a random instruction code that meets the resource pool constraint; first query the instruction number range corresponding to the whole word instruction in the instruction model, and then query the instruction number range of the memory access instruction, and select a random number from the intersection of the two numbers as the instruction number of the instruction to be generated; after determining the instruction number, the random number generator generates a random instruction field and passes it to the instruction model, and the instruction model splices each instruction field according to the instruction format to form a whole word instruction, which is filled in the corresponding position of the instruction fetch package.

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