Two-bus-based data receiving and processing method and system

Abstract

The invention relates to a data receiving and processing method and system based on two buses, and the method comprises the steps: a master device transmits a downlink voltage signal containing data information to a slave device through the two buses, and sets a return code voltage segment for receiving the data of the slave device; the main device converts the received uplink code returning current signal into a code returning voltage signal; the master device converts the code return voltage signal into a code return level signal; and after receiving the return code level signal, the main equipment analyzes an interference signal in the return code level signal, sequentially performs splitting, recombination, screening, calculation and verification processing on the return code level signal with the interference signal, and confirms correct data information contained in the return code level signal. Compared with the prior art, the method has the advantages that the reliability of uplink transmission of two-bus data is realized, the anti-interference capability and the uplink communication transmission quality are improved, and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of two-wire data processing, and in particular to a two-wire data reception and processing method and system. Background Art

[0002] Currently, in the field of fire-fighting electronic product systems, a two-wire communication method is usually used. Two-wire communication refers to a communication method in which there are only two wires on the communication bus and no additional power supply wire is required. All communication slave device nodes obtain power from the communication master device node through these two wires and communicate with the master device node. Different from the differential signal transmission adopted by the CAN and RS485 buses, the two-wire communication usually uses a voltage signal to modulate the downlink data, and the uplink data is modulated by a current signal. This design can meet the requirements of high-power load driving and multi-point (slave device) access to the maximum extent, and greatly expand the application field of two-wire communication. However, this characteristic makes it impossible to apply the differential signal processing and matching resistors in the CAN and RS485 communications in the two-wire system. The current analog signal received by the master device node fluctuates due to factors such as line parasitic capacitance and inductance, field interference, or impedance mismatch. Therefore, the data in the two-wire communication transmission is extremely vulnerable to field interference, affecting the communication transmission quality. Currently, there is no solution to address this problem in the market.

[0003] In the prior art, the master device receives the uplink current analog signal from the slave device, converts it into a voltage signal through a resistor or amplifies it through an amplifier and then accesses a single-chip microcomputer for data analysis and processing, so that the interference information is amplified and retained synchronously, and further leads to communication failure due to data analysis errors.

[0004] After retrieval, Chinese Patent Application Publication No. CN115550117A discloses a signal transmission method and device, storage medium, and electronic device for master-slave devices. The signal transmission method for master-slave devices includes: obtaining host downlink data, where the host downlink data is data that the host device is to transmit to the slave device, and the host device and the slave device are connected through a two-wire bus; performing voltage encoding on the host downlink data to obtain two voltage signals, where there is a differential relationship between the two voltage signals; and respectively transmitting the two voltage signals to the first bus and the second bus included in the two-wire bus to obtain the host downlink signal. This existing patent application only performs differential signal transmission on the downlink signal, and the uplink signal still uses current transmission, and no other processing measures are taken. Therefore, the anti-interference ability of the uplink signal is poor, and the uplink link transmission quality is not high.

[0005] How to improve the anti-interference ability of the uplink link during two-wire communication, thereby improving the communication transmission quality, has become a technical problem to be solved. Summary of the Invention

[0006] An object of the present invention is to provide a data reception and processing method and system based on a two-wire bus to overcome the defects of the above-mentioned existing technologies.

[0007] The object of the present invention can be achieved by the following technical solutions:

[0008] According to one aspect of the present invention, there is provided a data reception and processing method based on a two-wire bus, the method comprising:

[0009] The master device sends a downlink voltage signal containing data information to the slave device through the two-wire bus and sets a return code voltage segment for receiving data from the slave device;

[0010] The master device converts the received uplink return code current signal into a return code voltage signal;

[0011] The master device converts the return code voltage signal into a return code level signal;

[0012] After receiving the return code level signal, the master device analyzes the interference signals in the return code level signal and sequentially performs splitting and recombination processing on the return code level signals with interference signals until all the return code level signals with interference signals are processed;

[0013] Perform calculation, screening, and verification processing on the split and recombined data to confirm the correct data information contained in the return code level signal.

[0014] Preferably, the slave device sends an uplink return code current signal with a standard period T_BIT according to a set baud rate, and the uplink return code current signals of the slave devices in the same system are fixed values;

[0015] Perform serial data encoding on the uplink return code current signal, including 1 Bit start bit and m - 1 Bit data bits.

[0016] Preferably, the process of converting the return code voltage signal into a return code level signal includes:

[0017] The master device pre-obtains the amplitude of the static voltage signal when there is no uplink return code current. The return code voltage signal is superimposed on the static voltage signal after being processed, and the reference value of the hysteresis comparator is calculated according to the static voltage value;

[0018] The master device converts the reference value of the hysteresis comparator into an output threshold to shape and filter out some interference signals, so that the return code voltage signal is converted into a return code level signal.

[0019] Preferably, the determination process of the interference signal includes: after receiving the return code level signal, the master device sequentially judges the edge polarities of each return code level signal and numbers them;

[0020] Segment the level signal according to the edge polarity, divide it into multiple level signal segments, and calculate the corresponding width values;

[0021] When the width value of a certain level signal segment is less than the first threshold of the standard period T_BIT, then determine that this level signal segment is an interference signal, and record the current edge number Number; otherwise it is a normal signal.

[0022] More preferably, the process of splitting the return code level signal with interference signals includes: judging whether the edge corresponding to the signal level segment is the last edge according to the edge number. If so, mark the start number Start = N - 1 of the splitting reference and the end number End = N - 1 of the reference, where N is the number of edge signals in the signal level segment; if not, then sequentially judge whether the maximum Continue signal level segments after the signal level segment are all less than the first threshold of the standard period T_BIT. If so, judge these signal level segments after the signal level segment as interference signals as well, and record the continuous interference signals as the same interference signal for splitting processing, that is, mark the start number Start = Number of the splitting reference and the end number End = Start + Continue.

[0023] More preferably, after splitting the return code level signal with interference signals, the recombination process includes:

[0024] Each interference signal will cause the return code level signal to be recombined into four different level signals. Therefore, divide the start number and end number of the reference into four groups. Group_Start_1 to Group_Start_4 and Group_Stop_1 to Group_Stop_4 correspond to the start numbers and end numbers of the four groups respectively;

[0025] When the first interference signal is determined, the start numbers and end numbers of each group are the same as the start number Start and end number Stop of the reference respectively;

[0026] When a non-first interference signal is determined, the corresponding start number Start and end number Stop of the reference are re-determined and generated on the return code level signal after the previous split and recombination. The start and end numbers of each group are obtained by weighted calculation through the start number Start, end number Stop of the reference and the number Previous_Continue of the previous continuous interference signals. Specifically:

[0027] The calculation method is as follows:

[0028] The starting number of the first group Group_Start_1 = Start - (Previous_Continue + 1), and the ending number Group_Stop_1 = Stop - (Previous_Continue + 1);

[0029] The starting number of the second group Group_Start_2 = Start - (Previous_Continue - 1), and the ending number Group_Stop_2 = Stop - (Previous_Continue - 1);

[0030] The starting number of the third group Group_Start_3 = Start - Previous_Continue, and the ending number Group_Stop_3 = Stop - Previous_Continue;

[0031] The starting number of the fourth group Group_Start_4 = Start - Previous_Continue, and the ending number Group_Stop_4 = Stop - Previous_Continue;

[0032] The number of consecutive interfering signals for update determination Previous_Continue = Continue, which provides a calculation basis for setting the group starting number and group ending number of each group next time.

[0033] More preferably, the recombination process further includes processing each group of level signals respectively, specifically:

[0034] The first group: Delete all edge numbers between the starting number of the first group Group_Start_1 and the ending number of the first group Group_Stop_1;

[0035] The second group deletes all edge numbers between the ending number of the second group Group_Stop_2 - 2 or Group_Stop_2 - 1 and the starting number of the second group Group_Start_2;

[0036] The third group: Delete all edge numbers after the ending number of the third group Group_Stop_3 + 1;

[0037] The fourth group: Delete all edge numbers between the ending number of the fourth group Group_Stop_4 - 2 or Group_Stop_4 - 1 and Group_Start_4 - 1;

[0038] After the above processing, four groups of return code level signals are recombined. For each group of return code level signals, the level width value between the edge polarities corresponding to each adjacent edge number is recalculated and stored in the Array_Regroup array. At the same time, the number of valid values in each row is recorded.

[0039] More preferably, for the return code level signals with interference signals, data calculation and screening are performed on the return code level signals stored in each row of the Array_Regroup array; for normal signals, data calculation and screening are directly performed on the original return code level signals;

[0040] The data calculation and screening include:

[0041] Perform a division operation on the level width value and the standard period T_BIT. The quotient is the number n of T_BITs included. If the relative error between the remainder and the standard period T_BIT is less than the second threshold of the standard period T_BIT, the data is judged invalid; if the relative error between the remainder and the standard period T_BIT is greater than the third threshold of the standard period T_BIT, the data is judged valid, and the count n is incremented by 1; for the remainder between the second threshold and the third threshold of the standard period T_BIT, the data is judged suspected, and it is calibrated as a suspected valid width value, and both the valid and invalid data cases are retained;

[0042] Judge the logic level "0" or "1" represented by the signal level segment through the edge polarity, and store the calculation result in the two-dimensional array Array_Regroup_Calculate. Each row corresponds to an actual m-bit data and the number of valid Bit bits;

[0043] Screen out the data with the number of Bit bits exceeding m. Finally, only m - 1 Bit data bits are retained, which represent the data information contained in the return code level signal, and are stored in the two-dimensional array Array_Regroup_Check_Calculate. One byte of data information of the complete return code data frame is stored in each column, and the number of valid columns represents the number of bytes of the data frame.

[0044] According to another aspect of the present invention, a two-wire based data receiving and processing system is provided. The system is used for the master device and includes a single-chip microcomputer, a first DC power supply, a second DC power supply, and multiple hardware modules. The hardware modules include:

[0045] Output module: Control to output the first DC power supply to the two-wire to supply power to the slave device; at the same time, modulate the bus voltage waveform according to a specific timing for the downlink data through the single-chip microcomputer and transmit the data to the slave device;

[0046] Return code platform module: used for the master device to convert the second DC power source into a specific return code level through design and receive the upstream return code current signal sent by the slave device;

[0047] Return code receiving module: receives the upstream return code current signal from the return code platform module, amplifies, filters, and demodulates the signal and then converts it into a return code voltage signal, and outputs a return code level signal that can be directly processed by the single-chip microcomputer;

[0048] Short-circuit overcurrent protection module: used for the master device to monitor the real-time change of the two-wire line current. When the current exceeds the predetermined value or the line is short-circuited, the output module cuts off the bus output in time through the single-chip microcomputer to protect the hardware circuit of the master device.

[0049] Preferably, the functions of the single-chip microcomputer include:

[0050] Output control: used for the master device to control the output and shutdown of the first DC power source through the first I / O port;

[0051] Return code platform control: used for the master device to control the output and shutdown of the second DC power source through the second I / O port;

[0052] Return code receiving control: receives the return code level signal output by the return code receiving module of the master device, calculates the comparator voltage threshold of the return code receiving module, and uses the comparator voltage threshold as the reference value of the hysteresis comparator of the return code receiving module of the master device;

[0053] Return code data analysis: used for the master device to analyze the real data information contained in the level signal;

[0054] Short-circuit overcurrent protection: used for the master device to analyze the bus short-circuit or overcurrent situation through the current measurement value.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] 1) The present invention discriminates interference signals for the received return code level signal, and performs splitting, recombination, calculation, screening, and verification processing on the return code level signal containing interference signals to confirm the correct data information contained in the return code level signal, improving the anti-interference ability during the data transmission process, thereby enhancing the communication reliability of the two-wire data upstream transmission.

[0057] 2) The present invention sets a return code voltage segment to receive the upstream return code current signal, encodes the upstream return code current signal, and designs the format of serial data, making the data parsing more accurate, overcoming the parsing difficulties caused by distortion, twisting, and signal duration change during the data transmission process, and improving the accuracy of data transmission.

[0058] 3) The present invention pre-acquires the amplitude of the static voltage signal when there is no up-link return code current. The return code voltage signal is processed and superimposed on the static voltage signal, and the reference value of the hysteresis comparator is calculated according to the static voltage value. The master device converts the reference value of the hysteresis comparator into an output threshold to shape and filter out some interference signals, so that the return code voltage signal is accurately converted into a return code level signal, improving the anti-interference ability and the accuracy of data conversion.

[0059] 4) The scheme cost is extremely low: By simplifying the hardware scheme design and using an algorithm that can be executed by an ordinary single-chip microcomputer, the quality improvement of the two-wire communication up-link can be achieved with an extremely low scheme cost. Brief Description of the Drawings

[0060] Figure 1 It is a schematic flow chart of the master device data receiving and processing method in the present invention;

[0061] Figure 2 It is a schematic diagram of the coding structure of the return code current signal in the present invention;

[0062] Figure 3(a) is a schematic diagram of the return code voltage signal and the static voltage signal output by the normal return code hardware processing in the present invention;

[0063] Figure 3(b) is a schematic diagram of the return code level signal output by the normal return code hardware processing in the present invention;

[0064] Figure 4(a) is a schematic diagram of the return code voltage signal and the static voltage signal output by the normal return code hardware processing in the present invention;

[0065] Figure 4(b) is a schematic diagram of the return code level signal output by the normal return code hardware processing in the present invention;

[0066] Figure 5 It is a schematic diagram of the output comparison between the normal return code and the interference return code in the present invention;

[0067] Figure 6 It is a schematic diagram of the software processing process of the interference return code output in the present invention;

[0068] Figure 7 It is a schematic diagram of the structure of the master device data receiving and processing system in the present invention;

[0069] Figure 8 It is a schematic diagram of the master device receiving data analysis and calculation process in the present invention;

[0070] Figure 9 It is a schematic diagram of the static voltage measurement and reference value output process in the present invention. Detailed Embodiment

[0071] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0072] The present invention designs a method and system for receiving and processing two-bus data by combining a hardware circuit and a software algorithm. The embodiments of the present invention provide a simple and efficient communication receiving and processing method. By dynamically adjusting parameters through a hardware circuit in cooperation with a single-chip microcomputer, especially when the data is disturbed and fluctuates, it can restore the real data information as much as possible to ensure the correctness of the data. In addition, the real data is parsed through the algorithm processing of the single-chip microcomputer, ensuring the accuracy of data reception and analysis.

[0073] Embodiment 1

[0074] This embodiment relates to a method for receiving and processing data based on a two-bus, as Figure 1 shown, the method includes the following steps:

[0075] S1. The master device sends a downlink voltage signal containing data information through the two-bus (hereinafter referred to as the bus) and powers the slave device, sets a return code voltage segment to receive data from the slave device, and the slave device uploads data information through an uplink return code current signal to achieve two-way communication between the master and slave devices.

[0076] Further, specifically: the master device receives data from the slave device by designing a specific return code voltage segment (a voltage segment that can be DC12V and below), and the slave device sends an uplink return code current signal with a standard period T BIT at the set baud rate. The uplink return code current signals of the slave devices connected to the same system are fixed values. For example, 40mA represents that the Bit is 0, and 0mA represents that the Bit is 1. The transmission of byte stream data is realized through the combination of logic 0 and 1, that is, the received data is a byte stream composed of a group of current pulse signals, and its data coding is serial data, as Figure 2 shown, including a 1Bit start bit, m (such as 8) Bit data bits, and no stop bit. Within the V 回码 voltage segment, the slave device hardly consumes the current on the bus, and the static current on the bus is relatively stable and less than the return code current of the slave device, enabling the master device to correctly identify the current change.

[0077] S2. The master device receives the uplink return code current signal from the slave device, and converts it into a return code voltage signal V 回码 through amplification, filtering, and demodulation by a return code receiving and processing circuit;

[0078] S3. The single-chip microcomputer pre-obtains the amplitude of the static voltage signal when there is no uplink return code current through ADC analog-to-digital conversion. The return code voltage signal V of S2 回码 After being processed, it is superimposed on the static voltage signal V 静态电平 . The single-chip microcomputer calculates the reference value of the hysteresis comparator according to the static voltage value;

[0079] S4. The single-chip microcomputer dynamically adjusts the circuit parameters through DAC digital-to-analog conversion. It can also use PWM output to control the output of the DAC chip, so that the return code signal is converted into a return code level signal V 高 (0 / 1) that can be directly processed by the single-chip microcomputer;

[0080] S5. After the single-chip microcomputer receives the return code level signal V 高 (0 / 1), it analyzes the interference signals in the return code level signal, and performs algorithm processing such as splitting, recombination, calculation, screening, and verification on the return code level signal with interference signals to confirm the correct data information contained in the return code level signal.

[0081] As shown in FIGS. 3(a), 3(b), 4(a), and 4(b), they are the return code voltage signals V 回码 output by the hardware under normal and interference conditions, the static voltage signal, and the return code level signal respectively. It can be seen that the actual information cannot be confirmed at all under interference. By processing in an amplified manner, it is obviously impossible to obtain the true data information. In this application, through the combined processing of software and hardware, the output signal basically maintains the original data information, such as Figure 5 . At the same time, there is a deviation in the timing of the output signal compared to the standard period T BIT . Using ordinary methods for processing may lead to incorrect reception and judgment. It is necessary to process through the method of this application to confirm the actual information and ensure the accuracy of the data. FIGS. 4(a) and 4(b) are only examples under the interference condition. In actual applications, there are various uncertain forms of interference situations, but all can be effectively solved through this method.

[0082] Figure 6 The waveform group in is the return code level signal. After the hardware cannot effectively filter out the interference, software processing is still required. In actual applications, there may be multiple interference signals that are too strong to be filtered out. The characteristics of the interference information are significantly different from those of the normal signal. The interference signal is split and recombined into 3 groups of signals, and the original signal is also retained to participate in the subsequent processing. The purpose is to increase the fault tolerance processing to prevent the original signal from being misjudged as an interference signal due to the deviation of the period T BIT timing. After condition screening through software setting algorithms, the actual corresponding data information is calculated separately, and finally the correct data is obtained through verification.

[0083] Figure 8Among them, the return code output signal is processed through the cooperation of software and hardware, and finally the correct data information transmitted in the return code current signal is obtained. Hardware-wise, the output of the first DC power supply is sent to the two-wire bus through the output control of the single-chip microcomputer, the return code platform controls the output of the second DC power supply to the two-wire bus, and the slave device sends the return code current to the return code receiving module of the master device. As Figure 8 , the return code receiving module of the master device converts the return code current signal into a return code voltage signal. The single-chip microcomputer detects the return code static voltage through the ADC conversion interface, calculates the reference value of the hysteresis comparator, and then outputs it to the return code receiving module of the master device through the DAC conversion interface. The return code receiving module converts the reference value of the hysteresis comparator into an output threshold to shape and filter out some interference signals, and finally outputs a return code level signal that can be directly processed by the single-chip microcomputer.

[0084] The processing process of the software in the single-chip microcomputer is as Figure 9 , the single-chip microcomputer receives the return code level signal, judges the edge polarity and measures the width through edge polarity judgment and width measurement, and finds out the level signal segments in the waveform that do not conform to the standard period. If all level signal segments are within the error tolerance range, it is considered that there is no interference information, and the actual data is calculated through the following Step 4 and Step 5. If one of the level signal segments exceeds the error judgment range, it is considered an interference signal, and the single-chip microcomputer will split, reorganize, screen, and calculate the complete return code level signal. Finally, the check calculations are performed on all the obtained calculation results respectively, and the correct data information transmitted in the return code current signal is finally obtained.

[0085] The specific implementation process is as follows:

[0086] Step 1, interference determination: The single-chip microcomputer receives the return code level signal through a specific I / O port, sequentially judges the edge polarity of each return code level signal from left to right, and numbers them starting from 0, with the maximum number being N - 1, where N is the number of edge signals. Segment the level signals according to adjacent edge polarities and calculate the corresponding width values. The width value is theoretically T_BIT * n (n ranges from 1 to 9), where n represents the number of standard periods T_BIT contained in a single signal level segment. When the width value of a certain level signal segment is less than the first threshold of T_BIT (such as 1 / 3), it is determined that this level signal segment is an interference signal, count the interference signal once, and record the current edge number Number, and enter Step 2; otherwise, enter Step 4;

[0087] Step 2, Signal Splitting: Determine whether the edge number Number corresponding to the signal level segment is N - 1. If so, that is, the last edge of the return code level signal, mark the start number Start of the splitting reference as Start = N - 1, and the end number End of the reference as End = N - 1. In other cases, sequentially determine whether the next at most two signal level segments after the signal level segment are both less than 1 / 3 of T_BIT. The continuous interference signals are recorded as 1 interference signal for splitting processing, that is, Start = Number, End = Start + Continue, where the continuous count Continue of the interference signal level segments does not exceed 3, and the minimum value is 1. Set the edge number Number for the next interference judgment as Number + Continue.

[0088] Step 3, Signal Recombination: Each interference signal will cause the return code level signal to be recombined into four different level signals. Therefore, divide the reference start number and the reference end number into four groups. Group_Start_1 to Group_Start_4 and Group_Stop_1 to Group_Stop_4 correspond to the start numbers and end numbers of the four groups respectively. When the first interference signal is determined, the start numbers and end numbers of each group are the same as Start and Stop respectively. When a non-first interference signal is determined, the corresponding Start and Stop are re-determined and generated on the return code level signal after the previous splitting and recombination. The start numbers and end numbers of each group are obtained through weighted calculation using the reference numbers (Start and Stop) and the number Previous_Continue of the previous continuous interference signals. The calculation method is as follows:

[0089] The start number Group_Start_1 of the first group = Start - (Previous_Continue + 1), and the end number Group_Stop_1 = Stop - (Previous_Continue + 1);

[0090] The start number Group_Start_2 of the second group = Start - (Previous_Continue - 1), and the end number Group_Stop_2 = Stop - (Previous_Continue - 1);

[0091] The start number Group_Start_3 of the third group = Start - Previous_Continue, and the end number Group_Stop_3 = Stop - Previous_Continue;

[0092] The starting number of the fourth group Group_Start_4 = Start - Previous_Continue, and the ending number Group_Stop_4 = Stop - Previous_Continue.

[0093] The number of consecutive interference signals recorded for determination Previous_Continue = Continue, which provides a calculation basis for setting the starting number and ending number of each group in the next round.

[0094] Use a two-dimensional array Array_Regroup_Signal of (4 Num ) * N (where Num is the number of signals determined to be interference signals and N is the maximum number of edge polarities) to store the recombined return code level signals.

[0095] Process the four groups of split return code level signals respectively, specifically:

[0096] The first group: Delete all edge numbers between the starting number Group_Start_1 and the ending number Group_Stop_1 of the first group;

[0097] The second group: Delete all edge numbers between the ending number Group_Stop_2 - 2 or Group_Stop_2 - 1 and the starting number Group_Start_2 of the second group;

[0098] The third group: Delete all edge numbers after the ending number Group_Stop_3 + 1 of the third group;

[0099] The fourth group: Delete all edge numbers between the ending number Group_Stop_4 - 2 or Group_Stop_4 - 1 and Group_Start_4 - 1 of the fourth group.

[0100] After the above processing, four groups of recombined return code level signals are obtained. Calculate the level width value between the edge polarities corresponding to each adjacent edge number for each group of return code level signals respectively, and store them in the Array_Regroup array. At the same time, record the number of valid values in each row. After that, return to step two until all return code level signal judgments are completed, and after completing the splitting and recombination processing of steps two and three, enter step four.

[0101] Step 4, Data Calculation and Screening: When there is no interference signal, directly process the original return code level signal obtained by the single-chip microcomputer. When there is an interference signal, process the return code level signals stored in each row of the Array_Regroup array. Divide the level width value by T_BIT, and the quotient is the number n of T_BITs included. If the remainder has a relative error less than the second threshold (1 / 5) of T_BIT with respect to T_BIT, the data is judged invalid. If it is greater than the third threshold (4 / 5) of T_BIT, the data is judged valid, and the count n is incremented by 1. For the remainder between the second and third thresholds of T_BIT, the data is judged as suspected, that is, it may be valid or invalid, that is, 1 or 0 T_BITs. Calibrate the suspected valid width value, retain both cases, and obtain two calculation results of n + 1 and n T_BITs. Determine the logic level "0" or "1" represented by the signal level segment through the edge polarity. The return code level signal has a maximum of 9 Bit positions (such as Figure 2 ), so there are at most 9 level segments, and theoretically at most 9 suspected valid value width values, and their corresponding calculation results are 2^9. Store the calculation results in the two-dimensional array Array_Regroup_Calculate. Each row corresponds to an actual 9-Bit data and the number of valid Bit positions. During the calculation process, data with more than 9 Bit positions will be screened out, and finally only 8 Bit data positions ( Figure 2 's 8 data positions) will be retained, which represent the data information contained in the return code level signal and are stored in the two-dimensional array Array_Regroup_Check_Calculate. One byte of data information of the complete return code data frame is stored in each column, and the number of valid columns represents the number of bytes of the data frame.

[0102] Step 5 Check Calculation: After completing the above steps, the recombined data of the original data is obtained. Through the check calculation, find the complete data frame that conforms to the check byte data of the data frame and output it. Thus, the data of the device return code signal is completed and its uploaded data information is obtained, and the two-wire data reception and processing process is completed.

[0103] Embodiment 2

[0104] This embodiment also relates to a system based on two-wire data reception and processing, such as Figure 7 , which is used for the master device and includes a single-chip microcomputer, a first DC power supply ( Figure 7 's DC power supply 1 in Figure 7 ), a second DC power supply (

[0105] Output module: Controls the output of the first DC power supply to the bus to power the slave devices; at the same time, modulates the bus voltage waveform according to a specific timing through the single-chip microcomputer and transmits the data to the slave devices.

[0106] Return code platform module: Used for the master device to convert the second DC source into a specific return code level through design and receive the upstream return code current signal sent by the slave device.

[0107] Return code receiving module: Receives the upstream return code current signal from the return code platform module, amplifies, filters, and demodulates the signal and then converts it into a return code voltage signal, and outputs a return code level signal that can be directly processed by the single-chip microcomputer.

[0108] Short-circuit overcurrent protection module: Used for the master device to monitor the real-time change of the bus line current. When the current exceeds the predetermined value or the line is short-circuited, the bus output is cut off in time through the output module to protect the hardware circuit of the master device.

[0109] The functions of the single-chip microcomputer include:

[0110] Output control: Used for the master device to control the output and shutdown of the first DC power supply through specific I / O ports.

[0111] Return code platform control: Used for the master device to control the output and shutdown of the second DC source through specific I / O ports.

[0112] Return code receiving control: Receives the level signal output by the return code receiving module of the master device through the ADC analog-to-digital conversion interface, calculates the comparator voltage threshold of the return code receiving module according to the preset condition value, and outputs it to the return code receiving module through the DAC digital-to-analog conversion interface, and uses the comparator voltage threshold as the hysteresis comparator reference value of the return code receiving module of the master device. The single-chip microcomputer simultaneously receives, saves, and processes the level signal.

[0113] Return code data analysis: Used for the master device to analyze the real data information contained in the level signal.

[0114] Short-circuit overcurrent protection: Used for the master device to analyze the bus short-circuit or overcurrent situation through the current measurement value.

[0115] The ADC and DAC conversions of the single-chip microcomputer detect and control the return code receiving module in real time, not only filtering out some interference signals, but also accurately converting the return code voltage signal into a return code level signal.

[0116] Figures 3 and 4 show the output of the return code voltage signal under normal and interference conditions respectively. From Figure 5 the waveform comparison of the return code voltage signal V 回码 in the two cases, it can be seen that the actual information cannot be confirmed at all under interference, and obviously no real data information can be obtained by processing through amplification.

[0117] Through the combined processing of software and hardware, this application enables the output signal to basically maintain the original data information, such as Figure 6 . Figure 6 In [a certain situation], after the waveform group, which is the return code output level signal, cannot effectively filter out interference through hardware, software processing is continued. In actual applications, there may be multiple interference signals with excessive intensity that cannot be filtered out, and the characteristics of the interference signals are significantly different from those of normal signals. The single-chip microcomputer receives the return code level signal V 高 (0 / 1) through a specific I / O port, encodes the edges sequentially from left to right, and confirms the polarity of each level signal. Segment the level signals according to the edge polarity, and calculate the width value of each level signal segment. The width value is theoretically T BIT *n. In actual applications, there will be deviations, where n represents the number of standard periods T BIT contained in a single signal level segment. When the width value of a certain level signal segment is less than 1 / 3 of T BIT , it is determined that this level signal segment is an interference signal. Split and recombine the interference signal level segment into 3 level signals at the node of the interference signal level segment, and the original signal is also retained for subsequent calculations. The purpose is to increase fault tolerance processing to prevent the original signal from being misjudged as an interference signal due to deviations in the period T BIT timing. That is, for every 1 interference signal recognized, it is split and recombined into 4 groups of signals. For multiple interference signals Num, the final number of waveforms after splitting and recombination is 4 Num (that is Figure 9 4^Num in [a certain situation]). The single-chip microcomputer screens all the recombined return code level signals respectively. After removing the data information that exceeds the number of start bits plus data bits through screening, calculate the actual corresponding data information. After obtaining the complete data frame, obtain the correct complete data frame through verification.

[0118] In this embodiment, Figures 3 to Figure 6 are just examples under the interference situation. In actual applications, there are various uncertain forms of interference situations, but all can be effectively solved through this method.

[0119] The data reception and processing solution of this application can quickly adapt to different communication environments, interference types, intensities, and topological structures of communication lines, ensuring that communication can maintain high-efficiency and stable performance in various complex environments.

[0120] Embodiment 3

[0121] The electronic device of the present invention includes a central processing unit (CPU), which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) or computer program instructions loaded from a storage unit into a random access memory (RAM). In the RAM, various programs and data required for device operation can also be stored. The CPU, ROM, and RAM are connected to each other via a bus. An input / output (I / O) interface is also connected to the bus.

[0122] Multiple components in the device are connected to the I / O interface, including: an input unit, such as a keyboard, mouse, etc.; an output unit, such as various types of displays, speakers, etc.; a storage unit, such as a disk, optical disc, etc.; and a communication unit, such as a network card, modem, wireless communication transceiver, etc. The communication unit allows the device to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0123] The processing unit executes the various methods and processes described above. For example, in some embodiments, the method can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device via the ROM and / or the communication unit. When the computer program is loaded into the RAM and executed by the CPU, one or more steps of the method described above can be executed. Alternatively, in other embodiments, the CPU can be configured to execute the method by any other suitable means (e.g., by means of firmware).

[0124] The functions described above herein can be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), system on a chip (SOC), complex programmable logic devices (CPLD), and so on.

[0125] The program code for implementing the method of the present invention can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program code is executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, executed partially on the machine as an independent software package and partially on a remote machine, or executed entirely on a remote machine or server.

[0126] In the context of the present invention, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium would include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0127] As described above, only the specific embodiments of the present invention are provided, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A data receiving and processing method based on two buses, characterized in that: The method includes: The master device sends a downlink voltage signal containing data information to the slave device through the second bus, and sets the return code voltage segment for receiving data from the slave device; The master device converts the received uplink return code current signal into a return code voltage signal; The master device converts the return code voltage signal into a return code level signal; After receiving the return code level signal, the master device analyzes the interference signal in the return code level signal, and sequentially splits and reassembles the return code level signal with the interference signal until all the return code level signals with the interference signal are processed; The split and reassembled data are calculated, screened, and verified to confirm the correct data information contained in the return code level signal.

2. A data receiving and processing method based on two buses according to claim 1, characterized in that: The slave device sends an uplink return code current signal of a standard period T_BIT according to a set baud rate, and the uplink return code current signal of the slave device in the same system is a fixed value; The uplink return code current signal is serially encoded, including a 1-bit start bit and m-1 bits of data bits.

3. The data receiving and processing method based on two buses according to claim 1 is characterized in that: The process of converting the return code voltage signal into the return code level signal comprises: The master device obtains in advance the amplitude of the static voltage signal when there is no uplink feedback current, and the feedback voltage signal is processed and superimposed on the static voltage signal, and a hysteresis comparator reference value is calculated according to the static voltage value; The master device converts the hysteresis comparator reference value into an output threshold value to shape and filter out part of the interference signal, so that the return code voltage signal is converted into a return code level signal.

4. The data receiving and processing method based on two buses according to claim 1 is characterized in that: The interference signal determination process includes: after the master device receives the return code level signal, it sequentially determines the edge polarity of each return code level signal and numbers them; Segment the level signal according to the edge polarity into multiple level signal segments, and calculate the corresponding width values; When the width value of a certain level signal segment is smaller than the first threshold of the standard period T_BIT, the level signal segment is determined to be an interference signal, and the current edge number Number is recorded; otherwise, it is a normal signal.

5. A data receiving and processing method based on two buses according to claim 4, characterized in that: The process of splitting the return code level signal with interference signals includes: judging whether the edge corresponding to the signal level segment is the last edge according to the edge number, if yes, marking the splitting benchmark starting number Start=N-1, the benchmark ending number End=N-1, where N is the number of edge signals in the signal level segment; if no, judging in turn whether the maximum two signal level segments after the signal level segment are both less than the first threshold of the standard period T_BIT, if yes, judging these signal level segments after the signal level segment as interference signals, and recording the continuous interference signals as the same interference signal for splitting processing, that is, marking the splitting benchmark starting number Start=Number, the benchmark ending number End=Start+Continue, where Continue is the continuous count of interference signals in the signal level segment.

6. The data receiving and processing method based on two buses according to claim 5 is characterized in that: After splitting the return code level signal with interference signal, the reassembly process includes: Each interference signal will cause the return code level signal to be reorganized into four different level signals, so the reference start number and the reference end number are divided into four groups, Group_Start_1 to Group_Start_4 and Group_Stop_1 to Group_Stop_4 correspond to the group start number and the group end number of the four groups respectively; When the first interference signal is determined, the group start number and group end number of each group are the same as the reference start number Start and the reference end number Stop respectively; When it is determined that it is not the first interference signal, the corresponding reference start number Start and reference end number Stop are re-determined and generated based on the return code level signal after the last split and reorganization. The group start and group end numbers of each group are obtained by weighted calculation based on the reference start number Start, the reference end number Stop and the number of the last continuous interference signal Previous_Continue, specifically: The calculation method is as follows: The first group start number Group_Start_1 = Start - (Previous_Continue + 1), the end number Group_Stop_1 = Stop - (Previous_Continue + 1); The second group start number Group_Start_2 = Start-(Previous_Continue-1), the end number Group_Stop_2 = Stop-(Previous_Continue-1); The third group start number Group_Start_3 = Start-Previous_Continue, the end number Group_Stop_3 = Stop-Previous_Continue; The fourth group start number Group_Start_4 = Start-Previous_Continue, the end number Group_Stop_4 = Stop-Previous_Continue; The determined number of continuous interference signals Previous_Continue=Continue is updated to provide a calculation basis for setting the group start number and group end number of each group next time.

7. The data receiving and processing method based on two buses according to claim 6 is characterized in that: The reorganization process also includes processing each group of level signals separately, specifically: First group: delete all edge numbers between the first group start number Group_Start_1 and the first group end number Group_Stop_1; The second group deletes all edge numbers between the second group end number Group_Stop_2-2 or Group_Stop_2-1 and the second group start number Group_Start_2; The third group: delete all edge numbers after the third group end number Group_Stop_3+1; Fourth group: Delete the fourth group end number Group_Stop_4-2 or all edge numbers between Group_Stop_4-1 and Group_Start_4-1; After the above processing, four groups of return code level signals are reorganized. The level width value between the edge polarities corresponding to each adjacent edge number is recalculated for each group of return code level signals, and stored in the Array_Regroup array, and the number of valid values ​​in each row is recorded at the same time.

8. The data receiving and processing method based on two buses according to claim 7 is characterized in that: For the return code level signal with interference signal, the return code level signal stored in each row of Array_Regroup array is calculated and screened; For normal signals, the original return code level signal is directly calculated and screened; The calculations and screenings described include: Divide the level width value by the standard period T_BIT, and the quotient is the number n of T_BIT. If the relative error between the remainder and the standard period T_BIT is less than the second threshold of the standard period T_BIT, the data is judged to be invalid; if the relative error between the remainder and the standard period T_BIT is greater than the third threshold of the standard period T_BIT, the data is judged to be valid, and the count n is increased by 1; for the remainder between the second threshold and the third threshold of the standard period T_BIT, the data is judged to be suspected, and it is calibrated as a suspected valid width value, and the two cases of valid data and invalid data are retained; The logic level "0" or "1" represented by the signal level segment is determined by the edge polarity, and the calculation result is stored in the two-dimensional array Array_Regroup_Calculate. Each row corresponds to an actual m-bit data and the effective number of bits. Data with more than m bits of data bits are filtered out, and finally only m-1 bits of data bits are retained, which represent the data information contained in the return code level signal and are stored in the two-dimensional array Array_Regroup_Check_Calculate. Each column stores one byte of data information of the complete return code data frame, and the number of valid columns represents the number of bytes in the data frame.

9. A system using the data receiving and processing method based on two buses according to any one of claims 1 to 8, characterized in that: The system is used for a main device, including a single chip microcomputer, a first DC power supply, a second DC power supply and a plurality of hardware modules, wherein the hardware modules include: Output module: controls the output of the first DC power supply to the second bus, thereby supplying power to the slave device; at the same time, the downlink data is modulated by the single-chip microcomputer according to a specific timing sequence, and the bus voltage waveform is transmitted to the slave device; Back-code platform module: used by the master device to convert the second DC source into a specific back-code level through design, and receive the uplink back-code current signal sent by the slave device; Feedback receiving module: receives the uplink feedback current signal from the feedback platform module, amplifies, filters and modulates the signal, converts it into a feedback voltage signal, and outputs a feedback level signal that can be directly processed by the single-chip microcomputer; Short-circuit overcurrent protection module: used by the main device to monitor the real-time changes of the current of the second bus line. When the current exceeds the preset value or the line is short-circuited, the output module will cut off the bus output in time through the microcontroller to protect the hardware circuit of the main device.

10. The system according to claim 9, characterized in that The functions of the single chip microcomputer include: Output control: used by the master device to control the output and shutdown of the first DC power supply through the first I / O port; Back-code platform control: used by the master device to control the output and shutdown of the second DC source through the second I / O port; Return code receiving control: receiving the return code level signal output by the return code receiving module of the master device, calculating the comparator voltage threshold of the return code receiving module, and using the comparator voltage threshold as the hysteresis comparator reference value of the return code receiving module of the master device; Return code data analysis: used by the master device to analyze the real data information contained in the level signal; Short circuit and overcurrent protection: used by the master device to analyze bus short circuit or overcurrent conditions through current measurement.

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