Column memory circuit, chip, image sensor, and imaging apparatus

Abstract

The invention provides a column memory circuit, a chip, an image sensor and an imaging apparatus. The column memory circuit comprises M * N memory bank modules, N reading modules and a data transmission module, and a correlated double sampling unit of the column memory circuit is arranged in the data transmission module; the memory bank module receives a first data signal, the second end of the memory bank module is coupled with the first end of the reading module corresponding to the memory bank module, and the second end of the reading module is coupled with the data transmission module. The memory bank module converts a received first data signal into a second data signal, the reading module sends the received second data signal to the data transmission module, and the data transmission module performs correlated double sampling processing on the second data signal through a correlated double sampling unit to obtain and output a third data signal. According to the invention, the area of the column memory circuit can be obviously reduced, the circuit performance can be well ensured, and the cost of the image sensor can be obviously reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and particularly to a column memory circuit, a chip, an image sensor, and an imaging device. Background Art

[0002] An image sensor is a device that converts an optical image into an electrical signal, and generally includes components such as a pixel array, an analog-to-digital converter, and a column memory circuit. Exemplarily, please refer to Figure 1 , which schematically shows the flow diagram of data signals during the imaging process. As Figure 1 can be seen, the pixel unit 111 of the pixel array 110 ( Figure 1 not shown in the figure, see Figure 6 below) is responsible for converting the collected image optical signal into a voltage signal and outputting the voltage signal to the analog-to-digital converter 120 (Analog-to-digital Converter, ADC). The analog-to-digital converter 120 is responsible for comparing the received voltage signal with a ramp signal and generating a pulse signal when the two signals are equal; the column memory (Column) circuit 130 latches the data of the counter when receiving the pulse signal, and serially outputs the processed data to the image processor (Image Signal Processing, ISP) 150 in a certain manner. The image processor 150 extracts and optimizes the received image data (such as color correction, Gamma correction, etc.) to obtain an image that can be displayed, stored, and / or further processed, and outputs it through the interface (Interface) circuit 160.

[0003] It has been found through research that the current column memory circuit has a large area and high power consumption. Although it has been well applied in high-performance image sensors, it is difficult to be applied in low-cost image sensors.

[0004] It should be noted that the information disclosed in the background art of the present invention is only intended to deepen the understanding of the general background technology of the present invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0005] Aiming at the technical problems of the large area and high power consumption of the column memory circuit of the image sensor in the prior art, the present invention provides a column memory circuit, a chip, an image sensor, and an imaging device. The present invention can significantly reduce the area of the column memory circuit and well ensure the circuit performance. By using the column memory circuit provided by the present invention, the cost of the image sensor can be significantly reduced.

[0006] To achieve the above object, the present invention is implemented through the following technical solutions: A column memory circuit for an image sensor, comprising M×N memory bank modules, N readout modules, and a data transmission module. The correlated double sampling unit of the column memory circuit is disposed in the data transmission module; a first end of the memory bank module is configured to receive a first data signal, a second end of the memory bank module is coupled to a first end of the corresponding readout module, a second end of the readout module is coupled to the data transmission module, and M≥2;

[0007] The memory bank module is configured to convert the received first data signal into a second data signal, the readout module is configured to send the received second data signal to the data transmission module, and the data transmission module is configured to perform correlated double sampling processing on the second data signal through the correlated double sampling unit to obtain and output a third data signal.

[0008] Optionally, the correlated double sampling unit includes a plurality of first transistors.

[0009] Optionally, each memory bank module includes a first latch and a buffer unit connected in sequence, each readout module includes a flip-flop and a multiplexer connected in sequence, and the data transmission module includes a transcoding unit, a second latch, the correlated double sampling unit, and a data interface unit connected in sequence;

[0010] The first latch is configured to latch the first data signal when receiving a first control signal of the image sensor and send the latched first data signal to the buffer unit. The buffer unit is configured to buffer the first data signal to obtain the second data signal and send the second data signal to the flip-flop;

[0011] The flip-flop sends the second data signal to the multiplexer when receiving a second control signal of the image sensor. The multiplexer is configured to select a corresponding second data signal according to a third control signal of the image sensor and send it to the transcoding unit. The transcoding unit is configured to transcode the second data signal to obtain a first set of fourth data signals for sending to the second latch, and after obtaining the first set of fourth data signals, transcode the subsequent received second data signals to obtain a second set of fourth data signals for sending to the correlated double sampling unit. The second latch is configured to latch the first set of fourth data signals when receiving a fourth control signal. The correlated double sampling unit is configured to perform correlated double sampling processing according to the first set of fourth data signals and the second set of fourth data signals to obtain the third data signal.

[0012] Optionally, the transcoding unit includes a plurality of second transistors.

[0013] Optionally, the second data signal uses a Gray code encoding method, and the first group of fourth data signals, the second group of fourth data signals, and the third data signal use a binary encoding method.

[0014] To achieve the above object, the present invention also provides a chip for an image sensor, and the above-described column memory circuit is integrated on the chip.

[0015] To achieve the above object, the present invention also provides an image sensor, and the image sensor includes the above-described column memory circuit or the chip as described above.

[0016] Optionally, the image sensor further includes a digital circuit area and a pixel array, and the data transmission module of the column memory circuit is disposed in the digital circuit area;

[0017] The pixel array is configured to convert the collected image optical signal into the first data signal, the column memory circuit is configured to convert the first data signal into the second data signal, and convert the second data signal into the third data signal through the data transmission module located in the digital circuit area, and the image processor is configured to process the third data signal to obtain a target image of the object to be collected.

[0018] Optionally, the data transmission module is disposed in the digital circuit area by using a digital chip design tool.

[0019] To achieve the above object, the present invention also provides an imaging device, and the imaging device includes the above-described column memory circuit, the above chip, or the image sensor as described above.

[0020] Compared with the prior art, the column memory circuit, chip, image sensor, and imaging device provided by the present invention have the following advantages:

[0021] The column memory circuit for an image sensor provided by the present invention includes M×N memory bank modules, N readout modules, and a data transmission module. The correlated double sampling unit of the column memory circuit is arranged in the data transmission module. The first end of the memory bank module is configured to receive a first data signal. The second end of the memory bank module is coupled to the first end of the corresponding readout module. The second end of the readout module is coupled to the data transmission module, where M≥2. Further, the memory bank module is configured to convert the received first data signal into a second data signal. The readout module is configured to send the received second data signal to the data transmission module. The data transmission module is configured to perform correlated double sampling processing on the second data signal through the correlated double sampling unit to obtain and output a third data signal. Thus, the column memory circuit provided by the present invention abandons the design method in the prior art where the correlated double sampling unit is arranged in the memory bank module. By making full use of the objective fact that the number of data transmission modules is much smaller than the number of memory bank modules, and adopting the design method of arranging the correlated double sampling unit in the data transmission module, the number of correlated double sampling units can be significantly reduced. This not only saves costs but also reduces the circuit area occupied by the correlated double sampling unit, thereby significantly reducing the area of the column memory circuit and well ensuring the circuit performance. By using the column memory circuit provided by the present invention, the cost of the image sensor can be significantly reduced, and the column memory circuit provided by the present invention can be well applied to low-cost image sensors.

[0022] Since the chip for an image sensor, the image sensor, and the imaging device provided by the present invention belong to the same inventive concept as the column memory circuit provided by the present invention, therefore, the chip for an image sensor, the image sensor, and the imaging device provided by the present invention at least have all the advantages of the column memory circuit provided by the present invention. For the detailed content of the beneficial effects of the chip for an image sensor, the image sensor, and the imaging device provided by the present invention, please refer to the relevant description of the beneficial effects of the column memory circuit provided by the present invention above, and will not be elaborated here one by one. Brief Description of the Drawings

[0023] Figure 1 It is a schematic diagram of the data signal flow direction during the imaging process;

[0024] Figure 2 It is a schematic diagram of the data signal flow direction in the column memory circuit of the image sensor;

[0025] Figure 3 It is a schematic diagram of the topological structure of the column memory circuit of the image sensor in the prior art;

[0026] Figure 4Schematic block diagram of the column memory circuit provided by the present invention;

[0027] Figure 5 Schematic topological diagram of a specific example of the column memory circuit provided by the present invention;

[0028] Figure 6 Schematic block diagram of the imaging device provided by the present invention;

[0029] Among them, the reference numerals are as follows:

[0030] Pixel array - 110, pixel unit - 111, analog - to - digital converter - 120, column memory circuits - 130, 140, image processor - 150, interface circuit - 160;

[0031] Memory bank modules - Bank0, Bank1, Bank2, Bank3, 130A, 141, 141A, read - out modules - R01, R23, 130B, 142, 142A, data transmission modules - 170, 143;

[0032] First latch - 131, 141A1, transcoding unit - 132, 1431, second latch - 133, 1432, correlated double - sampling unit - 134, 1433, buffer unit - 135, 141A2, flip - flop - 136, 142A1, multiplexer - 137, 142A2, data interface unit - 1434;

[0033] Gray - code data - GC, binary data - BC, comparator data - CMP, black - level enable signal - BLK_EN, adjacent read - out module output signal terminal - GBL;

[0034] First data signal - D1, second data signal - D2, third data signal - D3, fourth data signal - D4;

[0035] First control signal - T1, second control signal - T2, third control signal - T3, fourth control signal - T4;

[0036] Digital circuit area - 180. Detailed implementation manners

[0037] The following further elaborates on a column memory circuit, a chip, an image sensor, and an imaging device proposed by the present invention in conjunction with the accompanying drawings. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in a very simplified form and use non-precise scales, solely for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention. To make the objectives, features, and advantages of the present invention more apparent and understandable, please refer to the accompanying drawings. It should be understood that the structures, scales, sizes, etc. depicted in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those skilled in this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Any modification of the structure, change in the proportional relationship, or adjustment of the size, in the case of being the same or similar to the effects that the present invention can produce and the objectives that can be achieved, should still fall within the scope covered by the technical content disclosed by the present invention. The specific design features of the present invention disclosed herein, such as specific dimensions, directions, positions, and shapes, will be partially determined by the specific application and usage environment. Also, in the embodiments described below, sometimes the same reference numerals are used between different drawings to represent the same part or parts having the same functions, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings. Additionally, if the methods described herein include a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps can be executed, and some of the described steps can be omitted and / or some other steps not described herein can be added to the method.

[0038] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element. The singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of "and / or", the term "several" is generally used in the sense of "at least one", the term "at least two" is generally used in the sense of "two or more", and in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.

[0039] It should be understood that when an element is referred to as being "connected", "connected to", "coupled to" another element, it can be directly connected to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly connected to" another element, there are no intervening elements.

[0040] To facilitate a better understanding and elaboration of the present invention, before describing the specific embodiments of the column memory circuit, image sensor and imaging device provided by the present invention, the main research process of the present invention will be described first.

[0041] First, please refer to Figure 2 , which schematically shows the flow diagram of the data signal in the column memory circuit of the image sensor. As Figure 2 shown, Figure 2 taking the column memory circuit including four bank modules Bank0, Bank1, Bank2 and Bank3, two readout modules R01 and R23, and a data io module 170 as an example, and the bank modules Bank0 and Bank1 share the readout module R01, and the bank modules Bank2 and Bank3 share the readout module R23, that is, every two bank modules share one readout module. The processing flow of the column memory circuit for the data signal is generally as follows: from the analog-to-digital converter 120 ( Figure 2 not shown in Figure 1Gray code data GC and comparator data CMP (for understanding) enter the memory bank modules Bank0, Bank1, Bank2, and Bank3 from the outside. The memory bank modules Bank0 and Bank1 send the processed data to the corresponding read modules R01 and then transmit it to the data transmission module 170. The memory bank modules Bank2 and Bank3 first send the processed data to the corresponding read modules R23 and then send it to the data transmission module 170 through the read module R01. All the read modules R01 and R23 together form the shift read function. The data transmission module 170 receives the data processed by the read modules R01 and R23 and outputs the data from the column memory circuit 130.

[0042] Please refer to Figure 3 , Figure 3 which is a schematic diagram of the topology of the column memory circuit of an image processor in the prior art. As Figure 3 shown, in this example, the column memory circuit 130 includes M×N memory bank modules ( Figure 3 schematically shown as the i-th memory bank module 130A, 1 ≤ i ≤ (M×N)), N read modules ( Figure 3 schematically shown as the j-th read module 130B, 1 ≤ j ≤ N) and 1 data transmission module 170. The processing process of the data signal is roughly as follows: At the falling edge of the comparator data CMP signal, the gray code data GC is latched in the first latch 131. The transcoding unit 132 converts the latched gray code data GC into binary data BC. The second latch 133 stores the black level signal of the image sensor when the black level enable signal BLK_EN is high. The correlated double sampling unit (CDS) 134 implements the CDS function according to the stored black level signal and pixel level data when the black level enable signal BLK_EN is low. The buffer unit 135 sends the data signal BIT_OUT that has completed CDS from the memory bank module 130A to the corresponding read module 130B. As mentioned above, N read modules together form the shift register function. Further, the read module 130A first sends out the data in the memory bank module 130A and the memory bank module ( Figure 3 not shown in the figure) that shares the read module 130A with the memory bank module 130A ( Figure 2 such as the memory bank modules bank0 and bank1 that share the read module R01 in the figure) through the flip-flop 136 (such as a D-type flip-flop, DFF) and the multiplexer 137. Immediately afterwards, the multiplexer 137 is switched to the output signal terminal GBL of the adjacent read module, and the read module 130B sends the data of other memory bank modules through the multiplexer 137 (such as Figure 2The data of memory bank modules bank2 and bank3 of the shared read module R23 are first sent to the read module R23, then transmitted to the read module R01 for output, and then output from the column memory circuit 130 through the data transmission module 170.

[0043] It should be noted that only the parts of the column memory circuit related to the present invention are described in this article. For more detailed content of the column memory circuit not mentioned in this article, please refer to the relevant technologies well-known to those skilled in the art for adaptive understanding.

[0044] From Figure 3 It can be seen that the column memory circuit in the prior art generally includes a data transmission module 170, N read modules 130B, and M×N memory bank modules 130A (the specific values of M and N are related to the resolution of the image sensor), and most functions are implemented in the memory bank module 130A. After a large number of studies, the inventor found that circuits with complex functions such as the transcoding unit 132 and the correlated double sampling unit 134 are usually composed of a large number of transistors. The complex functions and a large number of memory bank modules 130A lead to a large circuit area occupied by the column memory circuit 130, making it difficult to be applied to low-cost image sensor products.

[0045] Based on the above research, the core idea of the present invention is to provide a column memory circuit, an image sensor, and an imaging device. The present invention can significantly reduce the area of the column memory circuit and well ensure the circuit performance. By using the column memory circuit provided by the present invention, the cost of the image sensor can be significantly reduced.

[0046] It should be noted that the column memory circuit and chip for an image sensor provided by the present invention can be applied to the image sensor and imaging device provided by the present invention. The image sensor provided by the present invention can be applied to the imaging device provided by the present invention. It should be understood that the term "imaging device" or "of the imaging device" or other similar terms used herein include general imaging devices, such as, for example, but not limited to, cameras, video cameras, mobile phones, tablet computers, learning machines, and medical imaging devices having image sensors.

[0047] To achieve the above idea, the present invention provides a column memory circuit. Exemplarily, please refer to Figure 4 , which schematically shows the block structure diagram of the column memory circuit provided by the present invention. From Figure 4It can be seen that the column memory circuit for an image sensor provided by the present invention includes M×N memory bank modules 141, N readout modules 142, and a data transmission module 143. The correlated double sampling unit 1433 of the column memory circuit is disposed in the data transmission module 143. The first end of the memory bank module 141 is configured to receive a first data signal D1. The second end of the memory bank module 141 is coupled to the first end of the corresponding readout module 142. The second end of the readout module 142 is coupled to the data transmission module 143, where M≥2. Further, the memory bank module 141 is configured to convert the received first data signal D1 into a second data signal D2. The readout module 142 is configured to send the received second data signal D2 to the data transmission module 143. The data transmission module 143 is configured to perform correlated double sampling processing on the second data signal D2 through the correlated double sampling unit 1433 to obtain and output a third data signal D3.

[0048] Thus, for the column memory circuit provided by the present invention, the design method of disposing the correlated double sampling unit in the memory bank module in the prior art is abandoned. By making full use of the fact that the number of data transmission modules 143 is much smaller than the number of memory bank modules 141, and adopting the design method of disposing the correlated double sampling unit 1433 in the data transmission module 143, the number of correlated double sampling units 1433 can be significantly reduced, which not only saves costs but also reduces the circuit area occupied by the correlated double sampling unit 1433, thereby significantly reducing the area of the column memory circuit and well ensuring the circuit performance. By using the column memory circuit provided by the present invention, the cost of the image sensor can be significantly reduced, and the column memory circuit provided by the present invention can be well applied to low-cost image sensors.

[0049] Specifically, compared with the design method of disposing the correlated double sampling unit in the memory bank module in the prior art, for the column memory circuit provided by the present invention, with the correlated double sampling unit 1433 disposed in the data transmission module 143, M×N−1 correlated double sampling units 1433 can be saved.

[0050] Preferably, in some exemplary embodiments, the correlated double sampling unit 1433 includes a plurality of first transistors ( Figure 4(not shown in the figure). Thus, the design method of implementing the relevant double sampling unit 1433 by using a plurality of first transistors is easy to implement. It should be noted that those skilled in the art should be able to understand that the above implementation of the relevant double sampling unit 1433 by using the first transistor is only an exemplary illustration of the preferred implementation manner, rather than a limitation of the present invention. The present invention does not make any limitation on the specific implementation manner of the relevant double sampling unit 1433. For more detailed content about the relevant double sampling unit 1433, please refer to the relevant technologies well-known to those skilled in the art. Due to space limitations, this will not be elaborated in detail herein.

[0051] Exemplarily, taking the relevant double sampling unit 1433 including P first transistors as an example, the design method of arranging the relevant double sampling unit in the memory bank module 141 in the prior art requires a total of M×N×P first transistors, while only P first transistors are required by using the column memory circuit provided by the present invention. It can be seen that, compared with the prior art, the present invention can save at least (M×N−1)×P transistors.

[0052] Exemplarily, please refer to Figure 5 , which schematically shows the topology diagram of a specific example of the column memory circuit provided by the present invention. Figure 5 In the figure, the i-th memory bank module 141A and the j-th readout module 142A are taken as examples. From Figure 5As can be seen, in the column memory circuit provided by the present invention, each of the memory bank modules 141A includes a first latch 141A1 and a buffer unit 141A2 that are sequentially coupled. Each of the readout modules 142A includes a flip-flop 142A1 and a multiplexer 142A2 that are sequentially coupled. The data transmission module 143 includes a transcoding unit 1431, a second latch 1432, the correlated double sampling unit 1433, and a data interface unit 1434 that are sequentially coupled. Further, the first latch 141A1 is configured to latch the first data signal D1 (such as a voltage signal in Gray code format, which represents the output voltage value of a pixel) when receiving the first control signal T1 (such as comparator data CMP) of the image sensor, and send the latched first data signal D1 to the buffer unit 141A2. The buffer unit 141A2 is configured to buffer the first data signal D1 to obtain the second data signal D2 (such as a voltage signal in Gray code format, which represents the output voltage value of a pixel), and send the second data signal D2 to the flip-flop 142A1. The flip-flop 142A1 sends the second data signal D2 to the multiplexer 142A2 when receiving the second control signal T2 (such as a read clock signal) of the image sensor. The multiplexer 142A2 is configured to select the corresponding second data signal D2 according to the third control signal T3 (such as a memory bank module selection signal) of the image sensor and send it to the transcoding unit 1431. The transcoding unit 1431 is configured to transcode the second data signal D2 to obtain a first set of fourth data signals D41 (such as a voltage signal in binary format, which represents the voltage value of a black level signal) for sending to the second latch 1432, and after obtaining the first set of fourth data signals D41, transcode the subsequently received second data signal D2 to obtain a second set of fourth data signals D42 (a voltage signal in binary format, which represents the voltage value of an image pixel) for sending to the correlated double sampling unit 1433. The second latch 1432 is configured to latch the first set of fourth data signals D41 when receiving a fourth control signal T4 (such as a black level enable signal). The correlated double sampling unit 1433 is configured to perform correlated double sampling processing according to the first set of fourth data signals D41 and the second set of fourth data signals D42 to obtain the third data signal D3 (a voltage signal in binary format).

[0053] The column memory circuit provided by the present invention has a memory bank module 141A including a first latch 141A1 and a buffer unit 141A2. Thus, the stability of the first data signal D1 can be ensured by the first latch 141A1, and buffering the first data signal D1 by the buffer module 141A2 can ensure that the second data signal D2 of multiple memory bank modules connected to the read module 142A is stably transmitted to the flip-flop 142A1. Further, the read module 142A of the column memory circuit includes the flip-flop 142A1 and the multiplexer 142A2 connected in sequence. The flip-flop 142A1 can synchronize the switching of the multiplexer 142A2 between each read module 142 and the read timing, so that the multiplexer 142A2 can select the second data signal D2 of the corresponding read module 142 for output (for example, the multiplexer 142A2 can select to output the second signal data D2 of the read module 142A or the second signal data D2 of the read module 142B). Still further, the data transmission module 143 includes the transcoding unit 1431, the second latch 1432, the correlated double sampling unit 1433, and the data interface unit 1434. Thus, converting the second data signal D2 into the first group of fourth data signals D41 and the second group of fourth data signals D42 by the transcoding module 1431 can lay a solid foundation for the second latch 1432 to efficiently process the data signal, and the second latch 1432 can lay a good foundation for the correlated double sampling unit 1433 to suppress the fixed pattern noise and reset noise of the data signal to obtain the third data signal and further improve the image quality.

[0054] Preferably, still taking the read module 142A as an example, one input terminal of its multiplexer 142A2 is connected to the output terminal of the flip-flop 142A1 of the read module 142A, and the other input terminal of its multiplexer 142A2 is connected to the output terminal of the multiplexer ( Figure 5 not shown in the figure) of another read module 142B adjacent to the read module 142A. Further, most of the read modules 142 are connected to the data transmission module 143 through the multiplexers of other read modules 142 adjacent to them. For the last read module 142, the output terminal of its multiplexer is directly connected to the data transmission module 143.

[0055] Exemplarily, in some exemplary embodiments, the second data signal D2 is encoded in Gray code, and the first group of fourth data signals D41, the second group of fourth data signals D42, and the third data signal D3 are encoded in binary code. Thus, encoding the first data signal D1 in Gray code can effectively reduce transmission errors, and encoding the first group of fourth data signals D41, the second group of fourth data signals D42, and the third data signal D3 in binary code is more convenient for the subsequent efficient processing of the readout module. It should be noted that those skilled in the art should be able to understand that the present invention does not overly limit the specific format of encoding the first data signal D1, the first group of fourth data signals D41, the second group of fourth data signals D42, and the third data signal D3 in binary code. When implementing the present invention, it should be reasonably set according to actual needs.

[0056] Exemplarily, in some exemplary embodiments, the flip-flop 142A1 includes, but is not limited to, a D flip-flop. Thus, in the column memory circuit provided by the present invention, the flip-flop 142A1 of the readout module 142A is designed as a D flip-flop, which can well ensure the serial transmission of the second data signal D2.

[0057] Preferably, in some exemplary embodiments, the transcoding unit 1431 includes a plurality of second transistors ( Figure 6 not shown in the figure). Thus, the transcoding unit 1431 is designed with a plurality of second transistors, which has simple logic and is easy to implement. It should be noted that those skilled in the art should be able to understand that implementing the transcoding unit 1431 with second transistors is only an exemplary illustration of a preferred embodiment, rather than a limitation of the present invention. The present invention does not limit the specific implementation manner of the transcoding unit 1431. For more detailed content about the transcoding unit 1431, please refer to the related technologies well-known to those skilled in the art. Due to space limitations, this will not be elaborated further herein.

[0058] Exemplarily, taking the correlated double sampling unit 1433 including P first transistors and the transcoding unit 1431 including Q second transistors as an example, in the prior art, the design method of arranging both the transcoding unit 1431 and the correlated double sampling unit 1433 in the memory bank module 141 requires a total of M×N×P first transistors and M×N×Q second transistors for these two units. However, for the column memory circuit provided by the present invention, these two units only require P first transistors and Q second transistors in total. Thus, it can be seen that compared with the prior art, the present invention can save (M×N - 1)×(P + Q) transistors.

[0059] It can be understood that, according to the above description, compared with the prior art, in the column memory circuit provided by the present invention, the transcoding unit 1431 and the related dual-sampling unit 1433 are both arranged in the data transmission module 143, which will cause an increase in the amount of data output by the memory bank module 141A. If it is necessary to further improve the performance of the column memory circuit, although the performance requirements for the buffer unit 141A2 of the column memory circuit may be increased, and a larger data bit width needs to be supported, generally speaking, the column memory circuit provided by the present invention still has a good cost performance.

[0060] It should be noted that, as can be understood by those skilled in the art, the present invention does not overly limit the specific type of the image sensor. For example, the image sensor may be, but is not limited to, a CMOS image sensor. Further, the present invention does not overly limit the specific values of M, N, P, and Q. Preferably, the values of M and N are preferably related to the resolution of the image sensor, and should be reasonably set according to actual needs when implementing the present invention.

[0061] The second embodiment of the present invention provides a chip for an image sensor, and the column memory circuit as described in any of the above embodiments is integrated on the chip. Thus, by using the chip integrated with the column memory circuit provided by the present invention, not only can the cost of the image sensor be reduced, but also the integration degree of the image sensor can be further improved.

[0062] The third embodiment of the present invention provides an image sensor, and the image sensor includes the column memory circuit as described in any of the above embodiments or the chip as described in the above embodiments. Exemplarily, please refer to Figure 6 , Figure 6 which is a schematic block diagram of an imaging device provided by one exemplary embodiment of the present invention. As can be seen from Figure 6 it that, the image sensor further includes a digital circuit area 180 and a pixel array 110. The data transmission module 143 of the column memory circuit 140 is arranged in the digital circuit area 180, and the digital circuit area 180 is usually composed of digital circuit modules designed and implemented using hardware description languages such as Verilog. Further, the pixel array 110 is configured to convert the collected image optical signal into the first data signal, the column memory circuit is configured to convert the first data signal into the second data signal and convert the second data signal into the third data signal through the data transmission module 143 located in the digital circuit area 180, and the image processor is configured to process the third data signal to obtain the target image of the object to be collected.

[0063] The image sensor provided by the present invention adopts the design method in which the data transmission module 143 is arranged in the digital circuit area 180. Based on the fact that the digital circuit area usually realizes circuit functions by programming, the design can be further simplified and the flexibility can be improved. Further, since the image sensor provided by the present invention and the column memory circuit provided by the present invention belong to the same inventive concept, the image sensor provided by the present invention at least has all the advantages of the column memory circuit provided by the present invention. For the detailed content of the beneficial effects of the image sensor provided by the present invention, please refer to the relevant description of the beneficial effects of the column memory circuit provided by the present invention above, and will not be elaborated here one by one.

[0064] It should be noted that, as described above (for example, in combination with Figure 1 ), the image sensor may further include an analog-to-digital converter 120 coupled between the pixel array 110 and the column memory circuit 140, and an image processor for further processing the third data signal ( Figure 6 not shown in the figure) and the like. For more detailed content of the image sensor, please refer to the related technologies well-known to those skilled in the art. Due to space limitations, it will not be elaborated here.

[0065] Preferably, in some exemplary embodiments, the data transmission module 143 is arranged in the digital circuit area by using a digital chip design tool. It should be noted that those skilled in the art should be able to understand that the present invention does not impose any restrictions on the specific type of the digital chip design tool. For example, the digital chip design tool includes, but is not limited to, RTL and APR tools. For example, the transcoding unit 1431 and the correlated double sampling unit 1433 are implemented by using RTL and APR tools in the digital circuit area 180.

[0066] The fourth embodiment of the present invention provides an imaging device. The imaging device provided in this embodiment includes the column memory circuit provided in any of the above embodiments, or the chip provided in the embodiments of the present application, or the image sensor provided by the present invention. Since the imaging device provided in this embodiment and the image sensor provided by the present invention belong to the same inventive concept, and the image sensor provided by the present invention and the column memory circuit provided by the present invention belong to the same inventive concept, the imaging device provided in this embodiment at least has all the advantages of the column memory circuit provided by the present invention. For the detailed content, please refer to the relevant description of the beneficial effects of the column memory circuit above, and will not be elaborated here one by one for the time being.

[0067] Compared with the prior art, a column memory circuit, a chip, an image sensor, and an imaging device provided by the present invention have the following beneficial effects: The column memory circuit provided by the present invention abandons the design method in the prior art of arranging the correlated double sampling unit in the memory bank module, makes full use of the objective fact that the number of the data transmission modules is much smaller than the number of the memory bank modules, and adopts the design method of arranging the correlated double sampling unit in the data transmission module, which can significantly reduce the number of the correlated double sampling units, not only saving costs, but also reducing the circuit area occupied by the correlated double sampling units, thereby being able to significantly reduce the area of the column memory circuit and well ensuring the circuit performance. By using the column memory circuit provided by the present invention, the cost of the image sensor can be significantly reduced, and the column memory circuit provided by the present invention can be well applied to low-cost image sensors.

[0068] In addition, each functional module in each embodiment herein may be integrated together to form an independent part, may also be each module existing alone, or two or more modules may be integrated to form an independent part.

[0069] The above description is only a description of the preferred embodiments of the column memory circuit, chip, image sensor, and imaging device provided by the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure belong to the protection scope of the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations fall within the scope of the present invention and its equivalent technologies, the present invention also intends to include these modifications and variations.

Claims

1. A column memory circuit for an image sensor, characterized in that: The method comprises M×N memory modules, N readout modules and a data transmission module, wherein the correlated double sampling unit of the column memory circuit is arranged in the data transmission module; the first end of the memory module is configured to receive a first data signal, the second end of the memory module is coupled to the first end of the readout module corresponding thereto, and the second end of the readout module is coupled to the data transmission module, and M≥2; The storage module is configured to convert the received first data signal into a second data signal, the readout module is configured to send the received second data signal to the data transmission module, and the data transmission module is configured to perform correlated double sampling processing on the second data signal through the correlated double sampling unit to obtain and output a third data signal.

2. The column memory circuit according to claim 1, characterized in that: The correlated double sampling unit includes a plurality of first transistors.

3. The column memory circuit according to claim 1, characterized in that: Each of the memory modules comprises a first latch and a buffer unit coupled in sequence, each of the readout modules comprises a trigger and a multiplexer coupled in sequence, and the data transmission module comprises a transcoding unit, a second latch, the correlated double sampling unit and a data interface unit coupled in sequence; The first latch is configured to latch the first data signal and send the latched first data signal to the buffer unit when receiving the first control signal of the image sensor, and the buffer unit is configured to buffer the first data signal to obtain the second data signal and send the second data signal to the trigger; The trigger sends the second data signal to the multiplexer when receiving the second control signal of the image sensor, and the multiplexer is configured to select the corresponding second data signal according to the third control signal of the image sensor and send it to the transcoding unit; the transcoding unit is configured to transcode the second data signal to obtain a first group of fourth data signals for sending to the second latch, and after obtaining the first group of fourth data signals, transcode the subsequently received second data signal to obtain a second group of fourth data signals for sending to the correlated double sampling unit; the second latch is configured to latch the first group of fourth data signals when receiving the fourth control signal; the correlated double sampling unit is configured to perform correlated double sampling processing according to the first group of fourth data signals and the second group of fourth data signals to obtain the third data signal.

4. The column memory circuit according to claim 3, characterized in that: The transcoding unit includes a plurality of second transistors.

5. The column memory circuit according to claim 3, characterized in that: The second data signal is encoded in a Gray code manner, and the first group of fourth data signals, the second group of fourth data signals, and the third data signal are encoded in a binary code manner.

6. A chip for an image sensor, characterized in that: The column memory circuit according to any one of claims 1 to 5 is integrated on the chip.

7. An image sensor, characterized in that: The method comprises the column memory circuit according to any one of claims 1 to 5 or the chip according to claim 6.

8. The image sensor according to claim 7, characterized in that: The image sensor further comprises a digital circuit area and a pixel array, and the data transmission module of the column memory circuit is arranged in the digital circuit area; The pixel array is configured to convert the collected image light signal into the first data signal, the column memory circuit is configured to convert the first data signal into the second data signal and convert the second data signal into the third data signal through the data transmission module located in the digital circuit area, and the image processor is configured to process the third data signal to obtain a target image of the object to be collected.

9. The image sensor according to claim 8, characterized in that: The data transmission module is arranged in the digital circuit area by using a digital chip design tool.

10. An imaging device, characterized in that: The method comprises the column memory circuit according to any one of claims 1 to 5, the chip according to claim 6, or the image sensor according to any one of claims 7 to 9.

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