Signal detection unit, image sensor and self-checking method

Abstract

The invention provides a signal detection unit, an image sensor and a self-checking method. The signal detection unit comprises a reset clamping voltage line for transmitting a reset detection signal and an image clamping voltage line for transmitting an image detection signal, the reset clamping voltage line is used for transmitting a reset detection signal sent by the control circuit, and the image clamping voltage line is used for transmitting an image detection signal sent by the control circuit; and the reset detection signal and the image detection signal are transmitted by different clamping voltage lines, so that interference caused by transmission of the image detection signal and the reset detection signal in the same clamping voltage line is avoided.

Description

Technical Field

[0001] This application belongs to the technical field of image sensors, and particularly relates to a signal detection unit, an image sensor, and a self-checking method. Background Art

[0002] With the continuous intelligentization of the automotive industry, more and more image sensors are applied to automobiles. To ensure the safety of the entire automotive system, higher safety performance requirements are also put forward for the image sensors themselves, including the ability to identify errors and give alarm information to the outside once an internal error occurs in the image sensor. The traditional image sensor technical solutions cannot achieve real-time self-checking of pixels and readout circuits, and there are risks in application in the automotive system.

[0003] In the related art, for the reset detection signal and the image detection signal used in the signal detection of the image sensor, the driving output voltage needs to first pass through a switch and then be transmitted through a relatively long transmission line and enter the large array source follower load. Due to the influence of the parasitic resistance and parasitic capacitance existing on the transmission line, the voltage on the long transmission line takes a long time to reach a stable state after the switch is switched, and the sampling and quantization processes of it occur in an unstable state, resulting in large errors. Due to the limitation of the sampling and quantization time, there is not enough time for it to reach a stable state. Summary of the Invention

[0004] The purpose of this application is to provide a signal detection unit, an image sensor, and a self-checking method, aiming to solve the problem of interference existing in the traditional reset detection signal and image detection signal due to the use of the same bus for transmission.

[0005] In the first aspect of the embodiment of this application, a signal detection unit is proposed. The signal detection unit is correspondingly arranged with the photosensitive pixel units in the photosensitive pixel area. The photosensitive pixel units are used to output pixel data through a readout circuit under the control of a control circuit;

[0006] The signal detection unit is used to receive the input signal sent by the control circuit and output a corresponding output signal through the readout circuit, so as to detect the readout circuit or the control circuit according to the input signal and the output signal;

[0007] Wherein, the signal detection unit at least includes:

[0008] A reset clamping voltage line for transmitting a reset detection signal and an image clamping voltage line for transmitting an image detection signal; the reset clamping voltage line is used to transmit the reset detection signal sent by the control circuit, and the image clamping voltage line is used to transmit the image detection signal sent by the control circuit; the reset detection signal and the image detection signal are transmitted through different clamping voltage lines to avoid interference caused by transmitting the image detection signal and the reset detection signal in the same clamping voltage line.

[0009] In a second aspect of the embodiments of the present application, an image sensor is provided. The image sensor includes a signal detection area, and the signal detection area includes a plurality of signal detection units as described in any one of the above.

[0010] In a third aspect of the embodiments of the present application, an image sensor self-checking method is provided, which is applied to the image sensor as described in any one of the above. The method includes: determining whether the state of the readout circuit and / or the control circuit is abnormal based on whether the output signal output by the signal detection unit conforms to a preset correspondence relationship with the received input signal.

[0011] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above-mentioned signal detection unit at least includes: a reset clamping voltage line for transmitting a reset detection signal and an image clamping voltage line for transmitting an image detection signal; the reset clamping voltage line is used to transmit the reset detection signal sent by the control circuit, and the image clamping voltage line is used to transmit the image detection signal sent by the control circuit. The reset detection signal and the image detection signal are transmitted through different clamping voltage lines to avoid interference caused by transmitting the image detection signal and the reset detection signal in the same clamping voltage line. Description of the Drawings

[0012] Figure 1 It is a basic structural block diagram of an image sensor system;

[0013] Figure 2 It is a schematic diagram of a pixel circuit corresponding to a pixel unit in an image sensor;

[0014] Figure 3 It is a schematic diagram of an application scenario of the signal detection unit proposed by the present invention;

[0015] Figure 4 It is a schematic structural diagram of the signal detection unit provided by the embodiments of the present application;

[0016] Figure 5A It is a schematic structural diagram of a signal detection unit provided by the embodiments of the present application;

[0017] Figure 5B It is a transmission system diagram provided by the embodiments of the present application;

[0018] Figure 5C Schematic diagram of a structural deformation example of a signal detection unit provided by an embodiment of the present application;

[0019] Figure 6A Schematic diagram of another signal detection unit provided by an embodiment of the present application;

[0020] Figure 6B Another transmission system diagram provided by an embodiment of the present application;

[0021] Figure 6C Schematic diagram of the structure of a switch in another signal detection unit provided by an embodiment of the present application;

[0022] Figure 7 An image sensor architecture configured with a signal detection area provided by an embodiment of the present application. Detailed implementation manners

[0023] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0024] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0025] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0026] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0027] Figure 1Shown is a basic structural block diagram of an image sensor system. The image sensor includes a readout circuit and a control circuit connected to a pixel array. Additionally, a functional logic unit is connected to the readout circuit, and the readout circuit and the control circuit are connected to a status register to implement control of the pixel array. The pixel array includes a plurality of pixels (P1, P2, P3) arranged in rows (R1, R2, R3…Ry) and columns (C1, C2, C3…Cx). Pixel signals output by the pixel array are output to the readout circuit via column lines. In some applications, after the pixels acquire image data, they are read out in a readout mode specified by the status register and then transmitted to the functional logic unit. In a specific implementation, the readout circuit may include an analog-to-digital conversion (ADC) circuit and other circuits.

[0028] In certain applications, the status register may include a programmed selection system for determining whether the readout system exposes and reads out through a rolling shutter mode or a global shutter mode. The functional logic unit may store the original image data or the image data after image processing. In some implementations, the readout circuit may read out one row of image data along the readout column lines at a time. Of course, other methods may also be used to read out the image data. The operation of the control circuit can be determined by the current settings of the status register. For example, the control circuit generates a shutter signal for controlling image acquisition. In certain applications, this shutter signal may be a global exposure signal, enabling all pixels of the pixel array to simultaneously acquire their image data through a single acquisition window. In other applications, this shutter signal may also be a rolling exposure signal, enabling the pixels of each pixel row of the pixel array to continuously perform exposure reading operations through the acquisition window.

[0029] Figure 2 Shown is a schematic diagram of a pixel unit in an image sensor. As Figure 2 shown, each pixel unit includes a photoelectric conversion element (e.g., a photodiode) and a pixel circuit (shown as the transistors within the dashed box in the figure). The photodiode may be a buried photodiode (PPD) applied in the current image sensor. In an application example, the pixel circuit includes a reset transistor (RST), a source follower transistor (SF), and a pixel selection transistor (RS), connected to as Figure 2The transfer transistor (TX) and photodiode shown in [Fig.]. In an application example of a stacked structure, the pixel circuit includes a reset transistor, a source follower transistor, and a pixel selection transistor disposed on a first circuit chip, and further includes a transfer transistor disposed on a second circuit chip. The photodiode in the second circuit chip is connected to other transistors in the first circuit chip based on the transfer transistor. In a further application example, the pixel circuit may further include a gain control transistor (DCG) connected between a floating diffusion region (FD) and the reset transistor. During operation, the photoelectric conversion element generates photo charges in response to incident light during exposure. The transfer transistor connects a transfer signal, which controls the transfer transistor to transfer the charges accumulated in the photoelectric conversion element to the floating diffusion region. The reset transistor is connected between a power supply voltage and the floating diffusion region, and responds to a reset signal to reset the sensor pixel circuit (e.g., discharging or charging the floating diffusion region and the photodiode to the current voltage). The floating diffusion region is connected to the gate of the source follower transistor. The source follower transistor is connected between the power supply voltage and the pixel selection transistor, responds to the potential of the floating diffusion region and outputs it. The pixel selection transistor connects the source follower transistor and the bit line, and realizes pixel selection readout in response to a pixel selection control signal and outputs it to the readout column.

[0030] Among them, the image sensor includes multiple functional circuits, and each functional circuit can affect the image sensor to output an accurate image signal. For example, an error in the readout circuit will cause the image sensor to output an incorrect image signal; an error in the relevant circuit in the control circuit will also cause the image sensor to output an incorrect image signal, such as the relevant circuit for outputting the pixel selection signal.

[0031] Existing image sensors may include: a pixel array and a control circuit and a readout circuit coupled to the pixel array. The control circuit is configured to drive the pixel array to generate an image signal. The control circuit includes multiple control sub-circuits. In some implementations, each control sub-circuit is used to drive at least one row of pixels. The readout circuit is configured to read out the image signal generated by the pixel array, convert it into a digital signal, and output it, such as a binary digital signal. Similarly, the readout circuit includes multiple readout sub-circuits. In some implementations, each readout sub-circuit is used to read out at least one column of pixels.

[0032] Specifically, the pixel array may include a plurality of pixels arranged in an array along a plurality of row lines and a plurality of column lines. The pixels may include a photoelectric conversion element configured to generate charges in response to incident light, such as a photodiode, a phototransistor, a pinned photodiode, etc. The control circuit may include a row decoder and a row driver having required timing circuits. The readout circuit may include a column decoder and a column driver having required timing circuits. The control circuit and the readout circuit are also coupled to a status register. After each pixel acquires its image signal or image charge, the image signal is read out by the readout circuit according to the readout mode set by the status register and then transmitted to the functional logic unit. The functional logic unit may store the image data or may process the image data according to later image effects (e.g., cropping, rotating, removing red-eye, adjusting brightness, adjusting contrast, or other means), and may also perform other data processing according to requirements.

[0033] Among them, the readout circuit may include an amplification circuit, an analog-to-digital conversion circuit, etc. The status register may include a digitally programmed selection system for determining the readout mode. The readout circuit may read out the image signals row by row along the readout column lines, or may use other techniques to read out the image signals, for example, serial readout or fully parallel readout of all pixels. Each row in the pixel array may correspond to a row driving unit (which may be a part of the control sub-circuit), and the row driving unit is configured to output a plurality of signals to the identified pixels or pixel rows. For example, if the image sensor includes one thousand rows of pixels, one thousand row driving units may be configured, and a plurality of control signals include pixel selection signals, row reset signals, and transfer signals. When receiving each signal, the pixel array may perform various functions on the identified pixels and transfer the charges of one or more pixels in the identified pixel row.

[0034] As can be seen from the above description, the failure of each functional circuit will cause the image sensor to output an incorrect image.

[0035] In order to detect each functional circuit, in the related art, a signal detection unit is designed to detect the control circuit and the readout circuit. However, there are often problems of mutual influence between the detected signals in the signal detection unit in the related art. Especially during the process of signal switching, interference is easily generated, and unnecessary time delay will be caused during the provision of input signals.

[0036] Based on this, the present application proposes a new signal detection unit.

[0037] Figure 3 FIG. shows a schematic structural diagram of a signal detection unit provided by a preferred embodiment of the present application. For the convenience of description, only the parts related to this embodiment are shown and are described in detail as follows:

[0038] A signal detection unit 10, the signal detection unit 10 is correspondingly arranged with the photosensitive pixel unit 11 in the photosensitive pixel area. The above-mentioned photosensitive pixel unit 11 is used to output pixel data through the readout circuit 13 under the control of the control circuit 12.

[0039] The above-mentioned signal detection unit 10 is used to receive the input signal sent by the above-mentioned control circuit 12 and output a corresponding output signal through the above-mentioned readout circuit 13, so as to detect the above-mentioned readout circuit 13 or the above-mentioned control circuit 12 according to the above-mentioned input signal and the above-mentioned output signal.

[0040] Among them, the above-mentioned input signal includes a reset detection signal and an image detection signal.

[0041] Among them, the above-mentioned signal detection unit 10 at least includes: a reset clamping voltage line 110 for transmitting the reset detection signal and an image clamping voltage line 120 for transmitting the image detection signal.

[0042] The above-mentioned reset clamping voltage line 110 is used to transmit the reset detection signal sent by the above-mentioned control circuit, and the above-mentioned image clamping voltage line 120 is used to transmit the image detection signal sent by the above-mentioned control circuit.

[0043] The above-mentioned reset detection signal and the above-mentioned image detection signal are transmitted through different clamping voltage lines to avoid interference caused by transmitting the above-mentioned image detection signal and the above-mentioned reset detection signal in the same clamping voltage line. In the above technical solution of the present application, by transmitting the reset detection signal and the above-mentioned image detection signal through different clamping voltage lines, it is possible to avoid the interference between the reset detection signal and the above-mentioned image detection signal when using the same clamping voltage line for transmission, and prevent the delay caused by the switching between the two.

[0044] In some embodiments, as Figure 4 shown, the above-mentioned signal detection unit 10 further includes a first detection signal input module 101, a second detection signal input module 102 and an output module 103, where:

[0045] The above-mentioned first detection signal input module 101 is connected to the above-mentioned reset clamping voltage line 110 to receive the above-mentioned reset detection signal.

[0046] The above-mentioned second detection signal input module 102 is connected to the above-mentioned image clamping voltage line 120 to receive the above-mentioned image detection signal.

[0047] The above-mentioned output module 103 is connected to the above-mentioned first detection signal input module 101 and the second detection signal input module 102 to receive the output results of the two and output the corresponding above-mentioned output signal.

[0048] In this embodiment, the above-mentioned first detection signal input module 101 can input a reset detection signal, and the above-mentioned second detection signal input module 102 can input an image detection signal.

[0049] In one implementation, the above-mentioned first detection signal input module 101 and the above-mentioned second detection signal input module 102 perform conversion and output of the above-mentioned reset detection signal and the above-mentioned image detection signal based on the same or different amplification output elements.

[0050] In one implementation, the above-mentioned output module 103 includes at least one selection output element, and the above-mentioned output module 103 outputs the result obtained by amplifying and outputting the corresponding input module based on the same or different above-mentioned selection output elements to obtain the above-mentioned output signal.

[0051] In this embodiment, the above-mentioned amplification output element and selection output element can be implemented using CMOS (Metal-Oxide-Semiconductor). Through multiple CMOSs, different connection methods are used to form the above-mentioned amplification output element and selection output element. Among them, the amplification output element can be set corresponding to the source follower transistor SF in the image sensor pixel circuit, and the selection output element can be set corresponding to the pixel selection transistor RS in the image sensor pixel circuit, so that the data corresponding to the output can be quantified by the readout circuit to realize the detection of the signal detection unit.

[0052] See Figure 5A , the above-mentioned reset clamp voltage line 110 includes: a first clamp voltage line 21. The above-mentioned image clamp voltage line 120 includes: a third clamp voltage line 23.

[0053] The above-mentioned signal detection unit 10 adopts a first connection mode, including: a first source follower transistor SF1 (amplification output element), an image selection transistor RS2 (selection output element), a second source follower transistor SF2 (amplification output element), and a reset selection transistor RS1 (selection output element). Among them:

[0054] The gate of the above-mentioned first source follower transistor SF1 is physically connected to the first clamp voltage line 21, and the first clamp voltage line 21 is used to provide a first reset detection input signal.

[0055] The drain of the above-mentioned first source follower transistor SF1 is connected to the power supply VDD.

[0056] The source of the above-mentioned first source follower transistor SF1 is coupled to the drain of the above-mentioned reset selection transistor RS1.

[0057] The gate of the above-mentioned reset selection transistor RS1 is physically connected to the second clamping voltage line 22, and the second clamping voltage line 22 provides a reset selection signal for the reset selection transistor.

[0058] The source of the reset selection transistor RS1 is coupled to the corresponding column line to output a corresponding first reset detection output signal through the column line.

[0059] The gate of the second source follower transistor SF2 is physically connected to the third clamping voltage line 23.

[0060] The third clamping voltage line 23 is used to provide a first image detection input signal.

[0061] The drain of the second source follower transistor SF2 is connected to the power supply.

[0062] The source of the second source follower transistor SF2 is coupled to the drain of the image selection transistor RS2.

[0063] The gate of the image selection transistor RS2 is physically connected to the fourth clamping voltage line 24, and the fourth clamping voltage line 24 provides an image selection signal for the image selection transistor.

[0064] The source of the image selection transistor RS2 is coupled to the corresponding column line to output a first image detection output signal through the column line.

[0065] In this embodiment, the third clamping voltage line 23 transmits the image detection signal, and the first clamping voltage line 21 transmits the reset detection signal. The image detection signal and the reset detection signal are transmitted through two different clamping voltage lines.

[0066] Further, as Figure 5B shown, a connection manner of a signal detection unit based on Figure 5A shown is displayed. In this embodiment, the first clamping voltage line 21 (corresponding to the first reset detection input signal) and the third clamping voltage line 23 (corresponding to the first image detection input signal) are separately arranged. Further, the two can directly provide a set input voltage from the control circuit end, as shown by Vrst and Vsigx in the upper right box in the figure. Thus, the voltage switching is not required at the transmission line end, and the voltage switching is performed based on the selection output element. For example, the control of RSrst and RSsig shown on the right side of the figure. Based on the above design, interference between different signal transmissions and delay caused by different signal switching can be prevented, and the uneven influence received by large array pixels can be prevented.

[0067] See Figure 5CAs shown, in one embodiment, the configuration of the signal detection unit is improved. That is, the signal detection unit 10 still adopts the first connection mode and still includes: a first source follower transistor SF1 (amplifying output element), an image selection transistor RS2 (selecting output element), a second source follower transistor SF2 (amplifying output element), and a reset selection transistor RS1 (selecting output element). Different from the above example, the first source follower transistor SF1 (amplifying output element) and the second source follower transistor SF2 (amplifying output element) have different designs. In this example, SF1 and SF2 are in a parallel connection mode of SF >= 2. Based on the above design, the transmission effect can be effectively improved and the noise can be optimized.

[0068] See Figure 6A , in one embodiment, the above-mentioned reset clamping voltage line 110 includes a fifth clamping voltage line 43. The above-mentioned image clamping voltage line 120 includes a sixth clamping voltage line 44.

[0069] The above signal detection unit adopts the second connection mode and includes: a third source follower transistor 41 (amplifying output element) and a pixel selection transistor 42 (selecting output element). Among them:

[0070] The gate of the above-mentioned third source follower transistor 41 is connected to the sixth clamping voltage line 44 and the fifth clamping voltage line 43.

[0071] The above-mentioned fifth clamping voltage line 43 is used to provide a second reset detection input signal.

[0072] The above-mentioned sixth clamping voltage line 44 is used to provide a second image detection input signal.

[0073] The drain of the above-mentioned third source follower transistor 41 is connected to the power supply VDD.

[0074] The source of the above-mentioned third source follower transistor 41 is coupled to the drain of the above-mentioned pixel selection transistor 42;

[0075] The gate of the above-mentioned pixel selection transistor 42 is connected to the seventh clamping voltage line 45, and the seventh clamping voltage line 45 is used to provide a pixel selection signal.

[0076] The source of the above-mentioned pixel selection transistor 42 is coupled to the corresponding column line to output a corresponding output signal through the above-mentioned column line, which can be a second reset detection output signal or a second image detection output signal.

[0077] In this embodiment, the fifth clamping voltage line 43 is used to transmit the reset detection signal, and the sixth clamping voltage line 44 is used to transmit the image detection signal, achieving the technical effect of transmitting the reset detection signal and the image detection signal through different clamping voltage lines.

[0078] In one embodiment, a first switch module 46 is provided on the fifth clamping voltage line 43. When the first switch module 46 is closed, the fifth clamping voltage line 43 transmits a second reset detection input signal to the third source follower transistor SF3.

[0079] A second switch module 47 is provided on the sixth clamping voltage line 44. When the second switch module 47 is closed, the sixth clamping voltage line 44 transmits a second image detection input signal to the third source follower transistor SF3.

[0080] In this embodiment, by controlling the opening and closing of the first switch module 46, the transmission control of the reset detection signal on the fifth clamping voltage line 43 can be achieved. By controlling the opening and closing of the second switch module 47, the control of the image detection signal on the sixth clamping voltage line 44 can be achieved.

[0081] Figure 6B For Figure 6A the transmission system diagram, the first switch module and the second switch module are located near the third source follower transistor 41, and are arranged close to the third source follower transistor 41, avoiding signal distortion and deformation caused by long-distance transmission of signals after the switch is opened and closed due to setting the switch at a remote end. Among them, the switching method of the first switch module and the second switch module can be seen as shown by Srst and Ssigx in the figure; further, both can directly provide a set input voltage from the control circuit end, as shown by Vrst and Vsigx in the upper right square in the figure, so that the voltage switching is not required at the transmission line end.

[0082] As Figure 6C shown, a way to implement the switch in the first switch module and the second switch module can be the implementation method of two opposite NMOS transistors and PMOS transistors, which can be beneficial to effectively implement switch control and the switching of the corresponding detection signals in the way of this embodiment.

[0083] In some embodiments, the number of the reset clamping voltage lines is one to provide one of the reset detection signals, and the number of the image clamping voltage lines is at least one to provide at least one of the image detection signals. Refer to Figure 5B and Figure 6B shown, both show one reset clamping voltage line Vrst and four image clamping voltage lines V sig0 、V sig1 、V sig2 、V sig3 . For example, refer to Figure 5B , the reset clamping voltage line Vrst is one, providing one reset detection signal, and the image clamping voltage lines (V sig0 , V sig1 , V sig2, V sig3 ) There are four, each providing an image detection signal. SF1, RS1, SF2, and RS2 connected to the same column line form a basic sub-unit, that is, a signal detection unit. This basic sub-unit is connected to the column line bitline0 and is connected to the image clamping voltage line V sig0 . An adjacent basic sub-unit connected to the column line bitline1 is connected to the image clamping voltage line V sig1 , and so on. The basic sub-unit connected to the column line bitline2 is connected to the image clamping voltage line V sig2 , and the basic sub-unit connected to the column line bitline3 is connected to the image clamping voltage line V sig3。

[0084] In some embodiments, multiple adjacent basic sub-units form a basic combined sub-region. In this basic combined sub-region, the number of basic sub-units included is set to be the same as the number of image clamping voltage lines. According to the arrangement order of the image clamping voltage lines, each basic sub-unit is sequentially connected to each image clamping voltage line. The advantage of this is that since the image clamping voltage lines connected by any two adjacent basic sub-units are different, the image detection signals input to any two adjacent basic sub-units are different, which will result in different output signals of any two adjacent basic sub-units. This is conducive to identifying the output signals of each basic sub-unit, avoiding the confusion caused by the same output signals of two adjacent basic sub-units and making it difficult to distinguish the output signals of each basic sub-unit. Thus, it can also further identify whether there is a wiring connection error between adjacent basic sub-units.

[0085] In some embodiments, the output results of each sub-unit in a basic combined sub-region are stored in a storage region. In this storage region, multiple sub-storage regions can be set, and each sub-storage region stores the output results of each basic sub-unit in the above basic combined sub-region. The address of each storage sub-region can be set as the address of the corresponding sub-unit, or can be set as the column line identifier.

[0086] In a second aspect, the present application proposes an image sensor. The above image sensor includes a signal detection region, and the above signal detection region includes a plurality of signal detection units as described in any one of the above. For example, the above signal detection region may include a plurality of signal detection units connected in parallel as described in any one of the above.

[0087] In some embodiments, a plurality of the above-described detection pixel units connected in parallel in the above-described signal detection region form a plurality of signal detection groups. Among them, each of the above-described signal detection groups includes at least two of the above-described signal detection units, and each of the above-described signal detection groups corresponds to one of the above-described reset clamping voltage lines and at least two of the above-described image clamping voltage lines to provide different above-described image detection signals. The number of signal detection units in a signal detection group can be set according to actual performance requirements, cost, spatial resources of the image sensor, etc. In a further optional example, the signal detection units correspond one-to-one with the columns in the pixel array. Thus, it can be considered that the number of columns in the pixel array is distributed into several signal detection groups.

[0088] For example, Figure 5A and Figure 5B in, SF1, RS1, SF2, and RS2 connected to the same column line are a basic subunit. This basic subunit is connected to the column line bitline0 and is connected to the image clamping voltage line Vsig0. An adjacent basic subunit connected to the column line bitline1 is connected to the image clamping voltage line Vsig1, and so on. The basic subunit connected to the column line bitline2 is connected to the image clamping voltage line Vsig2, and the basic subunit connected to the column line bitline3 is connected to the image clamping voltage line Vsig3.

[0089] In some embodiments, a plurality of adjacent basic subunits form a signal detection group. In this signal detection group, the number of included basic subunits is set to be the same as the number of image clamping voltage lines. According to the arrangement order of the image clamping voltage lines, each basic subunit is sequentially connected to each image clamping voltage line. The advantage of this is that since the image clamping voltage lines connected by any two adjacent basic subunits are different, the image detection signals input to any two adjacent basic subunits are different, which will result in different output signals of any two adjacent basic subunits. This is beneficial for identifying the output signals of each basic subunit, avoiding confusion caused by the same output signals of two adjacent basic subunits and making it difficult to distinguish the output signals of each basic subunit. Thus, it can also further identify whether there is a wiring connection error between adjacent basic subunits.

[0090] In some embodiments, the output result of each subunit in a signal detection group is stored in a corresponding storage area. In this storage area, a plurality of sub-storage areas can be set, and each sub-storage area stores the output result of each basic subunit in the above-described signal detection group. The address of each storage sub-area can be set as the address of the corresponding subunit, or it can be set as the column line identifier.

[0091] See Appendix Figure 7, the above image sensor includes a pixel array, the pixel array includes the photosensitive pixel region 61 and the signal detection region, the photosensitive pixel region includes M rows and N columns of photosensitive pixel units arranged in an array, and the signal detection region includes:

[0092] The first signal detection region 621 includes n columns of the above signal detection units corresponding to the N columns of the above photosensitive pixel units in the photosensitive pixel region; each of the above signal detection units is used to receive a first input signal sent by the control circuit 12 and output a corresponding first output signal through the above readout circuit 13, so as to determine whether the state of the above readout circuit 13 is normal according to the above first input signal and the above first output signal. n is less than or equal to N, and n and N are natural numbers greater than 0; further, for the readout circuit, it can also be a way that one column of the above signal detection units corresponds to one readout unit. For example, in the configuration of SSADC, the readout circuit can realize the readout of the pixel array and the first signal detection region; and / or,

[0093] The second signal detection region 622 includes m rows of the above signal detection units corresponding to the M rows of the above photosensitive pixel units in the photosensitive pixel region; each of the above signal detection units is used to receive a second input signal sent by the control circuit 12 and output a corresponding second output signal through the above readout circuit 13 under the control of the above control circuit 12, so as to determine whether the state of the above control circuit 12 is normal according to the above second input signal and the above second output signal. Wherein, m is less than or equal to M, and m and M are natural numbers greater than 0. For example, it can be that one signal detection unit corresponds to each row of pixels.

[0094] In one implementation, taking the readout circuit detection as an example, by encoding the signals of each column of signal detection units, a unique row code can be determined in advance, that is, the input signals of each signal detection unit in a row are encoded and set. For example, the n columns of signal detection units in a row form an n-bit a-ary number, and the corresponding n-bit a-ary number is pre-stored in the image sensor. For the signal detection unit, when the image sensor reads out the signal, the output signal of the signal detection unit is also read out and compared with the pre-stored a-ary number (for example, it can represent the preset output signal corresponding to the signal detection unit under the selected preset clamping voltage). If it is determined that it does not correspond to the pre-stored a-ary number (that is, the input signal and the output signal of the signal detection unit do not correspond), the pixel address (column address) where the error occurs can be output, and thus the faulty readout circuit can be determined.

[0095] It is worth mentioning that each signal detection unit in the detection unit area also requires corresponding control units for control and is read out by the readout circuit. Therefore, each signal detection unit is configured with a corresponding pixel address. In addition, the hardware part has also added corresponding row lines and corresponding control units. The control unit corresponding to the detection unit area can be integrated into the existing control circuit or can be separately provided additionally.

[0096] In some embodiments, when the above-mentioned signal detection unit is used to receive the above-mentioned first input signal sent by the above-mentioned control circuit and output the above-mentioned first output signal through the above-mentioned readout circuit, the above-mentioned signal detection unit is configured in a first connection mode.

[0097] In this embodiment, refer to Figure 5A the schematic diagram of the first connection mode of the signal detection unit shown. In this mode, the signal detection unit is more suitable to be set at the position of the first signal detection area 621 in Figure 7

[0098] In some embodiments, when the above-mentioned signal detection unit is used to receive the above-mentioned second input signal sent by the above-mentioned control circuit and output the above-mentioned second output signal through the above-mentioned readout circuit under the control of the above-mentioned control circuit, the above-mentioned signal detection unit is configured in a second connection mode.

[0099] In this embodiment, refer to Figure 6A the schematic diagram of the second connection mode of the signal detection unit shown. In this mode, the signal detection unit is more suitable to be set at the position of the second signal detection area 622 in Figure 7

[0100] In some embodiments, the above-mentioned control circuit includes a signal generation circuit, and the signal generation circuit is configured to generate the above-mentioned input signal and output the generated above-mentioned input signal to the above-mentioned signal detection unit to obtain the corresponding above-mentioned output signal. Among them, the above-mentioned input signal can be a predetermined voltage signal, and an existing circuit can be used to form the signal generation circuit to provide the above-mentioned predetermined voltage signal, so as to correspondingly obtain the output voltage signal, thereby realizing circuit detection. This circuit can belong to the control circuit and is arranged in the control area.

[0101] In some embodiments, the above-mentioned control circuit includes a pixel driving circuit, which is at least configured to output a pixel control selection signal (the gate signal of the pixel selection transistor) and output the above-mentioned pixel control selection signal to the above-mentioned photosensitive pixel unit, so that the above-mentioned photosensitive pixel unit outputs the corresponding above-mentioned pixel data through the above-mentioned readout circuit under the control of the above-mentioned pixel control selection signal. Of course, the pixel driving circuit can provide control signals for other transistors in the pixel circuit of the pixel unit, such as the gate signal of the transfer transistor, etc.

[0102] ​​In some embodiments, the above pixel driving circuit is further configured to output the above input signal to the above signal detection unit, and generate the corresponding above output signal through the above readout circuit based on the above input signal, so as to implement the detection of the pixel driving circuit. In this embodiment, the same address information can be configured to generate the above input signal. In one implementation manner, the selection output element in the signal detection unit and the pixels of the corresponding output row received by the pixel driving circuit are configured with the same address information for detection.

[0103] In some embodiments, the above control circuit further includes a first determination module. When the above output signal output by the above signal detection unit does not conform to the preset corresponding relationship with the above input signal received by the above signal detection unit, the first determination module determines that the state of the above readout circuit and / or the above control circuit is abnormal. Among them, the first determination module can be implemented based on an existing comparison circuit, compare the output signal of the signal detection unit with a predetermined signal, and it can be configured in the image processing circuit.

[0104] In some embodiments, the above control circuit further includes an address output module, configured to output the address corresponding to the above signal detection unit when the first determination module determines that the state of the above readout circuit and / or the above control circuit is abnormal. In one implementation manner, it can be implemented by using an existing circuit, and when a certain condition is met, the corresponding address information in the register is output or displayed.

[0105] In this embodiment, when the above first output signal does not conform to the preset corresponding relationship with the above first input signal, the pixel column address corresponding to the above first output signal is output, corresponding to the first connection mode;

[0106] And / or, when the above second output signal does not conform to the preset corresponding relationship with the above second input signal, the pixel row address corresponding to the above second output signal is output, corresponding to the second connection mode.

[0107] In some embodiments, the above control circuit further includes a second determination module, configured to determine a connection error between readout sub-circuits when it is determined that the state of the above readout circuit is abnormal and in response to the corresponding above output signal being within a preset range. Among them, the second determination module can also be implemented based on an existing comparison circuit, and it can be configured in the image processing circuit.

[0108] In this embodiment, when the output signal does not conform to the preset correspondence relationship with the input signal, it is further determined whether the output signal exceeds the preset range. If it is within the preset range, it is determined that there is an error in the connection between the readout sub-circuits. Specifically, if the first output signal does not exceed the preset range, that is, the output deviation is relatively small, it can be determined that there is a problem with the connection between the readout sub-circuits. If it exceeds this preset range, it may be a connection problem or a problem with the readout sub-circuit itself.

[0109] In one implementation, the above-mentioned preset range is greater than or equal to a first preset value and less than or equal to a second preset value. Among them, the above-mentioned first preset value is greater than or equal to A and less than or equal to B. Wherein, A is the difference between the value of the first output signal in the preset correspondence relationship and 1 / 4 of the value of the first output signal in the preset correspondence relationship, and B is the difference between the value of the first output signal in the preset correspondence relationship and 1 / 8 of the value of the first output signal in the preset correspondence relationship. The above-mentioned second preset value is greater than or equal to C and less than or equal to D. Wherein, C is the sum value of the value of the first output signal in the preset correspondence relationship and 1 / 8 of the value of the first output signal in the preset correspondence relationship, and D is the sum value of the value of the first output signal in the preset correspondence relationship and 1 / 4 of the value of the first output signal in the preset correspondence relationship.

[0110] Specifically, for example, when the input signal of one of the signal detection units is 2V, the output signal in the preset correspondence relationship should be 4V. At this time, A is 4 - 4×(1 / 4) = 3, B is 4 - 4×(1 / 8) = 3.5, C is 4 + 4×(1 / 8) = 4.5, and D is 4 + 4×(1 / 4) = 5. That is, the preset range is (3 to 3.5) to (4.5 to 5). That is, the lower limit of the preset range is 3 to 3.5, and the upper limit of the preset range is (4.5 to 5).

[0111] In a third aspect, the present application proposes an image sensor self-checking method, which is applied to the image sensor as described in any one of the above. The above method includes the following steps:

[0112] Based on whether the output signal output by the signal detection unit conforms to the preset correspondence relationship with the received input signal, it is determined whether the state of the above-mentioned readout circuit and / or the above-mentioned control circuit is abnormal.

[0113] For example, corresponding Figure 5AIn the first connection method shown, it is possible to determine whether the first reset detection input signal and the first reset detection output signal satisfy a preset relationship, or it is also possible to determine whether the first image detection input signal and the first image detection output signal satisfy a preset relationship. Of course, for the output of the pixel array of the image sensor, it is also possible to determine whether the difference between the first reset detection output signal and the first image detection output signal corresponding to the first reset detection input signal and the first image detection input signal satisfies a preset relationship. In addition, corresponding to Figure 6A For the second connection method shown, the above-mentioned determination methods can also be used.

[0114] In some embodiments, before determining that the above-mentioned readout circuit and / or the above-mentioned control circuit is in an abnormal state, the above method may further include the following steps:

[0115] After controlling the reset detection signal transmitted on the reset clamping voltage line to stop transmitting, control the image clamping voltage line to transmit the image detection signal; or, after the image detection signal transmitted on the image clamping voltage line stops transmitting, control the reset detection signal to be transmitted on the reset clamping voltage line.

[0116] In this embodiment, in order to separate the reset detection signal and the image detection signal, the above-mentioned reset detection signal and image detection signal are respectively transmitted using different clamping voltage lines. In addition, this embodiment also controls the timing. The reset detection signal and the image detection signal are transmitted at different timings and there cannot be an overlap in time. After controlling the reset detection signal transmitted on the reset clamping voltage line to stop transmitting, control the image clamping voltage line to transmit the image detection signal, without an overlap in time, which is beneficial to eliminating the mutual influence of the above-mentioned reset detection signal and image detection signal.

[0117] Among them, in one embodiment, the reset detection signal can be controlled when the reset signal of the pixels in the pixel array is read out. For example, it is realized by reading out row by row in a rolling manner. Similarly, the image detection signal can be carried out when the image signal of the pixels in the pixel array is read out. For example, it can be that after the reset detection signal transmitted on the reset clamping voltage line stops transmitting, control the image clamping voltage line to transmit the image detection signal to perform detection corresponding to the correlated double sampling of the pixel array; or it can be that after the image detection signal transmitted on the image clamping voltage line stops transmitting, control the reset detection signal to be transmitted on the reset clamping voltage line to perform detection corresponding to the non-genuine correlated double sampling of the pixel array.

[0118] In some embodiments, when the above signal detection unit is in the second connection mode and there are a first switch module and a second switch module, it includes:

[0119] Control the above-mentioned first switch module to close, and control the above-mentioned second switch module to be in an open state, so that the above-mentioned fifth clamping voltage line transmits a second reset detection signal to the above-mentioned third source follower transistor.

[0120] In this embodiment, when the signal detection unit is in the second connection mode and there are a first switch module and a second switch module, only one of the above-mentioned first switch module and second switch module can be closed and the other can be open at a time point, and it is not possible that the first switch module and the second switch module are both in the closed state at the same time. When controlling the above-mentioned first switch module to close and the above-mentioned second switch module to be in an open state, the fifth clamping voltage line transmits a second reset detection signal to the above-mentioned third source follower transistor. When controlling the above-mentioned first switch module to open and the above-mentioned second switch module to be in a closed state, the sixth clamping voltage line transmits a second image detection signal to the above-mentioned third source follower transistor.

[0121] In some embodiments, in response to the cumulative closing time of the above-mentioned first switch module being equal to a predetermined first time threshold, control the above-mentioned first switch module to open and control the above-mentioned second switch module to close, so that the above-mentioned sixth clamping voltage line transmits a second image detection signal to the above-mentioned third source follower transistor.

[0122] In this embodiment, the cumulative closing time of the first switch module can be counted. When the cumulative closing time of the first switch module is equal to the predetermined first time threshold, a switch needs to be made. Control the above-mentioned first switch module to open and control the above-mentioned second switch module to close. The above-mentioned sixth clamping voltage line transmits a second image detection signal to the above-mentioned third source follower transistor.

[0123] It should be noted that the above time threshold can be set according to actual conditions. For example, for the exposure and readout quantization of each pixel unit in the pixel array, based on the quantization of the reset signal and the image signal, further, the difference between the output signal corresponding to the reset detection signal and the output signal corresponding to the image detection signal can be obtained, and then detection can be realized based on the comparison, that is, matching the correlated double sampling process of the pixels in the pixel unit.

[0124] See Appendix Figure 5B After the reset RSrst signal remains high for a predetermined time period T0, it turns low, and the image RSsig signal turns from low to high, and then switches after remaining high for a predetermined time period T1.

[0125] In some embodiments, when the above-mentioned signal detection unit is in the first connection mode, it includes:

[0126] The control circuit provides a reset selection signal for the reset selection transistor RS1 through the second clamping voltage line. The control circuit provides a pixel image selection signal for the pixel selection transistor RS2 through the fourth clamping voltage line.

[0127] In some embodiments, in response to the cumulative closing time of the reset selection transistor being equal to a predetermined second time threshold, the reset selection transistor is controlled to turn off to disconnect the reset detection signal, and the pixel selection transistor is controlled to turn on to provide the image detection signal.

[0128] In this embodiment, the cumulative closing time of the reset selection transistor can be counted. The second time threshold is the transmission time of the predetermined reset detection signal. When the cumulative closing time of the reset selection transistor is equal to the predetermined second time threshold, a switch is required. The reset selection transistor is controlled to turn off to disconnect the reset detection signal, and the pixel selection transistor is controlled to turn on to provide the image detection signal.

[0129] In some embodiments, when the difference between at least one or both of the reset detection signal and the image detection signal output by the signal detection unit does not conform to a preset corresponding relationship with the corresponding input signal received by the signal detection unit, in response to the output reset detection signal and image detection signal being within a preset range, a connection error between the corresponding sub-circuits of the circuit to be detected is determined.

[0130] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the above-mentioned division of each functional unit and module is used as an example. In practical applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of the present application. The specific working process of the units and modules in the above system can refer to the corresponding process in the foregoing method embodiments and will not be repeated here.

[0131] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0132] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0133] In the embodiments provided in this application, it should be understood that the disclosed device / terminal device and method can be implemented in other ways. For example, the device / terminal device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical or other forms.

[0134] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0135] In addition, the functional units in each embodiment of this application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0136] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-described embodiment methods of this application, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0137] The above-described embodiments are only used to illustrate the technical solutions of this application, rather than to limit them; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A signal detection unit, characterized in that, The signal detection unit is correspondingly arranged with the photosensitive pixel units in the photosensitive pixel region, where: The photosensitive pixel units are used to output pixel data through a readout circuit under the control of a control circuit; The signal detection unit is used to receive an input signal sent by the control circuit and output a corresponding output signal through the readout circuit, so as to detect the readout circuit or the control circuit according to the input signal and the output signal; Wherein, the signal detection unit at least includes: A reset clamping voltage line for transmitting a reset detection signal and an image clamping voltage line for transmitting an image detection signal; the reset clamping voltage line is used to transmit the reset detection signal sent by the control circuit, and the image clamping voltage line is used to transmit the image detection signal sent by the control circuit.

2. The signal detection unit according to claim 1, wherein The signal detection unit further includes a first detection signal input module, a second detection signal input module and an output module, where: The first detection signal input module is connected to the reset clamping voltage line to receive the reset detection signal, the second detection signal input module is connected to the image clamping voltage line to receive the image detection signal, and the output module is connected to the first detection signal input module and the second detection signal input module to receive the output results of both and output the corresponding output signal.

3. The signal detection unit according to claim 2, characterized in that The first detection signal input module and the second detection signal input module perform conversion and output of the reset detection signal and the image detection signal based on the same or different amplification output elements; and / or, the output module includes at least one selection output element, and the output module outputs the results obtained by amplifying and outputting the corresponding input module based on the same or different selection output elements to obtain the output signal.

4. The signal detection unit according to claim 1, characterized in that The signal detection unit is in a first connection mode, including: a first source follower transistor, an image selection transistor, a second source follower transistor, and a reset selection transistor; where: The gate of the first source follower transistor is physically connected to a first clamping voltage line, and the first clamping voltage line is used to provide a first reset detection input signal; The drain of the first source follower transistor is connected to a power supply; The source of the first source follower transistor is coupled to the drain of the reset selection transistor; The gate of the reset selection transistor is physically connected to a second clamping voltage line, and the second clamping voltage line provides a reset selection signal for the reset selection transistor; The source of the reset selection transistor is coupled to a corresponding column line to output a corresponding first reset detection output signal through the column line; The gate of the second source follower transistor is physically connected to a third clamping voltage line; The third clamping voltage line is used to provide a first image detection input signal; The drain of the second source follower transistor is connected to a power supply; The source of the second source follower transistor is coupled to the drain of the image selection transistor; The gate of the image selection transistor is physically connected to a fourth clamping voltage line, and the fourth clamping voltage line provides an image selection signal for the image selection transistor; The source of the image selection transistor is coupled to a corresponding column line to output a corresponding first image detection output signal through the column line.

5. The signal detection unit according to claim 1, characterized in that, The signal detection unit is in a second connection mode and includes: a third source follower transistor and a pixel selection transistor; wherein: The gate of the third source follower transistor is connected to a sixth clamping voltage line and a fifth clamping voltage line; The fifth clamping voltage line is used to provide a second reset detection input signal; The sixth clamping voltage line is used to provide a second image detection input signal; The drain of the third source follower transistor is connected to a power supply; The source of the third source follower transistor is coupled to the drain of the pixel selection transistor; The gate of the pixel selection transistor is connected to a seventh clamping voltage line, and the seventh clamping voltage line is used to provide a pixel selection signal; The source of the pixel selection transistor is coupled to a corresponding column line to output a corresponding output signal through the column line.

6. The signal detection unit according to claim 5, wherein a first switch module is provided on the fifth clamping voltage line; when the first switch module is closed, the fifth clamping voltage line transmits a second reset detection input signal to the third source follower transistor; a second switch module is provided on the sixth clamping voltage line; when the second switch module is closed, the sixth clamping voltage line transmits a second image detection input signal to the third source follower transistor.

7. The signal detection unit according to any one of claims 1 to 6, characterized in that, The number of the reset clamping voltage lines is one to provide one reset detection signal, and the number of the image clamping voltage lines is at least one to provide at least one image detection signal.

8. An image sensor, characterized in that, The image sensor includes a signal detection region, and the signal detection region includes at least one signal detection unit according to any one of claims 1 to 7.

9. The image sensor according to claim 8, wherein The signal detection units in the signal detection region form a plurality of signal detection groups, wherein each signal detection group includes at least two signal detection units, and each signal detection group corresponds to one reset clamping voltage line and at least two image clamping voltage lines to provide different image detection signals.

10. The image sensor according to claim 8, wherein The image sensor includes a pixel array, the pixel array includes the photosensitive pixel region and the signal detection region, the photosensitive pixel region includes M rows and N columns of photosensitive pixel units arranged in an array, and the signal detection region includes: a first signal detection region, including n columns of signal detection units corresponding to the N columns of photosensitive pixel units in the photosensitive pixel region; each signal detection unit is configured to receive a first input signal sent by a control circuit and output a corresponding first output signal through the readout circuit, so as to determine whether the state of the readout circuit is normal according to the first input signal and the first output signal, n is less than or equal to N, and n and N are natural numbers greater than 0; and / or, The second signal detection region includes m rows of the signal detection units respectively corresponding to M rows of the photosensitive pixel units in the photosensitive pixel region; each of the signal detection units is configured to receive a second input signal sent by a control circuit, and output a corresponding second output signal through the readout circuit under the control of the control circuit, so as to determine whether the state of the control circuit is normal according to the second input signal and the second output signal, where m is less than or equal to M, and m and M are natural numbers greater than 0.

11. The image sensor according to claim 10, wherein, When the signal detection unit is configured to receive the first input signal sent by the control circuit and output the first output signal through the readout circuit, the signal detection unit is configured in a first connection mode; When the signal detection unit is configured to receive the second input signal sent by the control circuit and output the second output signal through the readout circuit under the control of the control circuit, the signal detection unit is configured in a second connection mode.

12. The image sensor according to claim 8, wherein The control circuit includes a signal generation circuit configured to generate the input signal and output the generated input signal to the signal detection unit to obtain the corresponding output signal.

13. The image sensor according to claim 8, characterized in that, The control circuit includes a pixel driving circuit configured to at least output a pixel control selection signal and output the pixel control selection signal to the photosensitive pixel unit, so that the photosensitive pixel unit outputs the corresponding pixel data through the readout circuit under the control of the pixel control selection signal.

14. The image sensor according to claim 13, wherein The pixel driving circuit is further configured to output the input signal to the signal detection unit and generate the corresponding output signal through the readout circuit based on the input signal to implement the detection of the pixel driving circuit.

15. The image sensor according to any one of claims 8 to 14, characterized in that The control circuit further includes a first determination module, which, in response to the output signal output by the signal detection unit not conforming to a preset correspondence relationship with the input signal received by the signal detection unit, determines that the state of the readout circuit and / or the control circuit is abnormal.

16. The image sensor according to claim 15, wherein, The control circuit further includes a second determination module configured to, in the case of determining that the state of the readout circuit is abnormal and in response to the corresponding output signal being within a preset range, determine a connection error between readout sub-circuits; and / or, the control circuit further includes an address output module configured to output the address corresponding to the signal detection unit in the case where the first determination module determines that the state of the readout circuit and / or the control circuit is abnormal.

17. An image sensor self-checking method, characterized in that, Applied to the image sensor according to any one of claims 8 to 16, the method includes: Determining whether the state of the readout circuit and / or the control circuit is abnormal based on whether the output signal output by the signal detection unit conforms to a preset correspondence relationship with the received input signal.

18. The image sensor self-check method according to claim 17, wherein Before determining that the state of the readout circuit and / or the control circuit is abnormal, the method further includes: After controlling the reset detection signal transmitted on the reset clamping voltage line to stop transmitting, controlling the image clamping voltage line to transmit the image detection signal; or, After controlling the image clamping voltage line to stop transmitting the image detection signal, control the reset detection signal transmitted on the reset clamping voltage line.

19. The method for self-checking an image sensor according to claim 17, wherein When the signal detection unit is in the second connection mode and there are a first switch module and a second switch module, it includes: Control the first switch module to close and control the second switch module to be in the open state, so that the fifth clamping voltage line transmits a second reset detection signal to the third source follower transistor; In response to the cumulative closing time of the first switch module being equal to a predetermined first time threshold, control the first switch module to open and control the second switch module to close, so that the sixth clamping voltage line transmits a second image detection signal to the third source follower transistor; Alternatively, when the signal detection unit is in the first connection mode, it includes: The second clamping voltage line provides a reset selection signal for the reset selection transistor, and controls the opening and closing of the reset selection transistor through the second clamping voltage line; The fourth clamping voltage line provides an image selection signal for the pixel selection transistor, and controls the opening and closing of the pixel selection transistor through the fourth clamping voltage line; In response to the cumulative closing time of the reset selection transistor being equal to a predetermined second time threshold, control the reset selection transistor to open to disconnect the reset detection signal, and control the pixel selection transistor to close to provide the image detection signal.

20. The method for self-checking an image sensor according to any one of claims 17 to 19, characterized in that, In the case where the difference between at least one or both of the reset detection signal and the image detection signal output by the signal detection unit does not conform to the preset corresponding relationship with the corresponding input signal received by the signal detection unit, in response to the output reset detection signal and image detection signal being within a preset range, determine a connection error between sub-circuits of the corresponding circuit to be detected.

Images