Display device

Abstract

A display device according to the present disclosure includes: a substrate including a plurality of pixel regions, each pixel region having a plurality of sub-pixel regions; a first light emitting device disposed in each of the sub-pixel regions to form a plurality of sub-pixels; a first transistor configured to operate the first light emitting device; a second light emitting device disposed between sub-pixel regions of the plurality of sub-pixel regions; and a second transistor disposed between sub-pixel regions of the plurality of sub-pixel regions and configured to operate the second light emitting device. A bank layer is disposed between sub-pixel regions of the plurality of sub-pixel regions, and a second light emitting device is disposed over the bank layer.

Description

[0001] Cross-reference to related disclosures

[0002] This disclosure claims priority to Korean Patent Publication No. 10-2023-0192423, filed on December 27, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device having an improved aperture ratio and resolution. Background Art

[0004] Recently, the importance of display devices has increased with the development of multimedia. Various display devices, such as liquid crystal displays and organic light-emitting displays, have been proposed.

[0005] A display device includes a plurality of sub-pixels, and a display device is disposed in each sub-pixel to display an image. In a display device, a structure for dividing sub-pixels is required. However, these structures are regions that do not display an image. Summary of the Invention

[0006] It has been found that regions that do not display an image reduce the aperture ratio and / or resolution. An object of this disclosure is to provide a display device having an improved aperture ratio and high resolution.

[0007] In one aspect, a display device according to the present disclosure includes: a substrate including a plurality of pixel regions, each pixel region having a plurality of sub-pixel regions; a first light-emitting device disposed in each sub-pixel region to form a plurality of sub-pixels; a first transistor configured to operate the first light-emitting device; a second light-emitting device disposed between adjacent sub-pixel regions among the plurality of sub-pixel regions; and a second transistor disposed between sub-pixel regions among the plurality of sub-pixel regions and configured to operate the second light-emitting device; wherein a gap between the substrate and the second light-emitting device is greater than a gap between the first light-emitting device and the substrate. In the present disclosure, since the auxiliary sub-pixel region SPa is disposed in a region that does not display an image in a known general display device, the region for displaying an image increases.

[0008] A partition layer is disposed between sub-pixel regions among the plurality of sub-pixel regions, and the second light-emitting device is disposed above the partition layer. The partition layer may be a barrier rib that defines sub-pixel regions therebetween.

[0009] The first light-emitting device includes a first electrode disposed in each of a plurality of sub-pixel regions, a first light-emitting layer on the first electrode, and a second electrode on the first light-emitting layer. The second light-emitting device includes a third electrode disposed on the bank layer, a second light-emitting layer on the third electrode, and a fourth electrode on the second light-emitting layer. The second electrode and the fourth electrode are integrally formed.

[0010] A first pattern and a second pattern are formed in a protrusion structure between the bank layer and the second light-emitting device such that the first pattern and the second pattern are formed to protrude above the bank layer. The first light-emitting layer and the second light-emitting layer are disconnected by the protrusion structure.

[0011] The first transistor includes a first semiconductor layer on a buffer layer, a gate insulating layer covering the first semiconductor layer, a first gate electrode on the gate insulating layer, an interlayer insulating layer covering the first gate electrode, a first source electrode and a first drain electrode on the interlayer insulating layer. The second transistor includes a second semiconductor layer on the buffer layer, a gate insulating layer covering the second semiconductor layer, a second gate electrode on the gate insulating layer, an interlayer insulating layer covering the second gate electrode, a second source electrode and a second drain electrode on the interlayer insulating layer.

[0012] A planarization layer covers the first transistor and the second transistor, and the first drain electrode is electrically connected to the first electrode through a first contact hole formed in the planarization layer. The second drain electrode is electrically connected to the third electrode through a second contact hole formed in the planarization layer, the bank layer, the first pattern, and the second pattern.

[0013] In another aspect, a display device according to the present disclosure may include: a substrate including a plurality of pixels having a plurality of sub-pixel regions and at least one auxiliary sub-pixel region; a first light-emitting device disposed in each of the plurality of sub-pixel regions to form sub-pixels; a second light-emitting device disposed in the auxiliary sub-pixel region to form auxiliary sub-pixels; a first transistor configured to operate the first light-emitting device, and a second transistor disposed in the auxiliary sub-pixel region and configured to operate the second light-emitting device; wherein a gap between the substrate and the second light-emitting device is greater than a gap between the first light-emitting device and the substrate.

[0014] In yet another aspect, the auxiliary sub-pixels may include: a first auxiliary sub-pixel disposed between sub-pixel regions among the plurality of sub-pixel regions; and a second auxiliary sub-pixel disposed at an outer periphery of the pixel.

[0015] In another aspect, the display device may further include a bank layer formed between the plurality of sub-pixel regions and surrounding the outer periphery of the pixel.

[0016] In yet another aspect, the bank layer may include a plurality of opening regions formed through the bank layer, wherein the plurality of sub-pixel regions correspond to the plurality of opening regions.

[0017] In another aspect, the first light-emitting device may be disposed in each of the opening regions.

[0018] In yet another aspect, the second light-emitting devices of the first auxiliary sub-pixel and the second auxiliary sub-pixel may emit the same color as each other.

[0019] In another aspect, the second light-emitting devices of the first auxiliary sub-pixel and the second auxiliary sub-pixel may emit different colors from each other. Description of the Drawings

[0020] Figure 1 is a schematic block diagram of an organic light-emitting display device according to the present disclosure.

[0021] Figure 2 is a schematic block diagram of a sub-pixel of an organic light-emitting display device according to the present disclosure.

[0022] Figure 3 is a circuit diagram conceptually showing a sub-pixel of a display device according to the present disclosure.

[0023] Figure 4 is a plan view schematically showing a structure of a display device according to the present disclosure.

[0024] Figure 5 is a plan view showing a pixel structure of a display device according to the present disclosure.

[0025] Figure 6 is a plan view showing another structure of a pixel of a display device according to the present disclosure.

[0026] Figure 7 is a cross-sectional view of a display device according to an example of the present disclosure.

[0027] Figures 8A to 8H is a view showing a method of manufacturing a display device according to an example of the present disclosure. Detailed Description

[0028] Advantages and features of the present disclosure, and methods for realizing them, will become clear from the examples described in detail below with reference to the accompanying drawings. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the examples set forth herein. The examples are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art to which this disclosure pertains. The present disclosure is defined only by the scope of the appended claims.

[0029] The shapes, sizes, ratios, angles, quantities, etc. of the examples for describing the present disclosure disclosed in the drawings are illustrative, and thus the present disclosure is not limited to what is shown. Throughout the present disclosure, the same reference numerals refer to the same components. In addition, in the following description of the present disclosure, when it is determined that a detailed description of known related art is not necessary to obscure the gist of the present disclosure, its detailed description will be omitted herein. When terms such as "comprising", "having", "including" are used in the present disclosure, other parts may be added unless the term "only" is used herein. When a component is expressed in the singular, it includes the plural unless otherwise specified.

[0030] When analyzing a component, the error range is construed to be included even if not explicitly described.

[0031] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on", "above", "below", "next to", etc., unless "immediately" or "directly" is used, one or more other parts may be located between the two parts.

[0032] When describing a temporal relationship, for example, when a temporal precedence relationship is described as "after", "subsequently", "next", "before", etc., unless "immediately" or "directly" is used, discontinuous cases may also be included.

[0033] Although various components are described using terms such as first, second, etc., these components are not substantially limited by these terms. These terms are only used to distinguish one component from another, and a component is not substantially the second component.

[0034] When describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only used to distinguish an element from other elements, and the nature, order, or quantity of the element is not limited by the terms. When a component is described as "coupled" or "connected" to another component, the component may be directly coupled or connected to the other component, but may be indirectly coupled or connected to the other component without specific description. It should be understood that other components may be "inserted" between each component that is connected or may be connected.

[0035] As used herein, the term "device" may include a display device, such as a liquid crystal module (LCM) including a display panel and a driving unit for driving the display panel, and an organic light emitting display module (OLED module). In addition, the term "device" may also include a notebook computer, a television, a computer monitor, a vehicle electrical device including a device for a vehicle or other types of vehicles, and a set of electronic devices or a set of mobile electronic devices such as a smart phone or an electronic board, which are finished products (complete products or final products) including an LCM and an OLED module.

[0036] Therefore, the device in the present disclosure may include the display device itself, such as an LCM, an OLED module, etc., and application products including an LCM, an OLED module, etc., or a set of devices of the device as an end user.

[0037] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

[0038] The present disclosure can be applied to various display devices. For example, the display device of the present disclosure can be applied to various display devices, such as an organic light emitting display device, a liquid crystal display device, an electrophoretic display device, a quantum dot display device, a micro LED (light emitting device) display device, and a small LED display device. However, in the following description, for the sake of explanation, the organic light emitting display device will be described as an example.

[0039] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 is a schematic block diagram of an organic light emitting display device according to the present disclosure, Figure 2 is a schematic block diagram of a sub-pixel of an organic light emitting display device according to the present disclosure.

[0041] As Figure 1 shown, the organic light emitting display device 100 includes an image processing unit 102, a timing control unit 104, a gate driving unit 106, a data driving unit 107, a power supply unit 108, and a display panel 109.

[0042] The image processing unit 102 outputs image data provided from the outside of the organic light emitting display device and driving signals for driving various devices. For example, the driving signals from the image processing unit 102 may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0043] The image data and the driving signals are provided from the image processing unit 102 to the timing control unit 104. The timing control unit 104 writes and outputs a gate timing control signal GDC for controlling the driving timing of the gate driving unit 106 and a data timing control signal DDC for controlling the driving timing of the data driving unit 107 based on the driving signals from the image processing unit 102.

[0044] The gate driving unit 106 outputs a scan signal to the display panel 109 in response to the gate timing control signal GDC provided from the timing control unit 104. The gate driving unit 106 outputs the scan signal through a plurality of gate lines GL1 to GLm. In this case, the gate driving unit 106 may be formed in the form of an integrated circuit (IC), but is not limited thereto. The gate driving unit 106 includes various gate driving circuits, and the gate driving circuits may be directly formed on the substrate 110. In this case, the gate driving unit 106 may be a gate in panel (GIP).

[0045] The data driving unit 107 outputs a data voltage to the display panel 109 in response to the data timing control signal DDC input from the timing control unit 104. The data driving unit 107 samples and latches the digital data signal DATA provided from the timing control unit 104 to convert it into an analog data voltage based on a gamma voltage. The data driving unit 107 outputs the data voltage through a plurality of data lines DL1 to DLn. In this case, the data driving unit 107 may be mounted on the upper surface of the display panel 109 in the form of an integrated circuit (IC), but is not limited thereto.

[0046] In operation, the power supply unit 108 outputs a high potential voltage VDD and a low potential voltage VSS, etc., to supply them to the display panel 109. The high potential voltage VDD is supplied to the display panel 109 through a first power supply line EVDD, and the low potential voltage VSS is supplied to the display panel 109 through a second power supply line EVSS. In operation, the voltage from the power supply unit 108 is applied to drive the data driving unit 107 or the gate driving unit 106.

[0047] The display panel 109 displays an image based on the data voltage from the data driving unit 108, the scan signal from the gate driving unit 106, and the power from the power supply unit 108.

[0048] The display panel PAN includes a plurality of sub-pixels SP for displaying an image. The sub-pixels SP may include red sub-pixels, green sub-pixels, and blue sub-pixels. In addition, the sub-pixels SP may include white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels. The white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels may be formed in the same region or may be formed in different regions.

[0049] As Figure 2 shown, a sub-pixel SP may be connected to a gate line GL1, a data line DL1, a first power supply line EVDD, and a second power supply line EVSS. According to the configuration of the pixel circuit, the sub-pixel SP may include a plurality of thin film transistors and a storage capacitor. For example, the sub-pixel SP may include two transistors and one capacitor (referred to as 2T1C), but is not limited thereto. The sub-pixel SP may be composed of 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, 8T2C, etc. It should be understood that in the above abbreviations, 3T1C refers to three transistors and one capacitor; 8T2C refers to eight transistors and two capacitors; and so on.

[0050] Figure 3 is a circuit diagram showing a sub-pixel SP of the organic light emitting display device 100 according to the present disclosure.

[0051] As Figure 3 shown, the organic light emitting display device 100 according to the present disclosure includes a gate line GL, a data line DL, and a power supply line PL that cross each other to define a sub-pixel SP. A switching thin film transistor Ts, a driving thin film transistor Td, a storage capacitor Cst, and a light emitting device D are disposed in the sub-pixel SP.

[0052] The switching thin film transistor Ts is connected to the gate line GL and the data line DL, and the driving thin film transistor Td and the storage capacitor Cst are connected between the switching thin film transistor Ts and the power supply line PL. The light emitting device D is connected to the driving thin film transistor Td.

[0053] In the organic light emitting display device having such a structure, when the switching thin film transistor Ts is turned on according to a gate signal applied to the gate line GL, a data signal applied to the data line DL is applied to the gate electrode of the driving thin film transistor Td and one electrode of the storage capacitor Cst through the switching thin film transistor Ts.

[0054] In operation, the driving thin film transistor Td is turned on according to the data signal applied to the gate electrode. As a result, a current proportional to the data signal is supplied from the power supply line PL to the light emitting device D through the driving thin film transistor Td, and then the light emitting device D emits light with a brightness proportional to the current flowing through the driving thin film transistor Td.

[0055] In operation, a storage capacitor Cst is charged with a voltage proportional to a data signal so that the voltage of a gate electrode of a driving thin film transistor Td remains constant within one frame.

[0056] In Figure 3 , only two driving thin film transistors Td and switching thin film transistors Ts and one capacitor Cst are provided, but the present disclosure is not limited thereto. Three or more thin film transistors and two or more capacitors may be provided in the present disclosure.

[0057] Figure 4 is a plan view schematically showing a structure of a display device 100 according to the present disclosure.

[0058] As Figure 4 shown, a display device 100 according to the present disclosure includes a display area AA for displaying an image and a non-display area NA provided outside the display area AA.

[0059] A plurality of pixels P are arranged in the display area AA, and each pixel P includes a plurality of sub-pixels SP. The sub-pixel SP may be a red (R) sub-pixel, a green (G) sub-pixel, or a blue (B) sub-pixel. In addition, the sub-pixel SP may be a white (W) sub-pixel.

[0060] Although not shown in the figure, a plurality of gate lines and data lines are arranged in the display area AA, and the sub-pixels SP are provided in a crossing area of the gate lines and the data lines. In each sub-pixel SP, a thin film transistor serving as a switching element and a display device for displaying an image are provided.

[0061] The display device may include various display devices. For example, the display device may be an organic light emitting display device, a liquid crystal display device, a quantum dot display device, a micro LED display device, or a mini LED display device.

[0062] A gate driving unit and a data driving unit for applying various signals to the sub-pixels SP may be provided in the non-display area NA. The gate driving unit applies a scan signal to the sub-pixels SP through the gate lines, and the data driving unit applies an image signal to the sub-pixels SP through the data lines.

[0063] Figure 5 is a plan view showing a structure of a pixel P of a display device 100 according to the present disclosure.

[0064] As Figure 5 shown, a pixel P of a display device 100 according to the present disclosure includes first to third sub-pixel areas SP1, SP2, and SP3 and an auxiliary sub-pixel area SPa. As Figure 5As shown, when observed in a plan view within pixel P, the first to third sub-pixel regions SP1, SP2, and SP3 can be formed in a rectangular shape. In this figure, when observed in a plan view, the areas of the first to third sub-pixel regions SP1, SP2, and SP3 are the same, but the areas of the first to third sub-pixel regions SP1, SP2, and SP3 can be different.

[0065] In addition, when observed in a plan view, the first to third sub-pixel regions SP1, SP2, and SP3 can be formed in various shapes. For example, the first to third sub-pixel regions SP1, SP2, and SP3 can be formed in a rhombus, pentagon, hexagon, triangle, circle, or ellipse. Additionally, the first to third sub-pixel regions SP1, SP2, and SP3 can be formed in different shapes.

[0066] The auxiliary sub-pixel region SPa can be formed outside the first to third sub-pixel regions SP1, SP2, and SP3 and / or at the periphery of pixel P. That is, the auxiliary sub-pixel region SPa can be formed in a region where a structure for dividing the first to third sub-pixel regions SP1, SP2, and SP3 is provided. Therefore, in the present disclosure, since the auxiliary sub-pixel region SPa is provided in a region where an image is not displayed in a known general display device, the region for displaying an image can be increased, so that the aperture ratio of the display device 100 can be improved. In addition, in the present disclosure, since an image is displayed in a non-display region where an image is not displayed in a general display device, even if the area of pixel P is reduced, a desired image can be displayed, so that a high-resolution display device 100 can be manufactured.

[0067] The first to third sub-pixel regions SP1, SP2, and SP3 can be a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel respectively, but are not limited thereto. The auxiliary sub-pixel region SPa can be any one of a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel.

[0068] Figure 6 is a plan view showing another structure of pixel P of the display device 100 according to the present disclosure. In the display device 100 having such a structure, the auxiliary sub-pixel region SPa can include a plurality of auxiliary sub-pixel regions SPa1 and SPa2. In this figure, the first auxiliary sub-pixel region SPa1 is provided as a region outside pixel P, and the second auxiliary sub-pixel region SPa2 is provided as a region between the first to third sub-pixel regions SP1, SP2, and SP3, but is not limited thereto. For example, the auxiliary sub-pixel region SPa can include three or more auxiliary sub-pixels.

[0069] The first auxiliary sub-pixel region SPa1 and the second auxiliary sub-pixel region SPa2 may be auxiliary sub-pixels of different colors. For example, the first auxiliary sub-pixel region SPa1 and the second auxiliary sub-pixel region SPa2 are sub-pixels of different colors among red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels.

[0070] In the present disclosure, when the first light-emitting device and the second light-emitting device are said to have the same color, this means that the peak emission wavelengths of the first light-emitting device and the second light-emitting device are within at most 90 nm of each other. Similarly, when the first light-emitting device and the second light-emitting device are said to have different colors, the peak emission wavelengths of the first light-emitting device and the second light-emitting device have wavelengths that differ by at least 90 nm.

[0071] Figure 7 is a cross-sectional view of a display device 100 according to an example of the present disclosure. For ease of explanation, only one sub-pixel region SP and auxiliary sub-pixel region SPa are shown in the figure.

[0072] As Figure 7 shown, the substrate 140 includes a plurality of sub-pixel regions SP and auxiliary sub-pixel regions SPa. The substrate 140 may be made of a hard material such as glass or a flexible plastic-based material.

[0073] When the substrate 140 is made of a plastic-based material, the substrate is made of at least one of polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone, and polycarbonate, but is not limited thereto.

[0074] When the substrate 140 is made of polyimide, the substrate 140 may be made of a plurality of polyimide layers, and an inorganic layer may be further provided between the polyimide layers, but is not limited thereto.

[0075] A buffer layer 142 is formed on the substrate 140. The buffer layer 142 may be formed in the entire region of the substrate 140 to enhance the adhesion between the substrate 140 and the layers thereon. In addition, the buffer layer 142 may block various types of defects, such as alkaline components flowing out of the substrate 140. In addition, the buffer layer 142 may delay the diffusion of moisture or oxygen penetrating into the substrate 140.

[0076] The buffer layer 142 may be a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). When the buffer layer 142 is made of multiple layers, SiOx and SiNx may be alternately formed. The buffer layer 142 may be omitted based on the type and material of the substrate 140, the structure and type of the thin-film transistor, etc.

[0077] The first thin film transistor T1 is disposed on the buffer layer 142 adjacent to the sub-pixel region SP, for example, in the auxiliary sub-pixel region SPa. However, in some examples ( Figure 7 not shown), the first thin film transistor T1 may be located in the sub-pixel region SP. The second thin film transistor T2 is disposed on the buffer layer in the auxiliary sub-pixel region SPa. For ease of description, only the driving thin film transistor among the various thin film transistors that can be disposed in the display area AA is shown, but other thin film transistors such as switching thin film transistors may also be included. In Figure 7 this figure, a thin film transistor of a top gate structure is shown, but the thin film transistor is not limited to this structure and may be formed in other structures, such as a thin film transistor of a bottom gate structure.

[0078] The first thin film transistor T1 includes a first semiconductor layer 112 disposed on the buffer layer 142, a gate insulating layer 144 covering the first semiconductor layer 112, a first gate electrode 113 on the gate insulating layer 144, an interlayer insulating layer 146 covering the first gate electrode 113, and a first source electrode 115 and a first drain electrode 116 on the interlayer insulating layer 146.

[0079] The second thin film transistor T2 includes a second semiconductor layer 162 disposed on the buffer layer 142, a gate insulating layer 144 covering the second semiconductor layer 162, a second gate electrode 163 on the gate insulating layer 144, an interlayer insulating layer 146 covering the second gate electrode 163, and a second source electrode 165 and a second drain electrode 166 on the interlayer insulating layer 146.

[0080] The first semiconductor layer 112 and the second semiconductor layer 162 may be made of polycrystalline semiconductors. For example, the polycrystalline semiconductor may be made of low-temperature polycrystalline silicon (LTPS) having a high mobility, but is not limited thereto.

[0081] The first semiconductor layer 112 and the second semiconductor layer 162 may be made of oxide semiconductors. For example, the first semiconductor layer 112 and the second semiconductor layer 162 may be made of one of IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), IGTO (indium gallium tin oxide), and IGO (indium gallium oxide), but is not limited thereto.

[0082] The first semiconductor layer 112 and the second semiconductor layer 162 may be made of different materials. For example, the first semiconductor layer 112 may be made of an oxide semiconductor, and the second semiconductor layer 162 may be made of a polycrystalline semiconductor. In addition, the first semiconductor layer 112 may be made of a polycrystalline semiconductor, and the second semiconductor layer 162 may be made of an oxide semiconductor.

[0083] The first semiconductor layer 112 includes a first channel region 112a in a central region, and a first source region 112b and a first drain region 112c. The first source region 112b and the first drain region 112c are doped layers on both sides of the first channel region 112a. The second semiconductor layer 162 includes a second channel region 162a in a central region, and a second source region 162b and a second drain region 162c. The second source region 162b and the second drain region 162c are doped layers on both sides of the second channel region 162a.

[0084] The gate insulating layer 144 may be composed of a single layer or multiple layers made of an inorganic material such as SiOx or SiNx, but is not limited thereto.

[0085] The first gate electrode 113 and the second gate electrode 163 are made of metal. For example, the first gate electrode 113 and the second gate electrode 163 may be formed of a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy, but is not limited thereto.

[0086] The interlayer insulating layer 146 may be made of an organic material such as acrylate, or the interlayer insulating layer 146 may be formed of a single layer or multiple layers made of an inorganic material such as SiOx or SiNx, but is not limited thereto. In addition, the interlayer insulating layer 146 may be formed of multiple layers of an organic material layer and an inorganic material layer, but is not limited thereto.

[0087] The first source electrode 115 and the second source electrode 165, and the first drain electrode 116 and the second drain electrode 166 are formed of a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy, but is not limited thereto. The first source electrode 115 and the second source electrode 165, and the first drain electrode 116 and the second drain electrode 166 may be in contact with the first source region 112b and the second source region 162b, and the first drain region 112c and the second drain region 162c of the first semiconductor layer 112 and the second semiconductor layer 162, respectively, through contact holes formed in the gate insulating layer 144 and the interlayer insulating layer 146.

[0088] In Figure 7 not shown, a bottom shielding metal layer may be provided on the substrate 140 below the first semiconductor layer 112 and the second semiconductor layer 162. The bottom shielding metal layer minimizes the reverse channel phenomenon caused by charges trapped in the substrate 140 to prevent afterimages or deterioration of transistor performance. The bottom shielding metal layer may be composed of a single layer or multiple layers made of titanium (Ti), molybdenum (Mo), or an alloy thereof, but is not limited thereto.

[0089] A planarization layer 148 is formed on a substrate provided with a first thin film transistor T1 and a second thin film transistor T2. The planarization layer 148 may be formed of an organic material such as photoacrylic acid. However, it is not limited thereto. The planarization layer 148 may include a plurality of layers including an inorganic layer and an organic layer.

[0090] A first light emitting device D1 is disposed on the planarization layer 148. The first light emitting device D1 includes a first electrode 132, a first light emitting layer 134, and a second electrode 136.

[0091] The first electrode 132 may be an anode electrode. The first electrode 132 is disposed on the planarization layer 148 and is electrically connected to the first drain electrode 116 of the first thin film transistor T1 through a first contact hole H1 formed in the planarization layer 148. The first electrode 132 may be formed of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr) or an alloy thereof. In addition, the first electrode 132 may be formed of a transparent metal oxide material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0092] When the display device 100 is a top emission type display device, the first electrode 132 may further include an opaque conductive material layer to serve as a reflective electrode for reflecting light. When the display device 110 is a bottom emission type display device, the first electrode 132 may be made of a transparent conductive material such as ITO or IZO.

[0093] A bank layer BANK is formed above the planarization layer 148 in the auxiliary sub-pixel region SPa. The bank layer 152 may be a barrier wall for defining sub-pixels and / or sub-pixel regions. For example, an opening region formed through the bank layer 152 may at least partially define a sub-pixel region. The auxiliary sub-pixel region SPa may be defined as a region between adjacent opening regions or between opening regions. The bank layer BANK is made of at least one material such as an inorganic insulating material such as SiNx or SiOx, an organic insulating material such as benzocyclobutene, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or a photosensitizer including a black pigment, but is not limited thereto.

[0094] A first pattern 172 and a second pattern 174 are formed on the bank layer BANK. In Figure 7 the example, the width of the first pattern 172 is smaller than the width of the second pattern 174, so that an undercut or overhang with opposite steps is formed at the boundary between the first pattern 172 and the second pattern 174.

[0095] The first pattern 172 may be made of an inorganic insulating material such as SiOx or SiNx, and the second pattern 174 may be made of amorphous silicon, but is not limited thereto.

[0096] The first light-emitting layer 134 is formed on the upper surface of the first electrode 132 that is exposed to the outside through the opening regions between the bank layers BANK. As will be described in detail later, the first light-emitting layer 134 is formed on multiple sub-pixel regions SP at one time by the same process, but the first light-emitting layer 134 is disconnected between adjacent sub-pixel regions SP.

[0097] That is, the first light-emitting layer 134 is deposited above the entire region of the substrate 140, but due to the overhang structures of the first pattern 172 and the second pattern 174, portions of the first light-emitting layer 134 are disconnected from each other. As a result, the first light-emitting layer 134 formed in adjacent sub-pixel regions SP is disconnected.

[0098] For example, the first light-emitting layer 134 may be an organic light-emitting layer. In addition, the first light-emitting layer 134 may be an inorganic light-emitting layer, such as a nanomaterial layer, a quantum dot layer, a micro-LED light-emitting layer, or a mini-LED light-emitting layer, but is not limited thereto.

[0099] When the first light-emitting layer 134 is an organic light-emitting layer, the first light-emitting layer 134 includes a blue organic light-emitting layer and a yellow light-emitting layer to output white light. The first light-emitting layer 134 may be formed in a multi-stack structure. For example, when the first light-emitting layer 134 is formed in a triple-stack structure, the first stack to the third stack may be arranged with two charge generation layers therebetween. Each of the first stack to the third stack may include an organic light-emitting layer, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. For example, the organic light-emitting layer of the first stack may emit red light, the organic light-emitting layer of the second stack may emit blue light, and the organic light-emitting layer of the third stack may emit green light.

[0100] The second light-emitting device D2 is disposed above the bank layer BANK, that is, on the second pattern 174. The second light-emitting device D2 includes a third electrode 137, a second light-emitting layer 138, and a fourth electrode 139. As Figure 7 shown, the vertical gap between the substrate 140 and the first light-emitting device D1 (i.e., the gap in the direction perpendicular to the plane of the substrate) is smaller than the corresponding gap between the substrate 140 and the second light-emitting device D2.

[0101] The third electrode 137 may be an anode electrode. The third electrode 137 is disposed on the second pattern 174 and is electrically connected to the second drain electrode 166 of the second thin-film transistor T2 through a second contact hole H21 formed in the first pattern 172, the second pattern 174, the bank layer BANK, and the planarization layer 148. The third electrode 137 may be formed of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof. In addition, the third electrode 137 may be formed of a transparent metal oxide material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0102] The third electrode 137 may be made of the same material as the first electrode of the first light-emitting device D1, but may also be made of a material different from the first electrode of the first light-emitting device D1.

[0103] When the display device 100 is a top-emission display device, the third electrode 137 may further include an opaque conductive material layer to serve as a reflective electrode for reflecting light. When the display device 100 is a bottom-emission display device, the third electrode 137 may be made of a transparent conductive material such as ITO or IZO.

[0104] The second light-emitting layer 138 is formed on the upper surface of the third electrode 137. Since the second light-emitting layer 138 is formed on the first pattern 172 and the second pattern 174 forms a cantilever structure, the second light-emitting layer 138 formed in the auxiliary sub-pixel region SPa is disconnected from the first light-emitting layer 134 formed in the sub-pixel region SP.

[0105] Similar to the first light-emitting layer 134, the second light-emitting layer 138 may be composed of an organic light-emitting layer, a nanomaterial layer, a quantum dot layer, a micro-LED light-emitting layer, or a small-LED light-emitting layer. In addition, the second light-emitting layer 138 may be formed in a multi-stack structure.

[0106] That is, the second light-emitting layer 138 may be formed of the same material and the same structure as the first light-emitting layer 134, but may also be formed of a material and a structure different from those of the first light-emitting layer 134.

[0107] The fourth electrode 139 may be a cathode electrode. The fourth electrode 138 is disposed on the second light-emitting layer 1138. The fourth electrode 138 may be formed of a single layer or multiple layers made of a metal or an alloy thereof. In addition, the fourth electrode 139 may be made of a transparent metal oxide such as ITO or IZO, but is not limited thereto.

[0108] The fourth electrode 139 may be integrally formed with the second electrode 136. That is, a metal or a metal oxide is deposited over the entire area of the substrate 140 so that a common cathode electrode for the sub-pixel region SP and the auxiliary sub-pixel region SPa can be integrally formed.

[0109] An encapsulation layer 180 is formed in the sub-pixel region SP and the auxiliary sub-pixel region SPa to encapsulate the first light-emitting device D1 and the second light-emitting device D2. When the first light-emitting device D1 and the second light-emitting device D2 are exposed to impurities such as moisture or oxygen, a phenomenon of pixel shrinkage in which the light-emitting area decreases or defects such as dark spots in the light-emitting area may occur. In addition, the moisture or oxygen penetrating into the first light-emitting device D1 and the second light-emitting device D2 oxidizes the metal electrodes. The encapsulation layer 180 blocks impurities such as oxygen and moisture from the outside to prevent defects in the first light-emitting device D1 and the second light-emitting device D2 and various electrodes.

[0110] The encapsulation layer 180 may be formed of a first encapsulation layer 182, a second encapsulation layer 184, and a third encapsulation layer 186, but is not limited thereto. The encapsulation layer 180 may be formed of two layers having an organic layer and an inorganic layer or four or more layers having an organic layer and an inorganic layer.

[0111] The first encapsulation layer 182 and the third encapsulation layer 186 may be formed of a single layer or multiple layers including an inorganic material such as SiOx, SiON, SiNx, etc. At this time, an organic material may be further provided between the inorganic materials, but is not limited thereto. The second encapsulation layer 184 may be made of an organic insulating material such as an acrylic resin, an epoxy resin, a polyimide, a polyethylene, or a silicon oxycarbide (SiOC), but is not limited thereto. In addition, the third encapsulation layer 186 may be made of a thin metal (surface-sealing metal), but is not limited thereto.

[0112] In Figure 7 not shown, a touch member may be provided on the encapsulation layer 180. The touch member may detect external touch information using a user's finger or a touch pen.

[0113] As described above, in the display device 100 according to the present disclosure, since the auxiliary sub-pixel region SPa is formed in a region between the sub-pixel region SP above the bank layer BANK and a region outside the pixel P, and the second light-emitting device D2 is provided in the auxiliary sub-pixel region SPa, the area for displaying an image can be increased. As a result, the aperture ratio of the display device 100 is improved, and a high-resolution display device 100 can be manufactured.

[0114] Hereinafter, a method of manufacturing a display device according to an example of the present disclosure will be described in detail.

[0115] Figures 8A to 8H is a view showing a method of manufacturing the display device 100 according to the present disclosure. For ease of explanation, only two first sub-pixel regions SP1 and second sub-pixel regions SP2 and one auxiliary sub-pixel region SPa are shown in Figures 8A - 8H the figure.

[0116] First, asFigure 8A As shown, a buffer layer 142 is formed above the entire substrate 140 including a plurality of first sub-pixel regions SP1 and second sub-pixel regions SP2 and in the auxiliary sub-pixel region SPa. The substrate 140 can be made of a hard material such as glass or a plastic material, and the plastic material can include, for example, polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone, and polycarbonate. The buffer layer 142 can be formed of a single layer of SiNx or SiOx or multiple layers thereof.

[0117] Thereafter, a polycrystalline semiconductor material such as polysilicon or an oxide semiconductor material such as etched IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), IGTO (indium gallium tin oxide), and IGO (indium gallium oxide) is deposited and etched to form a first semiconductor layer 112 in each of the first sub-pixel regions SP1 and second sub-pixel regions SP2, and a second semiconductor layer 162 in the auxiliary sub-pixel region SPa. In addition, impurities are doped into both sides of the first semiconductor layer 112 and the second semiconductor layer 162 to form a first channel region 112a and a second channel region 162a, a first source region 112b and a second source region 162b, and a first drain region 112c and a second drain region 162c.

[0118] Subsequently, a gate insulating layer 144 is formed by depositing an inorganic material such as SiOx or SiNx, and then a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) is deposited by sputtering and etched by a wet etching method to form a first gate electrode 114 in each of the first sub-pixel regions SP1 and second sub-pixel regions SP2 and a second gate electrode 163 in the auxiliary sub-pixel region SPa.

[0119] Thereafter, an organic material such as a photoacrylic material or an inorganic material such as SiNx or SiOx is deposited on the first gate electrode 113 and the second gate electrode 163 to form an interlayer insulating layer 146, and then the interlayer insulating layer 146 above the first source region 112b and the first drain region 112c of the first semiconductor layer 112 and above the second source region 162b and the second drain region 162c of the second semiconductor layer 162 is dry-etched to form contact holes therein.

[0120] Subsequently, a metal such as Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy is deposited and etched by sputtering to form a first source electrode 115 and a first drain electrode 116, which are in ohmic contact with a first source region 112b and a first drain region 112c of the first semiconductor layer 112 through contact holes in each of the first sub-pixel region SP1 and the second sub-pixel region SP2, respectively, and a second source electrode 165 and a second drain electrode 166 are formed, which are in ohmic contact with a second source region 162b and a second drain region 162c of the second semiconductor layer 162 through contact holes in the auxiliary sub-pixel region SPa, respectively.

[0121] Subsequently, as Figure 8B shown, a planarization layer 148 is formed by depositing an organic material (such as photoacrylic) on the first source electrode 115 and the second source electrode 165, and the first drain electrode 116 and the second drain electrode 166, and then the planarization layer 148 on the first drain electrode 116 is dry-etched to form a first contact hole H1. Thereafter, a metal such as silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof, or a metal oxide such as ITO or IZO is deposited by a sputtering process and then etched by a wet etching process to form a first electrode 132 on the upper surface of the planarization layer 148 in the first sub-pixel region SP1 and the second sub-pixel region SP2. The first electrode 132 is electrically connected to the first drain electrode 116 of the first thin film transistor T1 through the first contact hole H1.

[0122] Thereafter, at least one material selected from an inorganic insulating material such as SiNx or SiOx, an organic material such as BCB (benzocyclobutene), acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin, and a photoresist including a black pigment is deposited on the planarization layer 148 and the first electrode 132, and dry-etched to form a bank layer BANK.

[0123] The bank layer BANK is formed in a matrix shape over the entire region of the substrate 140 and overlaps the edge of the first electrode 132, such that the first electrode 132 is exposed to the outside through an opening between the bank layers BANK.

[0124] Subsequently, as Figure 8C shown, a first insulating layer 172a and a second insulating layer 174a are continuously deposited over the entire region of the substrate 140, and then a photoresist is deposited thereon and patterned to form a photoresist pattern 190. Then, the photoresist pattern 190 is removed from the first sub-pixel region SP1 and formed only on the second sub-pixel region SP2 and the auxiliary sub-pixel region SPa.

[0125] Subsequently, as Figure 8DAs shown, the first insulating layer 172a and the second insulating layer 174a disposed under the photoresist pattern 190 are etched using the photoresist pattern 190 to form a first insulating pattern 172b and a second insulating pattern 174b. The first insulating layer 172a is made of an inorganic material such as SiOx or SiNx, and the second insulating layer 174a may be made of amorphous silicon, but is not limited thereto.

[0126] The second insulating layer 174 formed of an inorganic material such as SiOx or SiNx is etched by a dry etching process, and the first insulating layer 172a formed of amorphous silicon is etched by a wet etching process. Since the first insulating layer 172a is isotropically etched during the wet etching process, a part of the first insulating layer 172a under the second insulating pattern 174b is also etched, such that the width of the first insulating pattern 172b is smaller than the width of the second insulating pattern 174b thereon. Accordingly, the first insulating pattern 172b and the second insulating pattern 174b adjacent to the first sub-pixel region SP1 are formed in an undercut structure or an overhang structure.

[0127] Thereafter, a light-emitting material such as an organic light-emitting material is deposited over the entire region of the substrate 140 to form a light-emitting layer 134 on the first electrode 132 in the first sub-pixel region SP1 that is not blocked by the first insulating pattern 172b and the second insulating layer 174b, and a light-emitting pattern 134a is formed on the first insulating pattern 172b and the second insulating layer 174b. The first light-emitting layer 134 and the light-emitting pattern 134a are disconnected from each other through the undercut structure or the overhang structure of the first insulating pattern 172b and the second insulating pattern 174b.

[0128] Subsequently, as Figure 8E shown, the light-emitting pattern 134a is removed from the first insulating pattern 172b and the second insulating pattern 174b.

[0129] Thereafter, the process of Figures 8C - 8E is repeated to form a first light-emitting layer 134 on the first electrode 132 in the second sub-pixel region SP2, as Figure 8F shown.

[0130] If a pixel P of the display device includes three sub-pixels SP of R, G, and B, the process of Figures 8C to 8E is repeated three times to form a first light-emitting layer 143 in each of the R, G, and B sub-pixels SP. If a pixel P of the display device includes four sub-pixels SP, the process of Figures 8C to 8E is repeated four times to form a first light-emitting layer 143 in each of the four sub-pixels SP.

[0131] Thereafter, as Figure 8GAs shown, a second contact hole H2 is formed in the planarization layer 148, the bank layer BANK, the first pattern 172, and the second pattern 174 above the second drain electrode 166 of the second thin-film transistor T2 provided in the auxiliary sub-pixel region SPa. Subsequently, a metal, its alloy, or a metal oxide is deposited over the entire area of the substrate 140 and then etched to form a third electrode 137 that is electrically connected to the second drain electrode 166 above the second pattern 174 of the auxiliary sub-pixel region SPa.

[0132] Subsequently, a light-emitting material is deposited over the entire area of the substrate 140 and then patterned to form a second light-emitting layer 138 on the third electrode 137.

[0133] Thereafter, a metal or a metal oxide is deposited over the entire area of the substrate 140 to form a second electrode 136 on the first light-emitting layer 134 of the first sub-pixel SP1 and the second sub-pixel region SP2, and to form a fourth electrode 139 on the second light-emitting layer 138 of the auxiliary sub-pixel region SPa.

[0134] The second electrode 136 and the fourth electrode 139 are thus formed on the first light-emitting layer 134 of the first sub-pixel region SP1 and the second sub-pixel region SP2, on the second emission layer 138 of the auxiliary sub-pixel region SPa, and on the side surfaces of the bank layer BANK, the first pattern 172, and the second pattern 174 to form a cathode electrode as a continuous common layer.

[0135] Subsequently, as Figure 8H shown, an inorganic material is applied over the entire area of the substrate 140 to form a first encapsulation layer 382, and an organic material is applied on the first encapsulation layer 382 to form a second encapsulation layer 384. Thereafter, an inorganic material is applied on the second encapsulation layer 384 to form a third encapsulation layer 386, thereby forming an encapsulation layer 380 to seal the display device 300.

[0136] As described above, in the display device 100 according to the present disclosure, the first pattern 172 and the second pattern 174 that form an undercut structure or an overhang structure are formed, and a light-emitting material is simply deposited without a patterning process to form a patterned first light-emitting layer 134 in each sub-pixel region, such that the manufacturing method can be simplified compared to the conventional method.

[0137] The above description and the drawings are merely illustrative of the technical spirit of the present disclosure, and various modifications or variations such as separation, replacement, and change can be made by those of ordinary skill in the art to which the present disclosure pertains without departing from the basic features of the present disclosure. Therefore, the examples disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but are for explanation, and the scope of the technical spirit of the present disclosure is not limited by these examples.

Claims

1. A display device, comprising: A substrate, the substrate comprising a plurality of pixel regions, each pixel region having a plurality of sub-pixel regions; a first light emitting device disposed in each of the plurality of sub-pixel regions to form a plurality of sub-pixels; a first transistor configured to operate the first light emitting device; a second light emitting device, the second light emitting device being disposed between adjacent sub-pixel regions among the plurality of sub-pixel regions; as well as a second transistor disposed between sub-pixel regions among the plurality of sub-pixel regions and configured to operate the second light emitting device; Wherein, a gap between the substrate and the second light emitting device is larger than a gap between the first light emitting device and the substrate. 2 . The display device according to claim 1 , further comprising a bank layer between the plurality of sub-pixel regions.

3. The display device according to claim 2, wherein: The bank layer includes a plurality of opening regions formed therethrough, wherein the plurality of sub-pixel regions correspond to the plurality of opening regions.

4. The display device according to claim 3, wherein: The first light emitting device is disposed in each of the plurality of opening regions.

5. The display device according to any one of claims 2 to 4, wherein: The second light emitting device is disposed above the bank layer.

6. The display device according to claim 5, wherein: The first light emitting device comprises: a first electrode, the first electrode being disposed in each of the plurality of sub-pixel regions; a first light-emitting layer, the first light-emitting layer being on the first electrode; and A second electrode is provided on the first light-emitting layer.

7. The display device according to claim 6, wherein: The second light emitting device comprises: a third electrode, the third electrode being disposed on the bank layer; a second light-emitting layer, the second light-emitting layer being on the third electrode; and A fourth electrode is on the second light-emitting layer.

8. The display device according to claim 7, wherein: The second electrode and the fourth electrode are formed integrally.

9. The display device according to claim 7, wherein: The first pattern and the second pattern are disposed between the bank layer and the second light emitting device.

10. The display device according to claim 9, wherein: The first pattern and the second pattern include an overhang structure, and the overhang structure forms a step overhanging above the bank layer.

11. The display device according to claim 10, wherein: The first light-emitting layer and the second light-emitting layer are separated by the overhang structure.

12. The display device according to claim 7, wherein: The first transistor includes a first semiconductor layer on the buffer layer, a gate insulating layer covering the first semiconductor layer, a first gate electrode on the gate insulating layer, an interlayer insulating layer covering the first gate electrode, a first source electrode and a first drain electrode on the interlayer insulating layer, and The second transistor includes a second semiconductor layer on the buffer layer, a gate insulating layer covering the second semiconductor layer, a second gate electrode on the gate insulating layer, an interlayer insulating layer covering the second gate electrode, and a second source electrode and a second drain electrode on the interlayer insulating layer.

13. The display device according to claim 12, further comprising a planarization layer, the planarization layer covering the first transistor and the second transistor, and in, The first drain electrode is electrically connected to the first electrode through a first contact hole formed in the planarization layer.

14. The display device according to claim 13, wherein: The second drain electrode is electrically connected to the third electrode through a second contact hole formed in the planarization layer, the bank layer, the first pattern, and the second pattern.

15. A display device, comprising: a substrate including a plurality of pixels having a plurality of sub-pixel regions and at least one auxiliary sub-pixel region; a first light emitting device disposed in each of the plurality of sub-pixel regions to form a sub-pixel; a second light emitting device, the second light emitting device being disposed in the auxiliary sub-pixel region to form an auxiliary sub-pixel; a first transistor configured to operate the first light emitting device, and a second transistor disposed in the auxiliary sub-pixel region and configured to operate the second light emitting device; Wherein, a gap between the substrate and the second light emitting device is larger than a gap between the first light emitting device and the substrate.

16. The display device according to claim 15, wherein: The auxiliary sub-pixel comprises: a first auxiliary sub-pixel disposed between sub-pixel regions among the plurality of sub-pixel regions; and A second auxiliary sub-pixel is disposed at the periphery of the pixel. 17 . The display device according to claim 16 , further comprising a bank layer formed between the plurality of sub-pixel regions and surrounding a periphery of the pixel.

18. The display device according to claim 17, wherein: The bank layer includes a plurality of opening regions formed through the bank layer, wherein the plurality of sub-pixel regions correspond to the plurality of opening regions.

19. The display device according to claim 18, wherein: The first light emitting device is disposed in each of the opening regions.

20. The display device according to claim 16, wherein: The second light emitting devices of the first auxiliary sub-pixel and the second auxiliary sub-pixel emit the same color as each other.

21. The display device according to claim 16, wherein: The second light emitting devices of the first auxiliary sub-pixel and the second auxiliary sub-pixel emit colors different from each other.

Images