Display device

Abstract

A display device according to an exemplary embodiment of the present invention includes: a substrate including a display area, an optical area disposed in the display area and including a through hole, and a non-display area surrounding the display area; the first sensing line is arranged in the non-display area and surrounds the periphery of the display area; a second sensing line disposed on an inner side of the first sensing line and surrounding a periphery of the through hole and the display area; and a plurality of metal patterns disposed along a periphery of the through hole below the second sensing line, where at least one of the plurality of metal patterns is electrically connected to the second sensing line. Therefore, when a crack is generated in the non-display area or the optical area, the generation position of the crack can be distinguished.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0191299, filed with the Korean Intellectual Property Office on December 26, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a display device, and more particularly, to a display device that senses cracks generated in an optical region in which a camera or a sensor is provided. Background Art

[0004] As the information age has arrived, the field of display devices that visually present electrical information signals has developed rapidly, and continuous research has been conducted to improve the performance of various display devices, such as thin thickness, light weight, and low power consumption.

[0005] Representative display devices may include a liquid crystal display device (LCD), a field - emission display device (FED), an electro - wetting display device (EWD), and an organic light - emitting display device (OLED).

[0006] An electroluminescent display device represented by an organic light - emitting display device is a self - emissive display device, and thus does not require a separate light source, which is different from a liquid crystal display device. Therefore, an electroluminescent display device can be manufactured to have a light weight and a small thickness. In addition, since an electroluminescent display device is not only advantageous in terms of power consumption due to low - voltage driving, but also advantageous in terms of color realization, response speed, viewing angle, and contrast ratio (CR), it is expected to be used in various fields. Summary of the Invention

[0007] One object to be achieved by an exemplary embodiment of the present invention is to provide a display device that senses cracks generated in a non - display region or an optical region.

[0008] Another object to be achieved by another exemplary embodiment of the present invention is to provide a display device that distinguishes the generation location of a crack when a crack is generated in a non - display region or an optical region.

[0009] The objects of the present invention are not limited to the above - mentioned objects, and other objects not mentioned above can be clearly understood by those of ordinary skill in the art according to the following description.

[0010] According to one aspect of the present invention, a display device includes: a substrate including a display area, an optical area disposed in the display area and including a through hole, and a non-display area surrounding the display area; a first sensing line disposed in the non-display area and surrounding the periphery of the display area; a second sensing line disposed inside the first sensing line and surrounding the periphery of the through hole and the display area; and a plurality of metal patterns disposed along the periphery of the through hole under the second sensing line, and at least one of the plurality of metal patterns is electrically connected to the second sensing line.

[0011] According to another aspect of the present invention, a display device includes: a substrate including a display area, an optical area disposed in the display area and including a through hole, and a non-display area surrounding the display area; and a second sensing line surrounding the periphery of the through hole and the display area, wherein the display area includes a plurality of thin film transistors disposed on the substrate, and the plurality of thin film transistors include: a first thin film transistor disposed on the substrate of the display area and including a first active layer containing polysilicon; and a second thin film transistor including a second active layer containing an oxide.

[0012] Other details of the exemplary embodiments are included in the detailed description and the drawings.

[0013] The display device according to an exemplary embodiment of the present invention can sense cracks generated in the non-display area or the optical area.

[0014] When cracks are generated in the non-display area or the optical area, the display device according to an exemplary embodiment of the present invention can distinguish the generation position of the cracks.

[0015] Even if cracks are generated at the top of the encapsulation unit in the optical area including the through hole, or even if cracks are generated in the insulating film disposed under the plurality of thin film transistors, the display device according to an exemplary embodiment of the present invention can sense the cracks.

[0016] The effects according to the present invention are not limited to the above-exemplified contents, and more various effects are included in the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features, and other advantages of the present invention will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present invention;

[0019] Figure 2 is alongFigure 1 A sectional view taken along line II-II'

[0020] Figure 3 is Figure 1 An enlarged plan view of region A

[0021] Figure 4 is Figure 3 An enlarged plan view of region B

[0022] Figure 5 is a sectional view taken along Figure 4 line V-V'

[0023] Figure 6 is a plan view of a display device according to an exemplary embodiment of the present invention

[0024] Figure 7 is a plan view of a display device according to another exemplary embodiment of the present invention

[0025] Figure 8 is a plan view of a display device according to still another exemplary embodiment of the present invention Detailed embodiments

[0026] The advantages and characteristics of the present invention and the methods for achieving these advantages and characteristics will be clear by referring to the exemplary embodiments described in detail below together with the accompanying Figure 1 drawings. However, the present invention is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present invention and the scope of the present invention

[0027] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing the exemplary embodiments of the present invention are merely examples, and the present invention is not limited thereto. Similar reference numerals generally denote similar elements throughout the application. In addition, in the following description of the present invention, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present invention. Terms such as "comprising", "having", and "including" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Any singular reference may include the plural, unless otherwise explicitly stated

[0028] Even if not explicitly stated, components are construed as including ordinary error ranges

[0029] When using terms such as "on", "above", "below", and "after" to describe the positional relationship between two parts, one or more parts may be placed between these two parts, unless these terms are used together with the terms "immediately" or "directly".

[0030] When an element or layer is disposed "on" another element or layer, it may be directly on the other element or layer, or other layers or other elements may be interposed therebetween.

[0031] Although terms such as "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from other components. Thus, within the technical concept of the present invention, the first component mentioned hereinafter may be the second component.

[0032] Throughout the application, the same reference numerals generally denote the same elements.

[0033] For convenience of description, the dimensions and thicknesses of each component shown in the drawings are illustrated, and the present invention is not limited to the dimensions and thicknesses of the components shown.

[0034] The features of the embodiments of the present invention may be partially or wholly combined or combined with each other, and may be interlocked and operated in various ways technically. The embodiments may be implemented independently of each other or implemented in an interrelated manner.

[0035] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings.

[0036] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present invention.

[0037] Referring to Figure 1 , the display device 100 according to an exemplary embodiment of the present invention may include a circuit unit in which a display panel DP and a sensing pad PAD are provided.

[0038] According to an exemplary embodiment of the present invention, the display panel DP may include: a display area DA; an optical area OA provided in the display area DA and including a through hole TH; and a non-display area NDA surrounding the display area DA.

[0039] The display area DA is an area for displaying an image in the display panel DP.

[0040] In the display area DA, multiple pixels P and a circuit for driving the multiple pixels P can be provided. The multiple pixels P are the smallest units that make up the display area DA, and display elements can be provided in each of the multiple pixels P. For example, an organic light-emitting diode including an anode, a light-emitting layer, and a cathode can be provided in each of the multiple pixels P, but it is not limited thereto. In addition, the circuit for driving the multiple pixels P can include driving elements and wirings. For example, the circuit can be configured by thin-film transistors, storage capacitors, gate lines, and data lines, but it is not limited thereto.

[0041] The optical area OA is provided in the display area DA. In the optical area OA, a through hole TH formed by punching the display panel DP is provided therein. The optical area OA can be an area for placing optical electronic devices such as cameras, flashlights, speakers, and optical sensors in the display area DA. In the display panel DP, the through hole TH is provided in the display area DA to reduce the bezel area as the non-display area NDA and maximize the display area DA. A product with a design that maximizes the display area DA is aesthetically preferred by maximizing the user's screen immersion.

[0042] As Figure 1 shown, two through holes TH can be provided, but it is not limited thereto, and the through holes can be provided in various forms. For example, one or two holes are provided in the display area DA such that a camera is provided in the first hole, and a distance sensing sensor or a face recognition sensor and a wide-angle camera can be provided in the second hole.

[0043] The non-display area NDA is an area where an image is not displayed.

[0044] The non-display area NDA is bent so as not to be seen from the front surface or blocked by a housing (not shown), and the non-display area NDA is also referred to as a bezel area.

[0045] Although in Figure 1 it is shown that the non-display area NDA surrounds the quadrilateral display area DA, the shapes and placements of the display area DA and the non-display area NDA are not limited to Figure 1 the example shown. That is, the display area DA and the non-display area NDA can have shapes suitable for the design of the electronic device including the display device 100. For example, an exemplary shape of the display area DA can be a pentagon, a hexagon, a circle, or an ellipse.

[0046] In the non-display area NDA, various wirings and circuits for driving the organic light-emitting diodes in the display area DA can be provided. For example, in the non-display area NDA, linklines for transmitting signals to the multiple pixels and circuits in the display area DA, gate-in-panel (GIP) lines, or driving ICs such as a gate driver or a data driver can be provided, but it is not limited thereto.

[0047] In the non-display area NDA, a sensing line 130 for sensing cracks generated in the display panel DP may be provided. For example, the sensing line 130 may include: a first sensing line 131 that surrounds the periphery of the display area DA; and a second sensing line 132 that is disposed inside the first sensing line 131 and surrounds the through hole TH and the periphery of the display area DA. The first sensing line 131 may sense cracks generated at the periphery of the display panel DP, and the second sensing line 132 may sense cracks generated in the optical area OA.

[0048] One end and the other end of the first sensing line 131 and the second sensing line 132 are connected to a sensing pad PAD disposed in the non-display area NDA, and the sensing pad PAD may receive a sensing signal output via the sensing line 130.

[0049] The sensing pad PAD may be located in a printed circuit board (PCB) connected to the non-display area NDA of the display panel DP, but is not limited thereto, and it may be directly mounted on the non-display area NDA of the display panel DP. A data driver or a timing controller that generates a data signal to drive the pixel P may be further located in the printed circuit board, but is not limited thereto. When the sensing pad PAD is located on the printed circuit board, the first sensing line 131 and the second sensing line 132 may extend to the printed circuit board.

[0050] The sensing pad PAD applies a sensing signal to the first sensing line 131 and receives the first sensing signal received thereby to check whether the first sensing line 131 is normal. The sensing pad PAD applies a sensing signal to the second sensing line 132 and receives the second sensing signal received thereby to check whether the second sensing line 132 is normal. The sensing pad PAD may sense cracks around the non-display area NDA and the optical area OA based on whether the first sensing line 131 is normal and whether the second sensing line 132 is normal.

[0051] For example, when the display panel DP performs an illumination test (auto-probe) for final testing, a power supply of a predetermined level is applied to the sensing pad PAD from a separate device to compare the input value and the output value. The resistance level is confirmed by the difference between the output value and the input value, and based on the resistance level, it is confirmed whether the sensing line is disconnected. For example, when a crack is generated in the non-display area NDA of the display panel DP, a part or all of the sensing line 130 may be disconnected. For example, when a part of the sensing line 130 is disconnected, the resistance gradually increases to weaken the output power supply. Thus, based on the resistance-related characteristics, it is confirmed that a crack is generated in the display panel DP, but the method for confirming whether a crack is generated is not limited thereto.

[0052] The display device 100 may further include various additional elements for generating various signals or driving the pixels P in the display area DA. The additional elements for driving the pixels P may include an inverter circuit, a multiplexer, or an electrostatic discharge (ESD) circuit. The display device 100 may further include additional elements related to functions other than the function of driving the pixels P. For example, the display device 100 may further include additional elements providing a touch sensing function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure sensing function, or a haptic feedback function. The above-mentioned additional elements may be located in an external circuit connected to the non-display area NDA and / or the connection interface.

[0053] Here, the cross-sectional structure of the display area DA of the display device 100 will be described in more detail with reference to Figure 2 the cross-sectional structure of the display area DA of the display device 100 will be described in more detail.

[0054] Figure 2 FIG. is a cross-sectional view illustrating the cross-sectional structure of one pixel P provided in the display area DA according to an exemplary embodiment of the present invention.

[0055] The display device 100 according to an exemplary embodiment of the present invention may include: a substrate 110; a first buffer layer 111; a first thin film transistor TR1; a second thin film transistor TR2; a first gate insulating layer 112a; a first interlayer insulating layer 113a; a second buffer layer 114; a second gate insulating layer 112b; a second interlayer insulating layer 113b; a connection electrode CE; a first planarization layer 115a; a second planarization layer 115b; an auxiliary electrode 145; a bank 116a; a spacer 116b; an anode 121; a light emitting layer 122; a cathode 123; a packaging unit 117; and a touch sensing unit.

[0056] The substrate 110 is for supporting and protecting the components of the flexible display device provided thereon.

[0057] The substrate 110 is a component for supporting various components included in the display device 100 and may be formed of an insulating material. The substrate 110 may include a first substrate 110a, a second substrate 110b, and an interlayer insulating film 110c. The interlayer insulating film 110c may be disposed between the first substrate 110a and the second substrate 110b. As described above, the substrate 110 is configured by the first substrate 110a, the second substrate 110b, and the interlayer insulating film 110c to inhibit moisture penetration. For example, the first substrate 110a and the second substrate 110b may be polyimide (PI) substrates, and the interlayer insulating film 110c may be formed of a single layer or multiple layers of silicon nitride SiNx or silicon oxide SiOx.

[0058] A light shielding layer 125 may be disposed on the substrate 110.

[0059] The first buffer layer 111 may be disposed on the substrate 110 and may cover the light-shielding layer 125. Specifically, a multi-buffer layer 111a is disposed on the substrate 110 and covers the light-shielding layer 125, and an active buffer layer 111b may be disposed on the multi-buffer layer 111a.

[0060] The multi-buffer layer 111a delays the propagation of moisture or oxygen penetrating into the substrate 110 and may include at least any one of silicon nitride SiNx and silicon oxide SiOx.

[0061] The active buffer layer 111b protects the first active layer A1 and may block various defects introduced from the substrate 110. For example, the active buffer layer 111b may include at least any one of amorphous silicon (a-Si), silicon nitride SiNx, and silicon oxide SiOx.

[0062] The first thin-film transistor TR1 may be disposed on the first buffer layer 111. The first thin-film transistor TR1 may include a first active layer A1, a first gate G1, a first source S1, and a first drain D1. Herein, according to the design of the pixel circuit, the first source S1 may be used as the first drain, and the first drain D1 may be used as the first source.

[0063] The first active layer A1 may be disposed on the first buffer layer 111 and overlap with the light-shielding layer 125. The first active layer A1 may include amorphous silicon or polycrystalline silicon. For example, the first active layer A1 may include low-temperature polycrystalline silicon (LTPS). For example, the polycrystalline silicon material has a high mobility (100 cm 2 / Vs or higher), resulting in low energy consumption and excellent reliability. Therefore, the polysilicon material can be applied to a gate driver (or a gate driver for a driving element) for a driving element of a thin film transistor for driving a display element (or a thin film transistor for a display element) and / or a multiplexer (MUX), and can also be used as a first active layer A1 of a driving thin film transistor of the display device 100 according to an exemplary embodiment, but is not limited thereto. For example, according to the characteristics of the display device 100, the polysilicon material can also be used as a second active layer A2 of a switching thin film transistor. An amorphous silicon (a-Si) material is deposited on the first buffer layer 111, and a dehydrogenation process and a crystallization process are performed to form polysilicon, and the polysilicon is patterned to form the first active layer A1. Here, the first active layer A1 may include: a first channel region where a channel is formed when driving the first thin film transistor TR1; and a first source region and a first drain region located on both sides of the first channel region. The first source region refers to a part of the first active layer A1 connected to the first source S1, and the first drain region refers to a part of the first active layer A1 connected to the first drain D1. For example, the first source region and the first drain region can be configured by ion doping (impurity doping) of the first active layer A1. The first source region and the first drain region can be generated by doping ions into the polysilicon material, and the first channel region can refer to a part where ions are not doped but the polysilicon material remains.

[0064] The first gate insulating layer 112a can be disposed on the first active layer A1. The first gate insulating layer 112a can be configured by a single layer or multiple layers of silicon nitride SiNx or silicon oxide SiOx. In the first gate insulating layer 112a, contact holes can be formed, through which the first source S1 and the first drain D1 of the first thin film transistor TR1 are respectively connected to the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1.

[0065] The first gate G1 of the first thin film transistor TR1 and the first capacitor electrode C1 of the storage capacitor Cst can be disposed on the first gate insulating layer 112a.

[0066] In addition, the first gate G1 and the first capacitor electrode C1 can be formed by a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof. The first gate G1 can be formed on the first gate insulating layer 112a and overlap with the first channel region of the first active layer A1 of the first thin film transistor TR1.

[0067] Based on the driving characteristics of the display device 100 and the structure and type of the thin film transistor, the first capacitor electrode C1 can be omitted. The first gate G1 and the first capacitor electrode C1 can be formed by the same process. In addition, the first gate G1 and the first capacitor electrode C1 can be formed of the same material on the same layer.

[0068] The first interlayer insulating layer 113a can be disposed above the first gate insulating layer 112a, the first gate G1, and the first capacitor electrode C1. The first interlayer insulating layer 113a can be configured by a single layer or multiple layers of silicon nitride SiNx or silicon oxide SiOx. In addition, in the first interlayer insulating layer 113a, contact holes for exposing the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1 can be formed.

[0069] The second capacitor electrode C2 of the storage capacitor Cst can be disposed on the first interlayer insulating layer 113a. The second capacitor electrode C2 can be formed by a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof. The second capacitor electrode C2 can be formed on the first interlayer insulating layer 113a and overlap with the first capacitor electrode C1. In addition, the second capacitor electrode C2 can be formed of the same material as the first capacitor electrode C1. Based on the driving characteristics of the display device 100 and the structure and type of the thin film transistor, the second capacitor electrode C2 can be omitted.

[0070] The second buffer layer 114 can be disposed on the first interlayer insulating layer 113a and the second capacitor electrode C2. The second buffer layer 114 can be configured by a single layer or multiple layers of silicon nitride SiNx or silicon oxide SiOx. Contact holes for exposing the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1 can be formed in the second buffer layer 114. In addition, contact holes for exposing the second capacitor electrode C2 of the storage capacitor Cst can be formed in the second buffer layer 114.

[0071] The second buffer layer 114 can be formed by multiple layers, but is not limited thereto.

[0072] The second active layer A2 of the second thin film transistor TR2 can be disposed on the second buffer layer 114. Here, the second thin film transistor TR2 can include a second active layer A2, a second gate insulating layer 112b, a second gate G2, a second source S2, and a second drain D2. In addition, the first thin film transistor TR1 and the second thin film transistor TR2 can be disposed on different layers. The second thin film transistor TR2 can be disposed on the first thin film transistor TR1. However, the present invention is not limited thereto. Here, according to the design of the pixel circuit, the second source S2 can be used as the drain, and the second drain D2 can be used as the source.

[0073] In addition, the second active layer A2 may include: a second channel region where a channel is formed when driving the second thin film transistor TR2; and a second source region and a second drain region located on both sides of the second channel region. The second source region refers to a part of the second active layer A2 connected to the second source S2, and the second drain region refers to a part of the second active layer A2 connected to the second drain D2.

[0074] The second active layer A2 may be formed of an oxide semiconductor. The oxide semiconductor material has a larger bandgap than the silicon material, so that electrons do not jump across the bandgap in the off state. Therefore, the oxide semiconductor material has a low off-current. Therefore, a thin film transistor including an active layer formed of an oxide semiconductor is suitable for a switching thin film transistor that maintains a short on-time and a long off-time, but is not limited thereto. According to the characteristics of the display device 100, the oxide semiconductor can be used as a driving thin film transistor. In addition, due to the small off-current, the amplitude of the auxiliary capacitance can be reduced, so that the oxide semiconductor is suitable for a high-resolution display element. For example, the second active layer A2 may be formed of a metal oxide, and for example, may be formed of various metal oxides such as indium gallium zinc oxide (IGZO). Here, it is assumed that the second active layer A2 of the second thin film transistor TR2 is configured by IGZO among various metal oxides, but is not limited thereto. Therefore, the active layer may be formed of other metal oxides such as indium tin oxide (IZO), indium gallium tin oxide (IGTO), or indium gallium oxide (IGO) in addition to IGZO.

[0075] The second active layer A2 can be formed by depositing a metal oxide on the second buffer layer 114, performing heat treatment for stabilization, and then patterning the metal oxide.

[0076] The second gate insulating layer 112b may be provided on the entire substrate 110 including the second active layer A2. For example, the second gate insulating layer 112b may be configured by a single layer or multiple layers of silicon nitride SiNx or silicon oxide SiOx.

[0077] The second gate G2 may be provided on the second gate insulating layer 112b.

[0078] The second gate G2 may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof.

[0079] For example, a metal material is formed on the second gate insulating layer 112b, a photoresist pattern is formed on the metal material, and then the metal material is wet-etched using the photoresist pattern as a mask to form the second gate G2. As the wet etchant for etching the metal material, a material that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof that constitutes the metal material but does not etch the insulating material can be used.

[0080] The second interlayer insulating layer 113b may be disposed on the second gate insulating layer 112b and the second gate G2. Contact holes for exposing the first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2 may be formed in the second interlayer insulating layer 113b. For example, contact holes for exposing the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1 may be formed in the second interlayer insulating layer 113b. Contact holes for exposing the second source region and the second drain region of the second active layer A2 of the second thin film transistor TR2 may be formed in the second interlayer insulating layer 113b.

[0081] The second interlayer insulating layer 113b may be configured as a single layer or multiple layers of silicon nitride SiNx or silicon oxide SiOx.

[0082] The connection electrode CE, the first source S1 and the first drain D1 of the first thin film transistor TR1, and the second source S2 and the second drain D2 of the second thin film transistor TR2 may be disposed on the second interlayer insulating layer 113b.

[0083] The connection electrode CE may be electrically connected to the second drain D2 of the second thin film transistor TR2. In addition, the connection electrode CE may be electrically connected to the second capacitor electrode C2 of the storage capacitor Cst via contact holes formed in the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b. That is, the connection electrode CE may be used to electrically connect the second capacitor electrode C2 of the storage capacitor Cst and the second drain D2 of the second thin film transistor TR2 to each other.

[0084] Here, the first source S1 and the first drain D1 of the first thin film transistor TR1 may be connected to the first active layer A1 of the first thin film transistor TR1 via contact holes formed in the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0085] The second source S2 and the second drain D2 of the second thin film transistor TR2 may be connected to the second active layer A2 via contact holes formed in the second gate insulating layer 112b and the second interlayer insulating layer 113b.

[0086] The connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 can be formed of the same material by the same process.

[0087] For example, the connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 can be formed as a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof. For example, the connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 can be formed of a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but is not limited thereto.

[0088] The connecting electrode CE can be integrally formed to connect to the second drain electrode D2 of the second thin film transistor TR2, but is not limited thereto.

[0089] The planarization layer 115 includes a first planarization layer 115a and a second planarization layer 115b. The first planarization layer 115a can be disposed on the connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2, and the second interlayer insulating layer 113b.

[0090] The first planarization layer 115a can be an organic layer that planarizes the upper portions of the first thin film transistor TR1 and the second thin film transistor TR2 and protects the upper portions of the first thin film transistor TR1 and the second thin film transistor TR2. For example, the first planarization layer 115a can be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0091] The auxiliary electrode 145 can be disposed on the first planarization layer 115a. The auxiliary electrode 145 can be connected to the second drain electrode D2 of the second thin film transistor TR2 via a contact hole in the first planarization layer 115a. The auxiliary electrode 145 can be used to electrically connect the second thin film transistor TR2 and the anode 121 to each other. In addition, the auxiliary electrode 145 can be formed as a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof. The auxiliary electrode 145 can be formed of the same material as the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2.

[0092] The second planarization layer 115b may be disposed above the auxiliary electrode 145 and the first planarization layer 115a. In addition, although not shown in the figure, a third planarization layer may be disposed above the second planarization layer 115b. For example, the second planarization layer 115b and the third planarization layer may be formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The auxiliary electrode 145 may be disposed in at least one of the second planarization layer 115b and the third planarization layer to electrically connect the second thin film transistor TR2 to the light emitting diode 120.

[0093] The light emitting diode 120 may be disposed on the second planarization layer 115b.

[0094] The anode 121 may be disposed on the second planarization layer 115b. At this time, the anode 121 may be electrically connected to the auxiliary electrode 145 via a contact hole disposed in the second planarization layer 115b or the third planarization layer. The anode 121 may be formed of a metal material.

[0095] When the display device 100 is a top emission type in which light emitted from the light emitting diode 120 is emitted above the substrate 110, the anode 121 may further include a transparent conductive layer and a reflective layer on the transparent conductive layer. The transparent conductive layer may be formed of a transparent conductive oxide such as ITO or IZO, and the reflective layer may be formed of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

[0096] The bank 116a may be disposed while covering the anode 121. The bank 116a may be a pixel defining film that exposes the light emitting region of each pixel. A portion of the bank 116a corresponding to the light emitting region of the pixel may be exposed via an opening portion (hereinafter referred to as an opening region) of the bank 116a. At this time, the bank 116a may be formed of an inorganic insulating material such as silicon nitride SiNx or silicon oxide SiOx, an organic insulating material such as a benzocyclobutene-based resin, an acrylic-based resin, or an imide-based resin, or an opaque material (e.g., a black material) to prevent optical interference between adjacent pixels, and in this case, the bank 116a may include a light blocking material made of at least one of a color pigment, an organic black, and carbon, but is not limited thereto. The spacer 116b may be further disposed on the bank 116a.

[0097] The light emitting layer 122 may be disposed in the opening region of the bank 116a. Accordingly, the light emitting layer 122 may be disposed on the anode 121 exposed via the opening region of the bank 116a.

[0098] The cathode 123 may be disposed to cover the light emitting layer 122 and the bank 116a.

[0099] The light-emitting diode 120 may be formed by an anode 121, a light-emitting layer 122, and a cathode 123. The light-emitting layer 122 may include a plurality of organic films.

[0100] The encapsulation unit 117 may be located on the above-described light-emitting diode 120.

[0101] The encapsulation unit 117 may have a single-layer structure or a multi-layer structure. For example, the encapsulation unit 117 may include a first encapsulation layer 117a, a second encapsulation layer 117b, and a third encapsulation layer 117c.

[0102] At this time, the first encapsulation layer 117a and the third encapsulation layer 117c may be configured by an inorganic film, and the second encapsulation layer 117b may be configured by an organic film. Among the first encapsulation layer 117a, the second encapsulation layer 117b, and the third encapsulation layer 117c, the second encapsulation layer 117b is the thickest and serves as a planarization layer.

[0103] The first encapsulation layer 117a is disposed on the cathode 123 and may be disposed closest to the light-emitting diode 120. The first encapsulation layer 117a may be formed of an inorganic insulating material on which low-temperature deposition can be performed. For example, the first encapsulation layer 117a may be configured by silicon nitride SiNx, silicon oxide SiOx, silicon oxynitride SiON, or aluminum oxide Al2O3. The first encapsulation layer 117a is deposited in a low-temperature atmosphere so that damage to the light-emitting layer 122 including organic materials susceptible to high-temperature atmospheres can be suppressed during the deposition process.

[0104] The second encapsulation layer 117b may be formed to have a smaller area than the first encapsulation layer 117a. In this case, the second encapsulation layer 117b may be formed to expose both ends of the first encapsulation layer 117a. The second encapsulation layer 117b may serve as a buffer that reduces stress between layers due to bending of the flexible display device and enhances planarization performance.

[0105] For example, the second encapsulation layer 117b may be formed of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbide (SiOC). For example, the second encapsulation layer 117b may be formed by an inkjet method, but is not limited thereto.

[0106] The third encapsulation layer 117c may be formed above the substrate on which the second encapsulation layer 117b can be formed to cover the upper surface and side surfaces of the second encapsulation layer 117b and the first encapsulation layer 117a. At this time, the third encapsulation layer 117c may minimize or block the penetration of external moisture or oxygen into the first encapsulation layer 117a and the second encapsulation layer 117b. For example, the third encapsulation layer 117c may be configured by an inorganic insulating material such as silicon nitride SiNx, silicon oxide SiOx, silicon oxynitride SiON, or aluminum oxide Al2O3.

[0107] The touch sensing layer may be disposed on the encapsulation unit 117.

[0108] For example, the touch buffer layer 118a is disposed above the third encapsulation layer 117c, and the touch electrode TE may be disposed on the touch buffer layer 118a.

[0109] The touch electrode TE may include a touch sensor electrode TS and a touch bridge electrode BM located on different layers. A touch interlayer insulating layer 118b may be disposed between the touch sensor electrode TS and the touch bridge electrode BM.

[0110] The touch buffer layer 118a and the touch interlayer insulating layer 118b may be configured to remove steps at positions where the touch electrode TE is disposed and is electrically insulated.

[0111] Meanwhile, although not shown, a polarization layer may be disposed on the touch sensing layer.

[0112] The polarization layer suppresses reflection of external light on the display area DA of the substrate 110. When the display device 100 is used externally, external natural light enters and is reflected by the reflection layer included in the anode 121 of the light emitting diode 120 or is reflected by an electrode formed of metal and disposed below the light emitting diode 120. Therefore, the image of the display device 100 cannot be visually recognized due to the reflected light as described above. The polarization layer polarizes the light entering from the outside to a specific direction and suppresses the reflected light from being emitted to the outside of the display device 100.

[0113] Although not shown, a cover glass may be bonded to the polarization layer via an adhesive layer. The adhesive layer is used to adhere the components of the display device 100 to each other, and for example, an optically transparent display adhesive such as a pressure-sensitive adhesive, an optically clear adhesive (OCA), or an optically clear resin (OCR) may be used to form it, but is not limited thereto.

[0114] The cover glass protects the components of the display device 100 from external impacts and suppresses damage such as scratches.

[0115] Figure 3 corresponds to Figure 1 is an enlarged plan view of the region A of the optical area OA corresponding to Figure 4 is Figure 3 is an enlarged plan view of the region B of Figure 5 is Figure 4 is a cross-sectional view taken along the line V-V' of the region B of

[0116] Referring to Figure 3, the optical region OA includes a through hole TH for placing an optoelectronic device at the center, and a camera module or a sensor is disposed in the optical region. The optical region OA may include all regions where a circular or oval through hole TH, adjacent dams 150, and a connection suppression unit 140 are provided. The through hole TH can be removed by laser in the step of completing the panel. The non-display region NDA may be located between the through hole TH and the display region DA, and a high-potential power line PL and a gate line SL may be disposed therein. When the optical region OA is set, the pixel circuits and the light-emitting diodes 120 in the corresponding region are removed. However, it is necessary to electrically connect the pixel circuits and the light-emitting diodes 120 provided on the upper side, lower side, left side, and right side of the optical region OA. For this purpose, the high-potential power line PL and the gate line SL may be arranged to bypass the through hole TH and be connected in the upper side, lower side, left side, and right side in the non-display region NDA adjacent to the optical region OA.

[0117] Referring to Figure 3 , the connection suppression unit 140 is configured by a first suppression unit 141 and a second suppression unit 142, and a dam 150 surrounding the through hole TH may be disposed between the first suppression unit 141 and the second suppression unit 142. The connection suppression unit may be disposed closer to the through hole TH than the dam 150. In an exemplary embodiment of the present invention, one dam 150 is shown, but it is not limited thereto, and additional dams may be provided according to the spatial layout. Referring to Figure 3 , the first suppression unit 141, a metal wire 162, a second sensing line 132, a dam 150, and the second suppression unit 142 are sequentially disposed with respect to the through hole TH.

[0118] Generally, the dam 150 may be arranged to suppress the second encapsulation layer 117b, which is part of the encapsulation unit 117, located at the peripheral unit of the display panel DP, from flowing into the end portion of the peripheral unit of the display panel DP. Thereby, the adhesion between the upper substrate and the lower substrate constituting the display panel DP is maintained.

[0119] The dam 150 in the optical region OA is also formed to suppress the second encapsulation layer 117b of the encapsulation unit 117 for protecting the light-emitting diode 120 from invading or leaking into the optical region OA.

[0120] The first suppression unit 141 and the second suppression unit 142 may be arranged to protect the light-emitting diodes 120 in the display region from the influence of moisture or oxygen that may flow from the through hole TH. The cathode 123 of the light-emitting diode 120 is deposited on the front surface of the display panel DP and is also uniformly deposited in the optical region OA. Moisture and oxygen may be transmitted to the light-emitting diodes 120 in the display region DA via the cathode 123. To suppress this phenomenon, the cathode 123 may be partially disconnected by the first suppression unit 141 and the second suppression unit 142. In the present invention, two suppression units are shown, but it is not limited thereto.

[0121] The first suppression unit 141 includes a first structure 141-1 and a second structure 141-2, and the second suppression unit 142 includes a third structure 142-1 and a fourth structure 142-2. Refer to Figure 3 and 4 , it is understood that: the first suppression unit 141, the weir 150, and the second suppression unit 142 are formed within a closed loop around the through hole TH. The first suppression unit 141, the weir 150, and the second suppression unit 142 are formed in the closed loop. This is because, if any part is open, moisture and oxygen can penetrate from the outside into the display area DA, or conversely, the second encapsulation layer 117b can overflow from the inside to the optical area OA and further overflow to the through hole TH. Refer to Figure 4 , each of the first suppression unit 141 and the second suppression unit 142 can be configured by two structures, but it is not limited thereto. For example, one or three structures can be configured, but the present invention is not limited thereto.

[0122] Refer to Figure 3 , 4 and 5, the second sensing line 132 can be disposed between the first suppression unit 141 and the weir 150. That is, the second sensing line 132 can include a first branch portion 132a, a first external portion 132b, an internal portion 132c, a second external portion 132d, and a second branch portion 132e, and the internal portion 132c is disposed between the through hole TH and the first external portion 132b or the second external portion 132d. In addition, the first branch portion 132a and the second branch portion 132e are disposed to overlap the weir 150.

[0123] The through hole TH can be formed in the optical area OA of the display panel DP to provide a camera or an optical sensor. To form the through hole TH, a precise cutting process using a laser can be performed on the substrate 110 in the optical area OA of the display panel DP.

[0124] According to the shape of the optical area OA, the laser can be irradiated in a circular or elliptical shape, and all areas above the substrate 110 including the substrate 110 can be removed by irradiating the laser. However, the actual optical area OA and the laser irradiation area can be different, and for example, the laser irradiation area in the optical area OA can be an area starting from the inside by 100 μm. When the laser irradiation area and the optical area OA are different as described above, the insulating layer in the optical area OA will not be damaged due to laser irradiation.

[0125] As the laser, a picosecond laser or a femtosecond laser may be used, but not limited thereto. The laser uses stimulated emission light by amplifying light generated by applying energy to a specific material, and has characteristics similar to those of radio waves and has the directivity of monochromatic light, so that it is used for communication, medical, and industrial purposes. When using the laser, a pattern is formed in a desired portion or a specific portion can be easily removed. The laser uses energy to form or remove a pattern, and when the energy of the laser irradiates an object, the heat energy melts the object to form a pattern. As the irradiation time of the laser increases, a thermal effect that is transmitted adjacent to the portion where the pattern is formed can be generated. Due to this thermal effect, heat accumulates near the laser irradiation area of the object, so that an area larger than the surrounding area of the set pattern can be charred or deformed due to heat. If the area irradiated by the laser overlaps with or is adjacent to the insulating film, due to this laser characteristic, the heat energy of the laser can deform the insulating film. The insulating film deforms to generate cracks, and the cracks propagate through the insulating film, resulting in separation, or moisture or oxygen permeation can be generated therefrom. For example, within a distance of about 100 μm from the laser irradiation position, all insulating films can be removed to suppress the deformation or separation of insulating films such as the multiple buffer layer 111a, the active buffer layer 111b, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0126] Cracks generated when the substrate 110 is cut by the laser can be transmitted through a hard inorganic insulating layer that does not have flexibility. Optionally, when a camera or a sensor is assembled in the through hole TH formed by the laser, cracks may occur due to interruption. The cracks generated at this time also propagate through the inorganic insulating layer. When the cracks generated in the through hole TH propagate through the inorganic insulating layer, line defects or growth dark spot (GDS) defects may occur.

[0127] To suppress this problem, according to an exemplary embodiment of the present invention, when cracks appear near the through hole TH, a second sensing line 132 for sensing cracks may be provided. The second sensing line 132 may be provided on the same layer as the first sensing line 131.

[0128] According to an exemplary embodiment of the present invention, the second sensing line 132 may be formed to confirm the expansion of cracks generated on the cut surface of the through hole TH.

[0129] Refer to together Figure 2 、 45, according to an exemplary embodiment of the present invention, the second sensing line 132 may be disposed on the same layer as a plurality of touch sensor electrodes TS or a plurality of bridging electrodes BM provided on the encapsulation unit 117. Therefore, the second sensing line 132 can easily sense cracks generated on the encapsulation unit 117, but can hardly sense cracks generated in or transmitted through the inorganic insulating layer located below the encapsulation unit 117.

[0130] Therefore, according to an exemplary embodiment of the present invention, a plurality of metal patterns 161 may be further provided, which overlap with the second sensing line 132 below the second sensing line 132 along the periphery of the through hole TH. At least one of the plurality of metal patterns 161 may be electrically connected to the second sensing line 132. The plurality of metal patterns 161 may be formed in a polygon such as a triangle, a rectangle, or a pentagon, but the shape of the plurality of metal patterns 161 is not limited thereto.

[0131] For example, when cracks are generated in an inorganic insulating layer such as a multiple buffer layer 111a, an active buffer layer 111b, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, and a second interlayer insulating layer 113b, or the generated cracks are transmitted to an inorganic insulating layer such as a multiple buffer layer 111a, an active buffer layer 111b, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, and a second interlayer insulating layer 113b, a part of the second sensing line 132 connected to the plurality of metal patterns 161 is disconnected, and the resistance increases. Therefore, cracks generated in the inorganic insulating layer in the optical region OA or cracks transmitted to the inorganic insulating layer in the optical region OA can be accurately sensed.

[0132] According to an exemplary embodiment of the present invention, a metal wire 162 for connecting the plurality of metal patterns 161 may be further included. For example, the metal wire 162 may be disposed on the same layer as the gate line or the second gate G2 using the same material. The metal wire 162 connects between the plurality of metal patterns 161, so that even if cracks are generated in the region between the plurality of metal patterns 161, the cracks can be accurately sensed through the metal wire 162.

[0133] Refer together to Figure 4 and 5 , the first suppression unit 141 may include a first structure 141-1 and a second structure 141-2 (as referred to above with reference to Figure 4As described. The first structure 141-1 and the second structure 141-2 can be configured to have a two-level structure, including disconnecting the upper and lower parts of the cathode 123 that may become a moisture penetration path from the area provided with the through hole TH. In addition, an undercut structure can be formed on the upper side surface. Specifically, the upper part of the first structure 141-1 and the second structure 141-2 is set to have a trapezoidal cross-section that is regularly tapered (gradually narrowed), and the lower part is set to have a rectangular cross-section that is regularly tapered or has a constant height close to vertical. Therefore, there may be a difference in width on the bottom surface of the upper part and the top surface of the lower part where the upper and lower parts meet. The top surface of the lower part is formed to be narrower than the bottom surface of the upper part, and an undercut structure in which a part of the bottom surface of the upper part is exposed may occur. Thus, the cathode 123 deposited on the front surface of the display panel DP can be disconnected by the undercut structure on the upper side surface of the first structure 141-1 and the second structure 141-2 as described above.

[0134] The first structure 141-1 and the second structure 141-2 constituting the first suppression unit 141 can be formed of an organic material and an inorganic material. For example, the upper part of the first structure 141-1 and the second structure 141-2 can be formed of the same material as the first planarization layer 115a or the second planarization layer 115b, but is not limited thereto. In addition, the lower part of the first structure 141-1 and the second structure 141-2 can be formed of the same material as the second interlayer insulating layer 113b, but is not limited thereto.

[0135] The second suppression unit 142 can include a third structure 142-1 and a fourth structure 142-2. The third structure 142-1 and the fourth structure 142-2 constituting the second suppression unit 142 can be formed using a two-stage structure including an upper part and a lower part, which is similar to the first structure 141-1 and the second structure 141-2. The second encapsulation layer 117b provided on the second suppression unit 142 makes it difficult for moisture or oxygen to penetrate to the upper part. In order to block the path mainly penetrating through the side part provided with the through hole TH or the first suppression unit 141, similar to the first suppression unit 141, an undercut structure can be formed on the upper side surface. The first suppression unit 141 and the second suppression unit 142 are arranged such that moisture or oxygen penetrating through the cathode 123 into the light-emitting diode 120 in the optical region OA to the display region DA can be suppressed.

[0136] The third structure 142-1 and the fourth structure 142-2 constituting the second suppression unit 142 can also be formed of an organic material and an inorganic material. For example, the upper part of the third structure 142-1 and the fourth structure 142-2 can be formed of the same material as the first planarization layer 115a or the second planarization layer 115b, but is not limited thereto. In addition, the lower part of the third structure 142-1 and the fourth structure 142-2 can be formed of the same material as the second interlayer insulating layer 113b, but is not limited thereto.

[0137] As shown Figure 5 in FIG. 2, the dam 150 may be formed by laminating the second planarization layer 115b, the dam part 116a, and the spacer 116b, but is not limited thereto. The dam 150 may further include the first planarization layer 115a or other layers.

[0138] The second sensing line 132 disposed between the second structure 141-2 of the first suppression unit 141 and the dam 150 may be disposed on the same layer as the plurality of touch sensor electrodes TS or the plurality of touch bridge electrodes BM.

[0139] The second sensing line 132 may be electrically connected to the plurality of metal patterns 161 disposed on the same layer as the second gate G2 or the first gate G1 of the display panel DP through contact holes exposing a part of the plurality of metal patterns 161 on the plurality of metal patterns 161.

[0140] The line width of the second sensing line 132 is not limited, but may be selected in consideration of the structural dimensions of the first suppression unit 141 and the crack sensing sensitivity. The designed width of the second sensing line 132 may be smaller than the designed width of the structure of the first suppression unit 141 for suppressing the penetration of moisture and oxygen. The second sensing line 132 may be disposed adjacent to the second suppression unit 142. However, in order to detect whether a crack is generated in the initial stage, it is preferable to dispose the second sensing line between the first suppression unit 141 and the dam 150.

[0141] Figure 6 is a plan view of the display device 100 according to an exemplary embodiment of the present invention. Figure 6 The plan view of FIG. 3 is for explaining the contact of the plurality of metal patterns 161 and the second sensing line 132 in the optical region OA, and for ease of description, redundant descriptions other than the contact of the plurality of metal patterns 161 and the second sensing line 132 will be omitted.

[0142] According to another feature of the present invention, the plurality of metal patterns 161 may be connected to the second sensing line 132 on the plurality of metal patterns 161 through contact holes exposing a part of the plurality of metal patterns 161.

[0143] According to an exemplary embodiment of the present invention, even if only any one of the plurality of metal patterns 161 connected by a plurality of metal lines 162 is connected to the second sensing line 132, when cracks are generated in the inorganic insulating layer such as the multiple buffer layer 111a, the active buffer layer 111b, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b, or the generated cracks are transmitted to the inorganic insulating layer such as the multiple buffer layer 111a, the active buffer layer 111b, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b, a part of the second sensing line 132 connected to the plurality of metal patterns 161 is also disconnected and the resistance also increases. Therefore, cracks generated in the inorganic insulating layer in the optical area OA or cracks transmitted to the inorganic insulating layer in the optical area OA can be accurately sensed.

[0144] Hereinafter, reference will be made to Figure 7 describe the optical area OA of the display device according to another embodiment of the present invention in more detail.

[0145] Figure 7 is a plan view of a display device 200 according to another exemplary embodiment of the present invention. In Figure 7 In the plan view, the structure except for the metal lines connecting the plurality of metal patterns in the optical area OA is substantially the same as that described above. Therefore, for ease of description, redundant descriptions except for the plurality of metal patterns and metal lines such as the second sensing line 232 will be omitted.

[0146] In a display device 200 according to another exemplary embodiment of the present invention, a metal line 262 for connecting a plurality of metal patterns 261 is configured by a first part P1, a second part P2, a third part P3, and a fourth part P4. The second part P2 is opposite to the first part P1, the third part P3 is connected to one end of the first part P1 and one end of the second part P2, and the fourth part P4 is opposite to the third part P3 and is connected to the other end of the first part P1 and the other end of the second part P2. At least one of the first part P1, the second part P2, the third part P3, and the fourth part P4 of the metal line 262 is formed by a plurality of metal lines.

[0147] Specifically, the first part P1 may be formed by one metal line, the second part P2 may be formed by two metal lines, the third part P3 may be formed by three metal lines, and the fourth part P4 may be formed by four or five metal lines. For example, a plurality of metal lines 262 are connected in parallel or metal lines formed of the same material as the metal line 262 may be additionally arranged in parallel on the same layer.

[0148] According to another exemplary embodiment of the present invention, the number of metal wires 262 varies according to position, such that the first portion P1, second portion P2, third portion P3, and fourth portion P4 of the metal wires 262 may have different resistance values. Accordingly, when the metal wires 262 connecting the plurality of metal patterns 261 are disconnected due to cracks, the degree of increase in resistance may vary according to the number of cracks at which disconnection occurs. Therefore, when the number of metal wires 262 varies according to position, the location where cracks are generated can be accurately sensed.

[0149] Hereinafter, with reference to Figure 8 the optical area OA of the display device 300 according to still another exemplary embodiment of the present invention will be described in more detail.

[0150] Figure 8 is a plan view of the display device 300 according to still another exemplary embodiment of the present invention. In Figure 8 the plan view, the configuration except for the contact between the plurality of metal patterns 361 and the second sensing line 332 in the optical area OA is substantially the same as described above. Therefore, for ease of description, redundant descriptions except for the contact between the plurality of metal patterns 361 and the second sensing line 332 will be omitted.

[0151] In the display device 300 according to still another exemplary embodiment of the present invention, the plurality of metal patterns 361 may be connected to the second sensing line 332 on the plurality of metal patterns via contact holes exposing a portion of the plurality of metal patterns 361. For example, when contact holes are provided in at least two or more of the plurality of metal patterns 332, the second sensing line 332 may be electrically connected to at least two or more of the plurality of metal patterns 361 via the contact holes.

[0152] According to still another exemplary embodiment of the present invention, when at least two or more of the plurality of metal patterns 361 connected by a plurality of metal wires 362, and more desirably, when all of the plurality of metal patterns 361 connected by the plurality of metal wires 362 are connected to the second sensing line 332, if cracks are generated in the inorganic insulating layer such as the multiple buffer layer 111a, active buffer layer 111b, first gate insulating layer 112a, first interlayer insulating layer 113a, second buffer layer 114, second gate insulating layer 112b, and second interlayer insulating layer 113b, or if the generated cracks propagate to the inorganic insulating layer such as the multiple buffer layer 111a, active buffer layer 111b, first gate insulating layer 112a, first interlayer insulating layer 113a, second buffer layer 114, second gate insulating layer 112b, and second interlayer insulating layer 113b, a part of the second sensing line 332 connected to the plurality of metal patterns 361 is disconnected, and the resistance may increase. Accordingly, cracks generated in the inorganic insulating layer of the optical area OA or cracks propagating to the inorganic insulating layer of the optical area OA can be accurately sensed.

[0153] Exemplary embodiments of the present invention may also be described as follows.

[0154] According to one aspect of the present invention, a display device includes: a substrate including a display area, an optical area disposed in the display area and including a through hole, and a non-display area surrounding the display area; a first sensing line disposed in the non-display area and surrounding the periphery of the display area; a second sensing line disposed inside the first sensing line and surrounding the periphery of the through hole and the display area; and a plurality of metal patterns disposed along the periphery of the through hole under the second sensing line, and at least one of the plurality of metal patterns is electrically connected to the second sensing line.

[0155] The display device may further include a metal line for connecting the plurality of metal patterns.

[0156] The metal line for connecting the plurality of metal patterns may be configured by a first portion, a second portion, a third portion, and a fourth portion, the second portion being opposite to the first portion, the third portion being connected to one end of the first portion and one end of the second portion, the fourth portion being opposite to the third portion and connected to the other end of the first portion and the other end of the second portion, and at least one of the first portion, the second portion, the third portion, and the fourth portion of the metal line may be formed by a plurality of metal lines.

[0157] The second portion may be formed by two metal lines, the third portion may be formed by three metal lines, and the fourth portion may be formed by four metal lines.

[0158] The first portion, the second portion, the third portion, and the fourth portion of the metal line may have different resistance values.

[0159] The display area includes: a plurality of thin film transistors disposed on the substrate; a plurality of light emitting diodes disposed on the plurality of thin film transistors; a packaging unit covering the plurality of light emitting diodes; and a plurality of touch sensor electrodes and a plurality of touch bridging electrodes disposed on the packaging unit, wherein the second sensing line may be disposed on the same layer as the plurality of touch sensor electrodes or the plurality of touch bridging electrodes.

[0160] The first sensing line may be disposed on the same layer as the second sensing line.

[0161] The plurality of thin film transistors include: a first thin film transistor disposed on a substrate in the display area, the first thin film transistor including a first active layer containing silicon, a first gate, a first source, and a first drain; and a second thin film transistor disposed on the first thin film transistor, the second thin film transistor including a second active layer containing an oxide, a second gate, a second source, and a second drain, wherein the plurality of metal patterns may be formed on the same layer as the first gate.

[0162] The plurality of metal patterns may be connected to a second sensing line on the plurality of metal patterns through contact holes exposing a part of the plurality of metal patterns.

[0163] The contact holes may be provided in at least two or more of the plurality of metal patterns, and the second sensing line may be electrically connected to at least two or more of the plurality of metal patterns via the contact holes.

[0164] The display device may further include: at least one dam disposed on the substrate and surrounding the through hole; and at least one connection inhibiting unit disposed on the substrate and closer to the through hole than the at least one dam, and the second sensing line may be disposed between the dam and the connection inhibiting unit.

[0165] The display device may further include an optoelectronic device, and the optoelectronic device is disposed to overlap with the optical area.

[0166] Although the exemplary embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited thereto. Without departing from the technical concept of the present invention, the present invention can be implemented in many different forms. Therefore, the exemplary embodiments of the present invention are provided for illustrative purposes only and are not intended to limit the technical concept of the present invention. The scope of the technical concept of the present invention is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are exemplary in all respects and do not limit the present invention. The protection scope of the present invention should be interpreted based on the appended claims, and all technical concepts within the equivalent scope of the present invention should be interpreted as falling within the scope of the present invention.

Claims

1. A display device, comprising: A substrate, the substrate comprising a display area, an optical area disposed in the display area and comprising a through hole, and a non-display area surrounding the display area; a first sensing line, the first sensing line being disposed in the non-display area and surrounding a periphery of the display area; a second sensing line, the second sensing line being disposed at an inner side than the first sensing line and surrounding the through hole and the periphery of the display area; as well as a plurality of metal patterns, wherein the metal patterns are arranged below the second sensing line and along the periphery of the through hole, At least one of the plurality of metal patterns is electrically connected to the second sensing line.

2. The display device according to claim 1, further comprising: A metal line is used to connect the plurality of metal patterns.

3. The display device according to claim 1, wherein a metal line for connecting the plurality of metal patterns is configured by a first portion, a second portion, a third portion, and a fourth portion, the second portion being opposite to the first portion, the third portion being connected to one end of the first portion and one end of the second portion, the fourth portion being opposite to the third portion and connected to the other end of the first portion and the other end of the second portion, and at least one of the first portion, the second portion, the third portion, and the fourth portion of the metal line being formed by a plurality of metal lines. 4 . The display device according to claim 3 , wherein the second portion is formed by two metal lines, the third portion is formed by three metal lines, and the fourth portion is formed by four metal lines. 5 . The display device of claim 4 , wherein the first portion, the second portion, the third portion, and the fourth portion of the metal line have different resistance values.

6. The display device according to claim 1, wherein the display area comprises: a plurality of thin film transistors disposed on the substrate; a plurality of light emitting diodes disposed on the plurality of thin film transistors; a packaging unit covering the plurality of light emitting diodes; as well as A plurality of touch sensor electrodes and a plurality of touch bridge electrodes are arranged on the packaging unit, The second sensing line and the plurality of touch sensor electrodes or the plurality of touch bridge electrodes are arranged on the same layer. 7 . The display device according to claim 6 , wherein the first sensing line and the second sensing line are disposed on the same layer.

8. The display device according to claim 6, wherein the plurality of thin film transistors comprises: A first thin film transistor disposed on the substrate in the display area, the first thin film transistor comprising a first active layer including silicon, a first gate, a first source electrode, and a first drain electrode; as well as a second thin film transistor disposed on the first thin film transistor, the second thin film transistor comprising a second active layer including an oxide, a second gate electrode, a second source electrode, and a second drain electrode, The plurality of metal patterns are formed on the same layer as the first gate. 9 . The display device of claim 8 , wherein the plurality of metal patterns are connected to second sensing lines on the plurality of metal patterns through contact holes exposing portions of the plurality of metal patterns. 10 . The display device of claim 9 , wherein the contact hole is provided in at least two or more of the plurality of metal patterns, and the second sensing line is electrically connected to the at least two or more of the plurality of metal patterns via the contact hole.

11. The display device according to claim 1, further comprising: at least one dam disposed on the substrate and surrounding the through hole; as well as at least one connection suppressing unit provided on the substrate and disposed closer to the through hole than the at least one dam, The second sensing line is disposed between the at least one weir and the at least one connection suppressing unit.

12. The display device of claim 1, further comprising an optical electronic device disposed to overlap the optical zone.

13. A display device, comprising: A substrate, the substrate comprising a display area, an optical area disposed in the display area and comprising a through hole, and a non-display area surrounding the display area; a second sensing line, the second sensing line surrounding the through hole and the periphery of the display area, The display area includes a plurality of thin film transistors arranged on the substrate. The plurality of thin film transistors include: a first thin film transistor, the first thin film transistor being disposed on the substrate of the display area and comprising a first active layer including polycrystalline silicon; as well as The second thin film transistor includes a second active layer including an oxide. 14 . The display device according to claim 13 , wherein the first thin film transistor and the second thin film transistor are provided on different layers. 15 . The display device according to claim 14 , wherein the second thin film transistor is provided on the first thin film transistor. 16 . The display device according to claim 13 , wherein a first planarization layer is disposed on the first thin film transistor and the second thin film transistor, and a second planarization layer is disposed on the first planarization layer. 17 . The display device according to claim 16 , wherein a third planarization layer is provided on the second planarization layer. 18 . The display device according to claim 17 , wherein an auxiliary electrode is provided in at least one of the second planarization layer and the third planarization layer to electrically connect the second thin film transistor to a light emitting diode. 19 . The display device according to claim 18 , wherein the display area comprises a bank, and a light emitting layer of the light emitting diode is exposed through an opening area of ​​the bank.

20. The display device according to claim 19, wherein the bank is made of an opaque material.

21. The display device according to claim 19, wherein the bank comprises a light blocking material made of at least one of a color pigment, organic black, and carbon.

22. The display device according to claim 18, wherein a packaging unit is disposed above the light emitting diode. 23 . The display device according to claim 22 , wherein the display area comprises a plurality of touch sensor electrodes and a plurality of touch bridge electrodes disposed on the packaging unit. 24 . The display device of claim 23 , wherein the second sensing line is disposed on the same layer as the plurality of touch sensor electrodes or the plurality of touch bridge electrodes. 25 . The display device of claim 13 , wherein the second sensing line comprises a first branch portion, a first outer portion, an inner portion, a second outer portion, and a second branch portion, the inner portion being disposed between the through hole and the first outer portion or the second outer portion.

26. The display device according to claim 25, further comprising: at least one dam disposed on the substrate and surrounding the through hole, The first branch portion and the second branch portion are arranged to overlap with the at least one weir.

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