Local adaptive contrast enhancement techniques

Abstract

The invention relates to local adaptive contrast enhancement techniques. In one embodiment, an apparatus includes hardware circuitry to determine a tile brightness value and a tile contrast value for each of a plurality of tiles together constituting an input frame. The circuitry obtains a first enhancement factor based on the tile brightness value (e.g., from a first lookup table) and a second enhancement factor based on the tile contrast value (e.g., from a second lookup table). The circuitry generates an output frame based on the first enhancement factor and the second enhancement factor.

Description

Technical Field

[0001] The present disclosure relates to local adaptive contrast enhancement technology. Background Art

[0002] Contrast is a key element of visual perception because the human eye is very sensitive to differences in contrast. Enhancing contrast is effective in breaking stagnation, provides clarity, and helps the human eye distinguish different objects. Additionally, a sharp contrast image produces a "push-pull" effect on the human eye and attracts attention to where focus is needed, which is why high local contrast is appealing to users. Summary of the Invention

[0003] According to one aspect of the present disclosure, there is provided an apparatus including: a graphics processing circuit for: accessing an input frame of image data; determining a tile brightness value and a tile contrast value for each of a plurality of tiles that together constitute the input frame; obtaining a first enhancement factor based on the tile brightness value; obtaining a second enhancement factor based on the tile contrast value; and generating an output frame based on the first enhancement factor and the second enhancement factor.

[0004] According to one aspect of the present disclosure, there is provided a system including: a display; and a hardware circuit coupled to the display for: accessing an input frame of image data; determining a tile brightness value and a tile contrast value for each of a plurality of tiles that together constitute the input frame; obtaining a first enhancement factor based on the tile brightness value; obtaining a second enhancement factor based on the tile contrast value; generating an output frame based on the first enhancement factor and the second enhancement factor; and causing the output frame to be displayed on the display.

[0005] According to one aspect of the present disclosure, there is provided a method including: receiving an input frame of image data; accessing the input frame of image data; determining a tile brightness value and a tile contrast value for each of a plurality of tiles that together constitute the input frame; obtaining a first enhancement factor from a first look-up table based on the tile brightness value; obtaining a second enhancement factor from a second look-up table based on the tile contrast value; and generating an output frame based on the first enhancement factor and the second enhancement factor.

[0006] According to one aspect of the present disclosure, there is provided a computer program product including instructions that, when executed by a processor, cause the processor to perform the method as described above. Brief Description of the Drawings

[0007] Figure 1 Illustrates an example contrast enhancement technique according to an embodiment of the present disclosure.

[0008] Figures 2A - 2BIllustrates example lookup table values for the contrast enhancement techniques of the present disclosure.

[0009] Figure 3 Illustrates neighboring tiles of a display frame that can be considered in bilinear interpolation in the enhancement technique of the present disclosure.

[0010] Figure 4 Illustrates a flowchart of an example process for modifying an image to be displayed to enhance contrast according to an embodiment of the present disclosure.

[0011] Figure 5 Illustrates a simplified block diagram of a computing device that can incorporate aspects of the present disclosure.

[0012] Figure 6 Illustrates an example computing device that can incorporate aspects of the present disclosure.

[0013] Figure 7 Illustrates an example block diagram of a computing device that can incorporate aspects of the present disclosure.

[0014] Figure 8 Is a block diagram of computing device components that can be included in a mobile computing device incorporating aspects of the present disclosure.

[0015] Figure 9 Is a block diagram of an exemplary processor unit that can execute instructions. Detailed Description

[0016] In the following description, specific details are set forth, but aspects of the techniques described herein can be practiced without these specific details. Well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the understanding of this specification. Terms such as "one embodiment", "various embodiments", "some embodiments" may include features, structures, or characteristics, but not every embodiment necessarily includes that particular feature, structure, or characteristic.

[0017] Some embodiments may have some, all, or none of the features described for other embodiments. Descriptions such as “first,” “second,” “third,” etc. describe a common object and indicate that different instances of similar objects are being referred to. Such adjectives do not mean that the objects so described must be in a given sequence in terms of time or space, in ranking, or in any other way. “Connected” may indicate that elements have direct physical or electrical contact with each other, while “coupled” may indicate that elements cooperate or interact with each other, but they may or may not have direct physical or electrical contact. Terms modified by the word “substantially” include arrangements, orientations, spacings, or positions that are slightly different in meaning from the unmodified term. For example, a description of a lid of a mobile computing device that is rotatable relative to a base of the mobile computing to substantially 360 degrees includes a lid that is rotatable relative to the device base to within a few degrees of 360 degrees.

[0018] The description may use the phrases “in one embodiment,” “in an embodiment,” “in some embodiments,” and / or “in various embodiments,” each of which may refer to one or more identical or different embodiments. Additionally, the terms “comprising,” “including,” “having,” etc., used for aspects of the present disclosure are synonymous.

[0019] Reference is now made to the accompanying drawings, which are not necessarily drawn to scale, where like or identical reference numerals may be used to designate identical or similar parts in different figures. The use of like or identical reference numerals in different figures does not mean that all figures including the like or identical reference numerals constitute a single or the same embodiment. Like reference numerals with different alphabetical suffixes may represent different instances of similar components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed in this document.

[0020] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding thereof. However, it will be apparent that novel embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate the description. The intention is to cover all modifications, equivalents, and alternatives within the scope of the claims. Although aspects of the present disclosure may be used in any suitable type of computing device, the following examples describe an exemplary mobile computing device / environment in which aspects of the present disclosure may be implemented.

[0021] Aspects of the present disclosure provide techniques for enhancing local contrast in a memory - consuming - lower and adaptive manner. The term "adaptive" can refer to local correction depending on the environment and content, e.g., enhancement of a smaller region of a frame under different ambient lighting conditions. Currently, histogram equalization techniques can be used to perform local contrast enhancement. In these techniques, hardware (e.g., the display engine of a graphics processing unit) divides the frame buffer into square tiles (e.g., 128 - pixel square or 256 - pixel square) located at fixed positions within the frame, and calculates the histogram for each tile for each frame. Then, a software algorithm reads the histogram for each tile, calculates the image enhancement lookup table value (IET) for the tile, and programs the display engine hardware accordingly. With this technique, the processor (e.g., CPU) may need to be very busy reading histogram information and writing the IET into the hardware, even though the time required for the underlying algorithm processing is much less.

[0022] Embodiments herein provide enhancements to LUT - based techniques, such as the example described above. In a particular embodiment, for example, a variant of the unsharp masking (USM) technique can be employed, using two different user - configurable enhancement factors for contrast (e.g., FCLUT described below) and lightness (e.g., FBLUT described below) to enhance the image. These factors can address the over - sharpening problem common in USM techniques, which use a hardware - driven algorithm that requires less data movement (e.g., fewer reads / writes) between hardware and software, thus saving power compared to prior art that involves much more hardware reads / writes.

[0023] Figure 1 An example contrast enhancement technique in accordance with an embodiment of the present disclosure is illustrated. Figure 1 Aspects shown and described below can be implemented in hardware circuitry, e.g., within a graphics processing unit (e.g., Figure 5 in the display engine 513 of the graphics processing unit 512), within the timing controller (TCON) of a display (e.g., Figure 5 the TCON 519), or at another location (e.g., within other processing circuitry).

[0024] In the embodiments described herein, each frame may first be divided into rectangular or square tiles. Since the human eye can generally see objects within a 2-degree angle, the tile size may depend on the pixels per inch (PPI) of the display. For example, in some embodiments, 64x64 pixel square tiles may be used for a 1920x1080 resolution (e.g., the resolution of a standard 13-15 inch laptop display), which would result in approximately 510 tiles (number of tiles = round_up(1920 / 64)*round_up(1080 / 64) = 510), while a 4K resolution with the same display size may use tiles of double the size, 128x128 pixels (also resulting in approximately 510 tiles). In some embodiments, the position of the tiles may be fixed, while other embodiments may allow programmable tile positions.

[0025] As Figure 1 shown, certain aspects may be processed on a per-pixel basis ( Figure 1 the box with the white background in Figure 1 ), or on a per-tile basis (

[0026] the box with the shaded background in

[0027] ), for each frame. In an example technique, the frame is first processed to determine the luminance of each pixel in the frame. Luminance (luma) may represent the brightness of a pixel. Brightness may refer to the relative intensity of the energy output of a light source, which in this example is the pixel. In some embodiments, luminance may be determined based on a weighted sum of the linear RGB components of the pixel, where the value of each component may range from 0 - 255 respectively. An example formula for determining luminance (Y) using standard RGB color intensities is:

[0028] Luma(Y) = 0.299*R + 0.587*G + 0.114*B.

[0029] However, for each RGB color intensity, other weights may be used, such as:

[0030]

[0031] Next, a tile histogram can be generated (at 103) for each tile of the frame. The histogram can represent the pixel intensity (luminance) distribution in the frame and can be created for the pixel brightness determined for the tile using equally sized bins, where each bin represents a count of the number of pixels having a brightness within the brightness range of that bin. As an example, the histogram can include 32 bins, and an 8bpc image / frame can place luminance values [0 - 7] into bin 0, luminance values [8 - 15] into bin 1, and so on. Then, the tile histogram can be stored in the histogram buffer 104.

[0032] Then, based on the tile histogram, a tile contrast value can be determined (at 106) for each tile of the frame. Contrast can refer to the normalized distance between the highest and lowest filled bins in the tile histogram. For example, the tile contrast can be determined according to the following formula:

[0033]

[0034] where the dark bin index refers to the bin index when counting from the lowest bin index to the highest bin index and the cumulative histogram count totals to 4% of the pixel count in the tile; the bright bin index refers to the bin index when the cumulative histogram reaches 90% of the total pixel count while counting from the highest bin index to the lowest bin index; and the maximum bin index refers to the maximum possible separation between the bright bin index and the dark bin index (indicating the maximum possible contrast value). These thresholds (i.e., 4% and 90%) can be used because some bins may have very low pixel counts and treating these as the highest or lowest may not determine the accurate contrast perceived by the human eye. Thus, the above thresholds can be used to determine the points considered the darkest or brightest bins. In addition to the examples of 4% and 90%, other thresholds can be used as these are just examples.

[0035] Then, the contrast of each tile can be enhanced according to the disclosed technology. An existing contrast enhancement technique is unsharp masking (USM), which may result in oversharpening in low-contrast and low-luminance regions. Additionally, using standard USM techniques may also over-amplify noise in darker regions. However, embodiments herein overcome these limitations by using two user-configurable look-up tables for the enhancement factors to be used: FBLUT 105 for luminance and FCLUT 108 for contrast. Each of these tables may include a number of samples, and the value in each entry has a respective alpha value (also referred to herein as an "enhancement factor") for luminance or contrast, and these values can be used to determine the contrast enhancement value as further described below. In some embodiments, each alpha value can be in the range 0 - 1. These look-up tables are different from the prior art, which requires encoding a mathematical function (e.g., a power function or division) in hardware.

[0036] Figures 2A - 2B Illustrated are example look-up table values for the contrast enhancement technique of the present disclosure. Specifically, Figure 2A Illustrated are example alpha values for an FCLUT with 32 samples, and Figure 2B Illustrated are example alpha values for an FBLUT with 32 samples. Although each table includes 32 samples in the example shown, the number of samples can be any appropriate number. Each sample ( Figures 2A - 2B on the x-axis) can correspond to the scaled contrast / luminance value of the tile, as well as a scaling factor for determining which alpha to use in the table, which is determined by multiplying the normalized contrast / luminance of the tile by the number of samples in the table. That is, a tile with a lower normalized contrast / luminance value will use Figures 2A - 2B the alpha values on the left side of the chart shown, while a tile with a higher normalized contrast / luminance value will use Figures 2A - 2B the alpha values on the right side of the chart shown.

[0037] In some embodiments, the FCLUT alpha values can be selected to have a Gaussian distribution (e.g., similar to the kind shown in Figure 2A ). A Gaussian distribution may result in tiles with very low and very high contrast not being corrected much, and tiles with medium contrast being corrected relatively more. In some embodiments, the FBLUT alpha values can be selected to generally decrease gradually between samples, such that brighter tiles are not changed much, while tiles with medium contrast and medium to low luminance are enhanced relatively more. For example, referring to Figure 2A , tiles with lower and higher contrast values may be enhanced relatively less (i.e., lower alpha values) than tiles with medium-range contrast values, while referring to Figure 2B, tiles with lower lightness values may be enhanced more than tiles with higher lightness values. The distributions shown may be selected for at least the following reasons. If tiles with high contrast and high lightness values are enhanced, it may result in overcorrection. Additionally, enhancing tiles with low contrast values may result in noise. Therefore, medium range values may have a better enhancement range, and the distributions of the FCLUT and FBLUT may be selected accordingly, e.g., similar to those shown in Figures 2A - 2B However, aspects of the present disclosure may be implemented with other distributions different from those shown and described.

[0038] Returning to Figure 1 , the output brightness of the pixels of the enhanced frame image can then be determined using the FCLUT and FBLUT values, using the Adaptive Strength (AS) and Scaled Blurred Luma (SBL) values determined using the FCLUT and FBLUT at 110. The output brightness value can be determined, for example, according to the following formula (at 118):

[0039] OutLuma = AS' * InLuma – Scaled Blurred Luma;

[0040] where, OutLuma refers to the pixel brightness of the image output by the enhancement, InLuma refers to the pixel brightness of the image originally generated for display (the input of the enhancement algorithm), and:

[0041] AS (Adaptive Strength) = programmed fixed strength * alpha;

[0042] AS' = 1 + AS; and

[0043] Scaled Blurred Luma (SBL) = AS * Blurred Luma.

[0044] Blurred Luma may refer to the output of a spatial low-pass filter on a local area of the image. In some cases, the average brightness of the tiles of the pixels can be used for this value (i.e., Blurred Luma = Average Brightness). The average brightness can be determined based on a weighted average of histogram bins, where the weights of the bins are normalized bin indices, e.g., according to the following formula:

[0045]

[0046] The programmed fixed intensity can be a user-configurable constant value that the hardware can access from software. Alpha can be a function of the contrast and lightness of the tile and is determined by the alpha values in the FCLUT and FBLUT, respectively. For example, alpha can be determined by multiplying the alpha value obtained from a lookup in the FBLUT (first enhancement factor) by the alpha value obtained from a lookup in the FCLUT (second enhancement factor), as follows:

[0047] Alpha = alpha brightness *alpha contrast

[0048] The alpha values can be obtained from lookups in the FBLUT and FCLUT respectively based on the tile lightness and tile contrast values as described above, where the alpha values are selected based on scaled lightness or contrast values. For example, referring to the example LUT shown in Figures 2A - 2B a tile with a low-range lightness value and a mid-range contrast value can obtain a value of approximately 1 for each alpha value (see points 201, 202 in Figure 2A and 2B respectively). As another example, a tile with a low-range lightness value and a low-range contrast value can obtain a value of approximately 1 for the lightness alpha value (point 203 in Figure 2A ) and a value of approximately 0.4 for the contrast alpha value (point 204 in Figure 2B ).

[0049] As Figure 1 shown, AS' and SBL are values calculated for each tile. The AS' and SBL values for each tile are stored in memory (e.g., stored in random access memory (RAM) 116 as shown). This is different from existing solutions that may require storing the IET (lookup table) for each tile. This difference can save a significant amount of memory resources.

[0050] In some embodiments, spatial filtering (e.g., smoothing) can be performed to reduce the apparent differences at tile boundaries. For example, since the AS' and SBL values are calculated per tile, pixels of adjacent tiles may be enhanced in different ways. This can cause tile boundaries to be visible on the image output by the enhancement algorithm. By using a spatial filter (112), these between-tile variations in the enhancement factor can be minimized. For example, the parameters AS' and SBL of the current tile can be smoothed by using a weighted average of nearby tiles. For example, referring to Figure 3, the AS' and SBL values of tiles 301, 302, 303, 304, 306, 307, 308, 309 can all be used to determine the smoothed AS' and SBL values of the middle tile 305. The weights can represent a two-dimensional Gaussian function or some other spatial distribution.

[0051] Additionally, some embodiments may use a temporal filter (114) to provide smoothing over time between tiles, because the spatial smoothing described above may affect neighboring tiles even when not needed. For example, if a portion of a frame changes rapidly, that rapid change may affect pixels that have not changed. As an example, pixels that are changing within a certain portion of a video window may cause fluctuations in pixels that were originally fixed in another portion of the video (e.g., the background). To overcome these effects, an infinite impulse response (IIR) filter can be used to smooth out sharp changes in AS' and SBL over time. Then, these temporally smoothed AS' and SBL values can be used to determine the output luminance of the enhanced image.

[0052] In certain embodiments, bilinear interpolation can be performed on each pixel (e.g., at 120). Figure 3 Illustrated is an example of neighboring tiles of a display frame that can be considered in bilinear interpolation in the enhancement technique of the present disclosure. Consider Figure 3 the current pixel "P1" shown. The position of "P1" in tile 301 can be interpolated from the current tile 301 and its neighboring tiles 302, 304, 305. For example, the output luminance can be calculated using two linear interpolations between (1) the first and second tiles among the four tiles and (2) the third and fourth tiles among the four neighboring tiles, and the two interpolations are then combined. That is, the OutLuma value (e.g., the one described above) can be determined 4 times using the luminance of the current pixel (InLuma) and the (AS', SBL) from the four tiles surrounding the current pixel (i.e., Figure 3 (AS'1, SBL1), (AS'2, SBL2), (AS'3, SBL3), (AS'4, SBL4) shown for pixel P1 in

[0053] OutLuma′ = Bilinear Interpolation(OutLuma1, OutLuma2, OutLuma3, OutLuma4).

[0054] Then, based on the ratio of the interpolated output luminance (OutLuma') to the input luminance value (InLuma), a boost factor (LumaBoost) can be determined (at 122):

[0055] LumaBoost = L’out / Lin

[0056] Then, this boost factor can be used to determine (at 124) the output RGB value (RGBOut) of the pixel, for example:

[0057] RGBout = LumaBoost * RGBin

[0058] Figure 4 The flowchart of an example process 400 for modifying an image to be displayed to enhance contrast in accordance with an embodiment of the present disclosure is illustrated. Process 400 may include additional, fewer, or different operations compared to those shown or described below. In some embodiments, one or more of the operations shown include multiple operations, sub-operations, and the like. Particular embodiments may include hardware circuitry (e.g., the display engine circuitry or the timing controller circuitry described) to implement one or more of the operations shown. In some embodiments, instructions may be encoded into one or more computer-readable media such that, when executed, the instructions implement one or more of the operations shown.

[0059] At 402, frame data is accessed, e.g., from a system memory (e.g., a system random access memory (RAM)) or other memory. The frame data may have been previously generated by a graphics processing unit or other processing circuitry for display and stored in the memory. At 404, the frame is divided into a number of tiles as described above, and tile lightness values and tile contrast values are determined. The tile lightness value may be based on the average luminance of the constituent pixels of the tile, and the tile contrast value may be based on the tile histogram of the luminance values, e.g., as described above. In some embodiments, the tile contrast value may involve threshold processing such that outlier tiles (dark or bright) may not be considered, e.g., as described above.

[0060] At 406, a first enhancement factor and a second enhancement factor may be obtained for each tile. The enhancement factors may be obtained from a lookup table based on the tile lightness and contrast values, as described above. For example, alpha brightness may be the first enhancement factor obtained from the FBLUT, and alpha contrast may be the second enhancement factor obtained from the FCLUT. Thus, the first enhancement factor may be a lightness-related factor, and the second enhancement factor may be a contrast-related factor.

[0061] At 408, AS' and SBL values can be determined for each tile based on the obtained enhancement factor / alpha value. The AS' and SBL values can be determined in the manner described above. These values can be stored in the system memory (e.g., RAM). At 410, spatial filtering / smoothing can be performed using the AS' and SBL values of neighboring tiles, and at 412, temporal filtering / smoothing can be performed on the AS' and SBL values, as described above.

[0062] At 414, an output frame is generated using the AS' and SBL values, which includes determining output RGB values for display. The output RGB values can be determined by a luminance boost factor, e.g., as described above, and the luminance boost factor can be based on the ratio of the determined output luminance value (for the enhanced image) and the input luminance value of the pixel (from the unenhanced image). In some embodiments, bilinear interpolation of neighboring pixel luminance values can be performed to determine the output luminance value for each pixel.

[0063] Example computing system

[0064] Figure 5 A simplified block diagram of a computing device in which aspects of the present disclosure may be included is illustrated. A computing device 500 for selective update of a display is shown. In use, the illustrative computing device 500 determines one or more regions of the display to be updated. For example, a user may move a cursor, and the clock may vary from one frame to the next, requiring updates to two regions of the display. The computing device 500 sends the updated regions from a source to a sink in the display 518 via a link. In the illustrative embodiment, the source cannot directly access the link port, while the sink can directly access the link port. The source may send an indication that a particular update message is the last message to be sent for the current frame, after which the source will enter an idle period and not send update messages. Then, the sink can place the link in a low-power state to reduce power consumption.

[0065] The computing device 500 may be embodied as any type of computing device. For example, the computing device 500 may be embodied as or otherwise included in, without limitation, the following: server computers, embedded computing systems, system-on-a-chip (SoC), microprocessor systems, processor-based systems, consumer electronic devices, smart phones, cellular phones, desktop computers, tablet computers, notebook computers, laptop computers, network devices, routers, switches, networked computers, wearable computers, cellular phones, messaging devices, camera devices, and / or any other computing device. In some embodiments, the computing device 500 may be located in a data center, such as an enterprise data center (e.g., a data center owned and operated by a company and typically located at the company's location), a managed services data center (e.g., a data center managed by a third party on behalf of a company), a co-location data center (e.g., a data center in which the data center infrastructure is provided by a data center host and the company provides and manages its own data center components (servers, etc.)), a cloud data center (e.g., a data center operated by a cloud service provider that hosts company applications and data), and an edge data center (e.g., a data center that typically has a smaller footprint than other data center types and is located close to the geographical area it serves).

[0066] The illustrative computing device 500 includes a processor 502, a memory 504, an input / output (I / O) subsystem 506, a data storage device 508, a communication circuit 510, a graphics processing unit 512, a camera 514, a microphone 516, a display 518, and one or more peripheral devices 520. In some embodiments, one or more of the illustrative components of the computing device 500 may be included in another component or otherwise form a part of another component. For example, in some embodiments, the memory 504 or some portion thereof may be included in the processor 502. In some embodiments, one or more of the illustrative components may be physically separated from another component.

[0067] Processor 502 can be embodied as any type of processor capable of performing the functions described herein. For example, processor 502 can be embodied as a single-core or multi-core processor, a single-socket or multi-socket processor, a digital signal processor, a graphics processor, a neural network computing engine, an image processor, a microcontroller, or other processor or processing / control circuitry. Similarly, memory 504 can be embodied as any type of volatile or non-volatile memory or data storage device capable of performing the functions described herein. In operation, memory 504 can store various data and software used during the operation of computing device 500, such as an operating system, applications, programs, libraries, and drivers. Memory 504 is communicatively coupled to processor 502 via I / O subsystem 506, which can be embodied as circuitry and / or components for facilitating input / output operations with processor 502, memory 504, and other components of computing device 500. For example, I / O subsystem 506 can be embodied as or otherwise include a memory controller hub, an input / output control hub, a firmware device, a communication link (i.e., a point-to-point link, a bus link, a wire, a cable, an optical waveguide, a printed circuit board trace, etc.), and / or other components and subsystems for facilitating input / output operations. I / O subsystem 506 can utilize any suitable connectors, interconnections, buses, protocols, etc. (e.g., SoC architecture, USB2, USB3, USB4, etc.) to connect the various internal and external components of computing device 500 to each other. In some embodiments, I / O subsystem 506 can form part of a system-on-chip (SoC) and be included on a single integrated circuit chip along with processor 502, memory 504, and other components of computing device 500.

[0068] Data storage device 508 can be implemented as any type of one or more devices configured for short-term or long-term storage of data. For example, data storage device 508 can include any one or more memory devices and circuitry, memory cards, hard disk drives, solid state drives, or other data storage devices.

[0069] Communication circuitry 510 can be embodied as any type of interface capable of interfacing computing device 500 with other computing devices, such as via one or more wired or wireless connections. In some embodiments, communication circuitry 510 may be capable of interfacing with any suitable cable type, such as a cable or an optical fiber cable. Communication circuitry 510 can be configured to use any one or more communication technologies and associated protocols (e.g., Ethernet, WiMAX, near field communication (NFC), etc.). The communication circuit 510 may be located on a silicon chip separate from the processor 502, or the communication circuit 510 may be included in a multi-chip package together with the processor 502, or even on the same die as the processor 502. The communication circuit 510 may be embodied as one or more additional boards, daughter cards, network interface cards, controller chips, chip sets, specialized components such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), or other devices that can be used by the computing device 500 to connect to another computing device. In some embodiments, the communication circuit 510 may be embodied as part of a system-on-chip (SoC) that includes one or more processors, or may be included on a multi-chip package that also contains one or more processors. In some embodiments, the communication circuit 510 may include a local processor (not shown) and / or local memory (not shown) that are both local to the communication circuit 510. In such embodiments, the local processor of the communication circuit 510 may be capable of performing one or more functions of the processor 502 described herein. Additionally or alternatively, in such embodiments, the local memory of the communication circuit 510 may be integrated into one or more components of the computing device 500 at the board level, socket level, chip level, and / or other levels.

[0070] The graphics processing unit 512 is configured to perform certain computing tasks, such as video or graphics processing. The graphics processing unit 512 may be embodied as one or more processors, data processing units, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and / or any combination of the foregoing. In some embodiments, the graphics processing unit 512 may send frames or partial update regions to the display 518. For example, an exemplary graphics processing unit 512 includes a display engine 513, which may be embodied as hardware, firmware, software, virtualized hardware, emulation architectures, and / or combinations thereof, and is configured to determine the frames to be sent to the display 518 and send images to the display 518. In an illustrative embodiment, the display engine 513 is part of the graphics processing unit 512. In other embodiments, the display engine 513 may be part of the processor 502 or other components of the computing device 500.

[0071] In some embodiments, the display engine 513 may include circuitry for implementing aspects of the present disclosure, e.g., circuitry for implementing the computational aspects described above with reference to Figure 1 the computational aspects described above. For example, the display engine 513 may access frames stored in the memory 504, enhance the frames as described above, and then stream the frames to the display 518.

[0072] The camera 514 may include one or more fixed or adjustable lenses and one or more image sensors. The image sensor may be any suitable type of image sensor, such as a CMOS or CCD image sensor. The camera 514 may have any suitable aperture, focal length, field of view, etc. For example, the camera 514 may have a field of view of 60 - 110° in the azimuth and / or elevation directions.

[0073] The microphone 516 is configured to sense sound waves and output an electrical signal indicative of the sound waves. In an illustrative embodiment, the computing device 500 may have more than one microphone 516, e.g., an array of microphones 516 at different locations.

[0074] The display 518 may be embodied as any type of display that can be used to display information to a user of the computing device 500, such as a touchscreen display, a liquid crystal display (LCD), a thin film transistor LCD (TFT - LCD), a light - emitting diode (LED) display, an organic light - emitting diode (OLED) display, a cathode ray tube (CRT) display, a plasma display, an image projector (e.g., 2D or 3D), a laser projector, a head - up display, and / or other display technologies. The display 518 may have any suitable resolution, such as 7680×4320, 3840×2160, 1920×1200, 1920×1080, etc.

[0075] The display 518 includes a timing controller (TCON) 519 that includes circuitry to convert video data received from the graphics processing unit 512 into signals for driving the panel of the display 518. In some embodiments, the TCON 519 may also include circuitry to implement one or more aspects of the present disclosure. For example, the TCON 519 may include circuitry to implement the computational aspects described above with reference to Figure 1 the computational aspects described above. For example, the TCON 519 may enhance the frames received from the graphics processing unit 512 and stream the frames to the panel of the display 518.

[0076] In some embodiments, computing device 500 may include other or additional components, such as those common in computing devices. For example, computing device 500 may also have peripherals 520, such as a keyboard, a mouse, speakers, an external storage device, and so on. In some embodiments, computing device 500 may be connected to a docking station that can dock with various devices, including peripherals 520. In some embodiments, peripherals 520 may include additional sensors that computing device 500 can use to monitor video conferences, such as a time-of-flight sensor or a millimeter-wave sensor.

[0077] Figure 6 Illustrated is an example computing device 600 in which aspects of the present disclosure may be included. Computing device 600 may be a laptop computer (as shown) or another type of mobile computing device having similar form factors, such as a foldable tablet device or a smart phone. In some embodiments, embodiments of the present disclosure may be incorporated into a stand-alone display monitor that may be connected to a computing device that outputs image data to the display.

[0078] Computing device 600 includes a housing that includes a lid 623 having a cover A 624 and a cover B 625. When computing device 600 is in a closed configuration, cover A is the "world-facing" surface of lid 623, and when lid 623 is open (e.g., as shown), cover B includes a user-facing display 621. Computing device 600 also includes a base 629 having a cover C 626 and a cover D 627, where cover C includes a keyboard 622 that faces upward when device 600 is in an open configuration (e.g., as shown), and cover D forms the bottom of base 629. In some embodiments, base 629 includes the main computing resources of device 600 (e.g., one or more host processor units, a graphics processing unit (GPU)), as well as a battery, memory, and storage, and communicates with lid 623 via wires that pass through hinge 628 to connect base 629 and lid 623. In some embodiments, computing device 600 may be a dual-display device, and its second display includes a portion of cover C 626. For example, in some embodiments, an "always-on display" (AOD) may occupy an area of cover C that is located below the keyboard and is visible when lid 623 is closed. In other embodiments, the second display covers most of the surface of cover C, and a removable keyboard may be placed on the second display, or the second display may present a virtual keyboard to allow keyboard input.

[0079] Figure 7FIG. illustrates an example block diagram of a computing device in which aspects of the present disclosure may be included. Computing device 700 includes a base 710 connected to a lid 720 by a hinge 730. The mobile computing device (also referred to herein as a "user device") 700 may be a laptop computer or a mobile computing device with a similar form factor. Base 710 includes a host system-on-a-chip (SoC) 740, which includes one or more processor units integrated with one or more additional components, such as a memory controller, a graphics processing unit (GPU), a cache, an image processing module, and other components described herein. For example, SoC 740 may include Figure 5 one or more of the processor 502, memory 504, I / O subsystem 506, and graphics processing unit 512 of. Base 710 may also include a physical keyboard, a touchpad, a battery, a memory, a storage device, and external ports. Lid 720 includes an embedded display panel 745, a timing controller (TCON) 750, one or more microphones 758, one or more cameras 760, and a touch controller 765. TCON 750 converts the video data 790 received from SoC 740 into a signal for driving display panel 745.

[0080] Display panel 745 may be any type of embedded display in which the display elements responsible for generating or allowing the transmission of light are located in each pixel. Such displays may include TFT LCD (thin-film-transistor liquid crystal display), micro-LED (micro light-emitting diode (LED)), OLED (organic LED), and QLED (quantum dot LED) displays. Display panel 745 may include a touchscreen, which includes one or more dedicated layers for implementing touch capabilities, or "in-cell" or "on-cell" touchscreen technology that does not require a dedicated touchscreen layer. Touch controller 765 drives the touchscreen technology utilized in display panel 745 and collects touch sensor data provided by the touchscreen technology employed. Microphone 758 may include a microphone located in the bezel of the lid or an in-display microphone located in the display area, where the display area is the area of the panel's display content. One or more cameras 760 may similarly include a camera located in the bezel or an in-display camera located in the display area.

[0081] The hinge 730 can be any physical hinge that allows the base 710 and the lid 720 to be rotatably connected. The wires passing through the hinge 730 include wires for transferring video data from the SoC 740 to the TCON 750, wires for transferring audio data between the microphone 758 and the SoC 740, wires for providing image data from the camera 760 to the SoC 740, and wires for providing touch data from the touch controller 765 to the SoC 740. In some embodiments, the data shown as being transferred between the SoC and various components via different sets of wires is transferred via the same set of wires. For example, in some embodiments, all of the different types of data shown can be sent via a single PCIe-based or USB-based data bus. In some embodiments, the lid 720 is removably attached to the base 710. In some embodiments, the hinge can allow the base 710 and the lid 720 to rotate relative to each other by substantially 360 degrees.

[0082] Figure 7 The components illustrated as being located in the base of the mobile computing device can be located in the base housing (e.g., the base 629 of device 600), and Figure 7 The components illustrated as being located in the lid of the mobile computing device can be located in the lid housing (e.g., the lid 623 of device 600).

[0083] Figure 8 is a block diagram of computing device components that can be included in a mobile computing device incorporating aspects of the present disclosure. In some embodiments, for example, the illustrated components can be implemented within Figure 7 the SoC 740. Generally speaking, Figure 8 the illustrated components can communicate with the other illustrated components, although not all of the connections are shown for the sake of clarity. The component 800 includes a multi-processor system consisting of a first processor 802 and a second processor 804, and is illustrated as including point-to-point (P-P) interconnections. For example, the point-to-point (P-P) interface 806 of processor 802 is coupled to the point-to-point interface 807 of processor 804 via the point-to-point interconnect 805. It is to be understood that Figure 8 any or all of the point-to-point interconnections illustrated can alternatively be implemented as a multi-drop bus, and Figure 8 any or all of the buses illustrated can be replaced by point-to-point interconnections.

[0084] As Figure 8 shown, processors 802 and 804 are multi-core processors. Processor 802 includes processor cores 808 and 809, and processor 804 includes processor cores 810 and 811. Processor cores 808 - 811 can execute computer-executable instructions in a manner similar to that discussed below in connection with Figure 9 or in other ways.

[0085] Processors 802 and 804 also each include at least one shared cache memory 812 and 814, respectively. Shared caches 812 and 814 may store data (e.g., instructions) utilized by one or more components of the processors, such as processor cores 808 - 809 and 810 - 811. Shared caches 812 and 814 may be part of the memory hierarchy of the device. For example, shared cache 812 may locally store data that is also stored in memory 816 to allow components of processor 802 to access the data more quickly. In some embodiments, shared caches 812 and 814 may include multiple cache levels, such as a first level (L1), second level (L2), third level (L3), fourth level (L4), and / or other caches or cache levels, such as a last level cache (LLC).

[0086] Although two processors are shown, the device may include any number of processors or other computing resources. Additionally, a processor may include any number of processor cores. Processors may take various forms, such as a central processing unit, a controller, a graphics processor, an accelerator (e.g., a graphics accelerator, a digital signal processor (DSP), or an artificial intelligence (AI) accelerator). Processors in the device may be the same or different from other processors in the device. In some embodiments, the device may include one or more processors that are heterogeneous or asymmetric with respect to a first processor, an accelerator, a field programmable gate array (FPGA), or any other processor. Among the processing elements in the system, there may be a variety of differences in terms of the range of value metrics, including architectural characteristics, micro - architectural characteristics, thermal characteristics, power consumption characteristics, and so on. These differences may actually manifest themselves as asymmetry and heterogeneity among the processors in the system. In some embodiments, processors 802 and 804 reside in a multi - chip package. As used herein, the terms "processor unit" and "processing unit" may refer to any processor, processor core, component, module, engine, circuit, or any other processing element described herein. A processor unit or processing unit may be implemented in hardware, software, firmware, or any combination thereof that is capable of it.

[0087] Processors 802 and 804 also include memory controller logic (MC) 820 and 822. As Figure 8As shown, MCs 820 and 822 control memories 816 and 818 respectively coupled to processors 802 and 804. Memories 816 and 818 may include various types of memories, such as volatile memories (e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)) or non-volatile memories (e.g., flash memory, solid-state drive, chalcogenide-based phase change non-volatile memory). Although MCs 820 and 822 are illustrated as integrated into processors 802 and 804, in alternative embodiments, the MCs may be logic external to the processors and may include one or more layers of the memory hierarchy.

[0088] Processors 802 and 804 are coupled to an input / output (I / O) subsystem 830 via point-to-point (P-P) interconnections 832 and 834. Point-to-point interconnect 832 connects the point-to-point interface 836 of processor 802 to the point-to-point interface 838 of I / O subsystem 830, and point-to-point interconnect 834 connects the point-to-point interface 840 of processor 804 to the point-to-point interface 842 of I / O subsystem 830. Input / output subsystem 830 also includes an interface 850 to couple I / O subsystem 830 to a graphics module 852, which may be a high-performance graphics module. I / O subsystem 830 and graphics module 852 are coupled via a bus 854. Alternatively, bus 854 may be a point-to-point interconnect.

[0089] Input / output subsystem 830 is further coupled to a first bus 860 via an interface 862. First bus 860 may be a Peripheral Component Interconnect (PCI) bus, a PCI Express (PCIe) bus, another third-generation I / O (input / output) interconnect bus, or any other type of bus.

[0090] Various I / O devices 864 may be coupled to the first bus 860. A bus bridge 870 may couple the first bus 860 to the second bus 880. In some embodiments, the second bus 880 may be a low pin count (LPC) bus. Various devices may be coupled to the second bus 880, such as including a keyboard / mouse 882, an audio I / O device 888, and a storage device 890, such as a hard disk drive, a solid state drive, or other storage device for storing computer-executable instructions (code) 892. The code 892 may include computer-executable instructions for performing the techniques described herein. Other components that may be coupled to the second bus 880 include one or more communication devices or components 884, which may provide communication between the device and one or more wired or wireless networks 886 (such as Wi-Fi, cellular, or satellite networks) via one or more wired or wireless communication links (such as wires, cables, Ethernet connections, radio-frequency (RF) channels, infrared channels, Wi-Fi channels) using one or more communication standards (such as the IEEE 802.11 standards and their supplements).

[0091] The device may include removable memory, such as a flash card (e.g., Secure Digital (SD) card), a memory stick, a Subscriber Identity Module (SIM) card). Memory in the computing device (including caches 812 and 814, memories 816 and 818, and storage device 890) may store data and / or computer-executable instructions for executing an operating system 894 or an application 896. Example data includes web pages, text messages, images, sound files, video data, sensor data, or other data sets sent to or received from one or more network servers or other devices by the device via one or more wired or wireless networks and / or used by the device. The device may also access external memory (not shown), such as an external hard disk drive or cloud-based storage.

[0092] The operating system 894 may control Figure 8 the allocation and use of the components shown in, and support one or more applications 896. The applications 896 may include common mobile computing device applications (e.g., email applications, calendars, contact managers, web browsers, messaging applications) and other computing applications.

[0093] The device can support various input devices, such as touchscreens, microphones, cameras (single-lens or stereo), trackballs, touchpads, touch-sensitive pads, mice, keyboards, proximity sensors, light sensors, pressure sensors, infrared sensors, electrocardiogram (ECG) sensors, PPG (photoplethysmogram) sensors, galvanic skin response sensors, and one or more output devices, such as one or more speakers or displays. Either the input or output device can be internal to the device, external to the device, or removably attachable to the device. External input and output devices can communicate with the device via wired or wireless connections.

[0094] In addition, the computing device can provide one or more natural user interfaces (NUIs). For example, the operating system 894 or application 896 can include voice recognition as part of a voice user interface that allows the user to operate the device via voice commands. Additionally, the device can include input devices and components that allow the user to interact with the device via body, hand, or face gestures.

[0095] The device can also include one or more communication components 884. Component 884 can include a wireless communication component coupled to one or more antennas to support communication between the device and external devices. The antennas can be located in the base, the lid, or other parts of the device. The wireless communication component can support various wireless communication protocols and technologies, such as Near Field Communication (NFC), IEEE 802.11 (Wi-Fi) variants, WiMax, Bluetooth, Zigbee, 4G Long Term Evolution (LTE), Code Division Multiplexing Access (CDMA), Universal Mobile Telecommunication System (UMTS), and Global System for Mobile Telecommunication (GSM). Additionally, the wireless modem can support communication with one or more cellular networks to enable data and voice communication within a single cellular network, between cellular networks, or between the mobile computing device and the public switched telephone network (PSTN).

[0096] The device may also include at least one input / output port (such as a USB, IEEE 1394 (FireWire), Ethernet, and / or RS-232 port), which includes a physical connector; a power source (such as a rechargeable battery); a satellite navigation system receiver, such as a GPS receiver; a gyroscope; an accelerometer; and a compass. The GPS receiver may be coupled to a GPS antenna. The device may also include one or more additional antennas, coupled to one or more additional receivers, transmitters, and / or transceivers to enable additional features.

[0097] Figure 8 An example computing device architecture is illustrated. Computing devices based on alternative architectures may be used to implement the techniques described herein. For example, instead of having processors 802 and 804 and graphics module 852 located on separate integrated circuits, the computing device may include a system-on-chip (SoC) integrated circuit that includes one or more of the components shown in Figure 8 In one example, the SoC may include multiple processor cores, cache memory, a display driver, a GPU, multiple I / O controllers, an AI accelerator, an image processing unit driver, an I / O controller, an AI accelerator, an image processor unit. Additionally, the computing device may connect the components via a bus or point-to-point configuration different from that shown in Figure 8 Furthermore, Figure 8 the components illustrated in

[0098] Figure 9 are not necessarily required or all-inclusive, as in alternative embodiments, the illustrated components may be removed and other components may be added.

[0099] Figure 9 A block diagram of an example processor unit 900 for executing computer-executable instructions is also illustrated. The processor unit 900 may be any type of processor or processor core, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, or an accelerator. The processor unit 900 may be a single-threaded core or a multi-threaded core, as it may include more than one hardware thread context (or “logical processor”) in each core.

[0100] The processor core includes a front-end logic 920 that receives instructions from a memory 910. The instructions can be processed by one or more decoders 930. The decoder 930 can generate micro-operations such as fixed-width micro-operations in a predetermined format as its output, or can generate other instructions, micro-instructions, or control signals that reflect the original code instructions. The front-end logic 920 also includes a register renaming logic 935 and a scheduling logic 940, which generally allocate resources and queue operations corresponding to the execution of transformed instructions.

[0101] The processor unit 900 also includes an execution logic 950 that includes one or more execution units (EUs) 965-1 to 965-N. Some processor core embodiments may include several execution units dedicated to a specific function or set of functions. Other embodiments may include only one execution unit or an execution unit that can perform a specific function. The execution logic 950 executes the operations specified by the code instructions. After the execution of the operations specified by the code instructions is completed, the backend logic 970 retires the instructions using a retirement logic 975. In some embodiments, the processor unit 900 allows out-of-order execution of instructions but requires in-order retirement of instructions. The retirement logic 975 can take various forms known to those skilled in the art (e.g., a reorder buffer).

[0102] The processor unit 900 is transformed during the execution of the instructions, at least in terms of the output generated by the decoder 930, the hardware registers and tables utilized by the register renaming logic 935, and any registers (not shown) modified by the execution logic 950. Although not Figure 9 illustrated in, the processor may include other elements on the integrated chip together with the processor unit 900. For example, the processor may include additional elements such as memory control logic, one or more graphics modules, I / O control logic modules, and / or one or more caches.

[0103] As used in any embodiment herein, the term "module" refers to logic that can be implemented in a hardware component or device, software or firmware running on a processor, or a combination thereof, to perform one or more operations in accordance with the present disclosure. The software can be embodied as a software package, code, instructions, instruction set, and / or data recorded on a non-transitory computer-readable storage medium. The firmware can be embodied as code, instructions, or instruction set and / or data hard-coded (e.g., non-volatile) in a memory device. As used in any embodiment herein, the term "circuit" can include, alone or in any combination, hard-wired circuitry, programmable circuitry (e.g., a computer processor including one or more individual instruction processing cores), state machine circuitry, and / or firmware storing instructions executable by the programmable circuitry. The modules described herein can be embodied, collectively or individually, as circuitry forming part of one or more devices. Thus, any module can be implemented as circuitry, such as a consecutive item set generation circuit, an entropy-based discretization circuit, and so on. A computer device referred to as being programmed to perform a method can be programmed to perform the method via software, hardware, firmware, or a combination thereof.

[0104] The use of reference numerals in the claims and the specification is for the purpose of facilitating understanding of the claims and the specification and is not intended to be limiting.

[0105] Any disclosed method can be implemented as computer-executable instructions or a computer program product. Such instructions can cause a computer or one or more processors capable of executing computer-executable instructions to perform any disclosed method. Generally, as used herein, the term "computer" refers to any computing device or system described or referred to herein, or any other computing device. Thus, the term "computer-executable instructions" refers to instructions that can be executed by any computing device described or referred to herein or any other computing device.

[0106] The computer-executable instructions or the computer program product and any data created and used during the implementation of the disclosed technology can be stored on one or more tangible or non-transitory computer-readable storage media, such as optical media discs (e.g., DVDs, CDs), volatile memory components (e.g., DRAM, SRAM), or non-volatile memory components (e.g., flash memory, solid-state drives, chalcogenide-based phase change non-volatile memory). The computer-readable storage media can be included in a computer-readable storage device, such as a solid-state drive, a USB flash drive, and a memory module. Alternatively, the computer-executable instructions can be executed by a specific hardware component including hard-wired logic for performing all or part of the disclosed method, or by any combination of a computer-readable storage media and a hardware component.

[0107] Computer-executable instructions can be, for example, part of a dedicated software application or a software application accessed via a web browser or other software application (such as a remote computing application). Such software can be read and executed, for example, by a single computing device or by one or more networked computers in a network environment. Additionally, it is to be understood that the disclosed technology is not limited to any specific computer language or program. For example, the disclosed technology can be implemented by software written in C++, Java, Perl, Python, JavaScript, Adobe Flash, or any other suitable programming language. Similarly, the disclosed technology is not limited to any particular computer or any particular type of hardware.

[0108] Furthermore, any software-based embodiment (including, for example, computer-executable instructions for causing a computer to perform any of the disclosed methods) can be uploaded, downloaded, or remotely accessed by appropriate communication means. Such appropriate communication means include, for example, the Internet, the World Wide Web, an intranet, a cable (including an optical cable), magnetic communication, electromagnetic communication (including RF, microwave, and infrared communication), electronic communication, or other such communication means.

[0109] As used in this application and the claims, a list of items joined by the term "and / or" can mean any combination of the listed items. For example, the phrase "A, B, and / or C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C. Additionally, as used in this application and the claims, a list of items joined by the term "at least one of..." can mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C. Furthermore, as used in this application and the claims, a list of items joined by the term "one or more of..." can mean any combination of the listed terms. For example, the phrase "one or more of A, B, and C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0110] The disclosed methods, apparatuses, and systems should not be construed as limiting in any way. Instead, this disclosure is directed to all novel and non-obvious features and aspects of the various disclosed embodiments, whether alone or in various combinations and sub-combinations with each other. The disclosed methods, apparatuses, and systems are not limited to any particular aspect or feature or combination thereof, and the disclosed embodiments do not require the presence of any one or more particular advantages or the solution of any particular problems.

[0111] Although the operations of some of the disclosed methods are described in a particular order for convenience of presentation, it is to be understood that such description encompasses rearrangements, unless a particular order is required by specific language recited herein. For example, operations described in sequence may in some cases be rearranged or performed concurrently. In addition, for simplicity, the figures may not show the various ways in which the disclosed methods may be used in conjunction with other methods.

[0112] Certain non - limiting examples of the presently described technology are provided below. Each of the following non - limiting examples may stand alone, or may be combined with any one or more of the other examples provided below or throughout the present disclosure in any permutation or combination.

[0113] Example 1 is an apparatus that includes: a graphics processing circuit for: accessing an input frame of image data; determining a tile lightness value and a tile contrast value for each of a plurality of tiles that together form the input frame; obtaining a first enhancement factor based on the tile lightness value, e.g., from a first look - up table; obtaining a second enhancement factor based on the tile contrast value, e.g., from a second look - up table; and generating an output frame based on the first enhancement factor and the second enhancement factor.

[0114] Example 2 includes the subject matter of Example 1, wherein the circuit is further for each tile: determining an adaptive strength (AS) value by multiplying the first enhancement factor, the second enhancement factor, and a fixed value; and determining a scaled blur luminance (SBL) value by multiplying the AS value by the average luminance value of the tile; wherein the output frame is generated based on the AS value and the SBL value.

[0115] Example 3 includes the subject matter of Example 1 or 2, wherein each pixel of the output frame is generated based on multiplying the input luminance value of the pixel by the AS value corresponding to the frame of the pixel and subtracting the SBL value corresponding to the frame of the pixel.

[0116] Example 4 includes the subject matter of any one of Examples 1 - 3, wherein the circuit is for determining the tile contrast value based on a histogram of the lightness of the pixels of the tile.

[0117] Example 5 includes the subject matter of any one of Examples 1 - 4, wherein the circuit is for determining the tile lightness value by averaging the luminance values of the pixels of the tile.

[0118] Example 6 includes the subject matter of any one of Examples 2 - 5, wherein the circuit is further for performing temporal smoothing of the AS value and the SBL value using an infinite impulse response (IIR) filter to generate the output frame.

[0119] Example 7 includes the subject matter as described in any one of Examples 1-6, wherein the circuit is configured to perform bilinear interpolation of output luminance values of adjacent pixels to generate pixel luminance values of the output frame.

[0120] Example 8 includes the subject matter as described in any one of Examples 1-7, wherein the circuit is further configured to: determine a luminance boost factor for each pixel based on the input luminance value of the pixel and the output luminance value of the pixel, wherein the output luminance value is based on the first enhancement factor and the second enhancement factor; and generate the output frame by applying the luminance boost factor to the input RGB values for each pixel.

[0121] Example 9 is a system that includes: a display; and a circuit coupled to the display for: accessing an input frame of image data; determining a tile lightness value and a tile contrast value for each of a plurality of tiles that together form the input frame; obtaining a first enhancement factor based on the tile lightness value, for example, from a first look-up table; obtaining a second enhancement factor based on the tile contrast value, for example, from a second look-up table; generating an output frame based on the first enhancement factor and the second enhancement factor; and causing the output frame to be displayed on the display.

[0122] Example 10 includes the subject matter as described in Example 9, wherein the circuit is further configured for each tile to: determine an adaptive strength (AS) value by multiplying the first enhancement factor, the second enhancement factor, and a fixed value; and determine a scaled blur luminance (SBL) value by multiplying the AS value by the average luminance value of the tile; wherein the output frame is generated based on the AS value and the SBL value.

[0123] Example 11 includes the subject matter as described in Example 9 or 10, wherein each pixel of the output frame is generated based on multiplying the input luminance value of the pixel by the AS value corresponding to the frame of the pixel and subtracting the SBL value corresponding to the frame of the pixel.

[0124] Example 12 includes the subject matter as described in any one of Examples 9-11, wherein the circuit is configured to determine the tile contrast value based on a histogram of the lightness of the pixels of the tile.

[0125] Example 13 includes the subject matter as described in any one of Examples 9-12, wherein the circuit is configured to determine the tile lightness value by averaging the luminance values of the pixels of the tile.

[0126] Example 14 includes the subject matter as described in any one of Examples 10-13, wherein the circuit is further configured to perform temporal smoothing of the AS value and the SBL value using an infinite impulse response (IIR) filter to generate the output frame.

[0127] Example 15 includes the subject matter as described in any one of Examples 9-14, wherein the circuit is configured to perform bilinear interpolation of output luminance values of adjacent pixels to generate pixel luminance values of the output frame.

[0128] Example 16 includes the subject matter as described in any one of Examples 9-15, wherein the circuit is further configured to: determine a luminance boost factor for each pixel based on the input luminance value of the pixel and the output luminance value of the pixel, wherein the output luminance value is based on the first enhancement factor and the second enhancement factor; and generate the output frame by applying the luminance boost factor to the input RGB values for each pixel.

[0129] Example 17 includes the subject matter as described in any one of Examples 9-16, wherein the circuit is within a graphics processing unit (GPU) of the system, and the circuit is configured to access the input frame data from a memory of the system.

[0130] Example 18 includes the subject matter as described in any one of Examples 9-16, wherein the circuit is within a timing controller of the system.

[0131] Example 19 is a method that includes: receiving an input frame of image data; accessing the input frame of image data; determining a tile lightness value and a tile contrast value for each of a plurality of tiles that together constitute the input frame; obtaining a first enhancement factor from a first look-up table based on the tile lightness value; obtaining a second enhancement factor from a second look-up table based on the tile contrast value; and generating an output frame based on the first enhancement factor and the second enhancement factor.

[0132] Example 20 includes the subject matter as described in Example 19, and further includes, for each tile: determining an adaptive strength (AS) value by multiplying the first enhancement factor, the second enhancement factor, and a fixed value; and determining a scaled blur luminance (SBL) value by multiplying the AS value by an average luminance value of the tile; wherein the output frame is generated based on the AS value and the SBL value.

[0133] Example 21 includes the subject matter as described in Example 19 or 20, wherein each pixel of the output frame is generated based on multiplying the input luminance value of the pixel by the AS value corresponding to the frame of the pixel and subtracting the SBL value corresponding to the frame of the pixel.

[0134] Example 22 includes the subject matter as described in any one of Examples 19-21, wherein the tile contrast value is determined based on a histogram of the lightness of the pixels of the tile.

[0135] Example 23 includes the subject matter as described in any one of Examples 19-22, wherein the tile lightness value is determined by averaging the luminance values of the pixels of the tile.

[0136] Example 24 includes the subject matter as described in any one of Examples 19-23, and further includes performing temporal smoothing of the AS value and the SBL value using an infinite impulse response (IIR) filter.

[0137] Example 25 includes the subject matter as described in any one of Examples 19-24, and further includes performing bilinear interpolation of the output luminance values of neighboring pixels to generate the pixel luminance values of the output frame.

[0138] Example 26 includes the subject matter as described in any one of Examples 19-25, and further includes: determining a brightness boost factor for each pixel based on the input luminance value of the pixel and the output luminance value of the pixel, wherein the output luminance value is based on the first enhancement factor and the second enhancement factor; and generating the output frame by applying the brightness boost factor to the input RGB value for each pixel.

[0139] Example 27 includes the subject matter as described in any one of Examples 19-26, wherein the output frame is generated by circuitry within a graphics processing unit (GPU) of the system.

[0140] Example 28 includes the subject matter as described in any one of Examples 19-26, wherein the output frame is generated by a timing controller (TCON) of a display.

[0141] Example 29 includes one or more computer-readable storage media, the media including instructions that, when executed by a processing circuit, cause the processing circuit to implement the method as described in any one of Examples 19-28.

[0142] Example 30 is an apparatus that includes circuitry for implementing the method as described in any one of Examples 19-28 or for implementing any other aspect described herein.

[0143] Example 31 is a computing system that includes circuitry for implementing the apparatus as described in any one of Examples 1-8, circuitry for implementing the method as described in any one of Examples 19-28, or circuitry for implementing any other aspect described herein.

[0144] Example 32 includes the subject matter as described in any of the previous examples, wherein the first look-up table includes a set of values that generally decrease between its indices, and the second look-up table includes values that are generally or substantially Gaussian distributed between its indices.

Claims

1. A device comprising: Graphics processing circuit for: Access input frames of image data; determining a tile brightness value and a tile contrast value for each tile of a plurality of tiles that together constitute the input frame; Obtaining a first enhancement factor based on the tile brightness value; Obtaining a second enhancement factor based on the tile contrast value; and An output frame is generated based on the first enhancement factor and the second enhancement factor.

2. The device according to claim 1, wherein: The circuit is also used for each tile: determining an adaptation strength (AS) value by multiplying the first enhancement factor, the second enhancement factor, and a fixed value; and determining a scaled blurred brightness (SBL) value by multiplying the AS value by an average brightness value of the tile; The output frame is generated based on the AS value and the SBL value.

3. The device as claimed in claim 2, wherein: Each pixel of the output frame is generated based on multiplying the input luminance value of the pixel by the AS value corresponding to the frame of the pixel and subtracting the SBL value corresponding to the frame of the pixel.

4. The device according to claim 2, wherein: The circuit is further configured to perform temporal smoothing of the AS and SBL values ​​using an infinite impulse response (IIR) filter to generate the output frame.

5. The device according to claim 1, wherein: The circuit is for determining the tile contrast value based on a histogram of brightness of pixels of the tile.

6. The device according to claim 1, wherein: The circuit is used to determine the tile brightness value by averaging the brightness values ​​of the pixels of the tile.

7. The device of claim 1, wherein: The circuit is configured to perform bilinear interpolation of output luminance values ​​of neighboring pixels to generate pixel luminance values ​​of the output frame.

8. The device of claim 1, wherein: The first enhancement factor is obtained from a first lookup table, and the second enhancement factor is obtained from a second lookup table.

9. The device of claim 8, wherein: The first lookup table includes a generally decreasing set of values ​​across its indices, and the second lookup table includes a generally Gaussian distributed set of values ​​across its indices.

10. The device according to any one of claims 1 to 9, wherein: The circuit is also used for: Determine, for each pixel, a brightness boost factor based on an input brightness value of the pixel and an output brightness value of the pixel, wherein the output brightness value is based on the first enhancement factor and the second enhancement factor; and The output frame is generated by applying the brightness boost factor to the input RGB values ​​for each pixel.

11. A system comprising: monitor; as well as A hardware circuit coupled to the display, configured to: Access input frames of image data; determining a tile brightness value and a tile contrast value for each tile of a plurality of tiles that together constitute the input frame; Obtaining a first enhancement factor based on the tile brightness value; Obtaining a second enhancement factor based on the tile contrast value; generating an output frame based on the first enhancement factor and the second enhancement factor; and The output frame is caused to be displayed on the display.

12. The system of claim 11, wherein: The circuit is also used for each tile: determining an adaptation strength (AS) value by multiplying the first enhancement factor, the second enhancement factor, and a fixed value; and determining a scaled blurred brightness (SBL) value by multiplying the AS value by an average brightness value of the tile; The output frame is generated based on the AS value and the SBL value.

13. The system of claim 12, wherein: Each pixel of the output frame is generated based on multiplying the input luminance value of the pixel by the AS value corresponding to the frame of the pixel and subtracting the SBL value corresponding to the frame of the pixel.

14. The system of claim 12, wherein: The circuit is further configured to perform temporal smoothing of the AS and SBL values ​​using an infinite impulse response (IIR) filter to generate the output frame.

15. The system of claim 11, wherein: The circuit is configured to perform bilinear interpolation of output luminance values ​​of neighboring pixels to generate pixel luminance values ​​of the output frame.

16. The system of claim 11, wherein: The circuit is also used for: Determine, for each pixel, a brightness boost factor based on an input brightness value of the pixel and an output brightness value of the pixel, wherein the output brightness value is based on the first enhancement factor and the second enhancement factor; and The output frame is generated by applying the brightness boost factor to the input RGB values ​​for each pixel.

17. The system of claim 11, wherein: The first enhancement factor is obtained from a first lookup table, and the second enhancement factor is obtained from a second lookup table.

18. The system of claim 17, wherein: The first lookup table includes a generally decreasing set of values ​​across its indices, and the second lookup table includes a generally Gaussian distributed set of values ​​across its indices.

19. The system of any one of claims 11 to 18, wherein: The circuit is within a graphics processing unit (GPU) of the system, and the circuit is used to access the input frame data from a memory of the system.

20. The system of any one of claims 11-18, wherein: The circuit is within a timing controller of the system.

21. A method comprising: receiving an input frame of image data; Access input frames of image data; determining a tile brightness value and a tile contrast value for each tile of a plurality of tiles that together constitute the input frame; Obtaining a first enhancement factor based on the tile brightness value from a first lookup table; obtaining, from a second lookup table, a second enhancement factor based on the tile contrast value; and An output frame is generated based on the first enhancement factor and the second enhancement factor.

22. The method of claim 21, further comprising, for each tile: determining an adaptation strength (AS) value by multiplying the first enhancement factor, the second enhancement factor, and a fixed value; and A scaled blurred brightness (SBL) value is determined by multiplying the AS value by the average brightness value of the tile.

23. The method of claim 21, wherein: Each pixel of the output frame is generated based on multiplying the input luminance value of the pixel by the AS value corresponding to the frame of the pixel and subtracting the SBL value corresponding to the frame of the pixel.

24. The method of claim 21, wherein: The first lookup table includes a generally decreasing set of values ​​across its indices, and the second lookup table includes a generally Gaussian distributed set of values ​​across its indices.

25. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method according to any one of claims 21 to 24.

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