Gate driver and display device including the same

Abstract

The invention discloses a gate driver and a display device including the same. A gate driver includes: a plurality of signal transmission sections configured to be connected in correlation via carry lines to which carry signals are applied from previous signal transmission sections, in which an (n)-th signal transmission section includes: a first output circuit section configured to receive carry signals from the previous signal transmission sections, and to transmit the carry signals to the previous signal transmission sections; and outputs a carry signal and a first strobe signal according to the voltage of the first-1 control node and the voltage of the first-2 control node; a second output circuit section configured to output a second strobe signal in accordance with voltages of a second-1 control node connected to the first-2 control node and a second-2 control node connected to the first-1 control node; and a third output circuit section configured to output a third strobe signal in accordance with voltages of a third-1 control node connected to the first-2 control node and a third-2 control node connected to the first-1 control node.

Description

Technical Field

[0001] The present disclosure relates to a gate driver and a display device including the same. Background Art

[0002] Display devices include liquid crystal display (LCD) devices, electroluminescent display devices, field emission display (FED) devices, plasma display panels (PDPs), and the like.

[0003] According to the material of the light-emitting layer, electroluminescent display devices are classified into inorganic light-emitting display devices and organic light-emitting display devices. An active matrix organic light-emitting display device includes an organic light-emitting diode that emits light itself (hereinafter referred to as "OLED"), and has advantages such as a fast response speed, high luminous efficiency, high brightness, and a wide viewing angle.

[0004] Some of the display devices (e.g., liquid crystal display devices or organic light-emitting display devices) include: a display panel including a plurality of sub-pixels, a driver that outputs drive signals for driving the display panel, a power supply that generates power to be supplied to the display panel or the driver, and the like. The driver includes: a gate driver that supplies gate signals such as scan signals and emission signals to the display panel, and a data driver that supplies data signals to the display panel.

[0005] In such a display device, when drive signals such as scan signals, EM (emission) signals, and data signals are supplied to a plurality of pixels formed in the display panel, the selected pixels transmit light or directly emit light to thereby display an image. Summary of the Invention

[0006] Each of the plurality of pixels includes a pixel circuit and drives a plurality of switching elements included in the pixel circuit according to a plurality of gate signals. As the number of switching elements increases, the number of gate signals may increase, and the size of the bezel increases because a gate driver and signal lines configured to output the gate signals may be added as many as the number.

[0007] The present disclosure aims to solve all the above needs and limitations.

[0008] The present disclosure provides a gate driver and a display device including the same.

[0009] It should be noted that the benefits of the present disclosure are not limited to the above benefits, and other benefits of the present disclosure will be apparent to those skilled in the art from the following description.

[0010] A gate driver according to an embodiment of the present disclosure may include: a plurality of signal transmission units, the plurality of signal transmission units being configured to be connected in relation via a carry line to which a carry signal is applied from a previous signal transmission unit, wherein the (n)th signal transmission unit (where n is a positive integer) includes: a first output circuit unit configured to receive a carry signal from a previous signal transmission unit and output a carry signal and a first gate signal according to a voltage of a first - 1 control node and a voltage of a first - 2 control node; a second output circuit unit configured to output a second gate signal according to a voltage of a second - 1 control node connected to the first - 2 control node and a voltage of a second - 2 control node connected to the first - 1 control node; and a third output circuit unit configured to output a third gate signal according to a voltage of a third - 1 control node connected to the first - 2 control node and a voltage of a third - 2 control node connected to the first - 1 control node.

[0011] A display device according to an embodiment of the present disclosure may include: a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixels are arranged; a data driver configured to supply a data voltage of pixel data to the data lines; and a gate driver configured to supply a gate signal to the gate lines, wherein the gate driver includes a plurality of signal transmission units configured to be connected in relation via a carry line to which a carry signal is applied from a previous signal transmission unit, and wherein the (n)th signal transmission unit (where n is a positive integer) includes: a first output circuit unit configured to receive a carry signal from a previous signal transmission unit and output a carry signal and a first gate signal according to a voltage of a first - 1 control node and a voltage of a first - 2 control node; a second output circuit unit configured to output a second gate signal according to a voltage of a second - 1 control node connected to the first - 2 control node and a voltage of a second - 2 control node connected to the first - 1 control node; and a third output circuit unit configured to output a third gate signal according to a voltage of a third - 1 control node connected to the first - 2 control node and a voltage of a third - 2 control node connected to the first - 1 control node.

[0012] According to the present disclosure, by implementing one EM driver and two scan drivers that are separately driven as one gate driver, the number of gate drivers, the number of signal lines for them, and the number of pins on the pads can be reduced, thereby reducing the bezel size.

[0013] In the present disclosure, since multiple gate signals are output using internal signals instead of separate external signals, power consumption can be reduced, and low-power driving can be performed.

[0014] The effects of this specification are not limited to the effects mentioned above, and those skilled in the art will clearly understand other effects not mentioned above based on the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] By referring to the accompanying drawings and describing in detail the exemplary embodiments of the present disclosure, the above and other benefits, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art, where:

[0016] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0017] Figure 2 is an illustration of Figure 1 a cross-sectional view of the cross-sectional structure of the display panel shown;

[0018] Figure 3 is a diagram illustrating a pixel circuit according to a first embodiment of the present disclosure;

[0019] Figure 4 is an illustration of Figure 3 the driving timing of the pixel circuit shown;

[0020] Figure 5 is a diagram illustrating the configuration of a gate driver according to an embodiment of the present disclosure;

[0021] Figure 6 is for explaining Figure 5 the signal application principle of the third gate driver shown;

[0022] Figure 7 is a diagram schematically illustrating a shift register of a gate driver according to an embodiment of the present disclosure;

[0023] Figure 8 is a detailed circuit diagram illustrating a first EM driver according to an embodiment of the present disclosure;

[0024] Figure 9 is an illustration of Figure 8 the driving waveform of the first EM driver illustrated;

[0025] Figure 10 is a detailed circuit diagram illustrating a gate driver according to an embodiment of the present disclosure;

[0026] Figure 11 is an illustration of Figure 10Diagram of the driving waveform of the illustrated strobe driver;

[0027] Figures 12 to 17 is a diagram for explaining the operating principle of the strobe driver according to Figure 11 ; and

[0028] Figure 18 is a diagram illustrating the simulation results of the strobe driver according to an embodiment. Detailed Description of the Preferred Embodiment

[0029] With reference to the preferred embodiments described in detail in conjunction with the accompanying drawings, the advantages and features of this specification and the methods for realizing them will become apparent. However, this specification is not limited to the embodiments to be described below and can be implemented in different forms. These embodiments are provided only to fully disclose the present disclosure and convey the full scope of the present disclosure to those skilled in the art, and this specification is defined by the disclosed claims.

[0030] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings for explaining the embodiments of the present disclosure are illustrative, and the present disclosure is not limited to the details depicted. Throughout the specification, the same reference numerals refer to the same components. In addition, when describing the present disclosure, if it is determined that the relevant known technologies will unnecessarily obscure the key points of the present disclosure, the detailed descriptions of these technologies will be omitted.

[0031] When using terms such as "comprising", "having", "consisting of", etc. mentioned in this specification, other parts can be added unless "only" is used. Unless otherwise clearly stated, the case of expressing a component in the singular form includes the plural form.

[0032] When explaining a component, it can be understood that the error range is included even if there is no separate and explicit description.

[0033] In the case of describing the positional relationship, for example, when the positional relationship between two parts is described as "on", "on the upper part", "on the lower part", "next to", etc., unless "immediately" or "directly" is used, one or more other parts can be located between these two parts.

[0034] Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below can also be the second component within the technical concept of the present disclosure.

[0035] Throughout the present disclosure, the same reference numerals can refer to substantially the same elements.

[0036] The following embodiments can be joined or combined with each other in part or in whole, and can be linked and operated in technically different ways. These embodiments can be implemented independently of or in association with each other.

[0037] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0038] In the display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors can be implemented as oxide thin film transistors (oxide TFTs) including an oxide semiconductor, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, and the like.

[0039] A transistor is a three - electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers flow starting from the source. The drain is an electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. The n - channel transistor has a current direction flowing from the drain to the source. In the case of a p - channel transistor (p - channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as the first electrode and the second electrode.

[0040] The gate signal swings between a gate - on voltage and a gate - off voltage. The gate - on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate - off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0041] The transistor conducts in response to the gate - on voltage and cuts off in response to the gate - off voltage. In the case of an n - channel transistor, the gate - on voltage can be a gate - high voltage, and the gate - off voltage can be a gate - low voltage. In the case of a p - channel transistor, the gate - on voltage can be a gate - low voltage, and the gate - off voltage can be a gate - high voltage.

[0042] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2 is illustrative Figure 1 is a cross - sectional view illustrating the cross - sectional structure of the display panel shown.

[0043] Refer toFigure 1 and Figure 2 ,According to an embodiment of the present disclosure, a display device includes: a display panel 100, a display panel driving unit configured to write pixel data to pixels of the display panel 100, and a power supply unit 400 configured to generate power required to drive the pixels and the display panel driving unit.

[0044] The display panel 100 includes a pixel array AA that displays an input image. The pixel array AA includes: a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and pixels arranged in a matrix form.

[0045] The pixel array AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel row share the gate line GL. Sub-pixels arranged in the column direction Y along the data line direction share the same data line DL. One horizontal period 1H is a time obtained by dividing one frame period by the total number of the pixel rows L1 to LN.

[0046] A touch sensor may be disposed on the display panel 100. Touch input may be sensed using a separate touch sensor, or may be sensed through pixels. The touch sensor may be disposed as an on-cell type or an additional type on the screen of the display panel, or may be implemented as an in-cell type touch sensor embedded in the pixel array AA.

[0047] The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic film may be disposed on the backplane of the plastic OLED panel, and the pixel array AA may be formed on the organic film.

[0048] The backplane of the plastic OLED may be a polyethylene terephthalate (PET) substrate. The organic film is formed on the backplane. The pixel array AA and the touch sensor array may be formed on the organic film. The backplane blocks moisture penetration so that the pixel array AA is not exposed to moisture. The organic film may be a polyimide (PI) film substrate. A multi-layer buffer film may be formed of an insulating material (not shown) on the organic film. Circuits may be formed on the organic film to supply power or signals applied to the pixel array AA and the touch sensor array.

[0049] To achieve colors, each pixel may be divided into a red sub-pixel (hereinafter referred to as "R sub-pixel"), a green sub-pixel (hereinafter referred to as "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as "B sub-pixel"). Each pixel may also include a white sub-pixel. Each sub-pixel 101 includes a pixel circuit. The pixel circuit is connected to the data line DL and the gate line GL.

[0050] The cross-sectional structure of the display panel 100 may include a circuit layer CIR, a light-emitting element layer EMIL, and a packaging layer ENC laminated on a substrate SUBS, as Figure 2 shown.

[0051] The circuit layer CIR may include a thin-film transistor (TFT) array, a gate driver, and a demultiplexer. The thin-film transistor array includes pixel circuits connected to wirings such as data lines, gate lines, power supply lines, etc. The circuit layer CIR includes a plurality of metal layers and a semiconductor material layer insulated by an interposed insulating layer. All transistors formed in the circuit layer CIR may be implemented as n-channel oxide TFTs.

[0052] The light-emitting element layer EMIL may include light-emitting elements driven by pixel circuits. The light-emitting elements may include light-emitting elements for red sub-pixels, light-emitting elements for green sub-pixels, and light-emitting elements for blue sub-pixels. The light-emitting element layer EMIL may further include light-emitting elements for white sub-pixels. The light-emitting element layer EMIL corresponding to each sub-pixel may have a structure in which a light-emitting element and a color filter are laminated. The light-emitting elements EL in the light-emitting element layer EMIL may be covered by a plurality of protective layers including organic films and inorganic films.

[0053] The packaging layer ENC covers the light-emitting element layer EMIL to seal the circuit layer CIR and the light-emitting element layer EMIL. The packaging layer ENC may also have a multi-insulating film structure in which organic films and inorganic films are alternately laminated. The inorganic film blocks the penetration of moisture and oxygen. The organic film planarizes the surface of the inorganic film. When the organic film and the inorganic film are laminated in multiple layers, the movement path of moisture and oxygen becomes longer than that of a single layer, so that the penetration of moisture and oxygen affecting the light-emitting element layer EMIL can be effectively blocked.

[0054] A touch sensor layer (not shown) may be formed on the encapsulation layer ENC, and a polarizer or a color filter layer may be disposed thereon. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may have a metal wiring pattern and an insulating film that form the capacitance of the touch sensor. The insulating film may insulate an area where the metal wiring patterns intersect and may planarize the surface of the touch sensor layer. The polarizer may improve visibility and contrast by converting the polarization of external light reflected by the metal in the touch sensor layer and the circuit layer. The polarizer may be implemented as a circular polarizer or a polarizer in which a linear polarizer and a phase retardation film are bonded together. A cover glass may be adhered to the polarizer. The color filter layer may include a red color filter, a green color filter, and a blue color filter. The color filter layer may further include a black matrix pattern. The color filter layer may replace the polarizer by absorbing a part of the wavelength of light reflected from the circuit layer and the touch sensor layer and may increase the color purity of the image reproduced in the pixel array.

[0055] The power supply unit 400 generates direct current (DC) power required to drive the display panel driving unit and the pixel array of the display panel 100 by using a DC-DC converter. The DC-DC converter may include: a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 600 may adjust the level of the input DC voltage applied from a host system (not shown) to generate constant voltages (or DC voltages) such as a gamma reference voltage VGMA, a gate-on voltage VGH and VEH, a gate-off voltage VGL and VEL, a pixel driving voltage EVDD, a low-potential power supply voltage EVSS, an initialization voltage VINIT, and a reference voltage VREF. The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltage VGH and VEH and the gate-off voltage VGL and VEL are supplied to the gate driver 120. Constant voltages such as the pixel driving voltage EVDD, the low-potential power supply voltage EVSS, the initialization voltage VINIT, and the reference voltage VREF are commonly supplied to the pixels.

[0056] The display panel driving unit writes the pixel data of the input image into the pixels of the display panel 100 under the control of the timing controller (TCON) 130.

[0057] The display panel driving unit includes a data driver 110 and a gate driver 120.

[0058] A demultiplexer (DEMUX) may be disposed between the data driver 110 and the data line DL. From Figure 1The demultiplexer is omitted. The demultiplexer sequentially connects one channel of the data driver 110 to a plurality of data lines DL, and distributes the data voltage output from one channel of the data driver 110 to the data lines DL in a time-division manner, thereby reducing the number of channels of the data driver 110.

[0059] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. From Figure 1 the touch sensor driver is omitted. In the mobile device, the timing controller 130, the power supply unit 400, the data driver 110, etc. may be integrated into one driving integrated circuit (IC).

[0060] The data driver 110 converts the pixel data of the input image received from the timing controller 130 into a gamma compensation voltage at each frame period by using a digital-to-analog converter (DAC), thereby generating a data voltage Vdata. The gamma reference voltage VGMA is divided for each gray level through a voltage divider circuit. The gamma compensation voltage obtained by dividing the gamma reference voltage VGMA is supplied to the DAC of the data driver 110. The data voltage Vdata is output through an output buffer in each channel of the data driver 110.

[0061] In the data driver 110, the output buffer included in one channel may be connected to adjacent data lines DL through a demultiplexer array 112 (not shown). The demultiplexer array 112 may be directly formed on the substrate of the display panel 100, or the demultiplexer array 112 may be integrated with the data driver 110 into one driving IC.

[0062] The gate driver 120 may be implemented as an in-panel gate (GIP) circuit directly formed on the border BZ area of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs gate signals to the gate lines GL under the control of the timing controller 130. The gate driver 120 may sequentially supply gate signals to the gate lines GL by shifting the gate signals by using a shift register.

[0063] The clock output from the level shifter 140 may swing between the gate-on voltage VGH and the gate-off voltage VGL, and may be supplied to the gate driver 120 through the clock line CL. The gate driver 120 may use the clock output from the level shifter 140 to sequentially output gate signals.

[0064] The timing controller 130 receives digital video data DATA of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes: a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, a data enable signal DE, etc. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0065] The timing controller 130 multiplies the input frame frequency by i, and controls the operation timing of the display panel driving circuit at a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase Alternating Line) scheme.

[0066] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a MUX signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120.

[0067] The voltage level of the gate timing control signal output from the timing controller 130 can be converted into a gate on voltage VGH and VEH and a gate off voltage VGL and VEL by a level shifter (not shown), and then supplied to the gate driver 120. That is, the level shifter converts the low-level voltage of the gate timing control signal into the gate off voltage VGL and VEL, and converts the high-level voltage of the gate timing control signal into the gate on voltage VGH and VEH. The gate timing signal includes a start pulse and a shift clock.

[0068] The host system may include a motherboard of one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system. In this case, the data driver 110, the gate driver 120, the timing controller 130, etc. can be integrated into one driving IC (DIC) in a mobile device or a wearable device.

[0069] Figure 3 FIG. is an illustration of a pixel circuit according to a first embodiment of the present disclosure. Figure 4 is an illustration Figure 3 of the driving timing of the pixel circuit shown.

[0070] Refer to Figure 3, a pixel circuit according to a first embodiment of the present disclosure includes: a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switching elements T1 to T5 that switch a current path connected to the driving element DT, a first capacitor Cst that stores the gate-source voltage of the driving element DT, and a second capacitor C2. The driving element DT and the switching elements T1 to T7 can be implemented as N-channel TFTs, but are not limited thereto.

[0071] The light-emitting element EL emits light by a current applied through a channel of the driving element DT according to the gate-source voltage Vgs of the driving element DT, which varies according to the data voltage Vdata. The light-emitting element EL can be implemented as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include: a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, an electron injection layer EIL, etc., but is not limited thereto. The anode of the light-emitting element EL is connected to the driving element DT through a fourth node n4, and the cathode of the light-emitting element EL is connected to a pixel base voltage line or a second power supply line 42 to which a pixel base voltage EVSS is applied.

[0072] The OLED used as the light-emitting element EL may have a tandem structure in which a plurality of light-emitting layers are stacked. The OLED having a tandem structure can improve the brightness and lifetime of the pixel.

[0073] The driving element DT drives the light-emitting element EL by supplying current to the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes: a gate electrode connected to a second node n2, a first electrode (or drain) connected to a first node n1, and a second electrode (or source) connected to a third node n3.

[0074] The first switching element T1 is turned on according to the strobe conduction voltage of the first EM signal EM1 to supply a pixel driving voltage EVDD to the driving element DT. The first switching element T1 includes: a gate electrode to which the first EM signal EM1 is applied, a first electrode connected to a pixel driving voltage line or a first power supply line 41 to which a pixel driving voltage is applied, and a second electrode connected to the first node n1.

[0075] The second switching element T2 is turned on according to the strobe conduction voltage of the first scan signal SCAN1 to connect the data line DL to the second node n2, thereby applying a data voltage Vdata. The second switching element T2 includes: a gate electrode to which the first scan signal SCAN1 is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0076] The third switching element T3 is turned on according to the strobe conduction voltage of the second scan signal SCAN2 to apply a reference voltage Vref to the second node n2 by connecting the reference voltage line or the third power supply line 43 to the second node n2. The third switching element T3 includes: a gate electrode to which the second scan signal SCAN2 is applied, a first electrode connected to the third power supply line 43, and a second electrode connected to the second node n2.

[0077] The fourth switching element T4 is turned on according to the strobe conduction voltage of the second EM signal EM2 to connect the third node n3 and the fourth node n4. The fourth switching element T4 includes: a gate electrode to which the second EM signal EM2 is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0078] The fifth switching element T5 is turned on according to the strobe conduction voltage of the third scan signal SCAN3 to connect the initialization voltage line or the fourth power supply line 44 to the fourth node n4, thereby applying an initialization voltage Vinit. The fifth switching element T5 includes: a gate electrode to which the third scan signal SCAN3 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fourth power supply line 44.

[0079] The first capacitor Cst can be connected between the second node n2 and the third node n3. The first capacitor Cst can be charged with the gate-source voltage Vgs of the driving element DT.

[0080] The second capacitor C2 can be connected between the third node n3 and the first power supply line 41.

[0081] Referring Figures 3 to 4 , the pixel circuit according to an embodiment of the present disclosure can be driven in the order of an initialization step Tini, a sensing step Ts, a data writing step Tw, an OBS step Tobs, and a light emitting step Tem.

[0082] In the initialization step Tini, the pixel circuit is initialized. The reference voltage Vref initializes the second node n2, and the initialization voltage initializes the third node n3. In the sensing step Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst.

[0083] In the data writing step Tw, a data voltage Vdata of pixel data is applied to the second node n2.

[0084] In the OBS step Tobs, an initialization voltage Vinit is applied to the third node n3 and then the third node n3 is initialized. And in the light emission step Tem, after the voltages of the second node n2 and the third node n3 are increased, the light emitting element EL can emit light to a brightness corresponding to the gray value of the pixel data.

[0085] Figure 5 FIG. is a diagram illustrating a configuration of a gate driver according to an embodiment of the present disclosure. Figure 6 is for explaining Figure 5 a view of the signal application principle of the third gate driver shown.

[0086] Since Figure 3 the pixel circuit illustrated requires five gate signals (i.e., SCAN1, SCAN2, SCAN3, EM1, and EM2), five separate gate drivers should be configured. In order to reduce the bezel size by reducing the number of gate drivers, the embodiment aims to configure one gate driver that outputs multiple gate signals.

[0087] In this case, the gate driver configured to output SCAN1 can be implemented in a shift register type, and the gate drivers configured to output SCAN2, SCAN3, EM1, and EM2 can be implemented in an edge trigger type. Therefore, in the present embodiment, SCAN2, SCAN3, and EM2 of the same type or substantially the same type can be implemented as one gate driver.

[0088] Referring to Figure 5 , the gate driver 120 according to an embodiment of the present disclosure can be configured to include: a first gate driver 121 configured to output a first scan signal SCAN1, a second gate driver 122 configured to output a first EM signal EM1, and a third gate driver 123 configured to output a second scan signal SCAN2, a third scan signal SCAN3, and a second EM signal EM2.

[0089] Referring to Figure 6 , the third gate driver 123 according to the embodiment can apply a second scan signal SCAN2, a third scan signal SCAN3, and a second EM signal EM2 to the pixel circuit.

[0090] For example, the third gate driver 123 can apply a second scan signal SCAN2(1), a third scan signal SCAN3(1), and a second EM signal EM2(1) to the first pixel circuit P1.

[0091] As another example, the third gate driver 123 may apply a second scan signal SCAN2(n), a third scan signal SCAN3(n), and a second EM signal EM2(n) to the (n)th pixel circuit Pn.

[0092] Figure 7 FIG. is a diagram schematically illustrating a shift register of a gate driver according to an embodiment of the present disclosure.

[0093] Referring to Figure 7 , the gate driver according to the embodiment includes a shift register that sequentially outputs gate signals in synchronization with a shift clock CLK.

[0094] The shift register includes a plurality of signal transmission units ST_D(1), ST_D(2), ST(1),..., ST(n - 2), ST(n - 1), and ST(n), which are connected to each other via carry lines that transmit carry signals.

[0095] The start signal VST is generally input to the first signal transmission unit. Here, the first signal transmission unit ST_D(1) may be the first signal transmission unit that receives the start signal VST.

[0096] Each of the signal transmission units ST_D(1), ST_D(2), ST(1),..., ST(n - 2), ST(n - 1), and ST(n) receives a start pulse or a carry signal output from a previous signal transmission unit and receives the shift clock CLK. The first signal transmission unit ST_D(1) starts to be driven according to the start pulse Vst, and the other signal transmission units ST_D(2), ST(1),..., ST(n - 2), ST(n - 1), and ST(n) start to be driven by receiving a carry signal from a previous signal transmission unit. The shift clock CLK may be an N-phase clock (where N is a positive integer equal to or greater than 2). For example, the shift clock CLK may be a two-phase clock CLK1 and CLK2. The two-phase shift clocks CLK1 and CLK2 have opposite phases to each other.

[0097] Each of the signal transmission units ST(1),..., ST(n - 2), ST(n - 1), and ST(n) may output a first EM pulse [EM2(n)] through a first output node, output a second scan signal [SCAN2(n)] through a second output node, and output a third scan signal [SCAN3(n)] through a third output node.

[0098] Figure 8 FIG. is a circuit diagram specifically illustrating a first EM driver according to an embodiment of the present disclosure. Figure 9 FIG. is an illustration of Figure 8 a driving waveform of the illustrated first EM driver.

[0099] Reference Figures 8 to 9 Figures 8 to 9 , the first EM driver according to the embodiment can output a first EM signal EM1(n) and can include a plurality of transistors T1 to T7.

[0100]

[0100] When the shift clock CLK is a high voltage VGH2 equal to or greater than the strobe conduction voltage VEH, the first transistor T1 conducts to supply the voltage of the carry signal line C(n - 1) to the buffer node Qh. The first transistor T1 includes: a first electrode connected to the (n - 1)-th carry signal line C(n - 1), a gate electrode to which the shift clock CLK is applied, and a second electrode connected to the buffer node Qh.

[0101]

[0101] When the shift clock CLK is a voltage VGH2 equal to or greater than the strobe conduction voltage VEH, the second transistor T1A conducts to supply the voltage of the buffer node Qh to the first control node Q(n), thereby charging the first control node. The second transistor T1A includes: a first electrode connected to the buffer node Qh, a gate electrode to which the shift clock CLK is applied, and a second electrode connected to the first control node Q(n).

[0102]

[0102] The first transistor T1 and the second transistor T1A are connected in series. The first transistor T1 and the second transistor T1A are connected in series between the (n - 1)-th carry signal line C(n - 1) and the first control node Q(n).

[0103]

[0103] When the first control node Q(n) is charged, the third-q transistor T3q conducts to supply the second high potential voltage to the buffer node Qh through the second high potential voltage line GVDD1. The second high potential voltage is supplied to the buffer node Qh through the second high potential voltage line. The third-q transistor T3q includes: a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the first control node Q(n), and a second electrode connected to the buffer node Qh.

[0104] When the voltage of the Qb node Qb(n - 1) of the (n - 1)-th signal transmission unit ST(n - 1) is a high voltage equal to or higher than the strobe conduction voltage VEH, the fourth-1 transistor T41 and the fourth-1A transistor T41A are turned on, and the second high potential voltage is supplied to the first node 80 to charge the first node 80 to a voltage higher than the strobe conduction voltage VEH. The fourth-1 transistor T41 includes: a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the Qb node Qb(n - 1) of the (n - 1)-th signal transmission unit ST(n - 1), and a second electrode connected to the first electrode of the fourth-1A transistor T41A. The fourth-1A transistor T41A includes: a first electrode connected to the second electrode of the fourth-1 transistor T41, a gate electrode connected to the Qb node Qb(n - 1) of the (n - 1)-th signal transmission unit ST(n - 1), and a second electrode connected to the first node 80.

[0105] When the voltage of the first node 80 is a high voltage equal to or higher than the strobe conduction voltage VEH, the fourth transistor T4 and the fourth-A transistor T4A are turned on to connect the second high potential voltage line GVDD1 to the Qb node Qb(n), thereby charging the Qb node Qb(n) to a high voltage equal to or higher than the strobe conduction voltage VEH. The fourth transistor T4 includes: a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the first node 80, and a second electrode connected to the first electrode of the fourth-A transistor T4A. The fourth-A transistor T4A includes: a first electrode connected to the second electrode of the fourth transistor T4, a gate electrode connected to the first node 80, and a second electrode connected to the Qb node Qb(n). The first capacitor CF is connected between the gate electrode and the second electrode of the fourth-A transistor T4A. When the fourth-A transistor T4A is turned on through the first capacitor CF, the voltage of the first node 80 can be increased.

[0106] When the voltage of the buffer node Qh is a high voltage equal to or higher than the strobe conduction voltage VEH, the fourth-q transistor T4q is turned on to connect the first node 80 to the Qb node Qb(n). The fourth-q transistor T4q includes: a first electrode connected to the first node 80, a gate electrode connected to the buffer node Qh, and a second electrode connected to the Qb node Qb(n).

[0107] When the voltage of the buffer node Qh is a high voltage equal to or higher than the strobe turn-on voltage VEH, the fifth - q transistor T5q turns on, thereby connecting the Qb node Qb(n) to the second low - potential voltage line GVSS1 to discharge the voltage of the Qb node Qb(n) to the second low - potential voltage. The fifth - q transistor T5q includes: a first electrode connected to the Qb node Qb(n), a gate electrode connected to the buffer node Qh, and a second electrode connected to the second low - potential voltage line GVSS1.

[0108] The first pull - up transistor T6 and the first pull - down transistor T7 charge and discharge the first output node according to the voltages of the Q node Q(n) and the Qb node Qb(n) to output the first EM signal EM1(n). The first pull - up transistor T6 includes: a gate electrode coupled to the first control node Q(n), a first electrode coupled to the first high - potential voltage line to which a first high - potential voltage is applied, and a second electrode coupled to the first output node. The first pull - down transistor T7 is coupled to the first pull - up transistor T6, and the first output node is inserted therebetween. The first pull - down transistor T7 includes: a gate electrode coupled to the second control node Qb(n), a first electrode coupled to the first output node, and a second electrode coupled to the first low - potential voltage line GVSS0 to which a first low - potential voltage is applied. The second capacitor CB is connected between the gate electrode and the second electrode of the first pull - up transistor T6. When the first pull - up transistor T6 turns on through the second capacitor CB, the voltage of the first control node Q(n) can be increased.

[0109] The second pull - up transistor T6cr and the second pull - down transistor T7cr charge and discharge the second output node according to the voltages of the Q node Q(n) and the Qb node Qb(n) to output the carry signal EM1_C(n) of the first EM driver. The second pull - up transistor T6cr includes: a gate electrode connected to the Q node Q(n), a first electrode connected to the second high - potential voltage line GVDD1 to which a second high - potential voltage is applied, and a second electrode connected to the second output node. The second pull - down transistor T7cr is connected to the second pull - up transistor T6cr, and the second output node is inserted therebetween. The second pull - down transistor T7cr includes: a gate electrode connected to the Qb node Qb(n), a first electrode connected to the second output node, and a second electrode connected to the second low - potential voltage line GVSS1 to which a second low - potential voltage is applied.

[0110] Figure 10 is a circuit diagram of a strobe driver that exemplifies in detail an embodiment according to the present disclosure.

[0111] Refer to Figure 10, the strobe driver according to the embodiment includes: a first output circuit unit 71 configured to output a first strobe signal, a second output circuit unit 72 configured to output a second strobe signal, and a third output circuit unit 73 configured to output a third strobe signal.

[0112] The first output circuit unit 71 may output a first strobe signal (e.g., the second EM signal EM2(n)). The first output circuit unit 71 includes first-1 transistors T1 to first-13 transistors T13.

[0113] When the shift clock CLK is a high voltage VGH2 equal to or greater than the strobe turn-on voltage VEH, the first-1 transistor T1 turns on to supply the voltage of the (n - 1)-th carry signal line C(n - 1) of the previous signal transmission unit to the buffer node Qh. The first-1 transistor T1 includes: a first electrode connected to the (n - 1)-th carry signal line C(n - 1), a gate electrode to which the shift clock CLK is applied, and a second electrode connected to the buffer node Qh.

[0114] When the shift clock CLK is a voltage VGH2 equal to or greater than the strobe turn-on voltage VEH, the first-2 transistor T2 turns on to supply the voltage of the buffer node Qh to the first control node Q(n), thereby charging the first control node. The first-2 transistor T2 includes: a first electrode connected to the buffer node Qh, a gate electrode to which the shift clock CLK is applied, and a second electrode connected to the first control node Q(n).

[0115] The first-1 transistor T1 and the first-2 transistor T2 are connected in series. The first-1 transistor T1 and the first-2 transistor T2 are connected in series between the (n - 1)-th carry signal line C(n - 1) and the first control node Q(n).

[0116] When the first control node Q(n) is charged, the first-3 transistor T3 turns on to supply the second high potential voltage to the buffer node Qh through the second high potential voltage line GVDD1. The second high potential voltage is supplied to the buffer node Qh through the second high potential voltage line GVDD1. The first-3 transistor T3 includes: a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the first control node Q(n), and a second electrode connected to the buffer node Qh.

[0117] When the voltage of the first-2 control node Qb(n - 1) of the (n - 1)-th signal transmission unit ST(n - 1) is a high voltage equal to or higher than the strobe conduction voltage VEH, the first-4 transistor T4 and the first-5 transistor T5 are turned on to supply the second high potential voltage to the first node 80, thereby charging the first node 80 to a voltage higher than the strobe conduction voltage VEH. The first-4 transistor T4 includes: a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the first-2 control node Qb(n - 1) of the (n - 1)-th signal transmission unit ST(n - 1), and a second electrode connected to the first electrode of the first-5 transistor T5. The first-5 transistor T5 includes: a first electrode connected to the second electrode of the first-4 transistor T4, a gate electrode connected to the first-2 control node Qb(n - 1) of the (n - 1)-th signal transmission unit ST(n - 1), and a second electrode connected to the first node 80.

[0118] When the voltage of the first node 80 is a high voltage equal to or higher than the strobe conduction voltage VEH, the first-6 transistor T6 and the first-7 transistor T7 are turned on to connect the second high potential voltage line GVDD1 to the first-2 control node Qb(n), thereby charging the first-2 control node Qb(n) to a high voltage equal to or higher than the strobe conduction voltage VEH. The first-6 transistor T6 includes: a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the first node 80, and a second electrode connected to the first electrode of the first-7 transistor T7. The first-7 transistor T7 includes: a first electrode connected to the second electrode of the first-6 transistor T6, a gate electrode connected to the first node 80, and a second electrode connected to the Qb node Qb(n). A first capacitor CF is connected between the gate electrode and the second electrode of the first-7 transistor T7. When the first-7 transistor T7 is turned on through the first capacitor CF, the voltage of the first node 80 can be increased.

[0119] When the voltage of the buffer node Qh is a high voltage equal to or higher than the strobe conduction voltage VEH, the first-8 transistor T8 is turned on to connect the first node 80 to the first-2 control node Qb(n). The first-8 transistor T8 includes: a first electrode connected to the first node 80, a gate electrode connected to the buffer node Qh, and a second electrode connected to the first-2 control node Qb(n).

[0120] When the voltage of the buffer node Qh is a high voltage equal to or higher than the strobe turn-on voltage VEH, the first - 9 transistor T9 conducts to connect the first - 2 control node Qb(n) to the second low - potential voltage line GVSS1, thereby discharging the voltage of the first - 2 control node Qb(n) to the second low - potential voltage. The first - 9 transistor T9 includes: a first electrode connected to the first - 2 control node Qb(n), a gate electrode connected to the buffer node Qh, and a second electrode connected to the second low - potential voltage line GVSS1.

[0121] The first - 10 transistor or the first - 1 pull - up transistor T10 and the first - 11 transistor or the first - 1 pull - down transistor T11 charge and discharge the first - 1 output node OUT1 - 1 according to the voltages of the Q node Q(n) and the Qb node Qb(n) to output a second strobe signal (e.g., the second EM signal EM2(n)). The first - 1 pull - up transistor T10 includes: a gate electrode connected to the first control node Q(n), a first electrode connected to the first high - potential voltage line GVDD0 to which the first high - potential voltage is applied, and a second electrode connected to the first - 1 output node OUT1 - 1. The first - 1 pull - down transistor T11 is connected to the first - 1 pull - up transistor T10, and the first - 1 output node OUT1 - 1 is inserted therebetween. The first - 1 pull - down transistor T11 includes: a gate electrode connected to the second control node Qb(n), a first electrode connected to the first - 1 output node OUT1 - 1, and a second electrode connected to the first low - potential voltage line GVSS0 to which the first low - potential voltage is applied. The second capacitor CB is connected between the gate electrode and the second electrode of the first - 1 pull - up transistor T10. When the first - 1 pull - up transistor T10 conducts through the second capacitor CB, the voltage of the first control node Q(n) can be increased.

[0122] The first - 12 transistor or the first - 2 pull - up transistor T12 and the first - 13 transistor or the first - 2 pull - down transistor T13 charge and discharge the first - 2 output node OUT1 - 2 according to the voltages of the first - 1 control node Q(n) and the first - 2 control node Qb(n) to output a carry signal EM2_C(n). The first - 2 pull - up transistor T12 includes: a gate electrode connected to the first - 1 control node Q(n), a first electrode connected to the second high - potential voltage line GVDD1 to which a second high - potential voltage is applied, and a second electrode connected to the first - 2 output node OUT1 - 2. The first - 2 pull - down transistor T13 is connected to the first - 2 pull - up transistor T12, and the first - 2 output node OUT1 - 2 is inserted therebetween. The first - 2 pull - down transistor T13 includes: a gate electrode connected to the first - 2 control node Qb(n), a first electrode connected to the first - 2 output node OUT1 - 2, and a second electrode connected to the second low - potential voltage line GVSS1 to which a second low - potential voltage is applied.

[0123] The second output circuit unit 72 can output a second strobe signal (e.g., the second SCAN signal SCAN2(n + 2)). The second output circuit unit 72 includes the second - 1 transistor T21 to the second - 9 transistor T29.

[0124] The second - 1 transistor T21 connects the second low - potential voltage line GVSS1 to the second - 1 node 81 according to the voltage of the carry signal line EM2_C(n) of the first output circuit unit 71 to discharge it to the second low - potential voltage. The second - 1 transistor T21 includes: a gate electrode connected to the carry signal line EM2_C(n), a first electrode connected to the second low - potential voltage line GVSS1, and a second electrode connected to the second - 1 node 81.

[0125] The second - 2 transistor T22 connects the first - 2 control node Qb(n) of the first output circuit unit 71 to the second - 1 control node Q'(n) according to the voltage of the second - 1 node 81. The second - 2 transistor T22 includes: a gate electrode connected to the second - 1 node 81, a first electrode connected to the first - 2 control node Qb(n) of the first output circuit unit 71, and a second electrode connected to the second - 1 control node Q'(n).

[0126] The second-3 transistor T23 connects the carry signal line EM1_C(n) of the first EM driver to the second-1 node 81 according to the voltage of the first-2 control node Qb(n) of the first output circuit unit 71. The second-3 transistor T23 includes: a gate electrode connected to the first-2 control node Qb(n) of the first output circuit unit 71, a first electrode connected to the carry signal line EM1_C(n) of the first EM driver, and a second electrode connected to the second-1 node 81.

[0127] The second-4 transistor T24 connects the first-1 control node Q(n) of the first output circuit unit 71 to the second-2 control node Qb'(n) according to the voltage of the second-1 node 81. The second-4 transistor T24 includes: a gate electrode connected to the second-1 node 81, a first electrode connected to the first-1 control node Q(n) of the first output circuit unit 71, and a second electrode connected to the second-2 control node Qb'(n).

[0128] The second-5 transistor T25 connects the second control node Qb(n) of the first EM driver to the second-2 node 82 according to the voltage of the second control node Qb(n) of the first EM driver. The second-5 transistor T25 includes: a gate electrode and a first electrode connected to the second control node Qb(n) of the first EM driver, and a second electrode connected to the second-2 node 82.

[0129] The second-6 transistor T26 discharges the second-1 control node Q'(n) to the second low potential voltage according to the voltage of the second-2 node 82. The second-6 transistor T26 includes: a gate electrode connected to the second-2 node 82, a first electrode connected to the second-1 control node Q'(n), and a second electrode connected to the second low potential voltage line GVSS1.

[0130] The second-7 transistor T27 charges the second-2 control node Qb'(n) with the second high potential voltage according to the voltage of the second-2 node 82. The second-7 transistor T27 includes: a gate electrode connected to the second-2 node 82, a first electrode connected to the second-2 control node Qb'(n), and a second electrode connected to the second high potential voltage line GVDD1.

[0131] The second - 8 transistor or the second pull - up transistor T28 and the second - 9 transistor or the second pull - down transistor T29 charge and discharge the second output node OUT2 according to the voltages of the second - 1 control node Q'(n) and the second - 2 control node Qb'(n) to output a second strobe signal (e.g., the second SCAN signal SCAN2(n + 2)). The second pull - up transistor T28 includes: a gate electrode connected to the second - 1 control node Q'(n), a first electrode connected to the first high - potential voltage line GVDD0 to which a first high - potential voltage is applied, and a second electrode connected to the second output node. The second pull - down transistor T29 is connected to the second pull - up transistor T28, and the second output node OUT2 is inserted therebetween. The second pull - down transistor T29 includes: a gate electrode connected to the second - 2 control node Qb'(n), a first electrode connected to the second output node OUT2, and a second electrode connected to the first low - potential voltage line GVSS0 to which a first low - potential voltage is applied.

[0132] The third output circuit unit 73 can output a third strobe signal (e.g., the third SCAN signal SCAN3(n + 3)). The third output circuit unit 73 includes third - 1 transistors T31 to third - 8 transistors T38.

[0133] The third - 1 transistor T31 connects the first - 2 control node Qb(n) of the first output circuit unit 71 to the third - 1 control node Q"(n) according to the voltage of the first - 2 control node Qb(n - 1) of the (n - 1)th signal transmission unit ST(n - 1). The third - 1 transistor T31 includes: a gate electrode connected to the first - 2 control node Qb(n - 1) of the (n - 1)th signal transmission unit ST(n - 1), a first electrode connected to the first - 2 control node Qb(n) of the first output circuit unit 71, and a second electrode connected to the third - 1 control node Q"(n).

[0134] The third - 2 transistor T32 connects the first - 1 control node Q(n) to the third - 2 control node Qb"(n) according to the voltage of the first - 2 control node Qb(n - 1) of the (n - 1)th signal transmission unit ST(n - 1). The third - 2 transistor T32 includes: a gate electrode connected to the first - 2 control node Qb(n - 1) of the (n - 1)th signal transmission unit ST(n - 1), a first electrode connected to the first - 1 control node Q(n), and a second electrode connected to the third - 2 control node Qb"(n).

[0135] The third - 3 transistor T33 connects the second - 2 node 82 to the second - 3 node 83 according to the voltage of the carry signal line EM1_C(n) of the first EM driver. The third - 3 transistor T33 includes: a gate electrode connected to the carry signal line EM1_C(n) of the first EM driver, a first electrode connected to the second - 2 node 82, and a second electrode connected to the second - 3 node 83.

[0136] The third - 4 transistor T34 connects the carry signal line EM2_C(n) to the second - 3 node 83 according to the voltage of the carry signal line EM1_C(n) of the first EM driver. The third - 4 transistor T34 includes: a gate electrode connected to the carry signal line EM1_C(n) of the first EM driver, a first electrode connected to the carry signal line EM2_C(n), and a second electrode connected to the second - 3 node 83.

[0137] The third - 5 transistor T35 discharges the third - 1 control node Q"(n) to the second low - potential voltage according to the voltage of the second - 3 node 83. The third - 5 transistor T35 includes: a gate electrode connected to the second - 3 node 83, a first electrode connected to the third - 1 control node Q"(n), and a second electrode connected to the second low - potential voltage line GVSS1.

[0138] The third - 6 transistor T36 charges the third - 2 control node Qb"(n) with the second high - potential voltage according to the voltage of the second - 3 node 83. The third - 6 transistor T36 includes: a gate electrode connected to the second - 3 node 83, a first electrode connected to the third - 2 control node Qb"(n), and a second electrode connected to the second high - potential voltage line GVDD1.

[0139] The third - 7 transistor or the third pull - up transistor T37 and the third - 8 transistor or the third pull - down transistor T38 charge and discharge the third output node OUT3 according to the voltages of the third - 1 control node Q"(n) and the third - 2 control node Qb"(n) to output a third strobe signal (e.g., the third SCAN signal SCAN3(n + 3)). The third pull - up transistor T37 includes: a gate electrode connected to the third - 1 control node Q"(n), a first electrode connected to the first high - potential voltage line GVDD0 to which a first high - potential voltage is applied, and a second electrode connected to the third output node OUT3. The third pull - down transistor T38 is connected to the third pull - up transistor T37 with the third output node OUT3 inserted therebetween. The third pull - down transistor T38 includes: a gate electrode connected to the third - 2 control node Qb"(n), a first electrode connected to the third output node OUT3, and a second electrode connected to the first low - potential voltage line GVSS0 to which a first low - potential voltage is applied.

[0140] Figure 11 is an illustration Figure 10 of the driving waveforms of the illustrated strobe driver. Figures 12 to 17 is for explaining according to Figure 11 the operating principle of the strobe driver.

[0141] Referring to Figure 11 and Figure 12 , in interval ①, the first - 1 control node Q(n) of the first output circuit section becomes a high voltage, and the first - 2 control node Qb(n) becomes a low voltage, such that the first - 1 carry signal and the first strobe signal output high voltages.

[0142] The second - 1 control node Q'(n) of the second output circuit section becomes a low voltage, and the second - 2 control node Qb'(n) becomes a high voltage, such that the second strobe signal outputs a low voltage.

[0143] The third - 1 control node Q"(n) of the third output circuit section becomes a low voltage, and the third - 2 control node Qb"(n) becomes a high voltage, such that the third strobe signal outputs a low voltage.

[0144] Referring to Figure 11 and Figure 13 , in interval ②, the first - 1 control node Q(n) of the first output circuit section maintains a high voltage, and the first - 2 control node Qb(n) maintains a low voltage, such that the first - 1 carry signal and the first strobe signal maintain high voltages.

[0145] The second - 1 control node Q'(n) of the second output circuit section becomes a low voltage, and the second - 2 control node Qb'(n) becomes a high voltage, such that the second strobe signal maintains a low voltage.

[0146] The third-1 control node Q"(n) of the third output circuit section becomes a low voltage, and the third-2 control node Qb"(n) becomes a high voltage, such that the third strobe signal remains at a low voltage.

[0147] Refer to Figure 11 and Figure 14 , in interval ③, the first-1 control node Q(n) of the first output circuit section becomes a low voltage, and the first-2 control node Qb(n) becomes a high voltage, such that the first-1 carry signal and the first strobe signal output a low voltage.

[0148] The second-1 control node Q'(n) of the second output circuit section becomes a high voltage, and the second-2 control node Qb'(n) becomes a low voltage, such that the second strobe signal outputs a high voltage.

[0149] The third-1 control node Q"(n) of the third output circuit section becomes a high voltage, and the third-2 control node Qb"(n) becomes a low voltage, such that the third strobe signal outputs a high voltage.

[0150] Refer to Figure 11 and Figure 15 , in interval ④, the first-1 control node Q(n) of the first output circuit section remains at a low voltage, and the first-2 control node Qb(n) remains at a high voltage, such that the first-1 carry signal and the first strobe signal remain at low voltages.

[0151] The second-1 control node Q'(n) of the second output circuit section becomes a low voltage, and the second-2 control node Qb'(n) becomes a high voltage, such that the second strobe signal outputs a low voltage.

[0152] The third-1 control node Q"(n) of the third output circuit section becomes a high voltage, and the third-2 control node Qb"(n) becomes a low voltage, such that the third strobe signal remains at a high voltage.

[0153] Refer to Figure 11 and Figure 16 , in interval ⑤, the first-1 control node Q(n) of the first output circuit section becomes a high voltage, and the first-2 control node Qb(n) becomes a low voltage, such that the first-1 carry signal and the first strobe signal output high voltages.

[0154] The second-1 control node Q'(n) of the second output circuit section becomes a low voltage, and the second-2 control node Qb'(n) becomes a high voltage, such that the second strobe signal remains at a low voltage.

[0155] The third-1 control node Q"(n) of the third output circuit section maintains a high voltage, and the third-2 control node Qb"(n) maintains a low voltage, such that the third strobe signal maintains a high voltage.

[0156] Refer to Figure 11 and Figure 17 , in interval ⑥, the first-1 control node Q(n) of the first output circuit section maintains a high voltage, and the first-2 control node Qb(n) maintains a low voltage, such that the first-1 carry signal and the first strobe signal maintain a high voltage.

[0157] The second-1 control node Q'(n) of the second output circuit section becomes a low voltage, and the second-2 control node Qb'(n) becomes a high voltage, such that the second strobe signal maintains a low voltage.

[0158] The third-1 control node Q"(n) of the third output circuit section becomes a low voltage, and the third-2 control node Qb"(n) becomes a high voltage, such that the third strobe signal outputs a low voltage.

[0159] Figure 18 is a diagram illustrating simulation results of a strobe driver according to an embodiment.

[0160] Refer to Figure 18 , which shows output waveforms of a first EM signal EM1(n), a second EM signal EM2(n), a second scan signal SCAN2(n), and a third scan signal SCAN3(n) of each of a first EM driver, a second EM driver, a second scan driver, and a third scan driver according to an embodiment.

[0161] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical idea of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical idea of the present disclosure. The scope of the technical idea of the present disclosure is not limited thereto. Therefore, it is understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure.

[0162] Cross-reference to related applications

[0163] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0197824, filed in Korea on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A gate driver, comprising: A plurality of signal transmission sections configured to be connected in relation to each other via a carry line to which a carry signal is applied from a previous signal transmission section, wherein n is a positive integer, wherein the nth signal transmission section comprises: a first output circuit section configured to receive a carry signal from the previous signal transmission section and output the carry signal and a first selection signal according to a voltage of a first-1 control node and a voltage of a first-2 control node; a second output circuit section configured to output a second gating signal according to a voltage of a second-1 control node connected to the first-2 control node and a voltage of a second-2 control node connected to the first-1 control node; and A third output circuit section configured to output a third gating signal according to a voltage of a third-1 control node connected to the first-2 control node and a voltage of a third-2 control node connected to the first-1 control node.

2. The gate driver according to claim 1, wherein: The first output circuit unit includes: a first-1 pull-up transistor and a first-1 pull-down transistor, wherein the first-1 pull-up transistor and the first-1 pull-down transistor are configured to output the first gating signal to a first-1 output node according to a voltage of the first-1 control node and a voltage of the first-2 control node; and The first-2 pull-up transistor and the first-2 pull-down transistor are configured to output a carry signal to the first-2 output node according to the voltage of the first-1 control node and the voltage of the first-2 control node.

3. The gate driver according to claim 2, wherein: The second output circuit unit includes: The second-1 pull-up transistor and the second-1 pull-down transistor are configured to output the second selection signal to the second output node according to the voltage of the second-1 control node and the voltage of the second-2 control node.

4. The gate driver according to claim 3, wherein: The second output circuit section further includes second-1 transistor to second-4 transistor, The second-1 transistor includes a gate electrode connected to the first-2 output node, a first electrode connected to a low potential voltage line, and a second electrode connected to a second-1 node, the second-2 transistor includes a gate electrode connected to the second-1 node, a first electrode connected to the first-2 control node, and a second electrode connected to the second-1 control node, The second-3 transistor includes a gate electrode connected to the first-2 control node, a first electrode connected to a carry signal line of the first EM driver, and a second electrode connected to the second-1 node, and The 2nd-4 transistor includes a gate electrode connected to the 2nd-1 node, a first electrode connected to the 1st-1 control node, and a second electrode connected to the 2nd-2 control node.

5. The gate driver according to claim 4, wherein: The second output circuit section further includes second-5 transistors to second-7 transistors, the second-5 transistor includes a gate electrode and a first electrode connected to the first-2 control node of the first EM driver, and a second electrode connected to a second-2 node, The second-6 transistor includes a gate electrode connected to the second-2 node, a first electrode connected to the second-1 control node, and a second electrode connected to a low potential voltage line, and The second-7 transistor includes a gate electrode connected to the second-2 node, a first electrode connected to the second-2 control node, and a second electrode connected to a high potential voltage line.

6. The gate driver according to claim 3, wherein: The third output circuit unit includes: The third-1 pull-up transistor and the third-1 pull-down transistor are configured to output the third selection signal to a third output node according to the voltage of the third-1 control node and the voltage of the third-2 control node.

7. The gate driver according to claim 6, wherein: The third output circuit unit further includes third-1 transistor to third-2 transistor, The third-1 transistor includes a gate electrode connected to a first-2 control node of an n-1th signal transmission section, a first electrode connected to the first-2 control node, and a second electrode connected to the third-1 control node, and The third-2 transistor includes a gate electrode connected to the first-2 control node of the n-1th signal transmitting section, a first electrode connected to the first-1 control node, and a second electrode connected to the third-2 control node.

8. The gate driver according to claim 7, wherein: The third output circuit section further includes third-3 transistors to third-6 transistors, The third-3 transistor includes a gate electrode connected to the carry signal line of the first EM driver, a first electrode connected to the second-2 node, and a second electrode connected to the second-3 node. the third-4 transistor includes a gate electrode connected to the carry signal line of the first EM driver, a first electrode connected to the first-2 output node, and a second electrode connected to the second-3 node, The third-5 transistor includes a gate electrode connected to the second-3 node, a first electrode connected to the third-1 control node, and a second electrode connected to a low potential voltage line, and The third-6 transistor includes a gate electrode connected to the second-3 node, a first electrode connected to the third-2 control node, and a second electrode connected to a high potential voltage line.

9. A display device, comprising: a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixels are arranged; a data driver configured to supply a data voltage of pixel data to the data line; as well as a gate driver configured to supply a gate signal to the gate line, wherein the gate driver includes a plurality of signal transmission sections configured to be connected in relation to each other via a carry line to which a carry signal is applied from a previous signal transmission section, and Wherein, n is a positive integer, wherein the nth signal transmission unit comprises: a first output circuit section configured to receive a carry signal from the previous signal transmission section and output the carry signal and a first selection signal according to a voltage of a first-1 control node and a voltage of a first-2 control node; a second output circuit section configured to output a second gating signal according to a voltage of a second-1 control node connected to the first-2 control node and a voltage of a second-2 control node connected to the first-1 control node; and A third output circuit section configured to output a third gating signal according to a voltage of a third-1 control node connected to the first-2 control node and a voltage of a third-2 control node connected to the first-1 control node.

10. The display device according to claim 9, wherein: The first output circuit unit includes: a first-1 pull-up transistor and a first-1 pull-down transistor, wherein the first-1 pull-up transistor and the first-1 pull-down transistor are configured to output the first gating signal to a first-1 output node according to a voltage of the first-1 control node and a voltage of the first-2 control node; and The first-2 pull-up transistor and the first-2 pull-down transistor are configured to output a carry signal to the first-2 output node according to the voltage of the first-1 control node and the voltage of the first-2 control node.

11. The display device according to claim 10, wherein: The second output circuit unit includes: The second-1 pull-up transistor and the second-1 pull-down transistor are configured to output the second selection signal to the second output node according to the voltage of the second-1 control node and the voltage of the second-2 control node.

12. The display device according to claim 11, wherein: The second output circuit section further includes second-1 transistor to second-4 transistor, The second-1 transistor includes a gate electrode connected to the first-2 output node, a first electrode connected to a low potential voltage line, and a second electrode connected to a second-1 node, the second-2 transistor includes a gate electrode connected to the second-1 node, a first electrode connected to the first-2 control node, and a second electrode connected to the second-1 control node, The second-3 transistor includes a gate electrode connected to the first-2 control node, a first electrode connected to a carry signal line of the first EM driver, and a second electrode connected to the second-1 node, and The 2nd-4 transistor includes a gate electrode connected to the 2nd-1 node, a first electrode connected to the 1st-1 control node, and a second electrode connected to the 2nd-2 control node.

13. The display device according to claim 12, wherein: The second output circuit section further includes second-5 transistors to second-7 transistors, the second-5 transistor includes a gate electrode and a first electrode connected to the first-2 control node of the first EM driver, and a second electrode connected to a second-2 node, The second-6 transistor includes a gate electrode connected to the second-2 node, a first electrode connected to the second-1 control node, and a second electrode connected to the low potential voltage line, and The second-7 transistor includes a gate electrode connected to the second-2 node, a first electrode connected to the second-2 control node, and a second electrode connected to a high potential voltage line.

14. The display device according to claim 11, wherein: The third output circuit unit includes: The third-1 pull-up transistor and the third-1 pull-down transistor are configured to output the third selection signal to a third output node according to the voltage of the third-1 control node and the voltage of the third-2 control node.

15. The display device according to claim 14, wherein: The third output circuit unit further includes third-1 transistor to third-2 transistor, the third-1 transistor includes a gate electrode connected to the first-2 control node of the n-1th signal transmission section, a first electrode connected to the first-2 control node, and a second electrode connected to the third-1 control node, and The third-2 transistor includes a gate electrode connected to the first-2 control node of the n-1th signal transmitting section, a first electrode connected to the first-1 control node, and a second electrode connected to the third-2 control node.

16. The display device according to claim 15, wherein: The third output circuit section further includes third-3 transistors to third-6 transistors, The third-3 transistor includes a gate electrode connected to a carry signal line of the first EM driver, a first electrode connected to the second-2 node, and a second electrode connected to the second-3 node. the third-4 transistor includes a gate electrode connected to the carry signal line of the first EM driver, a first electrode connected to the first-2 output node, and a second electrode connected to the second-3 node, The third-5 transistor includes a gate electrode connected to the second-3 node, a first electrode connected to the third-1 control node, and a second electrode connected to a low potential voltage line, and The third-6 transistor includes a gate electrode connected to the second-3 node, a first electrode connected to the third-2 control node, and a second electrode connected to a high potential voltage line.

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