Synchronization system and method based on FPGA-based B-code time and TSN-sensitive network time

Abstract

The present application relates to the field of time synchronization technology, and in particular to a synchronization system and method for FPGA-based B-code time and TSN-sensitive network time. The FPGA-based B-code time and TSN-sensitive network time synchronization system includes a B-code time parsing module, a clock synchronization control module, a coarse and fine calibration module, a parameter configuration module, and a jump detection module. This system uses B-code time as a backup synchronization source, combined with a coarse and fine calibration mode to achieve fast and smooth synchronization, and uses noise suppression and intelligent switching strategies to improve accuracy and reliability. This application can effectively solve the problem of synchronization loss caused by a master clock source failure or step jump, significantly enhance the stability and applicability of the TSN network system, and is suitable for high-precision time-sensitive scenarios such as avionics and industrial automation. It has important practical value and promotion prospects.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer networks, and in particular relates to a system and method for synchronizing B-code time and TSN-sensitive network time based on FPGA. Background Art

[0002] With the continuous advancement of aviation technology, the data streams generated by sensors, cameras, and other devices on aircraft are becoming increasingly massive, significantly increasing the requirements for network bandwidth, communication reliability, real-time performance, and system integration. Existing communication technologies are increasingly unable to meet the demands of the aviation sector. Time-Sensitive Networking (TSN), an emerging network technology, offers higher bandwidth and lower latency, ensuring highly reliable transmission of critical flight information (such as flight attitude and altitude) between systems, thus meeting the high-volume data transmission needs of avionics equipment. TSN networks achieve precise time synchronization through the IEEE 802.1AS protocol. Its core principle is to maintain a master clock within the entire local area network, which is used as a reference for time synchronization by other nodes. The node hosting the master clock serves as the master node, interacting with slave nodes through protocol frames to achieve network-wide time synchronization.

[0003] Chinese patent application number CN202311254260.7 provides a time synchronization system, method, computer device, and storage medium. The system includes an IRIGB code decoder, a time compensation module, a time register, and a TSN network card. When the time synchronization system is connected between an IRIGB code clock device and a time-sensitive network, a conversion mode is activated. In the conversion mode, the IRIGB code decoder decodes a first IRIGB code signal to obtain first time information and writes it into the time register. The time compensation module determines a first compensation time based on the decoding time. The time register compensates the first time information based on the first compensation time. The TSN network card encapsulates the compensated first time information in a first time synchronization message and sends it to the time-sensitive network, so that the TSN switch and the first terminal device of the substation synchronize time based on the compensated first time information. In this way, time synchronization in the substation time-sensitive network can be achieved through IRIGB code, which can improve the accuracy of time synchronization.

[0004] However, in practical applications, time synchronization mechanisms in TSN networks still face numerous challenges. First, airborne equipment networks must maintain high-precision time synchronization with other systems. This is especially true when establishing timing synchronization between distant systems. This typically relies on external timing clock sources (such as GPS, Beidou, or rubidium clocks). However, if the timing clock device fails and cannot output a master clock, the airborne equipment network loses synchronization with other systems, leading to transmission errors in various sensor parameters and control command signals within the communication data payload, potentially causing flight accidents. Second, when synchronizing time with external systems, clock step transitions can disrupt real-time data transmission within the local area network (LAN) or between external networks, causing data transmission errors and system control jitter. Furthermore, when a local TSN network system needs to establish synchronization with other network systems using different clock sources, traditional approaches require replacing the local clock device and redesigning the processor software of the TSN master device. This not only increases hardware costs but also significantly increases labor and technical complexity.

[0005] In order to solve the above problems, there is an urgent need for a technical solution that can flexibly deal with clock source failures, clock jumps and switching between multiple clock sources. Summary of the Invention

[0006] The purpose of the present invention is to provide a system and method for synchronizing B-code time and TSN-sensitive network time based on FPGA to solve the problems mentioned in the above background technology.

[0007] To achieve the above objectives, the present invention provides the following technical solution: an FPGA-based B-code time and TSN-sensitive network time synchronization system, comprising a B-code time parsing module, a clock synchronization control module, a coarse and fine calibration module, a parameter configuration module, and a jump detection module; the B-code time parsing module is used to receive and parse external B-code signals to extract accurate time information; the clock synchronization control module is used to dynamically adjust the master clock of the TSN network system based on the parsed time information; the coarse and fine calibration module is used to selectively integrate B-code time into the current network time, supporting fast or smooth synchronization modes; the parameter configuration module is used to flexibly set synchronization parameters through multiple interfaces; and the jump detection module is used to monitor changes in the clock domain in real time and trigger switching to the B-code time source in abnormal situations.

[0008] As a further solution of the present invention, the coarse and fine calibration module includes a frequency calibration unit; the frequency calibration unit is used to gradually adjust the network time using a frequency accumulation algorithm according to the deviation between the B code time and the current network time. The formula is as follows:

[0009] ;

[0010] in, Indicates the new clock frequency, is the current network clock frequency, is the frequency calibration step value, To calibrate the attenuation coefficient, is the calibration time interval.

[0011] As a further solution of the present invention, the coarse and fine calibration module further includes a time format conversion unit; the time format conversion unit is used to directly convert the B code time into the TSN network master clock format in the coarse calibration mode, and the formula is as follows: ;

[0012] in, Indicates the time value after synchronization. is the B code time, is the local network time, is the time fusion coefficient, ranging from 0 to 1.

[0013] As a further solution of the present invention, the parameter configuration module includes a multi-interface adapter unit; the multi-interface adapter unit is used to dynamically update the key parameters in the synchronization parameter table through the serial port, PCIe bus or network port, and the formula is as follows: ;

[0014] in, Indicates the updated parameter value, is the default parameter value, Adjust the weights for the parameters, is the input parameter change.

[0015] As a further solution of the present invention, the jump detection module includes a clock step analysis unit; the clock step analysis unit is used to detect the step change of the clock domain and calculate whether the step amplitude exceeds a preset threshold. The formula is as follows:

[0016] ;

[0017] in, Indicates whether to trigger the step alarm. is the current clock value, is the previous clock value, is the step change threshold.

[0018] As a further solution of the present invention, the clock synchronization control module includes a clock source switching unit; the clock source switching unit is used to automatically switch to the B code time source when the main clock source fails or jumps stepwise. The formula is as follows:

[0019] ;

[0020] in, Indicates the currently used clock source. It is a step alarm sign provided by the jump detection module. Status flag of the main clock source.

[0021] As a further solution of the present invention, the time smooth transition unit is used to reduce time jitter by an interpolation algorithm when switching clock sources. The formula is as follows:

[0022] ;

[0023] in, represents the smoothed time value, is the original time value, is the new time value, is the smoothing coefficient, and its value range is between 0 and 1.

[0024] As a further solution of the present invention, the frequency calibration unit further introduces a noise suppression mechanism, and the specific calculation formula is:

[0025] ;

[0026] in, Represents the frequency value after filtering, Original frequency value, is the noise suppression factor, is the noise intensity, dynamically estimated by the Kalman filter.

[0027] As a further solution of the present invention, the clock source switching unit further optimizes the switching strategy and introduces a switching cost evaluation model. The specific calculation formula is:

[0028] ;

[0029] in, represents the switching cost, is the time deviation, is the frequency deviation, is the switching energy consumption, , , is the weight coefficient.

[0030] Also disclosed is a method for synchronizing B-code time and TSN-sensitive network time based on FPGA, which is characterized by comprising the following steps:

[0031] Step S1: Receive external B-code signal, parse and extract accurate time information;

[0032] Step S2: Based on the parsed B-code time information, dynamically adjust the master clock frequency and time value of the TSN network system;

[0033] Step S3: Selectively merge the B code time with the current network time and synchronize them through the coarse calibration mode or the fine calibration mode.

[0034] Step S4: Dynamically configure synchronization parameters through the serial port, PCIe bus or network port, including frequency calibration step value, time fusion coefficient and step change threshold;

[0035] Step S5: Real-time monitoring of the step changes in the clock domain. If it is detected that the main clock source fails or the step amplitude exceeds a preset threshold, a switch to the B-code time source is triggered;

[0036] Step S6: When switching the clock source, an interpolation algorithm is used to smooth the transition time value to reduce time jitter.

[0037] Compared with existing technologies, the present invention offers the following advantages: Based on the existing TSN network synchronization system, the system introduces B-code time as a backup synchronization source. When the existing network synchronization source fails or experiences significant time jumps, it can quickly switch to B-code time, preventing loss of synchronization between the local area network and other system networks. Furthermore, the system supports both coarse and fine calibration synchronization modes, allowing users to choose between rapid synchronization or smooth integration with the current network time based on actual needs, thereby reducing the risk of data disruption in real-time communications. Furthermore, the system supports flexible configuration, allowing key parameters to be adjusted via serial ports, PCIe buses, or network ports, further enhancing the system's adaptability and compatibility. This innovative design not only improves the reliability and stability of TSN networks in complex environments but also provides technical support for high-precision time synchronization in larger-scale network systems. It effectively addresses the issue of synchronization loss caused by master clock source failures or step jumps, significantly improving the reliability of TSN network systems. Furthermore, the combination of coarse and fine calibration modes balances the requirements of rapid synchronization and smooth transition, minimizing the impact on real-time communications. Finally, through flexible parameter configuration and intelligent switching strategies, the system supports seamless integration of multiple clock sources, expanding its applicability. In addition, the frequency calibration and noise suppression algorithms are used to improve the accuracy and stability of time synchronization. This method is suitable for high-precision time-sensitive scenarios such as avionics and industrial automation, and has important practical value and promotion prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a system structure diagram of the present invention. DETAILED DESCRIPTION

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0040] Synchronization system based on FPGA B code time and TSN sensitive network time, combined with attached Figure 1 The implementation process is described in detail. The system includes a B-code time parsing module, a clock synchronization control module, a coarse-fine calibration module, a parameter configuration module, and a transition detection module. Each module is implemented in FPGA hardware to ensure high-precision time synchronization. The following is a complete description of the implementation process.

[0041] First, refer to the attached Figure 1 , showing the overall system block diagram. The B-code time analysis module, as the system's first processing unit, is responsible for receiving the external B-code signal and decoding it to extract precise time information. B-code signals are typically generated by an external high-precision clock source and contain pulse-per-second (PPS) and time-encoded data. The analysis module captures and decodes the signal using hardware logic circuits, transmitting the extracted time information to subsequent modules. In practical applications, B-code signals may be subject to noise interference, so the analysis module incorporates a built-in digital filter to remove high-frequency noise and improve signal quality. The parsed B-code time information is stored in a register in a standard format for use by the clock synchronization control module. The analysis module utilizes a FIR low-pass filter with a cutoff frequency of 1 kHz. The filter order (default 64) can be dynamically adjusted through the parameter configuration module to suppress the effects of high-frequency noise on the B-code signal.

[0042] The clock synchronization control module is the core of the system. Its primary function is to dynamically adjust the TSN network system's master clock based on the parsed B-code time. The clock synchronization control module includes a clock source switching unit and a time smoothing unit. When the master clock source is operating normally, the system prioritizes the master clock source as the time reference. If the master clock source fails or experiences a step change, the clock source switching unit automatically switches to the B-code time source. The switching logic is implemented using the following formula:

[0043] ;

[0044] in, Indicates the currently used clock source. It is a step alarm sign provided by the jump detection module. Status flag of the main clock source. If the main clock source status is abnormal or the step change exceeds the preset threshold, it switches to the B code time source. To reduce the time jitter that may occur during the switching process, the time smoothing transition unit uses an interpolation algorithm to smooth the time value. The formula is as follows:

[0045] ;

[0046] in, represents the smoothed time value, is the original time value, is the new time value, The smoothing coefficient ranges from 0 to 1. By gradually adjusting the time value, the switching process is smooth and does not affect real-time communication. The smoothing coefficient is calibrated through experiments and can be adjusted as needed through the parameter configuration module. For example, in industrial automation scenarios, setting it to 0.5 speeds up convergence.

[0047] The coarse and fine calibration module is a key component for achieving time synchronization. It includes a frequency calibration unit and a time format conversion unit. The main task of the frequency calibration unit is to gradually adjust the network time using a frequency accumulation algorithm based on the deviation between the B code time and the current network time. The specific calculation formula is:

[0048] ;

[0049] in, Indicates the new clock frequency, is the current network clock frequency, is the frequency calibration step value, To calibrate the attenuation coefficient, is the calibration interval. This formula gradually adjusts the frequency using an exponential decay method to avoid oscillations caused by rapid calibration. Furthermore, the frequency calibration unit incorporates a noise suppression mechanism that dynamically estimates the noise intensity using a Kalman filter and filters the frequency value according to the following formula:

[0050] ;

[0051] in, Represents the frequency value after filtering, Original frequency value, is the noise suppression factor, is the noise intensity. This mechanism effectively improves the accuracy and stability of frequency calibration, and the state equation of the Kalman filter is , the observation equation is ,in and are process noise and observation noise respectively. By estimating the noise intensity in real time , dynamic adjustment value to achieve adaptive filtering.

[0052] The time format conversion unit is responsible for converting the B-code time directly into the TSN network master clock format in coarse calibration mode. The formula is as follows:

[0053] ;

[0054] in, Indicates the time value after synchronization. is the B code time, is the local network time, is the time fusion coefficient, and its value range is between 0 and 1. The value of can be flexibly selected for coarse calibration or fine calibration mode to meet the needs of different application scenarios.

[0055] The parameter configuration module provides a variety of interfaces for dynamically updating key parameters in the synchronization parameter table. Figure 1 The module includes a multi-interface adapter unit that supports parameter configuration via the serial port, PCIe bus or network port. The parameter update formula is as follows:

[0056] ;

[0057] in, Indicates the updated parameter value, is the default parameter value, Adjust the weights for the parameters, is the input parameter change. By flexibly configuring parameters, users can optimize system performance according to actual needs. For example, in an avionics scenario, the frequency calibration step value can be adjusted and calibrated attenuation coefficient To adapt to the time synchronization requirements in highly dynamic environments.

[0058] The jump detection module is used to monitor changes in the clock domain in real time and trigger a switch to the B-code time source in abnormal situations. This module includes a clock step analysis unit to detect step changes in the clock domain and calculate whether the step amplitude exceeds the preset threshold. The step alarm trigger condition is determined by the following formula:

[0059] ;

[0060] in, Indicates whether to trigger the step alarm. is the current clock value, is the previous clock value, is the step change threshold. Once a step change is detected that exceeds the threshold, the jump detection module will send an alarm signal to the clock synchronization control module to trigger the clock source switching operation. Supports dynamic adjustment based on network load. For example, when the network delay exceeds 2ms, the threshold is automatically increased to ; Restore to low load , to balance sensitivity and false alarm rate. In addition, the clock source switching unit further optimizes the switching strategy and introduces a switching cost evaluation model with the following formula:

[0061] ;

[0062] in, represents the switching cost, is the time deviation, is the frequency deviation, is the switching energy consumption, , , is the weight coefficient. By comprehensively considering time deviation, frequency deviation, and switching energy consumption, the system can intelligently select the optimal switching timing, thereby reducing the impact of switching on network communication.

[0063] In actual application scenarios, the synchronization system of the present invention is widely applicable to high-precision time-sensitive fields such as avionics and industrial automation. For example, in avionics systems, multiple subsystems need to exchange real-time data through the TSN network, and the accuracy of time synchronization directly affects the safety of flight control. By introducing B-code time as a backup synchronization source, the present invention effectively solves the problem of synchronization loss caused by failure of the main clock source or step jump, and significantly improves the reliability of the system. At the same time, combined with the coarse and fine calibration mode, the system can strike a balance between fast synchronization and smooth transition, reducing the impact on real-time communication. In addition, through flexible parameter configuration and intelligent switching strategies, the system supports seamless docking of multiple clock sources, expanding the scope of application.

[0064] In summary, the present invention realizes high-precision synchronization of B code time and TSN sensitive network time through FPGA hardware. Figure 1 The specific structure and operating principle are described in detail, and the functions of each module and their implementation methods are described. The system design fully considers the needs of actual application scenarios and has important practical value and promotion prospects.

[0065] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. FPGA-based B-code time and TSN-sensitive network time synchronization system, characterized by: It includes a B-code time parsing module, a clock synchronization control module, a coarse and fine calibration module, a parameter configuration module, and a jump detection module; the B-code time parsing module is used to receive and parse the external B-code signal to extract accurate time information; the clock synchronization control module is used to dynamically adjust the master clock of the TSN network system according to the parsed time information; the coarse and fine calibration module is used to selectively integrate the B-code time into the current network time, supporting fast or smooth synchronization mode; the parameter configuration module is used to flexibly set synchronization parameters through multiple interfaces; the jump detection module is used to monitor changes in the clock domain in real time and trigger switching to the B-code time source in abnormal situations; the coarse and fine calibration module includes a frequency calibration unit; the frequency calibration unit is used to gradually adjust the network time using a frequency accumulation algorithm based on the deviation between the B-code time and the current network time. The formula is as follows: ； in, Indicates the new clock frequency, is the current network clock frequency, is the frequency calibration step value, To calibrate the attenuation coefficient, is the calibration time interval; The coarse and fine calibration module further includes a time format conversion unit; the time format conversion unit is used to directly convert the B code time into the TSN network master clock format in the coarse calibration mode, and the formula is as follows: ; in, Indicates the time value after synchronization. is the B code time, is the local network time, is the time fusion coefficient, ranging from 0 to 1; The parameter configuration module includes a multi-interface adapter unit; the multi-interface adapter unit is used to dynamically update the key parameters in the synchronization parameter table through the serial port, PCIe bus or network port. The formula is as follows: ; in, Indicates the updated parameter value, is the default parameter value, Adjust the weights for the parameters, is the input parameter change.

2. The FPGA-based B-code time and TSN-sensitive network time synchronization system according to claim 1, characterized in that: The jump detection module includes a clock step analysis unit; the clock step analysis unit is used to detect the step change of the clock domain and calculate whether the step amplitude exceeds a preset threshold. The formula is as follows: ； in, Indicates whether to trigger the step alarm. is the current clock value, is the previous clock value, is the step change threshold.

3. The FPGA-based B-code time and TSN-sensitive network time synchronization system according to claim 1, characterized in that: The clock synchronization control module includes a clock source switching unit; the clock source switching unit is used to automatically switch to the B code time source when the main clock source fails or jumps stepwise. The formula is as follows: ； in, Indicates the currently used clock source. It is a step alarm sign provided by the jump detection module. Status flag of the main clock source.

4. The FPGA-based B-code time and TSN-sensitive network time synchronization system according to claim 3, characterized in that: The time smoothing unit is used to reduce time jitter by using an interpolation algorithm when switching clock sources. The formula is as follows: ； in, represents the smoothed time value, is the original time value, is the new time value, is the smoothing coefficient, and its value range is between 0 and 1.

5. The FPGA-based B-code time and TSN-sensitive network time synchronization system according to claim 1, characterized in that: The frequency calibration unit further introduces a noise suppression mechanism, and the specific calculation formula is: ； in, Represents the frequency value after filtering, Original frequency value, is the noise suppression factor, is the noise intensity, dynamically estimated by the Kalman filter.

6. The FPGA-based B-code time and TSN-sensitive network time synchronization system according to claim 3, characterized in that: The clock source switching unit further optimizes the switching strategy and introduces a switching cost evaluation model. The specific calculation formula is: ; in, represents the switching cost, is the time deviation, is the frequency deviation, is the switching energy consumption, , , is the weight coefficient.

7. The synchronization method of the FPGA-based B-code time and TSN-sensitive network time synchronization system according to any one of claims 1 to 6, characterized in that: The following steps are involved: Step S1: Receive external B-code signal, parse and extract accurate time information; Step S2: Based on the parsed B-code time information, dynamically adjust the master clock frequency and time value of the TSN network system; Step S3: Selectively merge the B code time with the current network time and synchronize them through the coarse calibration mode or the fine calibration mode. Step S4: Dynamically configure synchronization parameters through the serial port, PCIe bus or network port, including frequency calibration step value, time fusion coefficient and step change threshold; Step S5: Real-time monitoring of the step changes in the clock domain. If it is detected that the main clock source fails or the step amplitude exceeds a preset threshold, a switch to the B-code time source is triggered; Step S6: When switching the clock source, an interpolation algorithm is used to smooth the transition time value to reduce time jitter.

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