Data storage method, electronic device, storage medium and program product

Abstract

The present application discloses a data storage method, electronic device, storage medium, and program product, which relate to the field of computer technology. The method comprises receiving a write request, the write request being used to instruct writing target data in a solid-state drive; determining a target association relationship between a target logical address and a target physical address of the target data in the solid-state drive based on the write request; storing the target association relationship in a temporary cache area; and storing the target association relationship in a target storage unit of the solid-state drive after a cache threshold of the temporary cache area reaches a preset threshold. The target storage unit is a physical storage medium for storing the association relationship. The method can improve the processing efficiency of data storage.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data storage method, electronic equipment, storage medium, and program product. Background Art

[0002] A solid-state drive (SSD) is a high-performance storage device based on semiconductor storage technology. It can store data using NOT AND (NAND) flash memory particles.

[0003] When writing target data to a solid-state drive, the logical address corresponding to the target data can be determined. After obtaining the L2P table, the physical address can be determined in the L2P table, the association between the logical address and the physical address can be determined, and then the association can be stored in the target storage unit of the solid-state drive.

[0004] However, the above execution process requires the coordination processing unit of the global mapping table to determine the write processing unit of the local mapping table corresponding to each logical address, obtain the L2P table through the write processing unit, determine the physical address corresponding to the logical address in the L2P table, and then determine the association relationship, which makes the data storage processing efficiency low. Summary of the Invention

[0005] The present application provides a data storage method, electronic device, storage medium and program product to at least solve the problem of low data storage processing efficiency in related technologies.

[0006] In a first aspect, the present application provides a data storage method, comprising:

[0007] receiving a write request, wherein the write request is used to instruct to write target data into the solid state drive;

[0008] Determining, according to the write request, a target association relationship between a target logical address and a target physical address of the target data in the solid-state drive;

[0009] The target association relationship is stored in a temporary cache area. After the cache threshold of the temporary cache area reaches a preset threshold, the target association relationship is stored in a target storage unit of the solid state drive. The target storage unit is a physical storage medium for storing association relationships.

[0010] In a second aspect, the present application further provides a data storage device, comprising a receiving module, a determining module, and a storage module:

[0011] The receiving module is used to receive a write request, where the write request is used to instruct to write target data into the solid state drive;

[0012] The determining module is configured to determine, according to the write request, a target association relationship between a target logical address and a target physical address of the target data in the solid-state drive;

[0013] The storage module is used to store the target association relationship in a temporary cache area. After the cache threshold of the temporary cache area reaches a preset threshold, the target association relationship is stored in a target storage unit of the solid-state hard disk. The target storage unit is a physical storage medium for storing the association relationship.

[0014] In a third aspect, the present application further provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned data storage methods when executing the computer program.

[0015] In a fourth aspect, the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned data storage methods are implemented.

[0016] In a fifth aspect, the present application also provides a computer program product, comprising a computer program, which implements the steps of any of the above-mentioned data storage methods when executed by a processor.

[0017] The present application can receive a write request, which is used to instruct the writing of target data in a solid-state drive; determine a target association relationship between a target logical address and a target physical address of the target data in the solid-state drive based on the write request; store the target association relationship in a temporary cache area; and after a cache threshold of the temporary cache area reaches a preset threshold, store the target association relationship in a target storage unit of the solid-state drive, the target storage unit being a physical storage medium for storing the association relationship. The target association relationship of the target data can be directly determined and written to the target storage unit, eliminating the need to obtain an L2P table through a write processing unit before determining the target association relationship, thereby improving data storage processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 A schematic diagram of an application scenario provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of a data storage architecture provided in an embodiment of the present application;

[0021] Figure 3 A flowchart of a data storage method improved by an embodiment of the present application;

[0022] Figure 4 A schematic diagram of a process for dividing a sub-resource pool provided in an embodiment of the present application;

[0023] Figure 5 A flowchart of a method for processing a request provided in an embodiment of the present application;

[0024] Figure 6 A schematic diagram of another data storage architecture provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of the structure of a data storage device provided in an embodiment of the present application;

[0026] Figure 8 This is a schematic diagram of the structure of an electronic device provided in this application. DETAILED DESCRIPTION

[0027] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0028] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0029] Figure 1 This is a schematic diagram of an application scenario provided by an embodiment of this application. Figure 1 The server 100 includes at least one central processing unit (CPU) 101 and a solid-state drive (SSD) 102. The at least one central processing unit (CPU) 101 is based on symmetric multi-processing (SMP), which can implement global task scheduling and resource sharing, coordinate multiple CPU cores to jointly process I / O requests, and provide better firmware operating conditions for reading and writing to the SSD.

[0030] Symmetric multiprocessing can achieve parallel computing by installing multiple CPUs with similar performance on the motherboard. All processors can share the same memory and I / O resources, and can efficiently execute the same task or assign different tasks to improve overall performance.

[0031] According to the write request, the CPU 101 may write the target data corresponding to the write request into the solid state drive 102. The solid state drive 102 may include NAND (NOT AND) flash memory particles, which may be physical storage media for storing data.

[0032] A read logical-to-physical block logical mapping (L2P) table corresponding to a logical block address (LBA) and a physical block address (PBA) may be stored in the NAND flash memory of the solid state drive 102 to manage the storage of the NAND flash memory.

[0033] When a solid-state drive is first initialized, each logical unit number (LUN) is associated with multiple data blocks, defining multiple data block sets that form the SSD's corresponding resource pool. A LUN is a logical storage unit defined within the SSD that abstracts and manages physical storage resources, presenting storage space to hosts or applications through logical mapping. A data block set is used to indicate a super block (SPB), which is a collection of multiple data blocks and has a one-to-one correspondence with a logical unit.

[0034] Each data block set has a valid data frame counter (VDFC) and a valid data frame bit (VDFB). The VDFC records the reference count of a data block, while the VDFB records the actual location of the data block (for example, the physical address). The VDFC and VDFB effectively manage the valid data volume of each data block set.

[0035] After receiving a write request from the Work Manager (WM), the CPU can select the physical address of a data block set from the resource pool and use the physical address as the write destination address for the data corresponding to the write request. Through the destination address, the data is written to the NAND flash memory particles of the solid-state drive.

[0036] For ease of understanding, below, combined with Figure 2, the data storage in the related technology of this application is explained.

[0037] Figure 2 This is a schematic diagram of a data storage architecture provided by an embodiment of this application. Figure 2 ,WM can send table modification request and clear (obsolete) request to the target cache manager (CM) corresponding to the data block set in a polling manner, see Figure 2 The target cache manager is one of CM0, CM1, and CM2. The target cache manager controls the data block physical migration module (move engine) to modify the VDFC and VDFB corresponding to the data block set.

[0038] The logical address (LBA) corresponding to the data is written into the temporary cache area. When the temporary cache area is full, the cached data containing the logical address is sent to the coordination processing unit (JM-Master) of the global mapping table in the Journal Manager (JM). The JM-Master sends the logical address to the write processing unit (JM-Slavex) of a local mapping table in JM-Slavex0 and JM-Slavex1 through polling.

[0039] Through JM-Slavex, the logical to physical mapping table (Logical to Physical Mapping, L2P) is read to obtain the physical address, determine the association between the logical address (LBA) and the physical address, and store the association in the target storage unit of the solid-state drive. The target storage unit can be a single-level cell (SLC).

[0040] In related art, when writing target data to a solid-state drive, the logical address corresponding to the target data can be determined. After obtaining the L2P table, the physical address can be determined in the L2P table, the association between the logical address and the physical address can be determined, and then the association can be stored in the target storage unit of the solid-state drive. However, this execution process requires the coordination processing unit of the global mapping table to determine the write processing unit of the local mapping table corresponding to each logical address, obtain the L2P table through the write processing unit, determine the physical address corresponding to the logical address in the L2P table, and then determine the association, resulting in low data storage processing efficiency.

[0041] In an embodiment of the present application, a write request can be received, the write request being used to instruct the writing of target data in a solid-state drive; a target association relationship between a target logical address and a target physical address of the target data in the solid-state drive is determined based on the write request; the target association relationship is stored in a temporary cache area, and after a cache threshold of the temporary cache area reaches a preset threshold, the target association relationship is stored in a target storage unit of the solid-state drive, the target storage unit being a physical storage medium for storing the association relationship. The target association relationship of the target data can be directly determined and written to the target storage unit, without having to obtain an L2P table through a write processing unit before determining the target association relationship, thereby improving data storage processing efficiency.

[0042] Figure 3 This is a flowchart of a data storage method improved by the embodiment of the present application. Figure 3 , the method may include:

[0043] S301: Receive a write request.

[0044] The write request may be used to instruct writing target data in the solid-state drive.

[0045] S302: Determine, according to the write request, a target association relationship between a target logical address and a target physical address of the target data in the solid-state drive.

[0046] A plurality of cache managers are provided in the solid-state hard disk, and the cache managers are used to manage the corresponding plurality of data block sets.

[0047] In some possible embodiments, a target logical address can be determined based on a write request; a target cache manager corresponding to the target logical address can be determined among multiple cache managers; a target data block set can be determined among multiple data block sets corresponding to the target cache manager, and the physical address corresponding to the target data block set can be determined as the target physical address; and a target association relationship between the target logical address and the target physical address can be established.

[0048] Specifically, when determining the target logical address according to the write request, the storage capacity of the target data can be determined, and the target logical address can be determined according to the storage capacity of the target data. When allocating the target logical address, the target logical address can be a continuous logical address or a discrete logical address.

[0049] When allocating logical addresses, continuous LBAs can be allocated first, which can reduce addressing overhead and improve data storage performance.

[0050] Specifically, if there are continuous logical addresses in the unallocated logical addresses, and the storage capacity of the continuous logical addresses is greater than or equal to the storage capacity of the target data, then the logical address in the continuous logical addresses that meets the storage capacity of the target data is determined as the target logical address.

[0051] Multiple cache managers in a solid-state drive can allocate a corresponding logical address to each cache manager, and store the allocated logical address of each cache manager as address management information. For example, there are four cache managers, namely CM0, CM1, CM2, and CM3, with 256 logical addresses, namely LBA0-LBA255. Each cache manager can be allocated 64 logical addresses. Then, the logical addresses allocated to CM0 are LBA0-LBA63, the logical addresses allocated to CM1 are LBA64-LBA127, the logical addresses allocated to CM2 are LBA128-LBA191, and the logical addresses allocated to CM3 are LBA192-LBA255.

[0052] In some possible embodiments, the target cache manager may be determined as follows: determining an address value corresponding to the target logical address; and determining the target cache manager corresponding to the target logical address in the address management information based on the address value.

[0053] The address management information may include a manager identifier of each cache manager and an address value interval corresponding to each manager identifier.

[0054] For example, the target logical address is LBA45, and the address value corresponding to the target logical address is 45. Assuming that the address management information allocates the logical address of CM0 as LBA0-LBA63, the logical address allocated by CM1 as LBA64-LBA127, the logical address allocated by CM2 as LBA128-LBA191, and the logical address allocated by CM3 as LBA192-LBA255, it can be determined that the target cache manager is CM0.

[0055] S303: Storing the target association relationship in a temporary cache area. After a cache threshold of the temporary cache area reaches a preset threshold, storing the target association relationship in a target storage unit of the solid state drive.

[0056] The temporary cache area is also called a buffer. The temporary cache area is a transit queue for metadata and can be used to cache associations in batches.

[0057] The target storage unit is a physical storage medium for storing the association relationship. The target storage unit may be a single-level cell (SLC). SLC is a type of NAND flash memory technology. Each storage unit stores only one bit of data (0 or 1).

[0058] The data storage method provided in an embodiment of the present application may include a target storage unit in a solid-state drive, the target storage unit being used to store the association between the logical address and the physical address of the written data. The target association of the target data can be directly determined and written to the target storage unit, eliminating the need for a write processing unit to obtain an L2P table and then determine the target association, thereby improving data storage processing efficiency.

[0059] The data block collection in the SSD constitutes the entire resource pool. Since multiple cache managers are set up in the SSD, each cache manager can be divided into multiple corresponding data block collections. Multiple data block collections can form a sub-resource pool of the cache manager, and multiple sub-resource pools constitute the resource pool of the SSD.

[0060] Next, combine Figure 4 , the execution process of determining the sub-resource pool corresponding to each cache manager provided in the embodiment of the present application is explained.

[0061] Figure 4 This is a flow chart of the division of a sub-resource pool provided in an embodiment of the present application. Figure 4 , the method may include:

[0062] S401: Obtain the manager quantity of multiple cache managers and the first set quantity of data block sets.

[0063] The data blocks in the solid state drive can be divided into multiple data block sets, and the number of the multiple data block sets is the first number of sets.

[0064] For example, assuming that the solid state drive has four cache managers, the number of managers is four, there are 100 data block sets in total, and the number of the first set is 100.

[0065] S402: Determine the second set data volume N corresponding to each cache manager according to the number of managers and the number of first sets.

[0066] N is an integer greater than or equal to 2.

[0067] In some possible embodiments, the ratio of the first set quantity to the number of managers may be determined as the second set data volume corresponding to each cache manager.

[0068] For example, assuming that the first set number of data block sets is 100 and the number of managers of the cache manager is 4, the second set data amount N is 25.

[0069] S403: Divide the data block set into N allocation sets according to the second set quantity.

[0070] The number of data block sets in each allocation set is the number of managers.

[0071] For example, assuming there are 100 data block sets, namely spb0-spb99, and 4 cache managers, namely CM0-CM3, the 100 data block sets are divided into 25 allocation sets, namely allocation set 0-allocation set 24, each allocation set includes 4 data block sets, allocation set 0 includes spb0-spb3,..., allocation set 24 includes spb96-spb99.

[0072] S404: For any allocation set, allocate the data block set in the allocation set to multiple cache managers in sequence to determine the sub-resource pool corresponding to each cache manager.

[0073] In some possible embodiments, a first arrangement order of a data block set corresponding to an allocation set and a second arrangement order of multiple cache managers can be determined; in the first arrangement order and the second arrangement order, a sorted data block set and a sorted cache manager are determined, and the sequence numbers of the sorted data block set and the sorted cache manager are the same; and the sorted data block set is allocated to the sorted cache manager.

[0074] For example, assume that there are four cache managers, namely CM0 to CM3, and 25 allocation sets, namely allocation set 0 to allocation set 24, each including four data block sets. Assuming that the data block sets of allocation set 0 are spb0-spb3, spb0 can be assigned to CM0, spb1 can be assigned to CM1, spb2 can be assigned to CM2, and spb3 can be assigned to CM3; assuming that the data block sets of allocation set 1 are spb4-spb7, spb4 can be assigned to CM0, spb5 can be assigned to CM1, spb6 can be assigned to CM2, and spb7 can be assigned to CM3; by sequentially allocating the data block sets of allocation set 0-allocation set 24 to the four cache managers, it can be determined that the data block set of the sub-resource pool corresponding to CM0 includes spb0, spb4, spb8, ..., spb96, the data block set of the sub-resource pool corresponding to CM1 is spb1, spb5, spb9, ..., spb97, the data block set of the sub-resource pool corresponding to CM2 is spb2, spb6, spb10, ..., spb98, and the data block set of the sub-resource pool corresponding to CM3 is spb3, spb7, spb11, ..., spb99.

[0075] After receiving a write request, the corresponding data block set can be allocated for storing the target data. After the target data is written into the data set, the logical address corresponding to the write request can be handed over to the cache manager corresponding to the data block set to make a table change request.

[0076] The data storage method provided by the embodiment of the present application can obtain the number of managers of multiple cache managers and the number of first sets of data block sets; determine the second set data volume N corresponding to each cache manager based on the number of managers and the number of first sets; divide the data block set into N allocation sets based on the second set number, and the number of data block sets in each allocation set is the number of managers; for any allocation set, allocate the data block sets in the allocation set to multiple cache managers in turn to determine the sub-resource pool corresponding to each cache manager. The resource pool of the solid-state drive can be divided into multiple sub-resource pools based on the number of managers of the cache manager. After writing data, when making a table modification request, it is only necessary to determine the cache manager corresponding to the data block set where the target data is written, and perform the table modification operation in the sub-resource pool corresponding to the cache manager. There is no need to perform the table modification operation in the entire resource pool, which can improve processing efficiency.

[0077] Before storing the target association relationship in the temporary cache, it is necessary to perform table modification and clearing operations. Figure 5 Provide specific instructions.

[0078] Figure 5 This is a flowchart of a request processing method provided in an embodiment of the present application. Figure 5 , the method may include:

[0079] S501: Acquire a table modification request and a clearing request.

[0080] The table modification request may include a target logical address, and may be used to modify a mapping relationship of the target logical address and / or an access permission table.

[0081] The clear request may include a data block set identifier corresponding to the target physical address, which may be used to modify metadata of the VDFC and VDFB corresponding to the data block set.

[0082] S502: Lock the target logical address according to the data block set identifier in the table modification request, so that other table modification requests cannot request to update the target logical address.

[0083] Locking the target logical address is an access control mechanism for logical addresses in the storage system. It is used to prevent concurrent writes or illegal operations on the target logical address, ensuring data consistency and hardware security.

[0084] S503: Update the mapping relationship and / or access permission between the target logical address and the target physical address, and unlock the target logical address.

[0085] After the unlocking process, other table modification requests may perform table modification processes on the target logical address, wherein the table modification process is to update the mapping relationship and / or access rights between the target logical address and the target physical address.

[0086] S504: According to the clear request, update the counting information of the data block set corresponding to the target physical address.

[0087] The counting information may include a valid data count cell (VDFC) and a valid data cell bit (VDFB).

[0088] The valid data counting unit may be used to indicate the reference count of each data block in the corresponding data block set. For example, after the target data is written into the data block set, the reference count of the VDFC may be set to 1, indicating that the physical block is referenced by a logical address.

[0089] The valid data unit bit is used to indicate the metadata flag of each data block in its corresponding data block set. The metadata flag is used to indicate the clearing operation of metadata. For example, after the target data is written to the data block set, the physical address of the VDFB is updated and the metadata flag is set to 1 to indicate that the physical address of the VDFB is valid.

[0090] After the original logical address no longer executes the old data block set, the reference count of the VDFC corresponding to the data block set is set to 0, and the metadata flag of the VDFB is set to 0 to indicate that the physical address of the VDFB is invalid.

[0091] In related technologies, modifications need to be made through the move engine. The move engine is a dedicated hardware module in the solid-state drive (SSD) that is responsible for efficiently performing data migration and metadata update operations. For example, data is moved from the old physical block (SPB, assumed to be the physical block to be discarded) to the new physical block, and the related metadata (such as VDFC, VDFB) is updated synchronously.

[0092] In this application, counter information can be updated directly through CPU control, eliminating the need for additional hardware modules and reducing the complexity of the SSD. Furthermore, the move engine supports predefined operations, while the CPU handles complex logic, allowing for dynamic adjustment of metadata management policies and improving processing flexibility.

[0093] The data storage method provided in the embodiment of the present application can directly update the mapping relationship and / or access rights of the target logical address to the target physical address according to the table modification request, and update the counting information of the data block set corresponding to the target physical address according to the clear request, so as to directly respond to the request and improve the processing efficiency.

[0094] Figure 6 This is a schematic diagram of another data storage architecture provided in an embodiment of the present application. Figure 6 When the SSD is initialized for the first time, the resource pool corresponding to the SSD includes multiple data block sets. The SSD is equipped with multiple cache managers, each of which has its corresponding sub-resource pool in the resource pool. Each data block set corresponds to a VDFC and a VDFB.

[0095] Based on the write request, WM can determine the target cache manager corresponding to the target logical address in CM0, CM1, and CM2, select the physical address of a data block set from the sub-resource pool corresponding to the target cache manager, and use the physical address as the write target physical address of the data corresponding to the write request. Through the target physical address, the data is written to the NAND flash memory particles of the solid-state drive, and the target association relationship between the target logical address and the target physical address is determined.

[0096] The WM can send a table change request and a clear request to the target cache manager corresponding to the data block set, lock and change the table of the target logical address, and modify the VDFC and VDFB of the target physical address for the data block set.

[0097] The target association relationship is written into the temporary cache area. After the cache threshold of the temporary cache area reaches the preset threshold, the cache data containing the target association relationship is sent to the JM-Master, and the target association relationship is written into the SLC of the solid-state drive.

[0098] In this application, the target association relationship can be directly determined based on the write request and written to the SSD, eliminating the need to read the L2P table to determine the target physical address corresponding to the target logical address, thereby improving processing efficiency. Furthermore, by reducing the execution process of reading the L2P table by the JM-Slave in the JM, the JM's CPU resource usage can be reduced, thereby improving CPU processing efficiency.

[0099] Figure 7 This is a schematic diagram of the structure of a data storage device provided in an embodiment of the present application. Figure 7 The data storage device 700 may include a receiving module 701, a determining module 702 and a storage module 703:

[0100] The receiving module 701 is used to receive a write request, where the write request is used to instruct to write target data into the solid state drive;

[0101] The determination module 702 is configured to determine, according to the write request, a target association relationship between a target logical address and a target physical address of the target data in the solid-state drive;

[0102] The storage module 703 is used to store the target association relationship in a temporary cache area. After the cache threshold of the temporary cache area reaches a preset threshold, the target association relationship is stored in a target storage unit of the solid state drive. The target storage unit is a physical storage medium for storing the association relationship.

[0103] In some possible embodiments, the solid-state drive is provided with multiple cache managers, each of which is used to manage its corresponding multiple data block sets; the determination module 702 is specifically used to:

[0104] Determine the target logical address according to the write request;

[0105] Determine a target cache manager corresponding to the target logical address among the plurality of cache managers;

[0106] Determine a target data block set from a plurality of data block sets corresponding to the target cache manager, and determine a physical address corresponding to the target data block set as a target physical address;

[0107] A target association relationship is established between the target logical address and the target physical address.

[0108] In some possible embodiments, the determination module 702 is specifically configured to:

[0109] Determine the address value corresponding to the target logical address;

[0110] According to the address value, the target cache manager corresponding to the target logical address is determined in the address management information. The address management information includes the manager identifier of each cache manager and the address value interval corresponding to each manager identifier.

[0111] In some possible embodiments, multiple data block sets are sub-resource pools of their corresponding cache managers, and multiple sub-resource pools corresponding to multiple cache managers constitute a resource pool of the solid-state drive.

[0112] In some possible embodiments, the determining module 702 is further configured to:

[0113] Obtaining a manager quantity of a plurality of cache managers and a first set quantity of data block sets;

[0114] Determine, based on the number of managers and the number of first sets, the second set data volume N corresponding to each cache manager, where N is an integer greater than or equal to 2;

[0115] According to the number of the second sets, the data block set is divided into N allocation sets, and the number of data block sets in each allocation set is the number of managers;

[0116] For any allocation set, the data block sets in the allocation set are allocated to multiple cache managers in sequence to determine the sub-resource pool corresponding to each cache manager.

[0117] In some possible embodiments, the determining module 702 is further configured to:

[0118] Determine a first arrangement order of the data block set corresponding to the allocation set and a second arrangement order of the plurality of cache managers;

[0119] In the first arrangement sequence and the second arrangement sequence, determining a sorted data block set and a sorted cache manager, wherein the sequence numbers of the sorted data block set and the sorted cache manager are the same;

[0120] Allocate a collection of sorted data blocks to the sort cache manager.

[0121] In some possible embodiments, the apparatus 700 further comprises an acquisition module, a locking module, a first update module, an unlocking module, and a second update module:

[0122] The acquisition module is used to acquire a table modification request and a clearing request, wherein the table modification request includes a target logical address, and the clearing request includes a data block set identifier corresponding to the target physical address;

[0123] The locking module is used to lock the target logical address according to the table modification request, so that other table modification requests cannot request to update the target logical address;

[0124] The first update module is used to update the mapping relationship and / or access rights of the target logical address to the target physical address;

[0125] The unlocking module is used to unlock the target logical address so that other table modification requests can update the target logical address;

[0126] The second updating module is used to update the counting information of the data block set corresponding to the target physical address according to the data block set identifier in the clear request, where the counting information includes a valid data counting unit and a valid data unit bit;

[0127] Among them, the valid data counting unit is used to indicate the reference count of each data block in its corresponding data block set, the valid data unit bit is used to indicate the metadata mark of each data block in its corresponding data block set, and the metadata mark is used to indicate the clearing operation of the metadata.

[0128] For the description of the features in the embodiment corresponding to the data storage device, reference can be made to the relevant description of the embodiment corresponding to the data storage method, which will not be repeated here.

[0129] Figure 8 This is a schematic diagram of the structure of an electronic device provided by this application. Figure 8 As shown, the electronic device 800 provided in this embodiment includes: at least one processor 801 and a memory 802. Optionally, the electronic device 800 further includes a communication component 803. The processor 801, the memory 802 and the communication component 803 are connected via a bus.

[0130] During the specific implementation process, at least one processor 801 executes the computer-executable instructions stored in the memory 802, so that the at least one processor 801 executes the above-mentioned data storage method embodiment.

[0131] The specific implementation process of the processor 801 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0132] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0133] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0134] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0135] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned data storage method embodiments when run.

[0136] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0137] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned data storage method embodiments are implemented.

[0138] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned data storage method embodiments are implemented.

[0139] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0140] The above is a detailed introduction to a data storage method provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A data storage method, characterized in that: include: receiving a write request, wherein the write request is used to instruct to write target data into the solid state drive; Determining, according to the write request, a target association relationship between a target logical address and a target physical address of the target data in the solid-state drive; Storing the target association relationship in a temporary cache area, and after a cache threshold of the temporary cache area reaches a preset threshold, storing the target association relationship in a target storage unit of a solid-state hard disk, wherein the target storage unit is a physical storage medium for storing association relationships, and directly determining the target association relationship of the target data; The solid-state drive is provided with a plurality of cache managers, each of which is used to manage a plurality of data block sets corresponding thereto. Determining, according to the write request, a target association relationship between a target logical address and a target physical address of the target data in the solid-state drive includes: Determining the target logical address according to the write request; Determine, among the plurality of cache managers, a target cache manager corresponding to the target logical address; Determining a target data block set from a plurality of data block sets corresponding to the target cache manager, and determining a physical address corresponding to the target data block set as the target physical address; A target association relationship is established between the target logical address and the target physical address.

2. The method according to claim 1, characterized in that Determining, among the multiple cache managers, a target cache manager corresponding to the target logical address includes: Determine an address value corresponding to the target logical address; According to the address value, the target cache manager corresponding to the target logical address is determined in the address management information, wherein the address management information includes a manager identifier of each cache manager and an address value interval corresponding to each manager identifier.

3. The method according to claim 1, characterized in that The multiple data block sets are sub-resource pools of their corresponding cache managers, and the multiple sub-resource pools corresponding to the multiple cache managers constitute the resource pool of the solid state drive.

4. The method according to claim 3, characterized in that Also includes: Obtaining a number of managers of the plurality of cache managers and a first number of data block sets; Determine, based on the number of managers and the number of the first sets, a second set data volume N corresponding to each cache manager, where N is an integer greater than or equal to 2; Divide the data block set into N allocation sets according to the number of the second sets, where the number of data block sets in each allocation set is the number of managers; For any allocation set, the data block sets in the allocation set are allocated to the multiple cache managers in sequence to determine the sub-resource pools corresponding to the respective cache managers.

5. The method according to claim 4, characterized in that Allocating the data block sets in the allocation set to the multiple cache managers in sequence includes: Determining a first arrangement order of the data block set corresponding to the allocation set and a second arrangement order of the plurality of cache managers; In the first arrangement order and the second arrangement order, determining a sorted data block set and a sorted cache manager, wherein the sorted data block set and the sorted cache manager have the same sequence number; The sorted data block set is allocated to the sort buffer manager.

6. The method according to claim 1, characterized in that Before storing the target association relationship in the temporary cache area, the method further includes: Obtaining a table modification request and a clearing request, wherein the table modification request includes a target logical address, and the clearing request includes a data block set identifier corresponding to the target physical address; According to the table modification request, locking the target logical address so that other table modification requests cannot request to update the target logical address; Updating the mapping relationship and / or access rights of the target logical address to the target physical address, and unlocking the target logical address so that other table modification requests update the target logical address; updating counting information of the data block set corresponding to the target physical address according to the data block set identifier in the clear request, wherein the counting information includes a valid data counting unit and a valid data unit bit; The valid data counting unit is used to indicate the reference count of each data block in its corresponding data block set, the valid data unit bit is used to indicate the metadata tag of each data block in its corresponding data block set, and the metadata tag is used to indicate a clearing operation on the metadata.

7. A data storage device, characterized in that: Including receiving module, determining module and storage module: The receiving module is used to receive a write request, where the write request is used to instruct to write target data into the solid state drive; The determining module is configured to determine, according to the write request, a target association relationship between a target logical address and a target physical address of the target data in the solid-state drive; The storage module is used to store the target association relationship in a temporary cache area, and after the cache threshold of the temporary cache area reaches a preset threshold, store the target association relationship in a target storage unit of a solid-state hard disk, wherein the target storage unit is a physical storage medium for storing association relationships, and directly determines the target association relationship of the target data; The solid-state hard disk is provided with multiple cache managers, and the cache managers are used to manage the corresponding multiple data block sets; the determination module is specifically used to: determine the target logical address according to the write request; determine the target cache manager corresponding to the target logical address among the multiple cache managers; determine the target data block set among the multiple data block sets corresponding to the target cache manager, and determine the physical address corresponding to the target data block set as the target physical address; and establish a target association relationship between the target logical address and the target physical address.

8. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data storage method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data storage method according to any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the data storage method according to any one of claims 1 to 6 are implemented.

Images