Memory resource allocation method and device for server, equipment, medium and program product

Abstract

The invention provides a memory resource allocation method for a server, which can be applied to the technical field of servers and computers. The method comprises the steps that in response to detection that a server enters a power-on self-test stage, link information of a peripheral component interconnect (PCI) link in the server is obtained, and the link information of the PCI link comprises port information of a PCI port and equipment information of PCI equipment; determining a memory resource reservation scheme of the PCI link according to the port information of the PCI port and the equipment information of the PCI equipment; and in response to the detection that the server enters the system starting stage, under the condition that it is determined that the operating system of the server needs to perform memory resource reallocation, performing memory resource reallocation on the PCI link according to the memory resource reservation scheme of the PCI link. The invention further provides a memory resource allocation device and equipment, a storage medium and a program product.

Description

Technical Field

[0001] This application relates to the fields of servers and computer technologies, and particularly to a method, apparatus, device, medium, and program product for allocating memory resources of a server. Background Art

[0002] A server can connect various PCI devices through a Peripheral Component Interconnect (PCI) port. PCI devices can be, for example, Data Processing Unit (DPU) devices, Graphics Processing Unit (GPU) devices, graphics cards, and other devices. To ensure the normal operation of PCI devices, it is necessary to reserve memory resources for PCI devices when the server starts up. However, there are unreasonable problems with the memory resource reservation method. Summary of the Invention

[0003] In view of the above problems, this application provides a method, apparatus, device, medium, and program product for allocating memory resources of a server.

[0004] According to the first aspect of this application, there is provided a method for allocating memory resources of a server, including: in response to detecting that the server enters the power-on self-test stage, obtaining link information of a Peripheral Component Interconnect (PCI) link in the server, where the link information of the PCI link includes port information of a PCI port and device information of a PCI device; determining a memory resource reservation scheme for the PCI link according to the port information of the PCI port and the device information of the PCI device; in response to detecting that the server enters the system startup stage, and when it is determined that the operating system of the server needs to reallocate memory resources, reallocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link.

[0005] The second aspect of this application provides a device for allocating memory resources of a server, including: an obtaining module, configured to obtain link information of a PCI link in the server in response to detecting that the server enters the power-on self-test stage, where the link information of the PCI link includes port information of a PCI port and device information of a PCI device; a determining module, configured to determine a memory resource reservation scheme for the PCI link according to the port information of the PCI port and the device information of the PCI device; a first allocation module, configured to reallocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link in response to detecting that the server enters the system startup stage and when it is determined that the operating system of the server needs to reallocate memory resources.

[0006] A third aspect of the present application provides an electronic device, including: one or more processors; a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the above method.

[0007] A fourth aspect of the present application further provides a computer-readable storage medium, on which computer programs or instructions are stored, and when the computer programs or instructions are executed by a processor, the steps of the above method are implemented.

[0008] A fifth aspect of the present application further provides a computer program product, including computer programs or instructions, and when the computer programs or instructions are executed by a processor, the steps of the above method are implemented.

[0009] According to an embodiment of the present application, during the power-on self-test stage of the server, according to the port information of the PCI port and the device information of the PCI device, the memory resource reservation scheme of the PCI link can be confirmed. Thus, when the server enters the system startup stage, if memory resource reallocation is required, the memory resource reallocation can be performed according to the memory resource reservation scheme, making the memory resource allocation more reasonable and avoiding the problem of abnormal server operation caused by the PCI device or PCI port that needs to allocate memory resources not being allocated memory resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Through the following description of the embodiments of the present application with reference to the drawings, the above content and other objects, features, and advantages of the present application will become clearer.

[0011] Figure 1 Shows a schematic diagram of the physical connection of the motherboard of the server according to an embodiment of the present application.

[0012] Figure 2 Shows a schematic diagram of the internal structure of the DPU device according to an embodiment of the present application.

[0013] Figure 3 Shows a schematic diagram of the link structure of the switching module according to an embodiment of the present application.

[0014] Figure 4 Shows a schematic diagram of the link structure of the multi-layer switching module according to an embodiment of the present application.

[0015] Figure 5 Shows a flowchart of the memory resource allocation method of the server according to an embodiment of the present application.

[0016] Figure 6 Shows a flowchart of the memory resource allocation method of the server according to an embodiment of the present application when the PCI link is of the first type.

[0017] Figure 7 Shows a flowchart of the memory resource allocation method of a server according to an embodiment of the present application when the PCI link is of the second type.

[0018] Figure 8 Shows a flowchart of the memory resource allocation method of a server according to an embodiment of the present application during the system startup phase.

[0019] Figure 9 Shows a structural block diagram of the memory resource allocation device of a server according to an embodiment of the present application.

[0020] Figure 10 Shows a block diagram of an electronic device suitable for implementing the memory resource allocation method of a server according to an embodiment of the present application. Detailed implementation manners

[0021] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present application. In the following detailed description, for the sake of explanation, many specific details are set forth in order to provide a comprehensive understanding of the embodiments of the present application. However, it is obvious that one or more embodiments can be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0022] The terms used herein are merely for describing specific embodiments and are not intended to limit the present application. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0023] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0024] In the case of using expressions such as "at least one of A, B, and C", generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to having only A, having only B, having only C, having A and B, having A and C, having B and C, and or having A, B, and C, etc.).

[0025] A Smart Network Interface Card (SNIC) is a flexible and programmable network card that works in conjunction with a server. Since the smart network card has computing capabilities, in order to reduce the computing power consumption of the Central Processing Unit (CPU), data processing functions related to the network, security, storage, etc. that are not suitable for the CPU can be transferred to the smart network card for execution, enabling the server to run critical applications and operating systems more effectively and optimizing the overall efficiency of business data processing.

[0026] The development of smart network cards can be divided into three stages. The first stage is the basic function network card. The second stage is the hardware offloading network card. The third stage is the smart network card based on DPU devices. A DPU device is a dedicated processor that provides virtualization services for data center infrastructure such as network, storage, security, and management around data processing. The DPU device can fully offload security-related functions based on the data plane and the control plane. The DPU device can form a computing architecture with CPUs and hardware acceleration engines such as Application Specific Integrated Circuit (ASIC) / Network Processor (NP) / Field Programmable Gate Array (FPGA) under various architectures to form an entity that provides virtualization functions.

[0027] DPU devices have been widely used in various architecture servers in data centers. However, regardless of the architecture of the server, memory resource reservation needs to be made for the DPU device in advance when applying the DPU device because there are many devices inside the DPU device, such as physical or virtual devices like network interface devices, virtual network cards, Solid State Drives (SSDs), etc. These devices all need to use memory resources and some memory resources are prioritized. For example, 32-bit memory resources need to be highly prioritized. However, some DPU devices also contain a switching module inside. The switching module is a module that can connect other PCI devices. When other PCI devices are connected to the switching module, the PCI devices connected under the switching module may also need to allocate memory resources. At the same time, in addition to the DPU device in the server containing a switching module, the motherboard or PCI devices of the server may also contain a similar switching module. The same switching module and the PCI devices below it also need memory resources. However, the 32-bit memory resources are limited and the maximum is 4GB. If it exceeds 4GB, some devices will not be able to be used. For example, the interface of the display function (the display interface of the DPU device or the on-board VGA interface) will not be able to display, or the devices that need to be used cannot be used properly under the system or the devices are lost due to insufficient memory resource allocation.

[0028] For this reason, memory resource reservation is usually performed when the server starts up. However, the switching module can include multiple levels, and among the switching modules in each level, some need to perform memory resource reservation while others do not. Whether to perform memory resource reservation depends on the use of the port and the device. At this time, since the server may involve more switching modules, the levels of the switching modules cannot be fixed, and it is impossible to predict which switching module specifically needs to reserve memory resources.

[0029] In view of this, the present application provides a method for allocating memory resources of a server, including: in response to detecting that the server enters the power-on self-test stage, obtaining link information of a peripheral component interconnect (PCI) link in the server, where the link information of the PCI link includes port information of a PCI port and device information of a PCI device; determining a memory resource reservation scheme for the PCI link according to the port information of the PCI port and the device information of the PCI device; in response to detecting that the server enters the system startup stage, and when it is determined that the operating system of the server needs to perform memory resource reallocation, reallocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link.

[0030] To better understand the method for allocating memory resources of the server proposed in the present application, the following introduces the physical connection diagrams of the server, DPU device, switching unit, etc. involved in the present application.

[0031] Figure 1 Shows the physical connection diagram of the motherboard of the server according to an embodiment of the present application.

[0032] As Figure 1 shown, the server 100 may include a first CPU 111 and a second CPU 112 connected to the first CPU 111. The first CPU 111 includes four PCI ports, namely RC0, RC1, RC2, and RC3. The RC0 port can be connected to the first switching module 121, the RC1 port can be connected to a disk array card (RAID card), the RC2 port can be connected to a hard disk (such as an NVME hard disk), and the RC3 interface can be connected to the second switching module 122.

[0033] The first switching module 121 can be connected to a first PCI device 131, a second PCI device 132, and a third PCI device 133. The second switching module 122 can be connected to a fourth PCI device 134 and a third switching module 135. The third switching module 135 can be connected to a fifth PCI device 141.

[0034] The second CPU 112 can include two PCI ports, namely RC4 and RC5. The RC4 port can be connected to the DPU device 123, and the RC5 port can be connected to the fourth switching module 124.

[0035] The fourth switching module 124 can be connected to the fifth switching module 136, the sixth PCI device 137, the seventh PCI device 138, and the eighth PCI device 139. The fifth switching module 136 can be connected to the ninth PCI device 142, the tenth PCI device 143, and the sixth switching module 144. The sixth switching module 144 can be connected to the seventh switching module 151. The seventh switching module 151 can be connected to the eleventh PCI device 161, the twelfth PCI device 162, and the thirteenth PCI device 163.

[0036] The first CPU 111 can also be connected to a Baseboard Management Controller (BMC) 125, and the server 100 can detect the first CPU 111 through a Basic Input Output System (BIOS). The second CPU 112 can also include a USB interface and a data interface. The USB interface is used to connect a removable storage device with a USB interface. The data interface can be used to connect a hard disk with a data interface. The data transfer channels between the switching modules and between the switching modules and the CPUs can be 8 channels or 16 channels.

[0037] Figure 2 The internal structure connection diagram of the DPU device according to an embodiment of the present application is shown.

[0038] As Figure 2 shown, the DPU device 200 can include a third CPU 211. The third CPU 211 is connected to an eighth switching module 221 and a first PC hard disk 222. The third CPU 211 also includes a USB interface. The eighth switching module 221 is connected to a first PCI network card 231, a second PCI network card 232, and a second PC hard disk 233. Hotplug Enable indicates that the hot plug function of this port is enabled, and Hotplug Disable indicates that the hot plug function of this port is disabled. PCI 16 Lane indicates that the transmission channel of this port is 16.

[0039] Figure 3 The link structure connection diagram of the switching module according to an embodiment of the present application is shown.

[0040] As Figure 3 shown, the ninth switching module 311 can include four ports DP0, DP1, DP2, and DP3. Among them, PCISlot0 16 represents the PCI port of the ninth switching module 311. PCI Device indicates that this PCI port is connected to a PCI device, PCI No Device indicates that no PCI device is connected to the PCI port. PCI hotplug Enable indicates that the hot-plug function of the PCI port is enabled, and PCI hotplug Disable indicates that the hot-plug function of the PCI port is disabled. PCI Lane 16 or 8 indicates that the transmission channels of the switching module can be 16 channels or 8 channels. The PCI device connected to the PCI Device can be a PCI device that supports 32-bit memory resource expansion or a PCI device that does not support 32-bit memory resource expansion.

[0041] Figure 4 Shows a schematic diagram of the link structure of a multi-layer switching module according to an embodiment of the present application.

[0042] As Figure 4 shown, the multi-layer switching module includes a tenth switching module, an eleventh switching module, and a twelfth switching module connected in sequence, Figure 4 The explanations of each part in can refer to the explanations in Figure 3 and will not be elaborated here.

[0043] Figure 5 Shows a flowchart of a method for allocating memory resources of a server according to an embodiment of the present application.

[0044] As Figure 5 shown, the method for allocating memory resources of the server in this embodiment includes operations S510 to S530.

[0045] In operation S510, in response to detecting that the server enters the power-on self-test stage, obtain the link information of the PCI link in the server, where the link information of the PCI link includes the port information of the PCI port and the device information of the PCI device.

[0046] In operation S520, determine the memory resource reservation scheme of the PCI link according to the port information of the PCI port and the device information of the PCI device.

[0047] In operation S530, in response to detecting that the server enters the system startup stage, when it is determined that the operating system of the server needs to reallocate memory resources, reallocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link.

[0048] The power-on self-test stage can be the stage when the server conducts hardware self-test and initialization after power-on. During the power-on self-test stage of the server, the server's Basic Input Output System (BIOS) can be loaded. The BIOS can be responsible for memory resource allocation, hardware initialization, self-test, system setting management, and booting the operating system, preparing for the subsequent system startup of the server. The hardware structure of the server can refer to Figure 1 the structure shown in

[0049] The server can obtain the link information of the PCI links in the server through PCI enumeration by the BIOS. Among them, the link information of the PCI links includes the port information of the PCI ports and the device information of the PCI devices. The port information of the PCI ports can include the port type, transmission rate, etc. of the PCI ports. The device information of the PCI devices can include the type, subtype, Device Identification (DID), Vendor Identification (VID) of the PCI devices, and the port number of the PCI ports, etc.

[0050] Based on the port information of the PCI ports and the devices of the PCI devices, it can be confirmed whether the PCI ports or PCI devices need to allocate memory resources and the bit width of the allocated memory resources, thereby determining the memory resource reservation scheme for the PCI links.

[0051] The system startup stage of the server can be the process of the server loading the operating system. During the system startup stage, the server can detect the hardware devices in the server through the kernel of the server to determine the memory usage of the hardware devices, can also read the configuration files of various services and processes in the server to determine the memory resources to be used, and can also detect the usage of the memory resources in real time, thereby determining from multiple aspects whether it is necessary to re-allocate the memory resources.

[0052] According to the embodiments of the present application, during the power-on self-test stage of the server, based on the port information of the PCI ports and the device information of the PCI devices, the memory resource reservation scheme for the PCI link can be confirmed. Thus, when the server enters the system startup stage, if memory resource re-allocation is required, the memory resources can be re-allocated according to the memory resource reservation scheme, making the memory resource allocation more reasonable and avoiding the problem of abnormal server operation caused by the PCI devices or PCI ports that need to allocate memory resources not being allocated memory resources.

[0053] According to an embodiment of the present application, determining a memory resource reservation scheme for a PCI link based on the port information of a PCI port and the device information of a PCI device may include: when it is determined that the PCI link is of a first type and the PCI link includes a PCI device according to the link information of the PCI link, determining a memory resource reservation scheme for the PCI device in the PCI link according to the device information of the PCI device; when it is determined that the PCI link is of a first type and the PCI link does not include a PCI device according to the link information of the PCI link, determining a memory resource reservation scheme for the PCI port in the PCI link according to the port information of the PCI port in the PCI link.

[0054] The first type of PCI link may indicate that the PCI link does not include a second target device, and the second target device may be a switching module, such as Figures 1 to 4 the switching module shown therein. That the PCI link is of the first type means that a PCI port in the PCI link is connected to a PCI device or the PCI link only includes one PCI port.

[0055] When it is determined that the PCI link is of the first type and the PCI link includes a PCI device according to the link information of the PCI link, it is possible to determine whether the PCI device requires memory resources and the size of the required memory resources according to the device information of the PCI device, so as to determine a memory resource reservation scheme for the PCI device in the PCI link.

[0056] When it is determined that the PCI link is of the first type and the PCI link does not include a PCI device according to the link information of the PCI link, it is possible to determine whether it is necessary to reserve memory resources for the PCI port according to the port information of the PCI port in the PCI link, so as to determine a memory resource reservation scheme for the PCI port in the PCI link.

[0057] According to an embodiment of the present application, determining a memory resource reservation scheme for a PCI device in a PCI link according to the device information of the PCI device may include: determining whether the PCI device in the PCI link is a first target device according to the device information of the PCI device; when it is determined that the PCI device is the first target device, determining that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources with a target bit width; when it is determined that the PCI device is not the first target device and the PCI device supports memory resource expansion, determining that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources with an extended bit width; when it is determined that the PCI device is not the first target device and does not support memory resource expansion, determining that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources with a target bit width.

[0058] The first target device may be a DPU device. The structure of the first target device may refer to Figure 2 the structure in it. When it is determined that the PCI device is the first target device, the memory resource reservation scheme for the PCI device in the PCI link may be to reserve the memory resources with the target bit width. The memory resources with the target bit width may be, for example, 32-bit memory resources. When it is determined that the PCI device is not the first target device and the PCI device supports memory resource expansion, the memory resource reservation scheme for the PCI device in the PCI link may be to reserve the memory resources with the extended bit width. The memory resources with the extended bit width may be, for example, 64-bit memory resources. When it is determined that the PCI device is not the first target device and does not support memory resource expansion, the memory resource reservation scheme for the PCI device in the PCI link may be to reserve the memory resources with the target bit width.

[0059] Since the memory resources with the target bit width are limited, therefore, when the PCI device can support memory resource expansion, allocating the memory resources with the extended bit width for the PCI device can save the memory resources with the target bit width. Reserving memory resources for the first target device can ensure that the Internet access function of the server is not affected.

[0060] According to an embodiment of the present application, determining the memory resource reservation scheme for a PCI port in a PCI link according to the port information of the PCI port in the PCI link may include: determining whether the PCI port in the PCI link is a target port according to the port information of the PCI port in the PCI link; when it is determined that the PCI port is a target port, determining that the memory resource reservation scheme for the PCI port in the PCI link is to reserve the memory resources with the target bit width; when it is determined that the PCI port is not a target port, determining that the memory resource reservation scheme for the PCI port in the PCI link is not to reserve memory resources.

[0061] The target port may be a port that needs to reserve memory resources, such as a port that needs to connect to a graphics card, a hard disk, a network card, etc. When it is determined that the PCI port is a target port, memory resources may be reserved for the PCI port. When it is determined that the PCI port is not a target port, memory resources are not reserved for the PCI port. By identifying whether the PCI port is a target port, the memory resources reserved for the PCI port can be determined.

[0062] Figure 6 The flowchart shows the memory resource allocation method of the server according to an embodiment of the present application when the PCI link is of the first type.

[0063] As Figure 6 shown, the method includes operation S601 to operation S611.

[0064] In operation S601, in response to detecting that the server enters the power-on self-check phase, obtain the link information of the PCI link in the server, where the link information of the PCI link includes the port information of the PCI port and the device information of the PCI device.

[0065] In operation S602, determine that the PCI link is of the first type according to the link information of the PCI link.

[0066] In operation S603, determine whether the PCI link includes a PCI device. If it is determined that the PCI link includes a PCI device, perform operation S604. If it is determined that the PCI link does not include a PCI device, perform operation S609.

[0067] In operation S604, according to the device information of the PCI device, determine whether the PCI device in the PCI link is the first target device. If it is determined that the PCI device is the first target device, perform operation S605. If it is determined that the PCI device is not the first target device, perform operation S606.

[0068] In operation S605, determine that the memory resource reservation scheme for the PCI device in the PCI link is to reserve the memory resources with the target bit width.

[0069] In operation S606, determine whether the PCI device supports memory resource expansion. If the PCI device supports memory resource expansion, perform operation S607. If the PCI device does not support memory resource expansion, perform operation S608.

[0070] In operation S607, determine that the memory resource reservation scheme for the PCI device in the PCI link is to reserve the memory resources with the extended bit width.

[0071] In operation S608, determine that the memory resource reservation scheme for the PCI device in the PCI link is to reserve the memory resources with the target bit width.

[0072] In operation S609, according to the port information of the PCI port in the PCI link, determine whether the PCI port in the PCI link is the target port. If it is determined that the PCI port in the PCI link is the target port, perform operation S610. If it is determined that the PCI port is not the target port, perform operation S611.

[0073] In operation S610, determine that the memory resource reservation scheme for the PCI port in the PCI link is to reserve the memory resources with the target bit width.

[0074] In operation S611, determine that the memory resource reservation scheme for the PCI port in the PCI link is not to reserve memory resources.

[0075] According to an embodiment of the present application, by identifying the PCI link, a memory resource reservation scheme in various cases of the PCI link under the first type is fully considered, so that the memory resources can be reasonably reserved for the PCI devices and PCI ports in need during the power-on self-test stage of the server.

[0076] According to an embodiment of the present application, determining the memory resource reservation scheme of the PCI link according to the port information of the PCI port and the device information of the PCI device may further include: when it is determined that the PCI link is of the second type according to the link information of the PCI link, determining the first-level information of the PCI link, where the first-level information represents that the PCI link includes N second target devices connected in sequence, and N is an integer greater than 0.

[0077] According to an embodiment of the present application, when the second target device at the nth layer is connected to the PCI device at the n+1th layer, determine the memory resource reservation scheme for the PCI device at the n+1th layer in the PCI link according to the device information of the PCI device at the n+1th layer, where n = 1,..., N. When the second target device at the nth layer is not connected to the PCI device at the n+1th layer, determine the memory resource reservation scheme for the PCI port at the n+1th layer in the PCI link according to the port information of the second target device at the nth layer.

[0078] The second type may represent that the PCI link includes second target devices, that is, the PCI link is multi-layered. The second target device can be regarded as a type of PCI device. The second target device can refer to the structure as Figure 3 in, and the second target device can be extended to connect multiple PCI devices. The structure of the multi-layer second target device can refer to the structure as Figure 4 in.

[0079] When the PCI link is of the second type, it is necessary to sequentially confirm the port information of the multi-layer second target devices and the device information of the connected PCI devices.

[0080] For example, taking N = 2 as an example, the second target device of the first layer is sequentially connected to the second target device of the second layer. When the second target device of the first layer is connected to the PCI device of the second layer, according to the device information of the PCI device of the second layer, a memory resource reservation scheme for this PCI device is determined. When the second target device of the first layer is not connected to the PCI device of the second layer, according to the port information of the second target device of the first layer, a memory resource reservation scheme for the PCI port of the second layer is determined. When the second target device of the second layer is connected to the PCI device of the third layer, according to the device information of the PCI device of the third layer, a memory resource reservation scheme for this PCI device is determined. When the second target device of the second layer is not connected to the PCI device of the third layer, according to the port information of the second target device of the second layer, a memory resource reservation scheme for the PCI port of the third layer is determined.

[0081] According to an embodiment of the present application, determining a memory resource reservation scheme for the (n + 1)-th layer PCI device in the PCI link according to the device information of the (n + 1)-th layer PCI device may include: when it is determined that the (n + 1)-th layer PCI device is the first target device, determining that the memory resource reservation scheme for the (n + 1)-th layer PCI device in the PCI link is to reserve memory resources with a target bit width; when it is determined that the (n + 1)-th layer PCI device is not the first target device and the (n + 1)-th layer PCI device supports memory resource expansion, determining that the memory resource reservation scheme for the (n + 1)-th layer PCI device in the PCI link is to reserve memory resources with an extended bit width; when it is determined that the (n + 1)-th layer PCI device is not the first target device and the (n + 1)-th layer PCI device does not support memory resource expansion, determining that the memory resource reservation scheme for the (n + 1)-th layer PCI device in the PCI link is to reserve memory resources with a target bit width.

[0082] When it is determined that the second target device of the n-th layer is connected to the (n + 1)-th layer PCI device, it can be determined whether the (n + 1)-th layer PCI device is the first target device. When it is determined that the (n + 1)-th layer PCI device is the first target device, that is, the (n + 1)-th layer PCI device needs to reserve memory resources with a target bit width, then determine that the memory resource reservation scheme for the (n + 1)-th layer PCI device in the PCI link is to reserve memory resources with a target bit width. When it is determined that the (n + 1)-th layer PCI device is not the first target device, it can be detected whether the (n + 1)-th layer PCI device supports memory resource expansion. When the (n + 1)-th layer PCI device supports memory resource expansion, determine that the memory resource reservation scheme for the (n + 1)-th layer PCI device in the PCI link is to reserve memory resources with an extended bit width; when it is determined that the (n + 1)-th layer PCI device does not support memory resource expansion, determine that the memory resource reservation scheme for the (n + 1)-th layer PCI device in the PCI link is to reserve memory resources with a target bit width.

[0083] According to an embodiment of the present application, sequentially confirming the PCI devices connected to N second target devices can fully determine the corresponding memory resource reservation scheme for the PCI devices that need to reserve memory resources in the server, providing a basis for the memory resource allocation of the server. Moreover, it can also reduce the reservation of memory resources for irrelevant PCI devices.

[0084] According to an embodiment of the present application, determining the memory resource reservation scheme for the PCI port of the (n + 1)-th layer in the PCI link according to the port information of the second target device of the n-th layer may include: when it is determined that the PCI port of the (n + 1)-th layer of the second target device of the n-th layer is a target port, determining that the memory resource reservation scheme for the downstream port of the second target device of the n-th layer in the PCI link is to reserve the memory resource with the target bit width; when it is determined that the PCI port of the (n + 1)-th layer of the second target device of the n-th layer is not a target port, determining that the memory resource reservation scheme for the downstream port of the second target device of the n-th layer in the PCI link is not to reserve memory resources.

[0085] When it is determined that the second target device of the n-th layer is not connected to the PCI device of the (n + 1)-th layer, it can be determined whether the PCI port of the (n + 1)-th layer of the second target device of the n-th layer is a target port. The PCI port of the (n + 1)-th layer may be the downstream port of the second target device of the n-th layer. When it is determined that the PCI port of the (n + 1)-th layer is a target port, that is, the PCI port of the (n + 1)-th layer needs to reserve memory resources, it can be determined that the memory resource reservation scheme for the downstream port of the second target device of the n-th layer in the PCI link is to reserve the memory resource with the target bit width. When it is determined that the PCI port of the (n + 1)-th layer of the second target device of the n-th layer is not a target port, that is, the PCI port of the (n + 1)-th layer does not need to reserve memory resources, it can be determined that the memory resource reservation scheme for the downstream port of the second target device of the n-th layer in the PCI link is not to reserve memory resources.

[0086] Figure 7 The flowchart shows the method for allocating memory resources of a server according to an embodiment of the present application when the PCI link is of the second type.

[0087] As Figure 7 shown, the method includes operation S701 to operation S712.

[0088] In operation S701, in response to detecting that the server enters the power-on self-test stage, obtain the link information of the PCI link in the server, where the link information of the PCI link includes the port information of the PCI port and the device information of the PCI device.

[0089] In operation S702, determine that the PCI link is of the second type according to the link information of the PCI link, where the first-level information indicates that the PCI link includes N second target devices connected in sequence, and let n = N.

[0090] In operation S703, determine whether the second target device at the nth layer in the PCI link is connected to the PCI device at the n+1th layer. If it is determined that the second target device at the nth layer in the PCI link is connected to the PCI device at the n+1th layer, perform operation S704. If it is determined that the second target device at the nth layer in the PCI link is not connected to the PCI device at the n+1th layer, perform operation S709.

[0091] In operation S704, determine whether the PCI device at the n+1th layer is the first target device. If it is determined that the PCI device at the n+1th layer is the first target device, perform operation S705. If it is determined that the PCI device at the n+1th layer is not the first target device, perform operation S706.

[0092] In operation S705, determine that the memory resource reservation scheme for the PCI device at the n+1th layer in the PCI link is to reserve the memory resources with the target bit width.

[0093] In operation S706, determine whether the PCI device at the n+1th layer supports memory resource expansion. If it is determined that the PCI device at the n+1th layer supports memory resource expansion, perform operation S707. If it is determined that the PCI device at the n+1th layer does not support memory resource expansion, perform operation S708.

[0094] In operation S707, determine that the memory resource reservation scheme for the PCI device at the n+1th layer in the PCI link is to reserve the memory resources with the extended bit width.

[0095] In operation S708, determine that the memory resource reservation scheme for the PCI device at the n+1th layer in the PCI link is to reserve the memory resources with the target bit width.

[0096] In operation S709, according to the port information of the second target device at the nth layer, determine whether the PCI port at the n+1th layer is the target port. If it is determined that the PCI port at the n+1th layer is the target port, perform operation S710. If it is determined that the PCI port at the n+1th layer is not the target port, perform operation S711.

[0097] In operation S710, determine that the memory resource reservation scheme for the downstream port of the second target device at the nth layer in the PCI link is to reserve the memory resources with the target bit width.

[0098] In operation S711, it is determined that the memory resource reservation scheme for the downstream port of the second target device of the nth layer in the PCI link is not to reserve memory resources.

[0099] In operation S712, it is determined whether n is equal to 1. If n is equal to 1, the process ends. If n is not equal to 1, then n = n - 1, and operation S703 is executed.

[0100] According to the embodiments of the present application, by sequentially confirming the PCI ports of N second target devices, a corresponding memory resource reservation scheme can be fully determined for the PCI ports in the server that need to reserve memory resources, further providing a basis for the memory resource allocation of the server. And it can also reduce the reservation of memory resources for PCI ports that are not needed.

[0101] According to the embodiments of the present application, the memory resource allocation method of the server may further include: when memory resources are reserved for the PCI ports in the PCI link, the downstream ports of N second target devices, and the upstream ports corresponding to the downstream ports of each of the N second target devices, the hot-plug function of the PCI ports in the PCI link where memory resources are reserved, the downstream ports of N second target devices, and the upstream ports corresponding to the downstream ports of the N second target devices where memory resources are reserved is set to be enabled.

[0102] The hot-plug function of the PCI ports where memory resources are reserved can be enabled through the BIOS. The PCI ports where memory resources are reserved may include the PCI ports in the first type of PCI link, the upstream and downstream ports of the second target device in the second type of PCI link. When there are ports that need to reserve memory resources in the downstream port of the second target device, the upstream port of the second target device also needs to reserve memory resources, and the hot-plug functions of the upstream and downstream ports of the second target device need to be enabled.

[0103] According to the embodiments of the present application, enabling the hot-plug function for the ports that need to reserve memory resources can avoid the situation where the PCI ports or PCI devices that need to reserve memory resources do not have memory resources allocated during the reallocation of memory resources at the system startup stage.

[0104] According to an embodiment of the present application, in response to detecting that the server enters the system startup phase, when it is determined that the operating system of the server needs to reallocate memory resources, reallocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link may include: when it is determined that the PCI link is of the first type and the hot-plug function of the PCI port in the PCI link is enabled, allocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link; when it is determined that the PCI link is of the first type and the hot-plug function of the PCI port in the PCI link is disabled, reallocating memory resources for the PCI link; when it is determined that the PCI link is of the second type and the hot-plug functions of the upstream ports and downstream ports of the N second target devices are both enabled, allocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link; when it is determined that the PCI link is of the second type and the hot-plug function of at least one of the upstream ports and downstream ports of the N second target devices is disabled, reallocating memory resources for the PCI link.

[0105] According to an embodiment of the present application, when it is determined that the operating system of the server does not need to reallocate memory resources, memory resources are allocated for the PCI device and the PCI port according to the memory resource reservation scheme of the PCI link.

[0106] When the server enters the system startup phase, when it is determined that the operating system of the server needs to reallocate memory resources, the PCI=realloc parameter (a parameter for reallocating memory resources) can be added to the parameters of the Grub interface (the boot interface of the operating system) through the Grub interface, so as to achieve the reallocation of memory resources. When it is determined that the operating system of the server does not need to reallocate memory resources, the PCI=realloc parameter can be removed, so as to allocate memory resources for the PCI device and the PCI port according to the memory resource reservation scheme of the PCI link.

[0107] When it is determined that the operating system of the server needs to reallocate memory resources, the PCI link can be scanned in sequence to determine whether the hot-plug function of the PCI port in the PCI link is enabled.

[0108] When it is determined that the PCI link is of the first type, detect whether the hot-plug function of the PCI port is enabled. When the hot-plug function of the PCI port in the PCI link is enabled, allocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link; when the hot-plug function of the PCI port in the PCI link is disabled, reallocate memory resources for the PCI link.

[0109] When the PCI link is of the second type, determine whether the hot-plug functions of the upstream ports and downstream ports of the N second target devices in the PCI link are both enabled. When the hot-plug functions of the upstream ports and downstream ports of the N second target devices in the PCI link are both enabled, allocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link; when at least one of the hot-plug functions of the upstream ports and downstream ports of the N second target devices in the PCI link is disabled, re-allocate memory resources for the PCI link.

[0110] When the PCI link is of the second type, it is also possible to detect whether the hot-plug functions of the upstream and downstream ports of each second target device are enabled. When the hot-plug function of any node in the entire PCI link is not enabled, memory resources will be re-allocated. When the hot-plug functions of all nodes in the entire PCI link are enabled, the memory resource scheme in the power-on self-test stage will be used for memory resource allocation.

[0111] According to the embodiments of the present application, re-allocating memory resources according to the memory resource reservation scheme can enable the PCI devices that need to allocate memory resources to allocate corresponding memory resources based on evidence during the re-allocation process.

[0112] According to the embodiments of the present application, re-allocating memory resources for the PCI link may include: when it is determined that the memory resources allocated for the PCI link according to the memory resource reservation scheme of the PCI link are completed, obtain the remaining memory resources; re-allocate memory resources for the PCI link according to the remaining memory resources.

[0113] The PCI link that needs to re-allocate memory resources can re-allocate the remaining memory resources after the memory resource allocation of the PCI link that allocates memory according to the memory resource reservation scheme is completed.

[0114] When memory resources need to be re-allocated, the remaining memory resources can be re-allocated in the scanning order of the PCI link. When there is insufficient remaining memory resources, the memory resource allocation for the second target devices and PCI devices at the subsequent levels can be abandoned. At the same time, by judging whether the existing PCI devices support memory resource expansion, the PCI devices that support memory resource expansion are allocated memory resources with an extended bit width to save more memory resources with the target bit width, which is convenient for more PCI devices that only support memory resources with the target bit width to use, meeting the requirement of supporting more PCI devices under the operating system.

[0115] Taking the reallocation of memory resources with the PCI link being the second type as an example, after the PCI link scanning level is completed, the operating system reallocates resources for the scanned level. If there is no PCI device under the second target device of the first layer, no memory resource allocation is performed for this second target device, or if the hot-plug function of the second target device of the first layer is not enabled, the reserved memory resources are released; if there is a PCI device under the second target device of the first layer, memory resources are allocated to this PCI device, and if the hot-plug function of the second target device of the first layer is enabled, the operating system allocates memory resources to this PCI device; if there is a PCI device under the second target device of the first layer and there is also a lower-level second target device, memory resources need to be allocated to the PCI device and it is necessary to determine whether there is a PCI device under the lower-level second target device. If there is no PCI device under the lower-level second target device and the hot-plug function of the lower-level second target device is turned off, the lower-level second target device does not need to be allocated memory resources. If there is a PCI device under the lower-level second target device, memory resources are allocated to the lower-level second target device, or if the hot-plug function of the lower-level second target device is enabled, memory resources are allocated according to the memory resource reservation scheme. In this way, the memory resource allocation is performed N + 1 times until the remaining memory resource allocation is completed. When the memory resource allocation of all PCI devices of the server is completed, if the memory resources of the target bit width meet all the current PCI devices, there is no problem. If there is a shortage of memory resources of the target bit width, after the memory resources of the target bit width are allocated to the PCI devices connected to the second target device of the current layer and there are no memory resources available for allocation, the remaining PCI devices of the second target device of the current layer or the second target device and PCI devices of the next layer will not be allocated memory resources.

[0116] Figure 8 FIG. shows a flowchart of a method for allocating memory resources of a server in the system startup phase according to an embodiment of the present application.

[0117] As Figure 8 shown, the method includes operations S801 to S809.

[0118] In operation S801, it is determined whether the operating system of the server needs to reallocate memory resources. If it is determined that the operating system of the server needs to reallocate memory resources, operation S802 is executed. If it is determined that the operating system of the server does not need to reallocate memory resources, operation S809 is executed.

[0119] In operation S802, it is determined whether the PCI link is of the first type. If it is determined that the PCI link is of the first type, operation S803 is executed. If it is determined that the PCI link is not of the first type, operation S805 is executed.

[0120] In operation S803, it is determined whether the hot plug function of the PCI port in the PCI link is enabled. If the hot plug function of the PCI port is enabled, operation S804 is executed; if the hot plug function of the PCI port is disabled, operation S807 is executed.

[0121] In operation S804, memory resources are allocated to the PCI link according to the memory resource reservation scheme of the PCI link.

[0122] In operation S805, it is determined whether the hot plug functions of the upstream ports and downstream ports of the N second target devices in the PCI link are both enabled. If it is determined that the hot plug functions of the upstream ports and downstream ports of the N second target devices in the PCI link are both enabled, operation S806 is executed; if the hot plug function of at least one of the upstream ports and downstream ports of the N second target devices is disabled, operation S807 is executed.

[0123] In operation S806, memory resources are allocated to the PCI link according to the memory resource reservation scheme of the PCI link.

[0124] In operation S807, when it is determined that the memory resources allocated to the PCI link with the hot plug function enabled in the PCI link according to the memory resource reservation scheme of the PCI link are completed, the remaining memory resources are obtained.

[0125] In operation S808, the memory resources are reallocated to the PCI link according to the remaining memory resources.

[0126] In operation S809, memory resources are allocated to the PCI device and the PCI port according to the memory resource reservation scheme of the PCI link.

[0127] Since the hot plug function of the PCI link where the first target device and the target port that need to allocate memory resources are located is enabled during the power-on self-test stage, therefore, in the case of reallocating memory resources, it is possible to avoid the first target device and the target port being unable to be used due to reallocating memory resources to the first target device and the target port, ensuring that the first target device and the target port can be used normally at any time without worrying about the problem that the first target device and the target port cannot be used due to memory resource problems.

[0128] Based on the above memory resource allocation method for the server, the present application further provides a memory resource allocation device for the server. The following will be combined with Figure 9 This device will be described in detail.

[0129] Figure 9 The structural block diagram of the memory resource allocation device for the server according to the embodiment of the present application is shown.

[0130] As shown Figure 9 The memory resource allocation device 900 of the server in this embodiment includes an acquisition module 910, a determination module 920, and a first allocation module 930.

[0131] The acquisition module 910 is configured to obtain link information of a peripheral component interconnect (PCI) link in the server in response to detecting that the server enters the power-on self-test stage, where the link information of the PCI link includes port information of a PCI port and device information of a PCI device.

[0132] The determination module 920 is configured to determine a memory resource reservation scheme for the PCI link according to the port information of the PCI port and the device information of the PCI device.

[0133] The first allocation module 930 is configured to, in response to detecting that the server enters the system startup stage and when it is determined that the operating system of the server needs to reallocate memory resources, reallocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link.

[0134] The determination module 920 includes: a first determination sub-module, configured to, when it is determined according to the link information of the PCI link that the PCI link is of the first type and the PCI link includes a PCI device, determine a memory resource reservation scheme for the PCI device in the PCI link according to the device information of the PCI device; a second determination sub-module, configured to, when it is determined according to the link information of the PCI link that the PCI link is of the first type and the PCI link does not include a PCI device, determine a memory resource reservation scheme for the PCI port in the PCI link according to the port information of the PCI port in the PCI link.

[0135] The first determination sub-module includes: a first determination unit, configured to determine whether the PCI device in the PCI link is a first target device according to the device information of the PCI device; a second determination unit, configured to, when it is determined that the PCI device is the first target device, determine that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources with a target bit width; a third determination unit, configured to, when it is determined that the PCI device is not the first target device and the PCI device supports memory resource expansion, determine that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources with an extended bit width; a fourth determination unit, configured to, when it is determined that the PCI device is not the first target device and does not support memory resource expansion, determine that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources with a target bit width.

[0136] The second determination sub-module includes: a fifth determination unit, configured to determine whether a PCI port in a PCI link is a target port according to the port information of the PCI port in the PCI link; a sixth determination unit, configured to determine that the memory resource reservation scheme for the PCI port in the PCI link is to reserve memory resources with a target bit width when it is determined that the PCI port is a target port; a seventh determination unit, configured to determine that the memory resource reservation scheme for the PCI port in the PCI link is not to reserve memory resources when it is determined that the PCI port is not a target port.

[0137] The determination module 920 further includes: a third determination sub-module, configured to determine the first-level information of the PCI link when it is determined that the PCI link is of the second type according to the link information of the PCI link, where the first-level information characterizes that the PCI link includes N second target devices connected in sequence, and N is an integer greater than 0; a fourth determination sub-module, configured to determine the memory resource reservation scheme for the (n + 1)-th layer PCI device in the PCI link according to the device information of the (n + 1)-th layer PCI device when the n-th layer second target device is connected to the (n + 1)-th layer PCI device, where n = 1,..., N; a fifth determination sub-module, configured to determine the memory resource reservation scheme for the (n + 1)-th layer PCI port in the PCI link according to the port information of the n-th layer second target device when the n-th layer second target device is not connected to the (n + 1)-th layer PCI device.

[0138] The fourth determination sub-module includes: an eighth determination unit, configured to determine that the memory resource reservation scheme for the (n + 1)-th layer PCI device in the PCI link is to reserve memory resources with a target bit width when it is determined that the (n + 1)-th layer PCI device is a first target device; a ninth determination unit, configured to determine that the memory resource reservation scheme for the (n + 1)-th layer PCI device in the PCI link is to reserve memory resources with an extended bit width when it is determined that the (n + 1)-th layer PCI device is not a first target device and the (n + 1)-th layer PCI device supports memory resource expansion; a tenth determination unit, configured to determine that the memory resource reservation scheme for the (n + 1)-th layer PCI device in the PCI link is to reserve memory resources with a target bit width when it is determined that the (n + 1)-th layer PCI device is not a first target device and the (n + 1)-th layer PCI device does not support memory resource expansion.

[0139] The fifth determination sub-module includes: an eleventh determination unit, configured to determine that the memory resource reservation scheme for the downstream port of the second target device at the nth layer in the PCI link is to reserve the memory resources with the target bit width when it is determined that the PCI port at the (n + 1)th layer of the second target device at the nth layer is the target port; a twelfth determination unit, configured to determine that the memory resource reservation scheme for the downstream port of the second target device at the nth layer in the PCI link is not to reserve memory resources when it is determined that the PCI port at the (n + 1)th layer of the second target device at the nth layer is not the target port.

[0140] The memory resource allocation device 900 of the server may further include: an enabling module, configured to set the hot-plug function of the PCI port in the PCI link, the downstream ports of the N second target devices, and the upstream ports corresponding to the downstream ports of the N second target devices to be enabled when the memory resources are reserved for the PCI port in the PCI link, the downstream ports of the N second target devices, and the upstream ports corresponding to the downstream ports of the N second target devices.

[0141] The first allocation module 930 includes: a first allocation sub-module, configured to allocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link when it is determined that the PCI link is of the first type and the hot-plug function of the PCI port in the PCI link is enabled; a second allocation sub-module, configured to re-allocate memory resources for the PCI link when it is determined that the PCI link is of the first type and the hot-plug function of the PCI port in the PCI link is disabled; a third allocation sub-module, configured to allocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link when it is determined that the PCI link is of the second type and the hot-plug functions of the upstream and downstream ports of the N second target devices are both enabled; a fourth allocation sub-module, configured to re-allocate memory resources for the PCI link when it is determined that the PCI link is of the second type and the hot-plug function of at least one of the upstream and downstream ports of the N second target devices is disabled.

[0142] The second allocation sub-module includes: a first allocation unit, configured to obtain the remaining memory resources when it is determined that the memory resources allocated for the PCI link according to the memory resource reservation scheme of the PCI link are completed; a second allocation unit, configured to re-allocate memory resources for the PCI link according to the remaining memory resources.

[0143] The memory resource allocation device 900 of the server further includes: a second allocation module, configured to allocate memory resources for the PCI device and the PCI port according to the memory resource reservation scheme of the PCI link when it is determined that the operating system of the server does not require re-allocation of memory resources.

[0144] According to embodiments of the present application, any of the acquisition module 910, the determination module 920, and the first allocation module 930 may be combined and implemented in one module, or any one of them may be split into multiple modules. Alternatively, at least part of the functions of one or more of these modules may be combined with at least part of the functions of other modules and implemented in one module. According to embodiments of the present application, at least one of the acquisition module 910, the determination module 920, and the first allocation module 930 may be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or any other reasonable way of integrating or packaging circuits, etc., implemented by hardware or firmware, or implemented in any one or a suitable combination of the three implementation manners of software, hardware, and firmware. Alternatively, at least one of the acquisition module 910, the determination module 920, and the first allocation module 930 may be at least partially implemented as a computer program module, and when the computer program module is run, it can execute corresponding functions.

[0145] Figure 10 The block diagram of an electronic device suitable for implementing the memory resource allocation method for a server according to an embodiment of the present application is shown.

[0146] As Figure 10 shown, the electronic device 1000 according to an embodiment of the present application includes a processor 1001, which can perform various appropriate actions and processes according to the program stored in the read only memory (ROM) 1002 or the program loaded from the storage section 1008 into the random access memory (RAM) 1003. The processor 1001 may include, for example, a general microprocessor (such as a CPU), an instruction set processor, and / or a related chipset, and / or a dedicated microprocessor (such as an application specific integrated circuit (ASIC)), etc. The processor 1001 may also include on-board memory for caching purposes. The processor 1001 may include a single processing unit or multiple processing units for performing different actions of the method flow according to embodiments of the present application.

[0147] In the RAM 1003, various programs and data required for the operation of the electronic device 1000 are stored. The processor 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. The processor 1001 performs various operations of the method flow according to the embodiments of the present application by executing the programs in the ROM 1002 and / or the RAM 1003. It should be noted that the programs can also be stored in one or more memories other than the ROM 1002 and the RAM 1003. The processor 1001 can also perform various operations of the method flow according to the embodiments of the present application by executing the programs stored in the one or more memories.

[0148] According to an embodiment of the present application, the electronic device 1000 may further include an input / output (I / O) interface 1005, and the input / output (I / O) interface 1005 is also connected to the bus 1004. The electronic device 1000 may further include one or more of the following components connected to the input / output (I / O) interface 1005: an input part 1006 including a keyboard, a mouse, etc.; an output part 1007 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc. and a speaker, etc.; a storage part 1008 including a hard disk, etc.; and a communication part 1009 including a network interface card such as a LAN card, a modem, etc. The communication part 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the input / output (I / O) interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed so that a computer program read from it can be installed into the storage part 1008 as needed.

[0149] The present application also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or may exist separately without being assembled into the device / apparatus / system. The above computer-readable storage medium carries one or more programs, and when the one or more programs are executed, the method according to the embodiments of the present application is implemented.

[0150] According to an embodiment of the present application, the computer-readable storage medium may be a non-volatile computer-readable storage medium, for example, it may include but is not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In the present application, the computer-readable storage medium may be any tangible medium that contains or stores a program, and this program can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present application, the computer-readable storage medium may include the above-described ROM 1002 and / or RAM 1003 and / or one or more memories other than ROM 1002 and RAM 1003.

[0151] An embodiment of the present application also includes a computer program product, which includes a computer program, and the computer program contains program code for executing the method shown in the flowchart. When the computer program product runs in a computer system, the program code is used to enable the computer system to implement the method provided by the embodiment of the present application.

[0152] When the computer program is executed by the processor 1001, it executes the above functions defined in the system / apparatus of the embodiment of the present application. According to an embodiment of the present application, the above-described systems, apparatuses, modules, units, etc. can be implemented by computer program modules.

[0153] In one embodiment, the computer program may rely on tangible storage media such as optical storage devices and magnetic storage devices. In another embodiment, the computer program may also be transmitted and distributed in the form of a signal on a network medium, and is downloaded and installed through the communication part 1009, and / or installed from the removable medium 1011. The program code included in the computer program can be transmitted by any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0154] In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 1009, and / or installed from the removable medium 1011. When the computer program is executed by the processor 1001, it executes the above functions defined in the system of the embodiment of the present application. According to an embodiment of the present application, the above-described systems, devices, apparatuses, modules, units, etc. can be implemented by computer program modules.

[0155] Those skilled in the art will appreciate that the features described in the various embodiments of the present application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present application. In particular, without departing from the spirit and teachings of the present application, the features described in the various embodiments of the present application can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present application.

[0156] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although the various embodiments have been described separately above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present application.

Claims

1. A method for allocating memory resources of a server, characterized in that, The method includes: In response to detecting that the server enters the power-on self-test stage, obtaining link information of a peripheral component interconnect (PCI) link in the server, where the link information of the PCI link includes port information of a PCI port and device information of a PCI device; Determining a memory resource reservation scheme for the PCI link according to the port information of the PCI port and the device information of the PCI device; In response to detecting that the server enters the system startup stage, and when it is determined that the operating system of the server needs to reallocate memory resources, reallocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link.

2. The method according to claim 1, wherein The determining the memory resource reservation scheme for the PCI link according to the port information of the PCI port and the device information of the PCI device includes: When it is determined that the PCI link is of a first type and the PCI device is included in the PCI link according to the link information of the PCI link, determining a memory resource reservation scheme for the PCI device in the PCI link according to the device information of the PCI device; When it is determined that the PCI link is of a first type and the PCI device is not included in the PCI link according to the link information of the PCI link, determining a memory resource reservation scheme for the PCI port in the PCI link according to the port information of the PCI port in the PCI link.

3. The method according to claim 2, wherein The determining the memory resource reservation scheme for the PCI device in the PCI link according to the device information of the PCI device includes: Determining whether the PCI device in the PCI link is a first target device according to the device information of the PCI device; When it is determined that the PCI device is the first target device, determining the memory resource reservation scheme for the PCI device in the PCI link as reserving memory resources with a target bit width; When it is determined that the PCI device is not the first target device and the PCI device supports memory resource expansion, determining the memory resource reservation scheme for the PCI device in the PCI link as reserving memory resources with an extended bit width; When it is determined that the PCI device is not the first target device and does not support memory resource expansion, determining the memory resource reservation scheme for the PCI device in the PCI link as reserving the memory resources with the target bit width.

4. The method according to claim 3, characterized in that, The determining the memory resource reservation scheme for the PCI port in the PCI link according to the port information of the PCI port in the PCI link includes: Determining whether the PCI port in the PCI link is a target port according to the port information of the PCI port in the PCI link; When it is determined that the PCI port is the target port, determining the memory resource reservation scheme for the PCI port in the PCI link as reserving the memory resources with the target bit width; When it is determined that the PCI port is not the target port, determine that the memory resource reservation scheme for the PCI port in the PCI link is not to reserve memory resources.

5. The method according to claim 4, wherein The determining the memory resource reservation scheme for the PCI link according to the port information of the PCI port and the device information of the PCI device further includes: When it is determined that the PCI link is of the second type according to the link information of the PCI link, determine the first-level information of the PCI link, where the first-level information represents that the PCI link includes N second target devices connected in sequence, and N is an integer greater than 0; When the nth-layer second target device is connected to the (n + 1)th-layer PCI device, determine the memory resource reservation scheme for the (n + 1)th-layer PCI device in the PCI link, where n = 1,..., N; When the nth-layer second target device is not connected to the (n + 1)th-layer PCI device, determine the memory resource reservation scheme for the (n + 1)th-layer PCI port in the PCI link according to the port information of the nth-layer second target device.

6. The method according to claim 5, wherein The determining the memory resource reservation scheme for the (n + 1)th-layer PCI device in the PCI link according to the device information of the (n + 1)th-layer PCI device includes: When it is determined that the (n + 1)th-layer PCI device is the first target device, determine that the memory resource reservation scheme for the (n + 1)th-layer PCI device in the PCI link is to reserve the memory resources of the target bit width; When it is determined that the (n + 1)th-layer PCI device is not the first target device and the (n + 1)th-layer PCI device supports memory resource expansion, determine that the memory resource reservation scheme for the (n + 1)th-layer PCI device in the PCI link is to reserve the memory resources of the extended bit width; When it is determined that the (n + 1)th-layer PCI device is not the first target device and the (n + 1)th-layer PCI device does not support memory resource expansion, determine that the memory resource reservation scheme for the (n + 1)th-layer PCI device in the PCI link is to reserve the memory resources of the target bit width.

7. The method according to claim 5, wherein Determining the memory resource reservation scheme for the (n + 1)th-layer PCI port in the PCI link according to the port information of the nth-layer second target device includes: When it is determined that the (n + 1)th-layer PCI port of the nth-layer second target device is the target port, determine that the memory resource reservation scheme for the downstream port of the nth-layer second target device in the PCI link is to reserve the memory resources of the target bit width; When it is determined that the (n + 1)th-layer PCI port of the nth-layer second target device is not the target port, determine that the memory resource reservation scheme for the downstream port of the nth-layer second target device in the PCI link is not to reserve memory resources.

8. The method according to claim 7, wherein Further includes: When memory resources are reserved for the PCI port in the PCI link, the downstream ports of the N second target devices, and the upstream ports corresponding to the downstream ports of the N second target devices respectively, set the hot plug function of the PCI port in the PCI link for which memory resources are reserved, the downstream ports of the N second target devices, and the upstream ports corresponding to the downstream ports of the N second target devices for which memory resources are reserved to be enabled.

9. The method according to any one of claims 5 to 8, characterized in that In response to detecting that the server enters the system startup phase, when it is determined that the operating system of the server needs to reallocate memory resources, reallocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link includes: When it is determined that the PCI link is of the first type and the hot plug function of the PCI port in the PCI link is enabled, allocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link; When it is determined that the PCI link is of the first type and the hot plug function of the PCI port in the PCI link is disabled, reallocate memory resources for the PCI link; When it is determined that the PCI link is of the second type and the hot plug functions of the upstream ports and downstream ports of the N second target devices are both enabled, allocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link; When it is determined that the PCI link is of the second type and at least one of the hot plug functions of the upstream ports and downstream ports of the N second target devices is disabled, reallocate memory resources for the PCI link.

10. The method according to claim 9, characterized in that Reallocating memory resources for the PCI link includes: When it is determined that the memory resources allocated for the PCI link according to the memory resource reservation scheme of the PCI link are completed, obtain the remaining memory resources; Reallocate memory resources for the PCI link according to the remaining memory resources.

11. The method according to claim 9, wherein It also includes: When it is determined that the operating system of the server does not need to reallocate memory resources, allocate memory resources for the PCI device and the PCI port according to the memory resource reservation scheme of the PCI link.

12. A memory resource allocation device for a server, characterized in that, The device includes: An acquisition module, configured to, in response to detecting that the server enters the power-on self-test phase, acquire link information of a peripheral component interconnect PCI link in the server, where the link information of the PCI link includes port information of a PCI port and device information of a PCI device; A determination module, configured to determine a memory resource reservation scheme of the PCI link according to the port information of the PCI port and the device information of the PCI device; A first allocation module, configured to, in response to detecting that the server enters the system startup phase, when it is determined that the operating system of the server needs to reallocate memory resources, reallocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link.

13. An electronic device, including: One or more processors; A memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 11.

14. A computer-readable storage medium having a computer program or instructions stored thereon, characterized in that, The computer program or instruction, when executed by a processor, implements the steps of the method according to any one of claims 1 to 11.

15. A computer program product, comprising a computer program or instructions, characterized in that, The computer program or instruction, when executed by a processor, implements the steps of the method according to any one of claims 1 to 11.

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