Data sharing method of memory controller

Abstract

A data sharing method of a memory controller in an environment including a plurality of operating devices includes: determining whether a request packet corresponds to a predetermined operating device; determining whether an address included in the request packet corresponds to a predetermined address; obtaining a tag line corresponding to the request packet; and determining whether the request packet is serviceable based on the service bit included in the tag row.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2024 - 0000549, filed with the Korean Intellectual Property Office on January 2, 2024, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a data sharing method for a memory controller, and more particularly, to a source - identifying memory controller for a data processing pipeline. Background art

[0004] Many recently released systems - on - chip (SoCs) include processors or accelerators (e.g., data processing units (DPUs), image signal processors (ISPs), and neural processing units (NPUs)). In these cases, data may typically be shared among multiple processors / accelerators of the system - on - chip and a pipeline may be constructed. Data processing generally may involve a producer that generates data and a consumer that post - processes the generated data. For ensuring data consistency, memory copying and synchronization between the producer and the consumer are beneficial. Software running on a host processor may be involved in memory copying and synchronization and may cause significant stalls in the hardware. As a result, a large amount of time (e.g., running time) and resources (e.g., memory) may be wasted.

[0005] The above description was obtained during the process of conceiving the present disclosure or was already available at that time and is not necessarily known prior to the filing of this application. Summary of the invention

[0006] One or more embodiments may at least solve the above problems and / or disadvantages, as well as other disadvantages not described above. Additionally, an embodiment need not overcome and may not overcome any of the above problems and disadvantages.

[0007] According to an aspect of the present disclosure, a data sharing method of a memory controller in an environment including a plurality of operation devices includes: determining whether a request packet corresponds to a predetermined operation device; determining whether an address included in the request packet corresponds to a predetermined address; obtaining a tag row corresponding to the request packet; and determining whether the request packet is serviceable based on a service bit included in the tag row.

[0008] The memory controller may include at least one of a dynamic random access memory (DRAM) controller and a cache controller.

[0009] The data sharing method may further include: updating the tag row based on determining that the request packet is serviceable.

[0010] Updating a tag row may include: updating a service bit of the tag row from a first value to a second value based on the request group being a producer group.

[0011] Updating a tag row may include: updating a service bit of the tag row from the second value to the first value based on the request group being a consumer group.

[0012] Determining whether a request group is servable may include: based on the request group being a consumer group, determining that the consumer group can read data based on the service bit being the second value.

[0013] The data sharing method may further include: adding the request group to a request queue of a memory controller based on determining that the request group is not servable.

[0014] The data sharing method may further include: based on the number of multiple producer groups being greater than or equal to a predetermined number compared to the number of multiple consumer groups, requesting a producer operation device corresponding to a producer group among the multiple producer groups to reduce bandwidth.

[0015] The data sharing method may further include: based on the number of multiple consumer groups being greater than or equal to a predetermined number compared to the number of multiple producer groups, requesting a consumer operation device corresponding to a consumer group among the multiple consumer groups to reduce bandwidth.

[0016] According to one aspect of the present disclosure, a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to: determine whether a request group corresponds to a predetermined operation device; determine whether an address included in the request group corresponds to a predetermined address; obtain a tag row corresponding to the request group; and determine whether the request group is servable based on a service bit included in the tag row.

[0017] According to one aspect of the present disclosure, a memory controller includes: a request queue configured to store multiple request groups; a queue arbiter configured to determine priority information corresponding to the multiple request groups based on at least one of producer operation device information, consumer operation device information, and address information corresponding to a shared buffer; and a tag memory configured to store a tag row including a service bit indicating whether a request group among the multiple request groups is servable.

[0018] The memory controller may further include at least one of a dynamic random access memory (DRAM) controller and a cache controller.

[0019] The memory controller may further include a tag updater configured to update the tag row based on determining that the request group is servable.

[0020] The tag updater can also be configured to update the service bit of the tag line from a first value to a second value based on the request group being a producer group.

[0021] The tag updater can also be configured to update the service bit of the tag line from the second value to the first value based on the request group being a consumer group.

[0022] The tag updater can also be configured to determine that a consumer group can read data based on the request group being a consumer group and the service bit being the second value.

[0023] The tag updater can also be configured to input the request group into the request queue based on determining that the request group is not serviceable.

[0024] Based on the number of multiple producer groups being greater than or equal to a predetermined number compared to the number of multiple consumer groups, the memory controller can also be configured to request that a producer operation device corresponding to the producer group among the multiple producer groups reduce the bandwidth.

[0025] Based on the number of multiple consumer groups being greater than or equal to a predetermined number compared to the number of multiple producer groups, the memory controller can also be configured to request that a consumer operation device corresponding to the consumer group among the multiple consumer groups reduce the bandwidth. Description of the Drawings

[0026] The above and / or other aspects will become more apparent from the description of specific embodiments with reference to the accompanying drawings, in which:

[0027] Figure 1 is a diagram showing the operation of a system-on-chip (SoC) according to an embodiment;

[0028] Figure 2 is a flowchart showing a configuration method according to an embodiment;

[0029] Figure 3 is a flowchart showing the operation of a memory controller according to an embodiment;

[0030] Figure 4 is a block diagram of a memory controller according to an embodiment;

[0031] Figure 5 is a diagram showing a method for sharing data between operation devices according to an embodiment;

[0032] Figure 6 is a diagram showing the operation of a memory controller according to an embodiment;

[0033] Figure 7 is a diagram showing the operation of a memory controller according to an embodiment;

[0034] Figure 8 is a diagram showing a data congestion handling method according to an embodiment; and

[0035] Figure 9 is a flowchart showing a data sharing method according to an embodiment. Detailed implementation manners

[0036] The following structural or functional descriptions are merely exemplary to describe some embodiments, and the embodiments of the present disclosure can be implemented in various forms. The described embodiments are not intended to be limiting, but are intended to cover various modifications, equivalents, and alternatives within the scope of the present disclosure.

[0037] Terms such as first and second may be used herein to describe components. Each of these terms is not used to define the essence, order, or sequence of the corresponding component, but is only used to distinguish the corresponding component from other components. For example, within the scope of the rights according to the concept of the present disclosure, a "first" component may be referred to as a "second" component, or similarly, a "second" component may be referred to as a "first" component.

[0038] It should be noted that if a first component is described as "connected", "coupled", or "joined" to a second component, a third component may be "connected", "coupled", and "joined" between the first component and the second component, or the first component may be directly connected, coupled, or joined to the second component. However, if the first component is described as "directly connected", "directly coupled", or "directly joined" to the second component, there may be no third component between the first component and the second component. Expressions describing the relationship between components (such as "between", "directly between", or "directly adjacent", etc.) should be interpreted similarly.

[0039] The singular forms "a", "an", and "the" are intended to also include the plural forms unless the context clearly gives the opposite indication. It should also be understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0040] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms such as those defined in a common dictionary should be interpreted as having the same meaning as in the context of the related art and should not be interpreted as having an ideal or overly formal meaning unless expressly so defined herein.

[0041] Embodiments can be implemented as various types of products, such as, for example, a personal computer (PC), a laptop computer, a tablet computer, a smart phone, a television (TV), a smart home appliance, a smart vehicle, a kiosk, and a wearable device. Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to refer to the same elements.

[0042] Figure 1 is a diagram illustrating the operation of a system-on-chip (SoC) according to an embodiment.

[0043] Referring Figure 1 , the SoC 10 according to an embodiment may include a producer operation device 100, a consumer operation device 110, a serialization point (POS) 120, and a memory controller 150.

[0044] The SoC 10 may include a plurality of processors or a plurality of accelerators (e.g., a data processing unit (DPU), an image signal processor (ISP), and a neural processing unit (NPU)). The processors and accelerators included in the SoC 10 may be referred to as operation devices, cores, or intellectual property (IP) cores or IP blocks. In an embodiment, the IP core or IP block may be a reusable unit of logic, cell, or integrated circuit layout design, but the embodiment is not limited thereto. The operation device may include at least one of the producer operation device 100 and the consumer operation device 110, the producer operation device 100 may be configured to generate data, and the consumer operation device 110 may be configured to consume the data generated by the producer operation device 100. In some embodiments, a single operation device may be (or may act as) the producer operation device 100 when generating data and may be (or may act as) the consumer operation device 110 when consuming data, but the embodiment is not limited thereto.

[0045] The producer operation device 100 may be a processor or an accelerator responsible for generating data in the data processing (e.g., chaining and pipelining) of the SoC 10. The producer operation device 100 may execute driver software for managing the producer operation device 100, may generate data, and may enable the consumer operation device 110 to consume the generated data. The producer operation device 100 may write the data to a first controller, which may be the POS 120, through which the producer operation device 100 interfaces with the consumer operation device 110.

[0046] The consumer operating device 110 may be a processor or an accelerator responsible for consuming data in data processing. The consumer operating device 110 may execute driver software that manages the consumer operating device 110 and may function to read and process data generated by the producer operating device 100. The consumer operating device 110 may send a read request for the producer operating device 100 to the POS 120. Although Figure 1 only one consumer operating device 110 is shown, the embodiment is not limited thereto. For example, in some embodiments, the SoC 10 may include more than one consumer operating device 110.

[0047] The POS 120 may be a point that serializes the traffic generated by the producer operating device 100 and the consumer operating device 110. The POS 120 may include a memory controller 150 and a top-level interconnect through which the producer operating device 100 and the consumer operating device 110 may share data.

[0048] The write data 130 generated by the producer operating device 100 may be propagated into a source-aware memory controller (e.g., the memory controller 150) included in the POS 120. The write data 130 may be flushed from the local cache 101 corresponding to the producer operating device 100. In some embodiments, the SoC 10 may not include the local cache 101, and the write data 130 may directly reach the POS 120.

[0049] The read data 140 may be data read by the consumer operating device 110 from the memory controller 150 at the POS 120. The read data 140 may be stored in the local cache 111 corresponding to the consumer operating device 110. In some embodiments, the SoC 10 may not include the cache 111, and the read data 140 may be directly input into the consumer operating device 110.

[0050] The memory controller 150 may identify the traffic generated by the producer operating device 100 and the consumer operating device 110 according to a predetermined configuration and may function to complete the producer-consumer chain using at least one of the identification result of the traffic, the target address information, and the tag information.

[0051] As described above, in some implementations of the SoC, memory copy and synchronization may be performed between the producer operating device 100 and the consumer operating device 110 for data consistency. Software running on the host processor is involved in the memory copy and synchronization and may cause significant delays in the hardware. As a result, a large amount of time (e.g., running time) and resources (e.g., memory) may be wasted.

[0052] Some embodiments of the SoC may use software or hardware techniques to reduce host processor intervention. For example, hardware techniques can be used to create dedicated paths between operating devices so that the producer operating device and the consumer operating device can operate simultaneously.

[0053] For example, software techniques can be used to distinguish between a producer operating device and a consumer operating device during memory allocation, and add links to the producer operating device and the consumer operating device, where the links indicate that the producer operating device and the consumer operating device are virtually connected to each other so that the hardware can support the connection.

[0054] However, these methods may encounter the problem that the operation sequences of the producer operating device and the consumer operating device may be aligned with each other, which results in inevitable intervention by the host processor (e.g., governor software). When using a predetermined data size and buffer, new synchronization may be required. Operating devices that do not support synchronization may need additional development to support synchronization. Software techniques may only be applicable to processors and may not be used by accelerators.

[0055] Embodiments of the present disclosure relate to a method that can eliminate the above problems. When sharing data, it is inevitable to use memory or cache. Therefore, the memory controller 150 (or, for example, the cache controller) may have configurable registers that can identify the source (e.g., the producer operating device 100 or the consumer operating device 110), and data sharing can be performed between operating devices in the memory controller 150. When performing this data sharing, the memory controller 150 may perform sequential scheduling for data processing between the producer operating device 100 and the consumer operating device 110.

[0056] When applying a configuration (e.g., information related to at least one of the following: producer operating device IP information, consumer operating device IP information, shared buffer start address, shared buffer size offset, and start / end trigger) to the memory controller 150, consistency between operating devices can be achieved in the memory controller 150.

[0057] When the configuration in the memory controller 150 is completed and software for managing the producer operating device and / or the consumer operating device is executed, each software and hardware component can be set to execute a data processing pipeline without knowing the existence of data sharing.

[0058] According to some embodiments, data sharing can be performed in a circular queue format of a buffer by a single configuration of the producer operating device 100 and a single configuration of the consumer operating device 110 until the application terminates. In addition, modifications to the memory controller 150 of the POS 120 can accelerate all operating devices. This can help reduce the effort involved in creating a new SoC design. In addition, host processor intervention can be completely eliminated except for the initial execution of the application.

[0059] Figure 2 is a flowchart showing a configuration method according to an embodiment. Refer to Figure 1 the provided description can also be applied to Figure 2 . Figure 2 The operations of Figure 2 can be performed in the order and manner shown, but the embodiments are not limited thereto. For example, the order of some operations can be changed, or some operations can be omitted without departing from the spirit and scope of the shown embodiments. In some embodiments, Figure 2 the operations shown can be performed in parallel or simultaneously.

[0060] Refer to Figure 2 , the host processor can configure the memory controller 150. The host processor can store predetermined information in the configuration register of the memory controller 150 through this configuration.

[0061] At operation 210, the host processor can store source IP information (e.g., producer operating device IP information and consumer operating device IP information) in the memory controller 150. In an embodiment, this can be referred to as configuring source IP information.

[0062] At operation 220, the host processor can store shared memory address information (e.g., shared buffer start address) in the memory controller 150. In an embodiment, this can be referred to as configuring the base address corresponding to the shared memory information.

[0063] At operation 230, the host processor can store shared memory size information (e.g., shared buffer size offset) in the memory controller 150. In an embodiment, this can be referred to as configuring the address size corresponding to the shared memory information.

[0064] At operation 240, the host processor can store other information (e.g., information related to at least one of a shared start trigger and a shared end trigger) in the memory controller 150. In an embodiment, this can be referred to as configuring the start / end trigger corresponding to the shared memory information.

[0065] Figure 3is a flowchart showing the operation of the memory controller 150 according to an embodiment. Refer to Figure 1 and Figure 2 The descriptions provided can also be applied to Figure 3 . Figure 3 The operations of Figure 3 can be performed in the order and manner shown, but the embodiments are not limited thereto. For example, the order of some operations can be changed, or some operations can be omitted, without departing from the spirit and scope of the shown embodiments. In some embodiments, Figure 3 the operations shown can be performed in parallel or simultaneously.

[0066] At operation 310, the memory controller 150 can determine whether the request packet corresponds to a predetermined operation device (e.g., whether the packet corresponds to the producer operation device 100 or the consumer operation device 110). The memory controller 150 can determine whether the request packet corresponds to a predetermined operation device based on the source IP information stored through configuration.

[0067] At operation 320, based on determining that the request packet corresponds to the producer operation device 100, the memory controller 150 can determine whether the address included in the request packet corresponds to a predetermined address. The memory controller 150 can determine whether the address included in the request packet corresponds to a predetermined address based on the shared memory information stored through configuration.

[0068] At operation 330, based on determining that the request packet corresponds to the consumer operation device 110, the memory controller 150 can determine whether the address included in the request packet corresponds to a predetermined address. The memory controller 150 can determine whether the address included in the request packet corresponds to a predetermined address based on the shared memory information stored through configuration.

[0069] At operation 340, based on determining that the request packet does not correspond to a predetermined operation device, or the address included in the request packet does not correspond to a predetermined address, it can be determined that the request packet may correspond to a normal transaction unrelated to the shared memory.

[0070] At operation 350, the memory controller 150 can determine whether the request packet is servable, which can indicate whether the request packet is in a servable state. For example, when the producer operation device 100 writes data into the buffer, the memory controller 150 can determine whether the data has been acquired or consumed by the consumer operation device 110.

[0071] At operation 360, based on determining that the request packet is in a servable state, the memory controller 150 can write the data and update the tag line. Refer to Figure 4 for a detailed description of an example of tags and tag lines according to an embodiment.

[0072] At operation 370, the memory controller 150 may determine whether a request packet is serviceable, which may indicate whether the request packet is in a serviceable state. For example, the memory controller 150 may determine whether the producer operation device 100 has produced or written data.

[0073] At operation 380, based on determining that the request packet is in a serviceable state, the memory controller 150 may read the data and update the tag line.

[0074] At operation 390, the memory controller 150 may send a response or acknowledgment (shown as "ACK") to indicate completion of the corresponding task.

[0075] Figure 4 is a block diagram of a memory controller according to an embodiment. Refer to Figures 1 to 3 The description provided may also be applied to Figure 4 .

[0076] Refer to Figure 4 , the memory controller 150 may include a queue arbiter 410, a request queue 420, a tag 430, a tag match update module 440 (which may be referred to as a tag updater), and a memory input / output (I / O) queue 450. However, the embodiment is not limited thereto. For example, in some embodiments, the memory controller 150 may be implemented by more or fewer components than Figure 4 those shown.

[0077] The queue arbiter 410 may determine the order of servicing requests input to the request queue 420 based on priorities. In some embodiments, tag lookups or memory accesses may include elements such as quality of service (QoS), read / write balance, timeout, and channels. Source IP information (e.g., at least one of IP block information related to the producer operation device 100 and IP block information related to the consumer operation device 110), shared memory information (e.g., shared buffer start address and shared buffer size offset), and operation order information may be added to the queue arbiter 410. The queue arbiter 410 may determine priority information corresponding to multiple request packets based on at least one of the source IP information, the shared memory information, and the operation order information. For example, the queue arbiter 410 may determine the priority information based on at least one of the producer operation device information, the consumer operation device information, and the address information corresponding to the shared buffer.

[0078] The request queue 420 can be used to store memory input / output (I / O) request groups that can be requested by multiple operating devices. In an embodiment, the request queue 420 can have a predetermined depth. The request queue 420 can be implemented as a single merged queue or separate queues (e.g., read / write queues or read / write / producer / consumer queues) as needed. The memory controller 150 can select a group to send a request to the tag 430 based on the request queue 420 and the queue arbiter 410.

[0079] The tag 430 can be a memory that contains tag information (e.g., static random access memory (SRAM), which can also be referred to as tag memory. The tag 430 can be similar to the tags used in a general cache. The tag 430 can include a tag line 431. The tag line 431 can be the information contained in the tag 430. Based on the request queue 420, the queue arbiter 410 can determine to perform a lookup operation for the group based on the address or hash using the tag 430. The tag line 431 read or otherwise obtained as a result of the lookup operation can be one tag line or multiple tag lines based on a set-associative structure.

[0080] In addition to the tag line information (e.g., address, valid, dirty, etc.) contained in a general cache, the tag line 431 can also include information indicating whether an operating device is serviceable. This information can be referred to as a service bit 432.

[0081] The tag match update module 440 can update the tag line (e.g., tag line 431) based on the read tag information, or can determine whether the memory controller 150 is operating according to cache access or dynamic RAM (DRAM) access. Based on the memory controller 150 being a cache controller, the memory controller 150 can operate according to cache access. Based on the memory controller 150 being a DRAM controller, the memory controller 150 can operate according to DRAM access.

[0082] The tag match update module 440 can update the tag line 431 based on the serviceability of the request group. The tag match update module 440 can update the tag line 431 based on determining that the request group is serviceable. For example, the tag match update module 440 can perform operations such as determining whether a consumer group can read data by checking the service bit status in the tag line 431. If the service bit indicates that the data is ready to be read by the consumer, the tag match update module 440 can update the tag line 431 and notify that the request group is serviceable. The tag match update module 440 can input the request group into the request queue based on determining that the request group is not serviceable.

[0083] When multiple consumer operating devices are provided (which may be referred to as the multi-consumer mode), the tag matching update module 440 can support the multi-consumer mode by updating the service bits of the tag line 431. For example, based on the producer operating device 100 communicating with five consumer operating devices 110 using multicast, the service bit can display or otherwise indicate the number five or "5". Thereafter, whenever a consumer operating device 110 accesses the address region, the tag matching update module 440 can decrement the service bit by one or "1". However, the methods for implementing and updating the service bits are not limited to the above example, and various methods can be employed.

[0084] Figure 5 is a diagram showing a method for sharing data between operating devices according to an embodiment. Refer to Figures 1 to 4 the description provided can also be applied to Figure 5 .

[0085] Refer to Figure 5 , the SoC 50 may include a producer operating device 500, consumer operating devices 510-1 to 510-N, a POS 520, a memory controller 550, and a shared memory 570. In some embodiments, the producer operating device 500 may correspond to the producer operating device 100, the consumer operating devices 510-1 to 510-N may correspond to the consumer operating devices 110, the POS 520 may correspond to the POS120, and the memory controller 550 may correspond to the memory controller 150, but the embodiments are not limited thereto.

[0086] The producer operating device 500 can generate a producer packet 530. The producer packet 530 can be mapped to the transaction size, DRAM access size, or cache line size supported by the shared memory 570.

[0087] The consumer operating device 510-1 can generate a consumer packet 540. The size of the consumer packet 540 can be the same as the size of the producer packet 530. Similarly, the consumer packet 540 can be mapped to the transaction size, DRAM access size, or cache line size supported by the shared memory 570.

[0088] The shared memory 570 can be a shared buffer. The shared memory 570 can be a memory space set by the host, and depending on the level of the POS point 520, can be a buffer based on virtual addresses or a buffer based on physical addresses. The production order and consumption order of the shared buffer can be synchronized with each other in units of the cache line size, transaction size, or DRAM access size of the interconnect to which the memory controller 550 is connected, and can be internally managed.

[0089] For example, a fine-grained partitioning of the transaction order between the producer operating device 500 and the consumer operating device 510-1 can allow minimizing the idle time of each IP block to achieve fast data sharing. However, due to the constraints imposed by the tag memory or memory region management of the memory controller 550, the size or configuration of the shared buffer may be limited.

[0090] The memory controller 550 can receive general transactions 560-1 to 560-3. In addition to the transaction of writing data into the shared memory 570 (e.g., the producer packet 530), the producer operating device 500 can also request the general transaction 560-1. In addition to the transaction involving reading data into the shared memory 570 (e.g., the consumer packet 540), the consumer operating device 510-1 can also request the general transaction 560-2. Operating devices other than the producer operating device 500 and the consumer operating device 510-1 (e.g., the consumer operating devices 510-2 to 510-N) can also request the general transaction 560-3.

[0091] When writing the producer packet 530 into the shared memory 570, the memory controller 550 can change the service bit included in the tag row corresponding to the producer packet 530 from a first value (e.g., zero or "0") to a second value (e.g., one or "1"). When receiving the consumer packet 540, the memory controller 550 can determine that the consumer packet 540 can be in a state capable of reading data when the service bit included in the tag row corresponding to the consumer packet 540 is the second value (e.g., one or "1"). When reading the consumer packet 540 from the shared memory 570, the memory controller 150 can change the service bit included in the tag row corresponding to the consumer packet 540 from the second value (e.g., one or "1") to the first value (e.g., zero or "0"). The memory controller 550 can use a tag matching update module (e.g., the tag matching update module 440) to perform such a change or update of the service bit.

[0092] According to Figure 5 the example shown, the shared memory 570 can include a space for storing 32 pieces of data in the range from data #0 to data #31. The producer operating device 500 can generate producer packets corresponding to data #0 to data #18, where data #0 to data #13 can have been written into the shared memory 570, while data #14 to data #18 can have not been written into the shared memory 570 yet.

[0093] When writing multiple pieces of data within the range of Data #0 to Data #13, the service bits of the multiple pieces of data can be changed from a first value (e.g., zero or "0") to a second value (e.g., one or "1"). Data #0 to Data #4 can be written to the shared memory 570 before being read by the consumer operating device 510-1. Accordingly, the service bits included in the tag row can be changed back from the second value (e.g., one or "1") to the first value (e.g., zero or "0"). Thus, in Figure 5 only Data #5 to Data #13 can include service bits having the second value (e.g., one or "1").

[0094] Figure 6 is a diagram showing the operation of a memory controller according to an embodiment. Referring to Figures 1 to 5 the description provided can also be applied to Figure 6 .

[0095] Referring to Figure 6 the memory controller 550 can operate as a DRAM controller. Figure 6 The operation of Figure 6 can be performed in the order and manner shown, but the embodiment is not limited thereto. For example, some operation orders can be changed, or some operations can be omitted without departing from the spirit and scope of the shown embodiment. In some embodiments, Figure 6 the operations shown can be performed in parallel or simultaneously.

[0096] The memory controller 550 can push traffic to a request queue (e.g., Figure 4 the request queue 420 of

[0097] at operation 610), and can pop the request queue at operation 615. In an embodiment, "popping" the queue can mean removing an element from the front of the queue (e.g., removing the oldest element in the queue).

[0098] At operation 620, the memory controller 550 can determine whether the request packet corresponds to a predetermined operating device. At operation 625, based on determining that the request packet corresponds to a predetermined operating device, the memory controller 550 can determine whether the address included in the request packet corresponds to a predetermined address.

[0099] For example, the memory controller 550 can determine whether a request packet is in a servicable state by determining whether the corresponding data has been acquired by the consumer operation device 510-1 when the producer operation device 500 performs a buffer write. As another example, the memory controller 550 can determine whether a request packet is in a servicable state by determining whether the producer operation device 500 has uploaded the corresponding data. When the request packet is in an unservicable state, the request packet can be put back into the request queue, and later, the determination of the servicability of the request packet can be re-performed.

[0100] At operation 640, based on determining that the request packet is in a servicable state, the memory controller 550 can update the tag. At operation 645, the cache controller can push the read / write queue. In some embodiments, at operation 645, based on determining that the address included in the request packet does not correspond to a predetermined address, the cache controller can push the read / write queue. At operation 650, the memory controller 550 can pop the read / write queue.

[0101] The memory controller 550 can provide a read / write service at operation 655, and can send a response or confirmation for indicating the completion of the corresponding task at operation 660.

[0102] Figure 7 is a diagram showing the operations of a memory controller according to an embodiment. Refer to Figures 1 to 5 the description provided can also be applied to Figure 7 .

[0103] Refer to Figure 7 , the memory controller 550 can operate as a cache controller. Figure 7 the operations of can be performed in the order and manner shown in Figure 7 , but the embodiments are not limited thereto. For example, without departing from the spirit and scope of the illustrated embodiments, the order of some operations can be changed, or some operations can be omitted. In some embodiments, Figure 7 the operations shown in can be performed in parallel or simultaneously.

[0104] The memory controller 550 can push traffic to a request queue (e.g., Figure 4 the request queue 420 of ) at operation 710, and can pop the request queue at operation 715.

[0105] At operation 720, the memory controller 550 can determine whether the request packet corresponds to a predetermined operation device. At operation 725, based on determining that the request packet corresponds to a predetermined operation device, the memory controller 550 can determine whether the address included in the request packet corresponds to a predetermined address.

[0106] At operation 730, based on determining that the address included in the request packet corresponds to a predetermined address, the memory controller 550 may look up or otherwise obtain the tag line corresponding to the request packet. At operation 735, based on the service bit included in the tag line, the memory controller 550 may determine whether the request packet is in a servicable state.

[0107] For example, similar to Figure 6 the memory controller 550 may determine whether the request packet is in a servicable state by determining whether the corresponding data has been acquired by the consumer operation device 510-1 when the producer operation device 500 performs a buffer write. As another example, the memory controller 550 may determine whether the request packet is in a servicable state by determining whether the producer operation device 500 has uploaded the corresponding data. When the request packet is in an unservicable state, the request packet may be put back into the request queue, and the determination of the servicability of the request packet may be re-made later.

[0108] At operation 740, based on determining that the request packet is in a servicable state, the memory controller 550 may update the tag. At operation 745, the memory controller 550 may push the read / write queue, and at operation 750, the DRAM controller may pop the read / write queue.

[0109] The memory controller 550 may provide a read / write service at operation 755 and may send a response or confirmation indicating the completion of the corresponding task at operation 760.

[0110] Figure 8 is a diagram showing a data congestion handling method according to an embodiment. Referring to Figures 1 to 7 the description provided may also be applied to Figure 8 .

[0111] Referring to Figure 8 , the SoC 80 may include a producer operation device 800, a consumer operation device 810, and a memory controller 850. In some embodiments, the producer operation device 800 may correspond to the producer operation device 100, the consumer operation device 810 may correspond to the consumer operation device 110, and the memory controller 850 may correspond to the memory controller 150, but the embodiments are not limited thereto.

[0112] Referring to Figure 8When data congestion is caused by the producer operating device 800 and / or the consumer operating device 810, the memory controller 850 can apply backpressure to the producer operating device 800 and / or the consumer operating device 810, and request the producer operating device 800 and / or the consumer operating device 810 to reduce the bandwidth.

[0113] For example, the first path 880 (e.g., the backpressure line) can be connected between the memory controller 850 and the producer operating device 800, and the second path 890 (e.g., the backpressure line) can be connected between the memory controller 850 and the consumer operating device 810.

[0114] The memory controller 850 can determine whether a data bandwidth mismatch occurs between the producer operating device 800 and the consumer operating device 810. For example, the memory controller 850 can determine whether a mismatch occurs by comparing the number of producer groups with the number of consumer groups.

[0115] Based on the fact that the producer operating device 800 generates data too fast, resulting in a full tag capacity (e.g., when the number of producer groups is greater than or equal to a predetermined number compared to the number of consumer groups), the memory controller 850 can apply backpressure to the producer operating device 800, and can accelerate the consumer consumption rate of the consumer operating device 810.

[0116] When the consumer operating device 810 consumes prematurely (e.g., when the number of consumer groups is greater than or equal to a predetermined number compared to the number of producer groups), the capacity of the outstanding request queue may be full, which reduces the performance of other IP blocks. Therefore, the memory controller 850 can apply backpressure to the consumer operating device 810, and can request the consumer operating device 810 to slow down the consumer consumption rate, and can prioritize the write transactions of the producer operating device 800.

[0117] Figure 9 is a flowchart showing a data sharing method according to an embodiment. Refer to Figures 1 to 8 The description provided can also be applied to Figure 9 .

[0118] For ease of description, operations 910 to 940 are described as being performed using Figure 1 the memory controller 150 shown. However, operations 910 to 940 can be performed by any suitable electronic device in any suitable system.

[0119] In addition, Figure 9 the operations of Figure 9be performed in the order and manner shown, but the embodiments are not limited thereto. For example, without departing from the spirit and scope of the embodiments shown, the order of some operations may be changed, or some operations may be omitted. In some embodiments, Figure 9 the operations shown may be performed in parallel or simultaneously.

[0120] At operation 910, the memory controller may determine whether the request packet corresponds to a predetermined operating device. The memory controller may include at least one of a DRAM controller and a cache controller.

[0121] At operation 920, the memory controller may determine whether the address included in the request packet corresponds to a predetermined address.

[0122] At operation 930, the memory controller may look up or otherwise obtain a tag line corresponding to the request packet.

[0123] At operation 940, the memory controller may determine whether the request packet is serviceable (e.g., in a serviceable state) based on the service bit included in the tag line. When the request packet is a consumer packet, the memory controller may determine that the service bit is in a state capable of reading data when the service bit has a second value. The memory controller may input the request packet into the request queue of the memory controller based on determining that the request packet is in an unserviceable state.

[0124] The memory controller may update the tag line based on determining that the request packet is in a serviceable state. When the request packet is a producer packet, the memory controller may update the service bit of the tag line from a first value to a second value. When the request packet is a consumer packet, the memory controller may update the service bit of the tag line from a second value to a first value.

[0125] Based on the number of producer packets being greater than or equal to a predetermined number compared to the number of consumer packets, the memory controller may request that the producer operating device corresponding to the producer packets reduce the bandwidth. Based on the number of consumer packets being greater than or equal to a predetermined number compared to the number of producer packets, the memory controller may request that the consumer operating device corresponding to the consumer packets reduce the bandwidth.

[0126] The embodiments described herein may be implemented using hardware components, software components, and / or a combination thereof. A processing device may be implemented using one or more general-purpose or special-purpose computers (e.g., processors, controllers, and arithmetic logic units (ALUs), digital signal processors (DSPs), microcomputers, field programmable gate arrays (FPGAs), programmable logic units (PLUs), microprocessors, or any other device capable of responding and executing instructions in a defined manner). The processing device may run an operating system (OS) and one or more software applications running on the OS. The processing device may also access, store, manipulate, process, and create data in response to the execution of software. For ease of understanding, the processing device is described in the singular; however, those skilled in the art will understand that the processing device may include multiple processing elements and multiple types of processing elements. For example, the processing device may include multiple processors or a processor and a controller. Additionally, different processing configurations are possible, such as parallel processors.

[0127] Software may include a computer program, a piece of code, instructions, or a combination thereof, to independently or collectively direct or configure the processing device to operate as desired. Software and data may be permanently or temporarily embodied in any type of machine, component, physical or virtual device, computer storage medium or device, or in a propagated signal wave capable of providing instructions or data to, or being interpreted by, the processing device. Software may also be distributed over network-coupled computer systems such that the software is stored and executed in a distributed manner. Software and data may be stored by one or more non-transitory computer-readable recording media.

[0128] The method according to the above example may be recorded in a non-transitory computer-readable storage medium including program instructions for implementing various operations of the above embodiments. The medium may also include data files, data structures, etc., either alone or in combination with the program instructions. The program instructions recorded on the medium may be program instructions specially designed and constructed for the purposes of the embodiments, or they may be of the kind well-known and available to those skilled in the computer software art. Examples of non-transitory computer-readable storage media include magnetic media (e.g., hard disks, floppy disks, and magnetic tapes); optical media (e.g., CD-ROM disks, DVDs, and / or Blu-ray disks); magneto-optical media (e.g., floppy optical disks); and hardware devices specially configured to store and execute program instructions (e.g., read-only memory (ROM), random access memory (RAM), flash memory, etc.). Examples of program instructions include machine code (e.g., generated by a compiler) and files containing high-level code that can be executed by a computer using an interpreter.

[0129] Although some embodiments have been described above with reference to the accompanying drawings, those of ordinary skill in the art can, without departing from the scope of the present disclosure, apply various technical modifications and variations thereto. Appropriate results can be achieved if the described techniques are performed in a different order and / or if the components in the described system, architecture, device, or circuit are combined in a different manner and / or replaced or supplemented by other components or their equivalents.

[0130] Accordingly, other embodiments, other examples, and equivalents of the claims are also within the scope of the present disclosure as defined by the appended claims.

Claims

1. A data sharing method for a memory controller in an environment including multiple operating devices, the data sharing method comprising: Determining whether a request packet corresponds to a predetermined operating device; Determining whether an address included in the request packet corresponds to a predetermined address; Obtaining a tag line corresponding to the request packet; and Determining whether the request packet is serviceable based on a service bit included in the tag line.

2. The data sharing method according to claim 1, wherein, The memory controller includes at least one of a dynamic random access memory (DRAM) controller and a cache controller.

3. The data sharing method according to claim 1, further comprising: Updating the tag line based on determining that the request packet is serviceable.

4. The data sharing method according to claim 3, wherein, Updating the tag line includes: updating the service bit of the tag line from a first value to a second value based on the request packet being a producer packet.

5. The data sharing method according to claim 3, wherein, Updating the tag line includes: updating the service bit of the tag line from the second value to the first value based on the request packet being a consumer packet.

6. The data sharing method according to claim 1, wherein, Determining whether the request packet is serviceable includes: determining that the consumer packet can read data based on the request packet being a consumer packet and the service bit being the second value.

7. The data sharing method according to claim 1, further comprising: Adding the request packet to a request queue of the memory controller based on determining that the request packet is not serviceable.

8. The data sharing method according to claim 1, further comprising: Requesting a producer operating device corresponding to a producer packet among the multiple producer packets to reduce bandwidth based on a number of multiple producer packets being greater than or equal to a predetermined number compared to a number of multiple consumer packets.

9. The data sharing method according to claim 1, further comprising: Requesting a consumer operating device corresponding to a consumer packet among the multiple consumer packets to reduce bandwidth based on a number of multiple consumer packets being greater than or equal to a predetermined number compared to a number of multiple producer packets.

10. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to: Determine whether a request packet corresponds to a predetermined operating device; Determine whether an address included in the request packet corresponds to a predetermined address; Obtain a tag line corresponding to the request packet; and Determine whether the request packet is serviceable based on a service bit included in the tag line.

11. A memory controller, comprising: A request queue configured to store multiple request packets; A queue arbiter configured to determine priority information corresponding to the multiple request packets based on at least one of producer operating device information, consumer operating device information, and address information corresponding to a shared buffer; And A tag memory configured to store a tag line including a service bit that indicates whether a request packet among the multiple request packets is serviceable.

12. The memory controller according to claim 11, wherein The memory controller includes at least one of a dynamic random access memory (DRAM) controller and a cache controller.

13. The memory controller according to claim 11, further comprising: A tag updater configured to: update the tag row based on determining that the request packet is servable.

14. The memory controller according to claim 13, wherein, The tag updater is further configured to: update the service bit of the tag row from a first value to a second value based on the request packet being a producer packet.

15. The memory controller according to claim 13, wherein, The tag updater is further configured to: update the service bit of the tag row from the second value to the first value based on the request packet being a consumer packet.

16. The memory controller according to claim 13, wherein, The tag updater is further configured to: determine that the consumer packet can read data based on the request packet being a consumer packet and the service bit being the second value.

17. The memory controller according to claim 13, wherein, The tag updater is further configured to: input the request packet into the request queue based on determining that the request packet is not servable.

18. The memory controller according to claim 11, wherein, Based on the number of multiple producer packets being greater than or equal to a predetermined number compared to the number of multiple consumer packets, the memory controller is further configured to: request that a producer operation device corresponding to a producer packet among the multiple producer packets reduce bandwidth.

19. The memory controller according to claim 11, wherein, Based on the number of multiple consumer packets being greater than or equal to a predetermined number compared to the number of multiple producer packets, the memory controller is further configured to: request that a consumer operation device corresponding to a consumer packet among the multiple consumer packets reduce bandwidth.

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