Inter-core communication method, device, equipment and storage medium for multi-core system on chip

Abstract

The embodiments of the present application disclose an inter-core communication method, apparatus, device and storage medium for a multi-core system-on-chip. In this method, by obtaining operating parameters of multiple dimensions of the multi-core system-on-chip when executing tasks to be processed, the actual situation of the multi-core system-on-chip can be judged more accurately, and a target interrupt generation strategy that meets the requirements of the current tasks to be processed can be dynamically and accurately determined to generate interrupts, thereby achieving the compatibility and flexibility of the multi-core system-on-chip when processing complex data interaction scenarios, thereby improving communication efficiency.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and more specifically, to a method, apparatus, device, and storage medium for inter-core communication in a multi-core system-on-chip. Background Art

[0002] As SoCs increase in size and complexity, multi-core SoCs (System on Chips) are becoming increasingly common. For example, baseband chips now include ARM (Advanced RISC Machine) processors and DSP (Digital Signal Processing) coprocessors. Even DSPs include scheduling and computational DSPs. However, due to the increasing input bandwidth and computational complexity of chips, a single processor cannot perform such large-scale calculations. Therefore, calculations are often broken down into multiple steps, with each processor responsible for a different step, to reduce the load on the single processor. However, the results of multi-core calculations must be synchronized at the end. For example, if two DSPs calculate A×A and B×B respectively and then add them together to produce the final result, if neither DSP knows whether the other has completed the calculation, the final result is likely to be incorrect. Therefore, inter-core communication to achieve multi-core synchronization is becoming increasingly important.

[0003] At present, when dealing with complex data interaction scenarios, related technologies usually achieve communication through a pre-set fixed interrupt generation mechanism. However, due to the single interrupt generation mechanism, it is easy to lead to insufficient compatibility and flexibility, making it difficult to adapt to diverse task requirements, resulting in poor communication efficiency of multi-core on-chip systems. Summary of the Invention

[0004] To solve the above technical problems, embodiments of the present application provide a method, apparatus, device, and storage medium for inter-core communication in a multi-core system-on-chip, so as to improve the communication efficiency of the multi-core system-on-chip.

[0005] According to one aspect of an embodiment of the present application, a method for inter-core communication of a multi-core system-on-chip is provided, comprising: obtaining operating parameters of the multi-core system-on-chip when executing a task to be processed; wherein the operating parameters include one or more of the current load condition, data transmission volume and real-time requirements of the multi-core system-on-chip; determining a target interrupt generation strategy based on the operating parameters; wherein the target interrupt generation strategy is used to instruct the first processor in the multi-core system-on-chip to trigger a preset interrupt controller to generate an interrupt when performing a write operation in a target address; when the write address corresponding to the task to be processed matches the target address, an interrupt is generated according to the target interrupt generation strategy, and the interrupt is sent to the second processor; wherein the first processor and the second processor are processors in the multi-core system-on-chip that collaboratively execute the task to be processed.

[0006] In some embodiments, the target interrupt generation strategy includes a first target interrupt generation strategy; determining the target interrupt generation strategy based on the operating parameters includes: when the current load condition is lower than a first preset load threshold, the data transmission volume is lower than a first preset data volume threshold, and the real-time requirement is lower than a first preset requirement threshold, determining that the target interrupt generation strategy is the first target interrupt generation strategy; wherein, the target address corresponding to the first target interrupt generation strategy is the address of a dedicated register, and when a write operation is performed on the address of the dedicated register, a preset interrupt controller is triggered to simultaneously generate multiple first type interrupts and send them to multiple second processors; the meaning of the first type interrupt is a fixed meaning.

[0007] In some embodiments, the target interrupt generation strategy includes a second target interrupt generation strategy; determining the target interrupt generation strategy based on the operating parameters includes: when the current load condition is not higher than a second preset load threshold, the data transmission volume is lower than a second preset data volume threshold, and the real-time requirement is higher than a second preset requirement threshold, determining that the target interrupt generation strategy is the second target interrupt generation strategy; wherein, the target address corresponding to the second target interrupt generation strategy is the address of the shared memory, and when a write operation is performed on the address of the shared memory, the preset interrupt controller is triggered to generate a second type of interrupt and send it to the second processor; the meaning of the second type of interrupt is a custom meaning.

[0008] In some embodiments, the target address includes multiple sub-queues, different sub-queues correspond to different task priorities, and the data storage area of each sub-queue is a circular buffer; the method also includes: obtaining the task priority corresponding to the task to be processed; caching the data to be transmitted corresponding to the task to be processed in the sub-queue corresponding to the task priority in the target address.

[0009] In some embodiments, when the write address corresponding to the task to be processed matches the target address, an interrupt is generated according to the target interrupt generation strategy, and the interrupt is sent to the second processor. The method also includes: clearing the interrupt after detecting that the second processor performs a read operation in the target address.

[0010] In some embodiments, the method further includes: acquiring an environmental state and task requirements of the multi-core system on chip; and adjusting interrupt control parameters of the interrupt controller according to the environmental state and task requirements.

[0011] In some embodiments, the bus of the multi-core system on chip is an AMBA bus, and the target interrupt generation policy is mounted on the AMBA bus.

[0012] According to one aspect of an embodiment of the present application, an inter-core communication device of a multi-core system-on-chip is provided, comprising: an acquisition module, a determination module and a sending module; wherein the acquisition module is configured to acquire operating parameters of the multi-core system-on-chip when executing a task to be processed; wherein the operating parameters include one or more of the current load condition, data transmission volume and real-time requirements of the multi-core system-on-chip; the determination module is configured to determine a target interrupt generation strategy based on the operating parameters; wherein the target interrupt generation strategy is used to instruct the first processor in the multi-core system-on-chip to trigger a preset interrupt controller to generate an interrupt when performing a write operation in a target address; the sending module is configured to generate an interrupt according to the target interrupt generation strategy when the write address corresponding to the task to be processed matches the target address, and send the interrupt to the second processor; wherein the first processor and the second processor are processors in the multi-core system-on-chip that collaboratively execute the task to be processed.

[0013] According to one aspect of an embodiment of the present application, an electronic device is provided, comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the inter-core communication method of the multi-core system on chip as described above.

[0014] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor of a computer, the computer executes the inter-core communication method of the multi-core system on chip as described above.

[0015] In the technical solution provided in the embodiments of the present application, by obtaining the operating parameters of multiple dimensions of the multi-core system-on-chip when executing the tasks to be processed, the actual situation of the multi-core system-on-chip can be judged more accurately, and the target interrupt generation strategy that meets the requirements of the current tasks to be processed can be dynamically and accurately determined to generate interrupts, thereby achieving the compatibility and flexibility of the multi-core system-on-chip when processing complex data interaction scenarios, thereby improving communication efficiency.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application and, together with the specification, serving to explain the principles of the present application. It is obvious that the drawings described below are merely some embodiments of the present application, and a person of ordinary skill in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0018] Figure 1 1 is a schematic diagram of an implementation environment involved in a multi-core system-on-chip inter-core communication method according to an exemplary embodiment of the present application;

[0019] Figure 2 is a flow chart of an inter-core communication method of a multi-core system on chip shown in an exemplary embodiment of the present application;

[0020] Figure 3 yes Figure 2 Step S220 in the illustrated embodiment is a flow chart of determining a target interrupt generation strategy based on operating parameters in an exemplary embodiment;

[0021] Figure 4 yes Figure 2 Step S220 in the illustrated embodiment is a flow chart of determining a target interrupt generation strategy based on operating parameters in another exemplary embodiment;

[0022] Figure 5 is a flow chart of an inter-core communication method of a multi-core system on chip shown in another exemplary embodiment of the present application;

[0023] Figure 6 This is a schematic diagram of an application of an inter-core communication method for a multi-core system-on-chip according to an exemplary embodiment of the present application;

[0024] Figure 7 is a flow chart of an inter-core communication method of a multi-core system on chip shown in another exemplary embodiment of the present application;

[0025] Figure 8is a schematic structural diagram of an inter-core communication device shown in an exemplary embodiment of the present application;

[0026] Figure 9 A schematic diagram of the structure of a computer system suitable for implementing an electronic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0027] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments applicable to the present application. Rather, they are merely examples of apparatus and methods applicable to certain aspects of the present application, as detailed in the appended claims.

[0028] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. In other words, these functional entities may be implemented in the form of an application program, in one or more hardware modules or integrated circuits, or in different models and / or processor devices and / or microcontroller devices.

[0029] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0030] It should be noted that the term "plurality" used in this application refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0031] To facilitate understanding of the inter-core communication method of the multi-core system on chip provided by the embodiment of the present application, the following is combined with Figure 1 The implementation environment shown in FIG2 is used to introduce the inter-core communication scenario; the implementation environment is specifically a multi-core system on chip, such as Figure 1 As shown, the multi-core system on chip includes a first processor 110 , a monitoring module 120 , a dedicated address register 130 , a shared memory 140 , an interrupt controller 150 and a second processor 160 .

[0032] The multi-core system-on-chip includes multiple processors, which may be ARM (Advanced RISC Machine) processors and DSP (Digital Signal Processor) processors. The processors in the multi-core system-on-chip can write or read data to or from a shared memory module or dedicated address registers via an AMBA bus. In some embodiments, the first processor 110 and the second processor 160 are DSP processors.

[0033] The monitoring module 120 is used to monitor the multi-core system on chip, thereby obtaining the operating parameters of the multi-core system on chip when executing the task to be processed, and determining the target interrupt generation strategy according to the operating parameters.

[0034] Dedicated address registers 130 are a collection of small, high-speed memory cells within a multi-core SoC for fast data access. Their core function is to provide zero-latency operand access for the processor. In some embodiments, the dedicated address registers are a regfile (register file), which can be an array of multiple registers, each identified by a unique address.

[0035] The shared memory 140 may be an SRAM (Static Random Access Memory). SRAM has the advantages of low latency, low power consumption, and high reliability, and is suitable for fast data exchange between cores in a multi-core processor.

[0036] The interrupt controller 150 may be one INTC (Interrupt Controller) or multiple INTCs.

[0037] In the case of one interrupt controller, different types of interrupts are generated by the interrupt controller based on different interrupt generation strategies.

[0038] In the case of multiple interrupt controllers, each interrupt controller corresponds to a target interrupt generation strategy. For example, a multi-core on-chip system is provided with two target interrupt generation strategies and two interrupt controllers. The first interrupt controller generates a first type of interrupt based on the first target interrupt generation strategy, and the second interrupt controller generates a second type of interrupt based on the second target interrupt generation strategy.

[0039] In some embodiments, the interrupt controller includes an interrupt mask register and an interrupt enable register corresponding to the interrupt, which can be set in the following ways: setting or clearing different bits of the interrupt mask register through software programming can selectively mask specific types of interrupts; and making corresponding settings on the interrupt enable register can turn on or off the interrupt function to achieve fine control of the interrupt.

[0040] For example, by sending the mask signal MASK[31:0] to the interrupt mask controller, the corresponding interrupt is controlled to be masked; by sending the enable signal EN[31:0] to the interrupt enable register, the corresponding interrupt source is controlled to be enabled, so that an interrupt can be generated; by sending the signal SET[31:0] to the set register, writing 1 will set the corresponding position to 1 to enable the interrupt; by sending the signal CLR[31:0] to the clear register, writing 1 will set the corresponding position to 0 to clear the interrupt.

[0041] Figure 1 The working principle of the multi-core system on chip shown is:

[0042] When the first processor 110 (CPU1) is the communication initiator, the monitoring module 120 is used to obtain the operating parameters of the multi-core system on chip when executing the task to be processed, and the target interrupt generation strategy is determined based on the operating parameters; wherein the target interrupt generation strategy includes a first target interrupt generation strategy and a second target interrupt generation strategy.

[0043] If the target interrupt generation strategy determined according to the operating parameters is the first target interrupt generation strategy, the data (interaction data) corresponding to the task to be processed is written into the target address corresponding to the first target interrupt generation strategy (that is, the address corresponding to the dedicated address register 130), and then the first processor 110 (CPU1) performs a write operation to cache the data corresponding to the task to be processed in the dedicated address register 130, and at the same time outputs an interrupt request signal to the interrupt controller 150 (INTC1), triggering the interrupt controller 150 (INTC1) to simultaneously generate multiple first-type interrupts (including irq1, irq2 and irq3), and at the same time send the multiple first-type interrupts to multiple second processors 160 (CPU3, CPU4 and CPU5); after receiving the first-type interrupt, the multiple second processors 160 read the corresponding data in the dedicated address register 130 according to the target address, and then clear the interrupt in the interrupt controller 150 (INTC1).

[0044] If the target interrupt generation strategy determined according to the operating parameters is the second target interrupt generation strategy, the data (interaction data) corresponding to the task to be processed is written into the target address corresponding to the second target interrupt generation strategy (i.e., the address corresponding to the shared memory 140), and then the first processor 110 (CPU1) performs a write operation to cache the data corresponding to the task to be processed into the shared memory 140, and at the same time outputs an interrupt request signal to the interrupt controller 150 (INTC2), triggering the interrupt controller 150 (INTC2) to generate a second type of interrupt and send it to the second processor 160 (CPU2); after receiving the second type of interrupt, the second processor 160 (CPU2) reads the corresponding data in the shared memory 140 according to the target address, and then clears the interrupt in the interrupt controller 150 (INTC2).

[0045] In addition, the bus of the multi-core system on chip is an AMBA bus, and the target interrupt generation strategy is mounted on the AMBA bus. By mounting the target interrupt generation strategy on an AMBA (Advanced Microcontroller Bus Architecture, advanced microprocessor bus architecture) bus such as AHB or AXI, the compatibility and scalability are stronger, and it can be adapted to the vast majority of commercial processors, mounted on any bus interface, and support communication between any processors. After actual testing, it can run stably in a system composed of a variety of processors with different architectures, and the communication success rate is more than 99%. The inter-core communication method in the multi-core system on chip in the embodiment of the present application is highly scalable. When the number of processors in the SoC is increased, it only needs to add a set of inter-core communication devices to adapt, and there is no need to make large-scale changes to the original architecture.

[0046] The inter-core communication method of the multi-core system on chip provided by the embodiment of the present application is described in detail below.

[0047] Please continue reading Figure 2 , Figure 2 This is a flow chart of an inter-core communication method of a multi-core system on chip shown in an exemplary embodiment of the present application. This method can be applied to Figure 1 The embodiment shown in FIG. 1 is implemented in the embodiment shown in FIG. 1 and is specifically executed by a multi-core system-on-chip in the embodiment shown in FIG. 1 . It should be understood that the method may also be applicable to other exemplary implementation environments and be specifically executed by a multi-core system-on-chip in other implementation environments, and this embodiment does not limit the implementation environment to which the method is applicable.

[0048] like Figure 2 As shown, in an exemplary embodiment, the inter-core communication method of the multi-core system-on-chip includes at least steps S210 to S230, which are described in detail as follows:

[0049] Step S210 , obtaining operating parameters of the multi-core system on chip when executing the task to be processed.

[0050] It is important to understand that, because related technologies can only achieve inter-core communication through a single, pre-set interrupt generation mechanism, this can easily lead to insufficient compatibility and flexibility when handling complex data interaction scenarios, making it difficult to adapt to diverse task requirements and unable to optimize selections based on actual conditions, resulting in low communication efficiency. However, the operating parameters of the multi-core system-on-chip in this application can simultaneously include multi-dimensional influencing factors such as current load conditions, data transmission volume, and real-time requirements. It can take both task requirements and system processing capabilities into account, and thus determine a target interrupt generation strategy that meets both task requirements and is within the system processing capabilities.

[0051] In some embodiments, a monitoring module is provided in the multi-core system-on-chip, and the monitoring module is used to monitor the multi-core system-on-chip to obtain operating parameters of the multi-core system-on-chip. In some embodiments, the operating parameters include the current load of the multi-core system-on-chip, data transmission volume, and real-time requirements.

[0052] Step S220: determining a target interrupt generation strategy according to the operating parameters.

[0053] It can be understood that this application obtains the operating parameters of the multi-core on-chip system when executing the task to be processed. Since the operating parameters may include multi-dimensional influencing factors such as the current load of the multi-core on-chip system, data transmission volume and real-time requirements, it can simultaneously consider the influencing factors of task requirements and system processing capabilities, thereby improving the accuracy of the target interrupt generation strategy, so that the determined target interrupt generation strategy not only meets the task requirements but is also within the system processing capabilities, thereby further improving communication efficiency.

[0054] In an embodiment of the present application, a target interrupt generation policy is used to instruct the first processor in a multi-core system-on-chip to trigger a preset interrupt controller to generate an interrupt when performing a write operation at a target address. An interrupt is an event-handling mechanism in a computer system. Its core function is to allow the CPU to pause its current task to handle a more urgent or high-priority task, and then resume execution of the original task after the task is completed. The target interrupt generation policy manages interrupt triggering, priority assignment, and processing flow, thereby achieving a balance between limited resources and real-time requirements.

[0055] In some embodiments, combined Figure 3 As shown, Figure 3 yes Figure 2 Step S220 in the illustrated embodiment is a flow chart of determining a target interrupt generation strategy according to operating parameters in an exemplary embodiment; it includes at least steps S310 to S330, which are described in detail as follows:

[0056] Step S310, comparing the operating parameters with corresponding thresholds to obtain comparison results;

[0057] In embodiments of the present application, operating parameters include current load, data transfer volume, and real-time requirements. In some embodiments, each operating parameter corresponds to at least one threshold value. By comparing different operating parameters with their corresponding threshold values, the current actual state of the multi-core system-on-chip (i.e., system operating conditions and task requirements) can be determined, thereby facilitating more accurately determining a target interruption strategy that meets the current actual conditions.

[0058] For example, the threshold corresponding to the current load condition includes a first preset load threshold and a second preset load threshold, wherein the first preset load threshold is greater than the second preset load requirement threshold.

[0059] The threshold corresponding to the data transmission volume includes a first preset data volume threshold and a second preset data volume threshold, wherein the first preset data volume threshold is greater than the second preset data volume threshold.

[0060] The threshold corresponding to the low real-time requirement includes a first preset requirement threshold and a second preset requirement threshold, wherein the first preset requirement threshold is greater than the second preset requirement threshold.

[0061] Step S320, if the comparison result shows that the current load condition is lower than the first preset load threshold, the data transmission volume is lower than the first preset data volume threshold, and the real-time requirement is lower than the first preset requirement threshold, determining the target interrupt generation strategy to be the first target interrupt generation strategy;

[0062] In an embodiment of the present application, the target address corresponding to the first target interrupt generation strategy is the address of a dedicated register. When a write operation is performed on the address of the dedicated register, the preset interrupt controller is triggered to simultaneously generate multiple first-type interrupts and send them to multiple second processors; the meaning of the first-type interrupt is a fixed meaning.

[0063] For example, when the current load is lower than a first preset load threshold, it can be considered that the CPU resources required for the pending task are relatively low; when the data transmission volume is lower than a first preset data volume threshold, it can be considered that the data transmission volume is not too high; and when the real-time requirement is lower than a first preset requirement threshold, it can be considered that the real-time requirement is not high. Taking all operating parameters into consideration, the resources required to execute the pending task are relatively low, the data transmission volume is not large, and the real-time requirement is not high. In this case, by adopting the first target interrupt generation strategy, multiple interrupts can be generated simultaneously and sent to multiple second processors, achieving compatibility with shared memory and the most basic interrupt notification.

[0064] Step S330, when the comparison result shows that the current load situation is not higher than the second preset load threshold, the data transmission volume is lower than the second preset data volume threshold, and the real-time requirement is higher than the second preset requirement threshold, determine that the target interrupt generation strategy is the second target interrupt generation strategy.

[0065] In an embodiment of the present application, the target address corresponding to the second target interrupt generation strategy is the address of the shared memory. When a write operation is performed on the address of the shared memory, the preset interrupt controller is triggered to generate a second type of interrupt and send it to the second processor; the meaning of the second type of interrupt is a custom meaning.

[0066] For example, when the current load situation is not higher than the second preset load threshold, it can be considered that the CPU resource occupancy required for the task to be processed is high; when the data transmission volume is lower than the second preset data volume threshold, it can be considered that the data transmission volume of the task to be processed is small, or no data transmission is required; when the real-time requirement is higher than the second preset requirement threshold, it can be considered that the real-time requirement is high. Considering all the operating parameters, the resources required to execute the task to be processed are high, the data transmission volume is small, and the real-time requirement is high. In this case, by adopting the second target interrupt generation strategy, the meaning of the second type of interrupt can be customized in advance, so as to adapt to a variety of different scenarios and improve real-time performance. In addition, since the second target interrupt generation strategy is based on writing to shared memory to directly generate the second type of interrupt, and data can be directly transmitted through the second type of interrupt, data and notification can be combined into one operation, that is, the interrupt is triggered directly by writing to shared memory, and data is transmitted at the same time, which can further improve real-time performance.

[0067] In some embodiments, the present invention can flexibly support the amount of data carried by messages during inter-core communication, thereby being compatible with simple or complex multi-core synchronization tasks. For example, in graphics rendering tasks, a first-target interrupt generation strategy can be used to efficiently handle large amounts of texture data transfers; in real-time control tasks, a second-target interrupt generation strategy can be used to accurately transmit small amounts of critical instruction data.

[0068] In some embodiments, combined Figure 4 As shown, Figure 4 yes Figure 2 Step S220 in the illustrated embodiment is a flow chart of determining a target interrupt generation strategy according to operating parameters in another exemplary embodiment; the flow chart includes at least steps S410 to S420, which are described in detail as follows:

[0069] Step S410: Obtain a current measurement score corresponding to the multi-core system on chip according to the operating parameters.

[0070] In the embodiment of the present application, the current measurement score corresponding to the multi-core system-on-chip includes the sum of the scores corresponding to all operating parameters.

[0071] In some embodiments, the current measurement score corresponding to the multi-core system on chip can be obtained by: obtaining weight values corresponding to operating parameters; performing weighted summation on the operating parameters according to the weight values to obtain the current measurement score corresponding to the multi-core system on chip.

[0072] It is understood that different types of operating parameters can correspond to different weight ranges, and operating parameters of different sizes can correspond to different weight values. For example, operating parameters include current load, data transmission volume, and real-time requirements. The weight range for current load is 0.3-0.5, and the greater the current load, the greater the corresponding weight value; the weight range for data transmission volume is 0.2-0.4, and the greater the data transmission volume, the greater the corresponding weight value; the weight range for real-time requirements is 0.3-0.6, and the higher the real-time requirement, the greater the corresponding weight value.

[0073] The current load refers to the CPU utilization, which ranges from 0% to 100%.

[0074] Current load situation = current load / maximum load threshold × 100%.

[0075] In some embodiments, the maximum load threshold is less than 100%, for example, 90%. For example, if the load is 80% and the maximum load threshold is 90%, then the current load condition = 80 / 90×100%≈88.9%

[0076] Data transmission volume can refer to bandwidth utilization, which ranges from 0% to 100%.

[0077] Data transmission volume = current transmission volume / maximum bandwidth × 100%.

[0078] In some embodiments, the current transmission volume is 600 MB / s and the maximum bandwidth is 1 GB / s, so the data transmission volume is 60%.

[0079] The real-time requirement may refer to the deadline hit rate of pending tasks (ie, the probability that a pending task is completed within the deadline).

[0080] In some embodiments, if the deadline hit rate is within 90%-100%, the real-time requirement is considered high; if the deadline hit rate is within 50%-90%, the real-time requirement is considered medium; if the deadline hit rate is within 0%-50%, the real-time requirement is considered low.

[0081] In some embodiments, obtaining the current measurement score corresponding to the multi-core system-on-chip according to the operating parameters includes: calculating Get the current measurement score corresponding to the multi-core system on chip; where, is the current measurement score corresponding to the multi-core system-on-chip, is the current load condition, is the weight corresponding to the current load condition, is the data transmission volume, is the weight corresponding to the data transmission volume, For real-time requirements, The corresponding weights are calculated for real-time requirements. By obtaining the corresponding weight parameters and performing a weighted summation on each operating parameter, multi-scenario adaptation can be supported, and the weight parameters can be dynamically adjusted, thereby improving reliability and facilitating the determination of a more accurate target interruption generation strategy.

[0082] Step S420: Determine a target interruption generation strategy based on the current measurement score.

[0083] It is understandable that in the embodiment of the present application, a score threshold may be set, the current measurement score may be compared with the score threshold, and different target interruption generation strategies may be determined according to different comparison results.

[0084] In some embodiments, the target interrupt generation strategy includes a first target interrupt generation strategy and a second target interrupt generation strategy. The target address corresponding to the first target interrupt generation strategy is the address of a dedicated register. When a write operation is performed on the address of the dedicated register, a preset interrupt controller is triggered to simultaneously generate multiple first-type interrupts and send them to multiple second processors. The meaning of the first-type interrupt is a fixed meaning. The target address corresponding to the second target interrupt generation strategy is the address of a shared memory. When a write operation is performed on the address of the shared memory, a preset interrupt controller is triggered to generate a second-type interrupt and send it to the second processor. The meaning of the second-type interrupt is a custom meaning.

[0085] Exemplarily, in an embodiment of the present application, the target interruption generation strategy can be determined based on the current measurement score in the following manner, including: comparing the current measurement score with a preset score threshold; if the current measurement score is less than the preset score threshold, determining that the target interruption generation strategy is the first target interruption generation strategy; if the current measurement score is greater than the preset score threshold, determining that the target interruption generation strategy is the second target interruption generation strategy.

[0086] In some embodiments, the score threshold may also be dynamically adjusted according to different task scenarios, thereby improving the compatibility and stability of the multi-core system-on-chip.

[0087] In an embodiment of the present application, the target interrupt generation strategy may be determined based on the operating parameters by matching the target interrupt generation strategy corresponding to the operating parameters from a preset database, wherein the preset database stores the correspondence between the operating parameters and the target interrupt generation strategy.

[0088] Step S230 : When the write address corresponding to the task to be processed matches the target address, an interrupt is generated according to the target interrupt generation strategy, and the interrupt is sent to the second processor.

[0089] The first processor and the second processor are processors in a multi-core system-on-chip that collaboratively execute tasks to be processed.

[0090] In an embodiment of the present application, by obtaining operating parameters of multiple dimensions of the multi-core system-on-chip when executing tasks to be processed, the actual situation of the multi-core system-on-chip can be judged more accurately, and a target interrupt generation strategy that meets the requirements of the current tasks to be processed can be dynamically and accurately determined to generate interrupts, thereby achieving the compatibility and flexibility of the multi-core system-on-chip when processing complex data interaction scenarios, thereby improving communication efficiency.

[0091] Please continue reading Figure 5 In an exemplary embodiment, when the write address corresponding to the task to be processed matches the target address, the inter-core communication method of the multi-core system-on-chip further includes at least steps S510 to S520, which are described in detail as follows:

[0092] Step S510: Obtain the task priority corresponding to the task to be processed.

[0093] It should be understood that the target address in the embodiments of the present application is the address at which a write operation is performed, such as the address of a dedicated address register or the address of shared memory. This target address includes multiple subqueues, each of which corresponds to a different task priority. The data storage area of each subqueue is a ring buffer. By organizing the data storage area of each subqueue as a ring buffer, each subqueue has a fixed-size memory area for efficiently storing and managing messages or data. The ring buffer avoids frequent memory allocation and deallocation by circularly utilizing memory space, thereby improving data transmission efficiency.

[0094] In some embodiments, a fixed-size memory is pre-allocated to the data area of each sub-queue for storing messages or data. The sender writes the data to the tail of the queue in sequence, and when it reaches the end of the memory, it automatically returns to the beginning of the queue to continue writing. The receiver reads the data from the head of the queue, and when it reaches the end, it automatically returns to the beginning to continue reading. Since the data in the ring buffer is written and read in a circular manner, no memory gaps will be generated, so the ring buffer can avoid memory fragmentation problems. At the same time, the size of the ring buffer is dynamically adjusted according to actual needs, and a maximum of 1024 data items can be cached to avoid data overflow or blocking, thereby ensuring the reliability of data processing. In addition, the data cached in each sub-queue is managed using the first-in-first-out principle to avoid data loss. In this way, by setting up a cache mechanism, when the system is busy and cannot process messages in time, the messages can be temporarily stored in the cache area.

[0095] Step S520 , buffering the data to be transmitted corresponding to the task to be processed in a subqueue corresponding to the task priority at the target address.

[0096] In the embodiment of the present application, by storing data according to task priority, data can be automatically classified and prioritized according to data type and urgency, giving priority to high-priority data to ensure timely response to critical tasks. At the same time, by setting up a caching mechanism, message loss is avoided when the system is busy, thereby improving data processing reliability.

[0097] Exemplarily, the storage area in the target address may include multiple sub-queues; for example, divided into three sub-queues: a high priority queue, a medium priority queue, and a low priority queue. Data is stored in the corresponding sub-queue according to task priority, and the data in each sub-queue is arranged in a first-in-first-out order; when processing data, the data in the high priority queue is processed first, then the data in the medium priority queue, and finally the data in the low priority queue.

[0098] Please continue reading Figure 6 , Figure 6 This is a schematic diagram of an application of an inter-core communication method of a multi-core system-on-chip shown in an exemplary embodiment of the present application.

[0099] Step S601: The first processor writes first shared data into the memory address A in the shared memory. First, the first processor writes the first shared data to be transferred to the second processor into the memory address A in the shared memory.

[0100] In step S602, the first processor writes to the ring buffer and generates a request interrupt. In this embodiment of the present application, after writing the first shared data, the first processor performs a write operation in the ring buffer and generates a request interrupt cached at a target address, triggering the interrupt controller to generate a first interrupt and send it to the second processor. The target address is the address corresponding to the first target interrupt generation policy or the address corresponding to the second target interrupt generation policy.

[0101] Step S603: The second processor receives a first interruption, which carries a pointer address A, namely, a memory address A.

[0102] Step S604: read the first shared data in the shared memory according to the pointer address A.

[0103] Step S605: The second processor reads the ring buffer and clears the request interrupt. In the embodiment of the present application, after reading the first shared data, the second processor performs a read operation in the ring buffer and clears the request interrupt, thereby achieving one-way synchronization.

[0104] Step S606: The second processor writes the second shared data into the memory address B in the shared memory. The second processor then writes the second shared data to be transferred to the first processor into the memory address B in the shared memory.

[0105] In step S607, the second processor writes to the ring buffer and generates a request interrupt. In this embodiment of the present application, after writing the second shared data, the second processor performs a write operation in the ring buffer, and then generates a request interrupt cached in the target address, triggering the interrupt controller to generate a second interrupt and send it to the first processor.

[0106] Step S608: The first processor receives a second interrupt; the second interrupt carries a pointer address B, ie, a memory address B.

[0107] Step S609: Read the second shared data in the shared memory according to the pointer address B.

[0108] Step S610: The first processor reads the ring buffer and clears the request interrupt. In the embodiment of the present application, after reading the second shared data, the first processor performs a read operation in the ring buffer and clears the request interrupt, thereby achieving bidirectional synchronization.

[0109] In an embodiment of the present application, by generating interrupts according to corresponding interrupt generation strategies, communication efficiency can be improved. Moreover, by setting up a ring buffer to store messages, when the system is busy and cannot process messages in time, the messages can be temporarily stored in the cache. The cache is managed using the first-in-first-out principle to avoid message loss.

[0110] In some embodiments, when the write address corresponding to the task to be processed matches the target address, an interrupt is generated according to the target interrupt generation policy, and after the interrupt is sent to the second processor, the method further includes: clearing the interrupt after detecting that the second processor performs a read operation at the target address. In this way, when the second processor is detected to perform a read operation at the target address, it is assumed that the second processor has obtained the data that the first processor wants to share from the shared memory. At this time, by clearing the interrupt, the interrupt controller is notified that the interrupt has been processed, preventing repeated processing of the interrupt. By clearing the interrupt status, the interrupt controller is placed in a state of waiting for the next interrupt event, ensuring that the system can respond to subsequent interrupt requests in a timely manner, maintaining the system's real-time performance and responsiveness.

[0111] Combine Figure 7 As shown, in an exemplary embodiment, the inter-core communication method of the multi-core system-on-chip further includes steps S710 to S720, which are described in detail as follows:

[0112] Step S710: Obtain the environment status and task requirements of the multi-core system on chip.

[0113] In the embodiments of the present application, the environmental status may include resource status, power status, and bus bandwidth; the task requirements may include data transmission volume, communication mode, urgency, task deadline, and task priority. By obtaining parameters of multiple dimensions, it is easier to adjust the interrupt control parameters more accurately, thereby achieving a more accurate determination of the target interrupt generation strategy.

[0114] Resource status refers to load distribution, namely the real-time utilization of each core, as well as cache and memory pressure, such as miss rate and memory bandwidth utilization. Power status refers to whether the CPU core is in sleep or overclocked mode. Bus bandwidth refers to the remaining available bus bandwidth and conflict probability.

[0115] Data transmission rate can be the number of messages per unit time (e.g., a network packet rate of 10Gbps) or the data block size (e.g., 4KB / message). Communication mode can be unicast (point-to-point) or broadcast (one-to-many).

[0116] Step S720: Adjust the interrupt control parameters of the interrupt controller according to the environmental status and task requirements.

[0117] In the embodiment of the present application, by dynamically adjusting the interrupt control parameters of the interrupt controller according to the environmental status and task requirements, the target interrupt generation strategy can be determined more accurately, thereby achieving higher performance and resource utilization.

[0118] In some embodiments, interrupt control parameters include interrupt distribution parameters and interrupt processing parameters. Interrupt distribution parameters include priority (dynamically adjusting the response order of interrupts), affinity (binding interrupts to specific processors), and trigger mode (i.e., selecting edge triggering or level triggering); interrupt processing parameters include queue depth (adjusting the size of the circular buffer of the request interrupt queue), masking (temporarily disabling non-critical interrupts), and timeout threshold (adjusting the maximum allowed time for interrupt processing).

[0119] Exemplarily, adjusting an interrupt control parameter of an interrupt controller based on environmental conditions and task requirements includes: matching parameter adjustment values corresponding to both the environmental conditions and the task requirements from a preset database; and adjusting the interrupt control parameter accordingly based on the parameter adjustment values. The preset database stores correspondences between environmental conditions, task requirements, and parameter adjustment values.

[0120] Combine Figure 8 As shown, Figure 8 FIG. 1 is a structural diagram of an inter-core communication device shown in an exemplary embodiment of the present application. Figure 8 As shown, the exemplary inter-core communication device includes: an acquisition module 810, a determination module 820, and a sending module 830. The acquisition module 810 is configured to acquire the operating parameters of the multi-core system-on-chip when executing the task to be processed; wherein the operating parameters include one or more of the current load condition, data transmission volume, and real-time requirements of the multi-core system-on-chip; the determination module 820 is configured to determine the target interrupt generation strategy based on the operating parameters; wherein the target interrupt generation strategy is used to instruct the first processor in the multi-core system-on-chip to trigger a preset interrupt controller to generate an interrupt when performing a write operation in the target address; the sending module 830 is configured to generate an interrupt according to the target interrupt generation strategy when the write address corresponding to the task to be processed matches the target address, and send the interrupt to the second processor; wherein the first processor and the second processor are processors in the multi-core system-on-chip that collaboratively execute the task to be processed.

[0121] In an embodiment of the present application, by adopting this exemplary inter-core communication device, by obtaining the operating parameters of multiple dimensions of the multi-core system-on-chip when executing the tasks to be processed, the actual situation of the multi-core system-on-chip can be judged more accurately, and the target interrupt generation strategy that meets the requirements of the current tasks to be processed can be dynamically and accurately determined to generate interrupts, thereby achieving the compatibility and flexibility of the multi-core system-on-chip when processing complex data interaction scenarios, thereby improving communication efficiency.

[0122] In another exemplary embodiment, the target interrupt generation strategy includes a first target interrupt generation strategy; the determination module 820 is configured to determine the target interrupt generation strategy according to the operating parameters in the following manner: when the current load condition is lower than a first preset load threshold, the data transmission volume is lower than a first preset data volume threshold, and the real-time requirement is lower than a first preset requirement threshold, determine that the target interrupt generation strategy is the first target interrupt generation strategy;

[0123] Among them, the target address corresponding to the first target interrupt generation strategy is the address of the dedicated register. When a write operation is performed on the address of the dedicated register, the preset interrupt controller is triggered to simultaneously generate multiple first type interrupts and send them to multiple second processors; the meaning of the first type interrupt is a fixed meaning.

[0124] In another exemplary embodiment, the target interrupt generation strategy includes a second target interrupt generation strategy; the determination module 820 is configured to determine the target interrupt generation strategy according to the operating parameters in the following manner: determining the target interrupt generation strategy according to the operating parameters includes: when the current load condition is not higher than a second preset load threshold, the data transmission volume is lower than a second preset data volume threshold, and the real-time requirement is higher than a second preset requirement threshold, determining the target interrupt generation strategy to be the second target interrupt generation strategy;

[0125] Among them, the target address corresponding to the second target interrupt generation strategy is the address of the shared memory. When a write operation is performed on the address of the shared memory, the preset interrupt controller is triggered to generate a second type of interrupt and send it to the second processor; the meaning of the second type of interrupt is a custom meaning.

[0126] In another exemplary embodiment, the inter-core communication device also includes a cache module, the target address includes multiple sub-queues, different sub-queues correspond to different task priorities, and the data storage area of each sub-queue is a ring buffer; the cache module is configured to obtain the task priority corresponding to the task to be processed in the following manner; the data to be transmitted corresponding to the task to be processed is cached in the sub-queue corresponding to the task priority in the target address.

[0127] In another exemplary embodiment, when the write address corresponding to the task to be processed matches the target address, an interrupt is generated according to the target interrupt generation strategy, and the interrupt is sent to the second processor. The sending module 830 is also configured to clear the interrupt after detecting that the second processor performs a read operation in the target address.

[0128] In another exemplary embodiment, the inter-core communication device further includes an adjustment module, which is configured to obtain the environmental status and task requirements of the multi-core system on chip; and adjust the interrupt control parameters of the interrupt controller according to the environmental status and task requirements.

[0129] In another exemplary embodiment, the bus of the multi-core system on chip is an AMBA bus, and the target interrupt generation policy is mounted on the AMBA bus.

[0130] It should be noted that the inter-core communication device provided in the above embodiment and the inter-core communication method for a multi-core system-on-chip provided in the above embodiment are based on the same concept. The specific manner in which each module and unit performs operations has been described in detail in the method embodiments and will not be repeated here. In actual applications, the inter-core communication device provided in the above embodiment can, as needed, allocate the above functions to different functional modules, i.e., divide the internal structure of the device into different functional modules to perform all or part of the functions described above. This is not a limitation herein.

[0131] An embodiment of the present application also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the inter-core communication method of the multi-core system-on-chip provided in each of the above embodiments.

[0132] Figure 9 The following is a schematic diagram showing the structure of a computer system suitable for implementing an electronic device according to an embodiment of the present application. Figure 9 The computer system 900 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0133] like Figure 9 As shown, computer system 900 includes a central processing unit (CPU) 901, which can perform various appropriate actions and processes, such as the methods described in the above embodiments, based on programs stored in read-only memory (ROM) 902 or programs loaded from storage 908 into random access memory (RAM) 903. RAM 903 also stores various programs and data required for system operation. CPU 901, ROM 902, and RAM 903 are interconnected via a bus 904. An input / output (I / O) interface 905 is also connected to bus 904.

[0134] The following components are connected to the I / O interface 905: an input section 906 including a keyboard, a mouse, and the like; an output section 907 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and speakers; a storage section 908 including devices such as a hard disk; and a communication section 909 including a module interface card such as a LAN (Local Area Network) card or a modem. The communication section 909 performs communication processing via a module such as the Internet. A drive 910 is also connected to the I / O interface 905 as needed. Removable media 911, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 910 as needed, so that computer programs read from the removable media can be installed in the storage section 908 as needed.

[0135] In particular, according to embodiments of the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program including a computer program for executing the methods illustrated in the flowcharts. In such embodiments, the computer program can be downloaded and installed from the model via the communication section 909 and / or installed from removable media 911. When the computer program is executed by the central processing unit (CPU) 901, the various functions defined in the system of the present application are performed.

[0136] It should be noted that the computer-readable medium described in the embodiments of this application may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may, for example, be an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying a computer-readable computer program. This propagated data signal may take a variety of forms, including, but not limited to, an electromagnetic signal, an optical signal, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. A computer program embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0137] Another aspect of the present application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the aforementioned inter-core communication method for a multi-core system-on-chip. The computer-readable storage medium may be included in the electronic device described in the above embodiments, or may exist independently and not be incorporated into the electronic device.

[0138] Another aspect of the present application provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the inter-core communication method of the multi-core system-on-chip provided in each of the above embodiments.

[0139] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation scheme of the present application. Ordinary technicians in this field can easily make corresponding changes or modifications based on the main ideas and spirit of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection required by the claims.

[0140] It should be noted that when the embodiments of the present application are applied to specific products or technologies, such as when obtaining sample data, it is inevitable to obtain the operating parameters of the multi-core system-on-chip. In this case, it is necessary to obtain the permission or consent of the relevant objects, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

Claims

1. A method for inter-core communication in a multi-core system-on-chip, characterized in that: include: Obtaining operating parameters of the multi-core system-on-chip when executing the task to be processed; wherein the operating parameters include the current load, data transmission volume and real-time requirements of the multi-core system-on-chip; Determining a target interrupt generation strategy based on the operating parameters; wherein the target interrupt generation strategy is used to instruct the first processor in the multi-core system-on-chip to trigger a preset interrupt controller to generate an interrupt when performing a write operation in the target address; the target interrupt generation strategy includes a first target interrupt generation strategy and a second target interrupt generation strategy; The target address corresponding to the first target interrupt generation strategy is the address of a dedicated register. When a write operation is performed on the address of the dedicated register, a preset interrupt controller is triggered to simultaneously generate multiple first-type interrupts and send them to multiple second processors. The meaning of the first-type interrupt is a fixed meaning. The target address corresponding to the second target interrupt generation strategy is the address of the shared memory, and when a write operation is performed on the address of the shared memory, a preset interrupt controller is triggered to generate a second type of interrupt and send it to the second processor; the meaning of the second type of interrupt is a custom meaning; When the write address corresponding to the task to be processed matches the target address, an interrupt is generated according to the target interrupt generation policy, and the interrupt is sent to the second processor; wherein the first processor and the second processor are processors in the multi-core system-on-chip that collaboratively execute the task to be processed; Determining a target interrupt generation strategy according to the operating parameters includes: Comparing the operating parameters with corresponding thresholds to obtain comparison results; If the comparison result shows that the current load condition is lower than a first preset load threshold, the data transmission volume is lower than a first preset data volume threshold, and the real-time requirement is lower than a first preset requirement threshold, determining that the target interrupt generation strategy is a first target interrupt generation strategy; When the comparison result is that the current load situation is not higher than the second preset load threshold, the data transmission volume is lower than the second preset data volume threshold, and the real-time requirement is higher than the second preset requirement threshold, the target interrupt generation strategy is determined to be the second target interrupt generation strategy.

2. The method according to claim 1, characterized in that The target address includes multiple sub-queues, different sub-queues correspond to different task priorities, and the data storage area of each sub-queue is a ring buffer; the method further includes: Obtaining the task priority corresponding to the pending task; The data to be transmitted corresponding to the task to be processed is cached in a subqueue corresponding to the task priority at the target address.

3. The method according to claim 1, characterized in that After generating an interrupt according to the target interrupt generation policy when the write address corresponding to the task to be processed matches the target address and sending the interrupt to the second processor, the method further includes: After detecting that the second processor performs a read operation at the target address, the interrupt is cleared.

4. The method according to claim 1, wherein The method further comprises: Obtaining the environmental status and task requirements of the multi-core system-on-chip; The interrupt control parameters of the interrupt controller are adjusted according to the environmental status and task requirements.

5. The method according to claim 1, wherein The bus of the multi-core system on chip is an AMBA bus, and the target interrupt generation strategy is mounted on the AMBA bus.

6. An inter-core communication device for a multi-core system on chip, characterized in that: include: an acquisition module configured to acquire operating parameters of the multi-core system-on-chip when executing a task to be processed; wherein the operating parameters include a current load condition, data transmission volume, and real-time requirements of the multi-core system-on-chip; a determination module configured to determine a target interrupt generation strategy based on the operating parameters; wherein the target interrupt generation strategy is used to instruct the first processor in the multi-core system-on-chip to trigger a preset interrupt controller to generate an interrupt when performing a write operation in a target address; the target interrupt generation strategy includes a first target interrupt generation strategy and a second target interrupt generation strategy; The target address corresponding to the first target interrupt generation strategy is the address of a dedicated register. When a write operation is performed on the address of the dedicated register, a preset interrupt controller is triggered to simultaneously generate multiple first-type interrupts and send them to multiple second processors. The meaning of the first-type interrupt is a fixed meaning. The target address corresponding to the second target interrupt generation strategy is the address of the shared memory, and when a write operation is performed on the address of the shared memory, a preset interrupt controller is triggered to generate a second type of interrupt and send it to the second processor; the meaning of the second type of interrupt is a custom meaning; a sending module configured to generate an interrupt according to the target interrupt generation policy and send the interrupt to a second processor when the write address corresponding to the task to be processed matches the target address; wherein the first processor and the second processor are processors in the multi-core system-on-chip that collaboratively execute the task to be processed; Determining a target interrupt generation strategy according to the operating parameters includes: Comparing the operating parameters with corresponding thresholds to obtain comparison results; If the comparison result shows that the current load condition is lower than a first preset load threshold, the data transmission volume is lower than a first preset data volume threshold, and the real-time requirement is lower than a first preset requirement threshold, determining that the target interrupt generation strategy is a first target interrupt generation strategy; When the comparison result is that the current load situation is not higher than the second preset load threshold, the data transmission volume is lower than the second preset data volume threshold, and the real-time requirement is higher than the second preset requirement threshold, the target interrupt generation strategy is determined to be the second target interrupt generation strategy.

7. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, which, when executed by the one or more processors, enables the electronic device to implement the inter-core communication method of the multi-core system on chip as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that Computer-readable instructions are stored thereon, and when the computer-readable instructions are executed by a processor of a computer, the computer is caused to execute the inter-core communication method of a multi-core system on chip according to any one of claims 1 to 5.

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