Display control method, display control circuit, chip and display device

Abstract

The present application discloses a display control method, display control circuit, chip, and display device. The display control method includes: obtaining multiple frame change control signals; generating a line change control signal based on the frame change control signal, wherein the line change control signal includes multiple continuous pulse signals; generating a line change instruction based on the pulse signal of the line change control signal, and displaying the corresponding pixel row according to the line change instruction. The display control method also includes: when displaying each subframe, counting the multiple pulse signals of the line change control signal to obtain a count value; after detecting the frame change control signal, determining whether the count value is equal to a first value, and generating a frame change instruction when the count value is equal to the first value; and outputting a drive signal for the next frame of the display image according to the frame change instruction. This can eliminate the bright and dark ripples and flickering of the captured image.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display control method, a display control circuit, a chip, and a display device. Background Art

[0002] At present, LED display panels have become one of the mainstream of modern display technology with their advantages such as high brightness, high resolution, energy saving and high efficiency, unlimited splicing, good viewing angle and high reliability.

[0003] LED display panels consist of pixels arranged in an array. These pixels are scanned row by row during display. During rapid scanning, the human eye's persistence of vision is leveraged to present a complete image. Furthermore, a frame interval is typically set between adjacent frames, creating a period of inactivity. This prevents data conflicts between adjacent frames, thereby ensuring the integrity of the displayed image.

[0004] When photographing an LED display panel, the camera captures pixels that are lit and emitting sufficient light during the exposure time. If the camera's exposure cycle is inconsistent or out of sync with the frame rate of the LED display panel's video source, the exposure cycle and frame interval may overlap, causing bright and dark ripples in the image. Furthermore, as the camera continues to expose, the overlap between the exposure cycle and frame interval may gradually increase, causing a flickering effect in the image and affecting the quality of the shot. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a display control method, display control circuit, chip and display device to eliminate the bright and dark ripples and flickering in the captured image.

[0006] According to one aspect of the present application, a display control method is provided, which includes: obtaining multiple frame change control signals; generating a line change control signal according to the frame change control signal, the line change control signal including a plurality of continuous pulse signals; generating a line change instruction according to the pulse signal of the line change control signal, and displaying the corresponding pixel row according to the line change instruction, wherein the multiple pulse signals include a first pulse signal with a first pulse width and a plurality of second pulse signals with a second pulse width located between adjacent first pulse signals, the first pulse signal being used to indicate the switching of adjacent subframes, and the display control method also includes: when displaying each of the subframes, counting the multiple pulse signals of the line change control signal to obtain a count value; judging whether the count value is equal to a first value after detecting the frame change control signal, and generating a frame change instruction when the count value is equal to the first value; and outputting a drive signal for the next frame of display according to the frame change instruction.

[0007] Optionally, counting the multiple pulse signals of the line feed control signal includes: counting the first pulse signal and the second pulse signal, and the first value corresponds to the number of pixel rows of the display panel.

[0008] Optionally, the multiple frame change control signals are obtained according to the video source, and the multiple frame change control signals are obtained by: decoding the video source to obtain the frame change control signals; or calculating the frame change control signals according to the frame rate of the video source.

[0009] Optionally, the display control method further includes: obtaining a preset frame period based on the time interval between two adjacent frame change control signals; obtaining a preset number of sub-frames in each frame of the display screen based on the preset frame period; breaking up the row display data of each pixel row in each frame of the display screen to obtain a plurality of sub-frame row data, the number of the sub-frame row data being the same as the preset number of the sub-frames; and allocating each sub-frame row data to a corresponding sub-frame serial number.

[0010] Optionally, the display screen includes a first type of display screen and a second type of display screen, the actual number of subframes in the first type of display screen is less than the actual number of subframes in the second type of display screen, and at least one first type of display screen is included between two adjacent second type of display screens.

[0011] Optionally, the actual number of subframes in the first type of display picture is n-1, and the actual number of subframes in the second type of display picture is n.

[0012] ,

[0013] Tf is the preset frame period, Tr is the row scanning period, R is the number of pixel rows, INT represents rounding down, and n is also the preset number of subframes, n>1 and is an integer.

[0014] Optionally, the actual number of the subframes in the first type of display picture is m, and the actual number of the subframes in the second type of display picture is m+1.

[0015] ,

[0016] Tf is the preset frame period, Tr is the row scanning period, R is the number of pixel rows, INT represents rounding down, m is also the preset number of subframes, m≥1 and is an integer.

[0017] Optionally, when the product of the preset number of subframes and the subframe period is greater than the preset frame period, in the first type of display screen, the subframe row data corresponding to the largest subframe number is not displayed; when the product of the preset number of subframes and the subframe period is less than the preset frame period, in the second type of display screen, the subframe row data corresponding to the largest subframe number is repeatedly displayed in two subframes.

[0018] Optionally, the step of generating the line change control signal includes: generating the first first pulse signal based on the first frame change control signal, the first first pulse signal being phase-adapted to the first frame change control signal; and after generating the first first pulse signal, generating the next first pulse signal by counting a second number of the second pulse signals, the second number being one less than the number of pixel rows.

[0019] According to another aspect of the present application, a display control circuit is provided, which includes a receiving card and a data driving circuit, wherein the receiving card includes: a processing unit, which obtains a video source and obtains a plurality of frame change control signals according to the video source; a line change control signal generating unit, which generates a line change control signal according to the frame change control signal, wherein the line change control signal includes a plurality of continuous pulse signals, each pulse signal is used to control the display of a corresponding pixel row of a display panel, wherein the plurality of pulse signals include a first pulse signal with a first pulse width and a plurality of second pulse signals with a second pulse width located between adjacent first pulse signals, wherein the first pulse signal The pulse signal is used to indicate the switching of adjacent subframes. The data driving circuit includes: a control unit, which is used to receive the line break control signal and the frame break control signal, and generate a line break instruction according to the pulse signal of the line break control signal. The control unit is also used to count the multiple pulse signals of the line break control signal when displaying each of the subframes to obtain a count value, and generate a frame break instruction after detecting the frame break control signal and the count value is equal to a first value; an output unit, which is used to drive the corresponding pixel row to display according to the line break instruction, or output a drive signal for the next frame of display according to the frame break instruction.

[0020] According to a third aspect of the present application, a chip is provided, comprising: the display control circuit as described above.

[0021] According to a fourth aspect of the present application, a display device is provided, comprising: a display panel; and the display control circuit as described above.

[0022] According to the display control method, display control circuit, chip and display device of the present application, the line break control signal includes a plurality of continuous pulse signals, which can control the pixel rows to perform uninterrupted scanning and display. It avoids the display of a black screen caused by the interruption of scanning of the pixel rows at the frame interval. When using a camera to shoot, continuous display can eliminate the bright and dark ripples in the imaging picture, which is beneficial to improving the shooting effect. Pulse signals of different pulse widths can represent different types of line break control. Among them, the first pulse signal is used to indicate the switching of adjacent subframes, and its period is fixed, which is beneficial to simplifying the circuit. At the same time, through the coordination of the frame change control signal and the line break control signal, the frame change timing can be accurately located, avoiding the timing error caused by forcibly changing the frame according to the frame change control signal during the continuous display process, thereby avoiding the screen tearing during forced frame change, which is beneficial to improving the stability of the display.

[0023] Furthermore, in the case of uninterrupted display, if each display image is displayed with a fixed number of subframes and a fixed subframe display period, there will be a timing deviation between the actual display period of a single display image and the time interval between adjacent frame change control signals. This deviation will accumulate over the display process, ultimately leading to display errors. Therefore, when the subframe display period is fixed, this timing deviation can be compensated by adjusting the number of subframes in some display images, thereby improving display stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0025] Figure 1 A schematic structural diagram of a display device is shown;

[0026] Figure 2 A schematic timing diagram showing subframe driving;

[0027] Figure 3 A schematic flow chart showing a display control method according to an embodiment of the present application is shown;

[0028] Figure 4 The corresponding relationship between the subframe sequence number and the frame change control signal in some embodiments is shown;

[0029] Figure 5 The corresponding relationship between the subframe sequence number and the frame change control signal in some other embodiments is shown;

[0030] Figure 6 Showing a schematic structural diagram of a receiving card;

[0031] Figure 7 A schematic structural diagram of a data driving circuit is shown. DETAILED DESCRIPTION

[0032] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0033] Certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different terms to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in their functions.

[0034] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0035] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0036] It should also be noted that, in the various methods and processes of the present application, the size of the step numbers does not mean the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of the present application.

[0037] Figure 1 Schematic diagram of the structure of the display device is shown. Figure 1 The display device is, for example, an LED display device, which includes a receiving card 10 , a scan driving circuit 20 , a data driving circuit 30 and a display panel 40 .

[0038] The receiving card 10 is connected to the scan driver circuit 20 and the data driver circuit 30, respectively. It is configured to provide a first timing signal to the scan driver circuit 20 based on externally provided image data and control signals, and to provide a second timing signal and display data to the data driver circuit 30. The scan driver circuit 20 outputs a scan signal based on the first timing signal, and the data driver circuit 30 converts the display data into a drive signal based on the second timing signal and outputs the result.

[0039] It should be noted that the first and second timing signals described above should be understood as a general term for a class of signals rather than individual signals. For example, the first timing signal may include the line feed control signal DCK and the register clock RCK provided to the scan driver circuit 20. The second timing signal may include the reference clock DCLK, the line feed control signal Hsync, and the frame feed control signal Vsync provided to the data driver circuit 30. In a preferred embodiment, the frame feed control signal Vsync is typically transmitted as the command signal LE. Pulse signals of varying pulse widths in the command signal LE may represent, for example, the frame feed control signal Vsync, a data latch instruction, a write register instruction, and the like.

[0040] Furthermore, the line feed control signal DCK sent to the scan driving circuit 20 and the line feed control signal Hsync sent to the data driving circuit 30 should be compatible, so that the scan driving circuit 20 and the data driving circuit 30 work together to achieve progressive scanning driving of the display panel.

[0041] The display panel 40 includes multiple pixel rows, multiple data lines, and multiple scan lines. Each pixel row includes multiple pixels, each of which is connected to the data driver circuit 30 via a corresponding data line and to the scan driver circuit 20 via a corresponding scan line. Each pixel turns on when the scan signal received via the scan line has an active level and displays according to the drive signal received via the data line.

[0042] To increase the refresh rate, a display panel is driven using subframe driving. This involves dividing a frame into multiple subframes, and sequentially driving each pixel row within each subframe. Each pixel displays the subframe row data for that subframe during its corresponding row display phase. Assume the display panel has s pixel rows, and each frame contains k subframes. Figure 2 Schematic timing diagram of sub-frame driving is shown in FIG. Figure 2 As shown in the figure, the entire display process of the i-th frame display picture is: the first row of the 1st subframe, the second row of the 1st subframe to the s-th row of the 1st subframe are displayed in sequence, and the luminance of each pixel in its corresponding row display stage corresponds to the subframe data of the pixel in the 1st subframe; then the first row of the 2nd subframe is displayed, the second row of the 2nd subframe... and so on, until the display of all k subframes is completed.

[0043] More specifically, the sub-frame row data can be obtained by breaking up the row display data of the pixel row using a preset breaking up algorithm to obtain a plurality of sub-frame row data equal in number to the number of sub-frames, and then allocating the sub-frame row data to corresponding sub-frame numbers using a method such as binary division. The sub-frame numbers correspond to the display order of the sub-frames, thereby enabling sub-frame driving.

[0044] The present application provides a display control method, which enables a display panel to continuously scan and display by generating a line break control signal including multiple continuous pulse signals, and is not limited by whether the frame break control signal is obtained and the display is interrupted. It avoids the different exposure levels of each pixel row caused by displaying a black screen while waiting for the frame break control signal, thereby eliminating the bright and dark ripples when the camera is shooting, which is beneficial to improving the shooting effect.

[0045] Figure 3 The schematic flow chart of the display control method of the embodiment of the present application is shown. The display control method provided by the present application is implemented, for example, by the receiving card 10 and the data driving circuit 30. Figure 3 , the display control method provided by this application includes:

[0046] Step S11, obtaining multiple frame change control signals;

[0047] Step S12, generating a line feed control signal according to the frame feed control signal, wherein the line feed control signal includes a plurality of continuous pulse signals;

[0048] Step S13, generating a line break instruction according to the pulse signal of the line break control signal, and displaying the corresponding pixel row according to the line break instruction;

[0049] Step S14, when displaying each subframe, counting multiple pulse signals of the line feed control signal to obtain a count value;

[0050] Step S15, after detecting the frame change control signal, determining whether the count value is equal to the number of pixel rows of the display panel, and generating a frame change instruction when the count value corresponds to the number of pixel rows of the display panel;

[0051] Step S16: outputting a driving signal for the next frame of display image according to the frame change instruction.

[0052] The above steps are further explained below.

[0053] Step S11 may be to obtain a frame change control signal based on the video source. Specifically, in some embodiments, step S11 decodes the video source received by the display device to obtain the frame change control signal. In other embodiments, step S11 may also obtain the frame change control signal by calculating the frame rate of the video source.

[0054] The duration between two adjacent frame change control signals is a preset frame period. In conventional display control methods, the display screens of adjacent frames are switched according to the frame change control signal instructions. When each frame of the display screen is displayed, the number of line change control signals is fixed, corresponding to the number of sub-frames of the display screen and the number of pixel rows of the display panel. After generating these fixed number of line change control signals, the generation of line change control signals will stop until the next frame change control signal is obtained and resumed. During the stage when no line change control signal is generated, the display panel will display a black screen. This black screen stage is usually called the frame interval. When using a camera to shoot the display panel, if the shutter exposure period overlaps with the frame interval, it will cause bright and dark ripples to appear in the image, and the screen will flicker when shooting continuous pictures.

[0055] To address this issue, in an embodiment of the present application, the line break control signal generated in step S12 includes multiple continuous pulse signals. That is, the generation of the line break control signal is not interrupted by whether or not a frame break control signal is received. Accordingly, the line break command generated in step S13 is not interrupted by whether or not a frame break control signal is received. Therefore, the display panel will not display a black screen due to the interruption of the line break command, thus avoiding the bright and dark ripples and screen flickering caused by the overlap of the shutter exposure cycle and the frame interval when shooting with the camera, thereby improving the shooting effect.

[0056] Furthermore, in a subframe-driven display mode, a preset frame period is divided into a preset number of subframes based on a set row scanning period and the number of pixel rows in the display image. The row display data of the pixel rows is broken up using a preset breaking up algorithm to obtain a plurality of subframe row data, and the subframe row data is assigned to corresponding subframe sequence numbers. The number of subframe row data is the same as the preset number of subframes, the subframe row data is assigned using a binary division method, and the subframe sequence numbers correspond to the display order of the subframes.

[0057] If the number of subframes and the subframe period of each display frame are the same, during the continuous scanning and display process, the data transmission timing and display timing of the display frame will be mismatched, resulting in display anomalies.

[0058] To further address this issue, the actual number of subframes displayed in some display images can be adjusted to compensate for the mismatch between the data transmission timing and the display timing of the display images. Specifically, the display images include a first type of display image and a second type of display image. The actual number of subframes in the first type of display image is less than the actual number of subframes in the second type of display image, and at least one first type of display image is located between two adjacent second type of display images. When the subframe period is fixed, the timing mismatch can be compensated by adjusting the actual number of subframes in some display images, thereby avoiding display anomalies caused by the timing mismatch.

[0059] The actual number of subframes in each display frame can also be calculated based on the preset frame period, row scanning period, and the number of pixel rows on the display panel. The calculation method is described in detail below. When the subframe period is fixed, at least one first-category display image is displayed between two adjacent second-category display images to compensate for any mismatch between the data transmission timing and the display timing of the display images, thus avoiding display anomalies caused by the timing mismatch.

[0060] Continuous scanning can also cause the actual frame period of a displayed frame to differ from the preset frame period, that is, the time interval between two adjacent frame change control signals. If the frame change control signal is still used to indicate the switching of adjacent display frames, a forced frame change will occur mid-display, resulting in screen tearing.

[0061] Therefore, in an embodiment of the present application, the multiple pulse signals of the line feed control signal may include a first pulse signal having a first pulse width and a second pulse signal having a second pulse width located between adjacent first pulse signals. Each pulse signal is used to control the display of a corresponding pixel row of the display panel, and the first pulse signal is also used to indicate the switching of adjacent subframes.

[0062] Specifically, step S12 further includes: generating a first first pulse signal according to the first frame change control signal, wherein the first first pulse signal is phase-matched with the first frame change control signal; and after generating the first first pulse signal, generating a next first pulse signal by counting a second number of second pulse signals, wherein the second number is one less than the number of pixel rows of the display panel.

[0063] It should be noted that the first first pulse signal is phase-matched with the first frame change control signal, and the rising edge of the first first pulse signal is aligned with the falling edge of the first frame change control signal, or the rising edge of the first first pulse signal lags behind the falling edge of the first frame change control signal by several clock cycles of the reference clock.

[0064] The line break control command generated by the display control method of the present application can be used to indicate line switching between subframes using a first pulse signal, i.e., switching from displaying the last row of pixels in the current subframe to displaying the first row of pixels in the next subframe. It is also possible to indicate line switching within a subframe using a second pulse signal. Because the first and second pulse signals are sent cyclically at a fixed period, this facilitates circuit simplification. Accordingly, the frame break control signal is used to separate the display data of adjacent frames during data transmission.

[0065] The line feed control signal may include the line feed control signal DCK sent to the scan driving circuit 20 and the line feed control signal Hsync sent to the data driving circuit 30 as described above. The line feed control signal DCK and the line feed control signal Hsync have the same period, and their phase relationship may be advanced, identical, or delayed.

[0066] Because the pulse signals in the line break control signal are continuous, the generated line break commands are also continuous. This means that the generation of line break commands is not interrupted by the receipt of a frame break control signal. The display panel will not display a black screen due to line break command interruptions. This prevents bright and dark ripples and image flickering caused by the overlap of the shutter exposure cycle and the frame interval when shooting with a camera, improving shooting quality.

[0067] Continuous scanning can also cause the actual frame period of a displayed frame to differ from the preset frame period. In other words, the product of the number of subframes actually displayed per frame and the subframe period differs from the preset frame period. If the frame change control signal is still used to indicate the switching of adjacent display frames, forced frame changes will occur mid-display, resulting in screen tearing.

[0068] Therefore, the display control method of the present application also includes step S14 and step S15.

[0069] For example, when displaying each subframe, the first pulse signal and the second pulse signal of the line break control signal are counted to obtain a count value. After detecting the frame break control signal, it is determined whether the count value is equal to the first value, and a frame break instruction is generated when the count value is equal to the first value. The first value corresponds to the number of pixel rows of the display panel. Take the number of pixel rows s as an example. In some embodiments, the correspondence between the above-mentioned first value and the number of pixel rows can be that the first value is s-1, and accordingly, in each subframe, the count value increases from 0 to s-1. In some other embodiments, the correspondence between the above-mentioned first value and the number of pixel rows can be that the first value is s, and accordingly, in each subframe, the count value increases from 1 to s.

[0070] It should be noted that the purpose of determining whether the count value is the first value after detecting the frame change control signal is to ensure that the frame change timing correctly corresponds to the last line of the current subframe of the current frame display screen being fully displayed. Specifically, in some embodiments, the frame change instruction can be generated at the same time as the next first pulse signal is detected to ensure correct timing. In other embodiments, timing can also be performed after detecting the first pulse signal, and the timing can be reset after detecting the next first pulse signal. When the frame change control signal is detected and the timing duration corresponds to the subframe period, a frame change instruction is generated. Among them, timing after detecting the first pulse signal can be obtained by counting the reference clock DCLK. DCLK is generated by the receiving card 10 and sent to the data driving circuit 30. Specifically, DCLK can be obtained by dividing the preset frame period, or it can be independently generated within the receiving card 10.

[0071] Furthermore, in some embodiments, the display control method may further include: generating a serial decoding input signal having the same phase as the first pulse signal.

[0072] The serial decode input signal is the aforementioned serial decode input signal SDI sent to the scan driver circuit 20. The serial decode input signal SDI is used to reset the pixel rows being displayed. Upon receiving the serial decode input signal SDI, the scan driver circuit 20 controls the pixel rows to be sequentially turned on, starting with the first row. During the continuous scanning and display process, the serial decode input signal SDI includes a plurality of consecutive third pulse signals, each having a third pulse width. Specifically, the serial decode input signal being in phase with the first pulse signal means that the rising edges of the first and third pulse signals are aligned.

[0073] Figure 4 Schematic waveform diagram of line feed control signal in some embodiments of the present application is shown. Figure 4 The frame change control signal Vsync, for example, has a width of 3 DCLKs, namely, the illustrated signal w3. The first pulse width of the first pulse signal, for example, has a width of 12 DCLKs, namely, the illustrated signal w12. The second pulse width of the second pulse signal, for example, has a width of 4 DCLKs, namely, the illustrated signal w4. The third pulse width of the third pulse signal in the serial decode input signal SDI, for example, has a width of 1 DCLK, namely, the illustrated signal w1. In some embodiments, counting the first and second quantities, i.e., the transmission timing of each pulse signal in the line change control signal and the serial decode input signal, can be obtained by counting DCLKs.

[0074] In such Figure 4In the embodiment shown, the actual number of subframes in the first type of display picture is n-1, and the actual number of subframes in the second type of display picture is n. n>1 and is an integer, and can be calculated according to the following formula (1):

[0075] (1)

[0076] Where Tf is the preset frame period, i.e., the time interval between two adjacent frame change control signals; Tr is the row scan period; R is the number of pixel rows on the display panel; and INT indicates rounding down. n is also the preset number of subframes, i.e., the number of subframe rows after each row of display data is broken up.

[0077] When calculating with reference to the above formula (1), the product of n and the subframe period is greater than the preset frame period. That is, the actual frame period of a single second-category display screen is greater than the preset frame period. In order to compensate for this timing deviation, some subframes need to be skipped in each first-category display screen. Preferably, when allocating subframe row data by binary division, the subframe sequence number increases with the display order of the subframes, and the subframe with the largest subframe sequence number is not displayed. For example, Figure 4 As shown, taking the example of breaking up a display frame into n subframes, namely the 1st subframe, the 2nd subframe, ... the nth subframe, in each first type of display frame, the subframe with subframe sequence number n is not displayed.

[0078] Furthermore, the number of first-category display pictures between two adjacent second-category display pictures may be determined according to the difference between an actual frame period of a single second-category display picture and a preset frame period, as well as a sub-frame period.

[0079] The serial decoded input signal SDI has the same phase as the line feed control signal Hsync of the first line of each subframe.

[0080] Figure 5 Schematic waveform diagrams of line feed control signals in some other embodiments of the present application are shown. Figure 5 In, with Figure 4 The embodiment shown is the same, and the frame change control signal Vsync also has a width of 3 DCLKs, the first pulse width of the first pulse signal has a width of 12 DCLKs, and the second pulse width of the second pulse signal has a width of 4 DCLKs as an example. Figure 5 The serial decoder input signal SDI is hidden in the figure.

[0081] and Figure 4 The embodiment shown differs in that Figure 5 In the example, the actual number of subframes in the first type of display screen is m, and the actual number of subframes in the second type of display screen is m+1. m≥1 is an integer and can be calculated according to the following formula (2):

[0082] (2)

[0083] Where Tf is the preset frame period, i.e., the time interval between two adjacent frame change control signals; Tr is the row scan period; R is the number of pixel rows on the display panel; and INT indicates rounding down. m is also the preset number of subframes, i.e., the number of subframe rows after each row of display data is broken up.

[0084] When calculating with reference to the above formula (2), the product of m and the subframe period is less than the preset frame period. That is, the actual frame period of a single first-category display screen and a second-category display screen is less than the preset frame period. In order to further compensate for the timing deviation in the display, some subframes need to be displayed repeatedly in each second-category display screen. In some embodiments, when allocating subframe row data by binary division, the subframe with the largest subframe number is displayed repeatedly. Preferably, referring to Figure 5 The subframe numbers decrease in the order in which the subframes are displayed. After m subframes are displayed in sequence, the subframe with the largest subframe number is repeated as the last subframe. In other words, taking a display frame as an example, where the display is broken up into the 1st, 2nd, ...mth subframes, in each second-type display frame, the mth subframe, then the m-1th subframe are displayed in sequence, until the mth subframe is repeated after the 1st subframe.

[0085] Likewise, the number of first-category display pictures between two adjacent second-category display pictures may be determined according to the difference between the actual frame period of a single second-category display picture and the preset frame period, as well as the sub-frame period.

[0086] According to the display control method of the present application, the line break control signal includes a plurality of continuous pulse signals, which can control the pixel rows to perform uninterrupted scanning and display. It avoids the display of a black screen caused by the interruption of scanning of the pixel rows at the frame interval. When using a camera to shoot, continuous display can eliminate the bright and dark ripples in the imaging picture, which is beneficial to improving the shooting effect. Pulse signals of different pulse widths can represent different types of line break control. Among them, the first pulse signal is used to indicate the switching of adjacent subframes, and its period is fixed, which is beneficial to simplifying the circuit. At the same time, through the coordination of the frame change control signal and the line break control signal, the frame change timing can be accurately located, avoiding the timing error caused by forcibly changing the frame according to the frame change control signal during the continuous display process, thereby avoiding the screen tearing during forced frame change, which is beneficial to improving the stability of the display.

[0087] Furthermore, in the case of uninterrupted display, if each display image is displayed with a fixed number of subframes and a fixed subframe display period, there will be a timing deviation between the actual display period of a single display image and the time interval between adjacent frame change control signals. This deviation will accumulate over the display process, ultimately leading to display errors. Therefore, when the subframe display period is fixed, this timing deviation can be compensated by adjusting the number of subframes in some display images, thereby improving display stability.

[0088] The present application also provides a display control circuit, for example, including a receiving card and a data driving circuit.

[0089] Figure 6 The schematic structure diagram of the receiving card is shown. Figure 6 , the receiving card includes:

[0090] Processing unit 11 is configured to obtain multiple frame change control signals. In some embodiments, processing unit 11 may obtain the multiple frame change control signals based on the acquired video source by referring to the method corresponding to step S11 described above. The frame change control signals are used to separate display data of adjacent frames during data transmission.

[0091] The line break control signal generating unit 12 is configured to generate a line break control signal according to the frame break control signal.

[0092] The line break control signal includes a plurality of continuous pulse signals, each of which is used to control the display of a corresponding pixel row of the display panel. The plurality of pulse signals includes a first pulse signal having a first pulse width and a plurality of second pulse signals having a second pulse width located between adjacent first pulse signals. The first pulse signal is also used to indicate the switching between adjacent subframes. The line break control signal generation unit 12 can perform the steps described in the display control method described above to generate the first pulse signal and the second pulse signal.

[0093] In some embodiments, the receiving card further includes a calculation unit configured to obtain a preset frame period according to a time interval between two adjacent frame change control signals, and obtain a preset number of subframes in each frame of the display image according to the preset frame period.

[0094] In some embodiments, the receiving card further includes a serial decoding input signal generating module for generating a serial decoding input signal according to the number of pulse signals of the line feed control signal and the number of pixel rows. The serial decoding input signal can also be generated by referring to the above-mentioned display control method.

[0095] Figure 7 Schematic diagram of the data driving circuit is shown. Figure 7 , the data driving circuit includes:

[0096] a control unit 31 for receiving a line break control signal and a frame break control signal, and generating a line break instruction based on a pulse signal of the line break control signal; the control unit is further configured to count a plurality of pulse signals of the line break control signal when displaying each subframe to obtain a count value, and generate a frame break instruction when the frame break control signal is detected and the count value is equal to a first value;

[0097] The output unit 32 is used to drive the corresponding pixel row to display according to the line change instruction, or output the driving signal for the next frame of display according to the frame change instruction.

[0098] Furthermore, when the display control circuit of the present application executes the above-described display control method to perform line and frame switching, the display screen may include a first-category display screen and a second-category display screen. The actual number of subframes in the first-category display screen is smaller than the actual number of subframes in the second-category display screen, and at least one first-category display screen is included between two adjacent second-category display screens.

[0099] The number of subframes in the first type of display picture and the second type of display picture can be calculated with reference to the above formula (1) or (2).

[0100] In some embodiments, the data driving circuit further includes a PWM generating unit for breaking up each frame of display data according to a preset number of subframes calculated by the processing unit to obtain subframe row data of each pixel row in each subframe.

[0101] The present application also provides a chip, which includes the display control circuit. The present invention also provides a display device, which includes a display panel and the chip.

[0102] According to the display control circuit, chip and display device of the present application, the line break control signal includes a plurality of continuous pulse signals, which can control the pixel rows to perform uninterrupted scanning and display. It avoids the display of a black screen caused by the interruption of scanning of the pixel rows at the frame interval. When using a camera to shoot, continuous display can eliminate the bright and dark ripples in the imaging picture, which is beneficial to improving the shooting effect. Pulse signals of different pulse widths can represent different types of line break control. Among them, the first pulse signal is used to indicate the switching of adjacent subframes, and its period is fixed, which is beneficial to simplifying the circuit. At the same time, through the coordination of the frame change control signal and the line break control signal, the frame change timing can be accurately located, avoiding the timing error caused by forcibly changing the frame according to the frame change control signal during the continuous display process, thereby avoiding the screen tearing during forced frame change, which is beneficial to improving the stability of the display.

[0103] Furthermore, in the case of uninterrupted display, if each display image is displayed with a fixed number of subframes and a fixed subframe display period, there will be a timing deviation between the actual display period of a single display image and the time interval between adjacent frame change control signals. This deviation will accumulate over the display process, ultimately leading to display errors. Therefore, when the subframe display period is fixed, this timing deviation can be compensated by adjusting the number of subframes in some display images, thereby improving display stability.

[0104] The embodiments of the present application are as described above, and these embodiments do not describe all details in detail, nor do they limit the present application to specific embodiments. Obviously, based on the above description, many modifications and variations can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The scope of protection of the present application shall be based on the scope defined by the claims of the present application.

Claims

1. A display control method, wherein: include: Obtaining multiple frame change control signals; generating a line feed control signal according to the frame feed control signal, wherein the line feed control signal includes a plurality of continuous pulse signals; generating a line break instruction according to the pulse signal of the line break control signal, and displaying the corresponding pixel row according to the line break instruction, The multiple pulse signals include a first pulse signal with a first pulse width and a plurality of second pulse signals with a second pulse width located between adjacent first pulse signals, wherein the first pulse signal is used to indicate the switching of adjacent subframes. The display control method further includes: When displaying each of the subframes, counting the plurality of pulse signals of the line feed control signal to obtain a count value; After detecting the frame change control signal, determining whether the count value is equal to a first value, and generating a frame change instruction when the count value is equal to the first value; and Outputting a driving signal for the next frame display according to the frame change instruction, The display screen includes a first type of display screen and a second type of display screen. The actual number of subframes in the first type of display picture is less than the actual number of subframes in the second type of display picture, There is at least one first-category display screen between two adjacent second-category display screens.

2. The display control method according to claim 1, wherein: The counting of the plurality of pulse signals of the line feed control signal comprises: counting the first pulse signal and the second pulse signal, The first value corresponds to the number of pixel rows of the display panel.

3. The display control method according to claim 1, wherein: Obtaining the plurality of frame change control signals according to a video source, The obtaining of multiple frame change control signals includes: Decoding the video source to obtain the frame change control signal; or The frame change control signal is obtained by calculation according to the frame rate of the video source.

4. The display control method according to claim 3, wherein: The display control method further includes: Obtaining a preset frame period according to the time interval between two adjacent frame change control signals; Obtaining a preset number of subframes in each frame of the display image according to the preset frame period; Scattering the row display data of each pixel row in each frame of the display image to obtain a plurality of sub-frame row data, the number of the sub-frame row data being the same as the preset number of sub-frames; and Allocate each subframe row data to a corresponding subframe sequence number.

5. The display control method according to claim 4, wherein: The actual number of subframes in the first type of display picture is n-1, and the actual number of subframes in the second type of display picture is n. ， Tf is the preset frame period, Tr is the row scanning period, R is the number of pixel rows, INT represents rounding down, and n is also the preset number of subframes, n>1 and is an integer. The display control method according to claim 4 , wherein: The actual number of subframes in the first type of display picture is m, and the actual number of subframes in the second type of display picture is m+1. ， Tf is the preset frame period, Tr is the row scanning period, R is the number of pixel rows, INT represents rounding down, and m is also the preset number of subframes, m≥1 and is an integer.

7. The display control method according to claim 5 or 6, wherein: When the product of the preset number of subframes and the subframe period is greater than the preset frame period, the subframe row data corresponding to the largest subframe sequence number is not displayed in the first type of display image; When the product of the preset number of subframes and the subframe period is less than the preset frame period, in the second type of display image, the subframe row data corresponding to the largest subframe sequence number is repeatedly displayed in two subframes.

8. The display control method according to claim 1, wherein: The step of generating the line feed control signal comprises: generating a first first pulse signal according to the first frame change control signal, wherein the first first pulse signal is phase-matched with the first frame change control signal; and After generating the first first pulse signal, each time a second number of the second pulse signals is counted, the next first pulse signal is generated. The second number is one less than the number of pixel rows.

9. A display control circuit, wherein: Including receiving card and data driving circuit, The receiving card includes: A processing unit, configured to obtain a plurality of frame change control signals; a line break control signal generating unit, which generates a line break control signal according to the frame break control signal, wherein the line break control signal includes a plurality of continuous pulse signals, each pulse signal being used to control the display of a corresponding pixel row of the display panel, The multiple pulse signals include a first pulse signal with a first pulse width and a plurality of second pulse signals with a second pulse width located between adjacent first pulse signals, wherein the first pulse signal is used to indicate the switching of adjacent subframes. The data driving circuit includes: a control unit, configured to receive the line break control signal and the frame break control signal, and generate a line break instruction according to the pulse signal of the line break control signal, the control unit further configured to count the plurality of pulse signals of the line break control signal when displaying each of the subframes to obtain a count value, and generate a frame break instruction when the frame break control signal is detected and the count value is equal to a first value; An output unit, configured to drive the corresponding pixel row for display according to the line-change instruction, or output a drive signal for the next frame of display according to the frame-change instruction, The display screen includes a first type of display screen and a second type of display screen. The actual number of subframes in the first type of display picture is less than the actual number of subframes in the second type of display picture, There is at least one first-category display screen between two adjacent second-category display screens.

10. A chip, wherein: include: The display control circuit according to claim 9.

11. A display device, wherein: include: Display panel; as well as The display control circuit according to claim 9.

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