Display driving method, circuit, chip, and display device

Abstract

The present application discloses a display driving method, circuit, chip, and display device. The display driving method includes: receiving a line break control signal, the line break control signal including multiple continuous pulse signals; generating a line break instruction based on the pulse signals of the line break control signal, and displaying the corresponding pixel row according to the line break instruction. The display driving method also includes: after receiving a frame break control signal, generating a frame break instruction based on the count value of the multiple pulse signals of the line break control signal, and outputting a driving signal for the next frame of the display image according to the frame break instruction. This can eliminate bright and dark ripples and flickering in the captured image.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display driving method, circuit, chip, and display device. Background Art

[0002] At present, LED display panels have become one of the mainstream of modern display technology with their advantages such as high brightness, high resolution, energy saving and high efficiency, unlimited splicing, good viewing angle and high reliability.

[0003] LED display panels consist of pixels arranged in an array. These pixels are scanned row by row during display. During rapid scanning, the human eye's persistence of vision is leveraged to present a complete image. Furthermore, a frame interval is typically set between two adjacent frames. This interval prevents data conflicts between adjacent frames, thereby ensuring the integrity of the displayed image.

[0004] When photographing an LED display panel, the camera captures pixels that are lit and emitting sufficient light during the exposure time. If the camera's exposure cycle is inconsistent or out of sync with the frame rate of the LED display panel's video source, the exposure cycle and frame interval may overlap, causing bright and dark ripples in the image. Furthermore, as the camera continues to expose, the overlap between the exposure cycle and frame interval may gradually increase, causing a flickering effect in the image and affecting the quality of the shot. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a display driving method and circuit, chip, and display device to eliminate the bright and dark ripples and flickering in the captured image.

[0006] According to one aspect of the present application, a display driving method is provided, which includes: receiving a line break control signal, the line break control signal including a plurality of continuous pulse signals; generating a line break instruction according to the pulse signal of the line break control signal, and displaying a corresponding pixel row according to the line break instruction, wherein the display driving method also includes: after receiving a frame break control signal, generating a frame break instruction according to the count value of the plurality of pulse signals of the line break control signal, and outputting a driving signal for the next frame of display according to the frame break instruction.

[0007] Optionally, each frame of the display picture includes a plurality of sub-frames, and the display driving method further includes: breaking up the display data of each frame of the display picture according to a preset number of sub-frames.

[0008] Optionally, the display screen includes a first type of display screen and a second type of display screen, the actual number of subframes of the first type of display screen is smaller than the actual number of subframes of the second type of display screen, and at least one first type of display screen is included between two adjacent second type of display screens.

[0009] Optionally, the actual number of subframes of the first type of display picture is n-1, and the actual number of subframes of the second type of display picture is n.

[0010] ,

[0011] Tf is a preset frame period, Tr is a row scanning period, R is the number of pixel rows of the display panel, INT represents rounding down, wherein n is also the preset number of subframes, n>1 and is an integer.

[0012] Optionally, the actual number of subframes of the first type of display picture is m, and the actual number of subframes of the second type of display picture is m+1.

[0013] ,

[0014] Tf is a preset frame period, Tr is a row scanning period, R is the number of pixel rows of the display panel, INT represents rounding down, wherein m is also the preset number of subframes, m≥1 and is an integer.

[0015] Optionally, the multiple pulse signals include a first pulse signal having a first pulse width and a second pulse signal having a second pulse width, the first pulse signal also indicating pixel row switching between frames, and generating a frame change instruction based on a count value of the line change control signal after receiving the frame change control signal, including: counting the multiple pulse signals of the line change control signal when displaying each of the subframes to obtain the count value; and after receiving the frame change control signal, determining whether the count value corresponds to the number of pixel rows, and generating the frame change instruction when the count value corresponds to the number of pixel rows.

[0016] Optionally, the step of obtaining the count value further includes: determining whether a next pulse signal is detected after the count value corresponds to the number of pixel rows; and resetting the count value after the next pulse signal is detected.

[0017] Optionally, breaking up the display data of each frame of the display screen according to a preset number of subframes includes: breaking up the row display data of each pixel row in each frame of the display screen to obtain the preset number of subframe row data; and allocating each subframe row data to a corresponding subframe serial number.

[0018] Optionally, the method of allocating each subframe row data to a corresponding subframe sequence number includes a binary method, where when the product of the preset number of subframes and the subframe period is greater than the preset frame period, in each frame of the display screen, the subframe sequence number increases with the display order of the subframe, and the subframe sequence number is reset when the frame change control signal is received and the count value is equal to the number of pixel rows; when the product of the preset number of subframes and the subframe period is less than the preset frame period, in each frame of the display screen, the subframe sequence number decreases with the display order of the subframe, and the subframe sequence number is reset when the frame change control signal is received and the count value is equal to the number of pixel rows.

[0019] Optionally, when the product of the preset number of subframes and the subframe period is greater than the preset frame period, in the first type of display screen, the subframe row data corresponding to the largest subframe number is not displayed; when the product of the preset number of subframes and the subframe period is less than the preset frame period, in the second type of display screen, the subframe row data corresponding to the largest subframe number is repeatedly displayed in two subframes.

[0020] According to another aspect of the present application, a display driving circuit is provided, which includes: a control unit for receiving a line break control signal and a frame break control signal, the line break control signal including a plurality of continuous pulse signals, the control unit further for generating a line break instruction according to the pulse signal of the line break control signal, and generating a frame break instruction according to a count value of the line break control signal after receiving the frame break control signal; an output unit for driving the corresponding pixel row display according to the line break instruction, or outputting a driving signal for the next frame of the display according to the frame break instruction.

[0021] According to a third aspect of the present application, a chip is provided, which includes the driving circuit as described above.

[0022] According to a fourth aspect of the present application, a display device is provided, comprising: a display panel; and the chip as described above, configured to provide a driving signal for the display panel.

[0023] The display driving method, circuit, chip, and display device of the present application generate continuous line break instructions based on a line break control signal having a continuous pulse signal, enabling the display panel to continuously scan and display without being interrupted by whether or not a frame break control signal is received. This avoids the uneven exposure of each pixel row caused by a black screen while waiting for a frame break control signal, thereby eliminating bright and dark ripples during camera shooting and improving shooting effects. Furthermore, through the coordinated coordination of the frame break control signal and the line break control signal, the frame break timing can be precisely determined, avoiding display anomalies caused by timing errors.

[0024] Furthermore, when scanning and displaying with a fixed subframe period, the mismatch between the data transmission timing and the display timing of the display screen is compensated by adjusting the number of subframes in part of the display screen, which can avoid display anomalies caused by timing mismatch and help improve display stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0026] Figure 1 A schematic structural diagram of a display device is shown;

[0027] Figure 2 A schematic timing diagram showing subframe driving;

[0028] Figure 3 A schematic structural diagram of a display driving circuit according to an embodiment of the present application is shown;

[0029] Figure 4 Show Figure 3 A schematic structural diagram of the buffer in the middle;

[0030] Figure 5 Show Figure 3 A schematic structural diagram of the pulse width modulation unit;

[0031] Figure 6 Show Figure 3 The working waveform diagram of the display driving circuit in some embodiments is shown;

[0032] Figure 7 Show Figure 3 The working waveform diagram of the display driving circuit in some other embodiments is shown;

[0033] Figure 8 A schematic flow chart of a display driving method according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0035] Certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different terms to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in their functions.

[0036] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0037] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0038] It should also be noted that, in the various methods and processes of the present application, the size of the step numbers does not mean the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of the present application.

[0039] Figure 1 Schematic diagram of the structure of the display device is shown. Figure 1 The display device is, for example, an LED display device, which includes a receiving card 10 , a scan driving circuit 20 , a data driving circuit 30 and a display panel 40 .

[0040] The receiving card 10 is connected to the scan driver circuit 20 and the data driver circuit 30, respectively. It is configured to provide a first timing signal to the scan driver circuit 20 based on externally provided image data and control signals, and to provide a second timing signal and display data to the data driver circuit 30. The scan driver circuit 20 outputs a scan signal based on the first timing signal, and the data driver circuit 30 converts the display data into a drive signal based on the second timing signal and outputs the result.

[0041] It should be noted that the first and second timing signals described above should be understood as a general term for a class of signals rather than individual signals. For example, the first timing signal may include the line feed control signal DCK and the register clock RCK provided to the scan driver circuit 20. The second timing signal may include the reference clock DCLK, the line feed control signal Hsync, and the frame feed control signal Vsync provided to the data driver circuit 30. In a preferred embodiment, the frame feed control signal Vsync is typically transmitted as the command signal LE. Pulse signals of varying pulse widths in the command signal LE may represent, for example, the frame feed control signal Vsync, a data latch instruction, a write register instruction, and the like.

[0042] Furthermore, the line feed control signal DCK sent to the scan driving circuit 20 and the line feed control signal Hsync sent to the data driving circuit 30 should be compatible, so that the scan driving circuit 20 and the data driving circuit 30 work together to achieve progressive scanning driving of the display panel.

[0043] The display panel 40 includes multiple pixel rows, multiple data lines, and multiple scan lines. Each pixel row includes multiple pixels, each of which is connected to the data driver circuit 30 via a corresponding data line and to the scan driver circuit 20 via a corresponding scan line. Each pixel turns on when the scan signal received via the scan line has an active level and displays according to the drive signal received via the data line.

[0044] To increase the refresh rate, a subframe drive method is preferably used to drive the display panel. This involves dividing a display frame into multiple subframes, and then sequentially driving each pixel row within each subframe to display the corresponding subframe row data. Assuming the display panel includes s pixel rows, each display frame contains k subframes. Figure 2 Schematic timing diagram of sub-frame driving is shown in FIG. Figure 2 As shown in the figure, the entire display process of the i-th frame display picture is: the first row of the 1st subframe, the second row of the 1st subframe to the s-th row of the 1st subframe are displayed in sequence, and the luminous brightness of each pixel row in its corresponding row display stage corresponds to the subframe row data of the pixel row in the 1st subframe; then the first row of the 2nd subframe is displayed, the second row of the 2nd subframe... and so on, until the display of all k subframes is completed.

[0045] Figure 3 Schematic diagram of the structure of the display driving circuit of the embodiment of the present application is shown. The display driving circuit of the present application can be used as the data driving circuit 30 in the above-mentioned display device, for example. Figure 3 The display driving circuit may include: a shift register 31 , a control unit 32 , a buffer 33 , a pulse width modulation unit 34 , and an output unit 35 .

[0046] Furthermore, Figure 4Show Figure 3 A schematic structural diagram of the buffer 33; Figure 5 Show Figure 3 The schematic structure diagram of the pulse width modulation unit 34 is shown below in conjunction with Figures 3 to 5 The display driving circuit of the present application is described in detail.

[0047] The control unit 32 receives the instruction signal LE and the line feed control signal Hsync.

[0048] The command signal LE can be a pulse signal with different pulse widths to carry different command data. For example, the control unit 32 decodes the command signal LE with a pulse width (ie, effective level width) of 3 reference clocks DCLK into the frame switching control signal Vsync.

[0049] In a traditional data drive circuit, the control unit generates a frame change instruction based on the frame change control signal Vsync and a line change instruction based on the active level of the line change control signal Hsync. However, the number of active levels of the line change control signal Hsync between adjacent frame change control signals Vsync is fixed, corresponding to the product of the number of subframes and the number of pixel rows on the display panel. After generating this fixed number of line change instructions, the control unit stops generating line change instructions until it receives the next frame change control signal Vsync. During the period when no line change instructions are generated, the display panel displays a black screen. This black screen period is commonly referred to as the frame interval. When using a camera to capture a display panel, if the shutter exposure period overlaps with the frame interval, it will cause bright and dark ripples in the image, resulting in flickering when capturing continuous images.

[0050] To address this issue, in an embodiment of the present application, the line feed control signal Hsync includes multiple continuous pulse signals. The control unit 32 generates continuous line feed instructions ROW based on the pulse signals of the line feed control signal Hsync to display the corresponding pixel rows. In other words, the control unit 32 is not limited by whether it receives the frame feed control signal Vsync and interrupts the transmission of the line feed instructions ROW, and the display panel will not display a black screen due to the interruption of the line feed instructions ROW. Therefore, the bright and dark ripples and image flicker caused by the overlap of the shutter exposure cycle and the frame interval when using the camera can be avoided, which helps improve the shooting effect.

[0051] If the number of subframes and the subframe period of each display frame are the same, during the continuous scanning and display process, the data transmission timing and display timing of the display frame will be mismatched, resulting in display anomalies.

[0052] To further address this issue, in a preferred embodiment, the number of subframes actually displayed in a portion of the display screen can be adjusted to compensate for the mismatch between the data transmission timing and the display timing of the display screen. Specifically, the display screen includes a first type of display screen and a second type of display screen, each having a different number of subframes actually displayed. The actual number of subframes in the first type of display screen is smaller than that in the second type of display screen, and at least one first type of display screen is located between two adjacent second type of display screens. When the subframe period is fixed, the timing mismatch is compensated by adjusting the actual number of subframes displayed in a portion of the display screen, thereby avoiding display anomalies caused by the timing mismatch.

[0053] Continuous scanning display can also cause the actual frame period of a displayed frame to differ from the preset frame period. That is, the product of the number of subframes actually displayed per frame and the subframe period differs from the preset frame period. If the frame change instruction Fr is still generated based on the frame change control signal Vsync, a forced frame change will occur mid-display, resulting in screen tearing. Therefore, in a preferred embodiment, the multiple pulse signals of the line change control signal Hsync can include a first pulse signal having a first pulse width and a second pulse signal having a second pulse width. The first pulse signal and the second pulse signal indicate different types of line change operations. For example, the first pulse signal is used to indicate the switching of two adjacent display frames, that is, switching the last pixel row displayed in the current frame to the first pixel row displayed in the next frame. The second pulse signal is used to indicate the switching of pixel rows within the same display frame. After receiving the frame change control signal Vsync, the control unit 32 generates the frame change instruction Fr based on the count value of the line change control signal, so that the display driver circuit outputs the drive signal for the next display frame according to the frame change instruction Fr. Through the coordinated cooperation of the frame change control signal Vsync and the line change control signal Hsync, the frame change timing can be accurately located, avoiding the screen tearing caused by forced frame change when the frame change control signal Vsync arrives during the continuous scanning display process, which is beneficial to improving the display stability.

[0054] For example, when displaying each subframe, the number of pulses of the line-swap control signal Hsync is counted to obtain a count value. After receiving the frame-swap control signal Vsync, a determination is made as to whether the count value equals the number of pixel rows. If the count value equals the number of pixel rows, a frame-swap command Fr is generated. In other words, the frame-swap command Fr is generated after the frame-swap control signal Vsync is detected and the current display image is completed.

[0055] In the example above where a pulse signal count equal to the number of pixel rows is used as one of the conditions for generating the frame change command Fr, the count value must be reset after each subframe is displayed. Specifically, whenever the count value corresponds to the number of pixel rows, a determination is made as to whether the next pulse signal has been detected, and the count value is reset upon detection of the next pulse signal. For example, the count value may be reset upon receiving the frame change control signal Vsync and detecting the first pulse signal.

[0056] Furthermore, taking the number of pixel rows as s as an example, in some embodiments, the correspondence between the count value and the number of pixel rows can be such that whenever the count value reaches s-1, the count value is reset to 0 according to the next pulse signal. In still other embodiments, the correspondence between the count value and the number of pixel rows can also be such that whenever the count value reaches s, the count value is reset to 1 according to the next pulse signal.

[0057] After detecting the frame change control signal, a frame change instruction is generated by counting the pulse signal. At this time, the first pulse signal can also be used to verify the timing of generating the frame change instruction, thereby further improving the accuracy of the timing.

[0058] The buffer 33 buffers display data in units of frames according to the frame change instruction Fr. When each frame of display picture is displayed, the display data of the display picture has been written into the buffer 33 and is read line by line.

[0059] Combine Figure 4 In an embodiment of the present application, the buffer 33 includes a first buffer area 33a and a second buffer area 33b. The buffer 33 performs ping-pong caching on the display data of the display screen in units of frames according to the selection signal SC. The selection signal SC has a first level and a second level. The selection signal SC jumps according to the last line break instruction of the current frame display screen. When the selection signal SC is at the first level, the display data of the current frame display screen is read line by line from the first buffer area 33a, and the display data of the next frame display screen is written into the second buffer area 33b; when the selection signal SC is at the second level, the display data of the current frame display screen is read line by line from the second buffer area 33b, and the display data of the next frame display screen is written into the first buffer area 33a. Similarly, cross-writing and reading of the first buffer area 33a and the second buffer area 33b are achieved, thereby improving the processing efficiency of the display data and ensuring the smoothness of the display screen.

[0060] The pulse width modulation unit 34 is configured to generate a pulse width modulation signal PWM according to the read row display data.

[0061] Combine Figure 5In the embodiment of the present application, the pulse width modulation unit 34 includes a subframe counter 34a, a breaking module 34b and a signal generating module 34c.

[0062] The subframe counter 34a is used to obtain the subframe sequence number of each subframe in the current frame display image. In some embodiments, the subframe counter 34a can be obtained by counting the line feed instruction ROW output by the control unit 32. The scattering module 34b obtains the subframe row data of the corresponding pixel row in each subframe based on the read row display data. Specifically, the scattering module 34b scatters the row display data into multiple subframe row data according to a preset scattering algorithm, and allocates these subframe row data to the corresponding subframe sequence number. The number of subframe row data is the same as the preset number of subframes, and the allocation method includes binary division. The signal generation module 34c provides a corresponding pulse width modulation signal PWM based on the subframe row data of each pixel row under the subframe sequence number corresponding to the current subframe.

[0063] The output unit 35 provides a corresponding driving signal to the display panel according to the row change command ROW and the frame change command Fr. Specifically, the output unit 35 provides a corresponding driving current Iout to each pixel according to the pulse width modulation signal PWM obtained under the corresponding row change command ROW and the frame change command Fr.

[0064] The display driver circuit of the present application generates continuous line break instructions based on a line break control signal having a continuous pulse signal, enabling the display panel to continuously scan and display, without being interrupted by whether or not a frame break control signal is received. This avoids the uneven exposure of each pixel row caused by a black screen while waiting for a frame break control signal, thereby eliminating bright and dark ripples during camera shooting and improving shooting effects. Furthermore, through the coordinated coordination of the frame break control signal and the line break control signal, the frame break timing can be precisely determined, avoiding display anomalies caused by timing errors.

[0065] Figure 6 Shown Figure 3 The following diagram illustrates operating waveforms of a display driver circuit in some embodiments. The frame change control signal Vsync, for example, has a width of 3 DCLKs, i.e., signal w3 shown in the figure. The first pulse signal has a first pulse width of 12 DCLKs, i.e., signal w12 shown in the figure. The second pulse signal has a second pulse width of 4 DCLKs, i.e., signal w4 shown in the figure.

[0066] References Figure 6 In the embodiment shown, the actual number of subframes of the first type of display screen is n-1, and the actual number of subframes of the second type of display screen is n. n>1 and is an integer, and can be calculated according to the following formula (1):

[0067] (1)

[0068] Where Tf is the preset frame period, i.e., the time interval between two adjacent frame change control signals Vsync. This preset frame period may be determined by the frame rate of the video source. Tr is the row scan period, R is the number of pixel rows on the display panel, INT indicates rounding down, and n is the preset number of subframes in the aforementioned scattering algorithm.

[0069] When obtaining the number of subframes n with reference to the above formula (1), the product of n and the subframe period is greater than the preset frame period. That is, the actual frame period of a single second-category display screen is greater than the preset frame period. In order to compensate for this timing deviation, some subframes need to be skipped in each first-category display screen. Preferably, when allocating subframe row data by binary division, the subframe sequence number increases with the display order of the subframes, and the subframe with the largest subframe sequence number is not displayed. For example, taking the example of breaking up a frame display screen into n subframes, namely the 0th subframe, the 1st subframe...the n-1th subframe, the subframe with the subframe sequence number n-1 is not displayed in each first-category display screen.

[0070] Furthermore, the subframe counter 34a can obtain the subframe sequence number according to the number of line break instructions ROW, that is, obtain the subframe sequence number according to the number of pulse signals of the line break control signal Hsync. When the display panel includes S pixel rows, each time the display driving circuit receives S pulse signals, that is, each time the control unit 32 generates S line break instructions ROW, the subframe counter 34a counts once, and the subframe sequence number increases by one. Until the control unit 32 receives the frame break control signal Vsync, and the count value of the multiple pulse signals of the line break control signal Hsync corresponds to the number of pixel rows, the subframe counter 34a is reset to 0. As described above, during the display process of one frame of display image, the count value of the multiple pulse signals of the line break control signal Hsync is reset with the number of pixel rows as a period. For example, referring to Figure 6 If the current display frame is of the first type, i.e., comprising n-1 subframes, subframe counter 34a increments sequentially from 0 to n-2 and is reset to 0 upon the next count change. If the current display frame is of the second type, i.e., comprising n subframes, subframe counter 34a increments sequentially from 0 to n-1 and is reset to 0 upon the next count change. In a preferred embodiment, subframe counter 34a is reset based on the last line break instruction of each display frame. This isolates subframe number changes from subframe switching, thus conserving computational resources in the driver circuit.

[0071] The select signal CS may also change based on the last line break instruction of the display image. Similarly, the control unit 32 may control the level of the select signal SC provided to the buffer 33 to change when it receives the frame break control signal Vsync and the count value of the multiple pulse signals of the line break control signal corresponds to the number of pixel rows.

[0072] Furthermore, to reduce the computational burden of the data driving circuit, the preset number of subframes can be calculated by the receiving card 10 and sent along with the serial data SI to the driving circuit 30. For example, after decoding the serial data, the shift register 31 sends the preset number of subframes to the pulse width modulation unit 34 via the control unit 32.

[0073] Figure 7 Shown Figure 3 The working waveform diagram of the display driving circuit in some other embodiments is shown. Figure 6 In the same embodiment shown, the frame change control signal Vsync has a width of 3 DCLKs, i.e., signal w3 shown in the figure. The first pulse width of the first pulse signal has a width of, for example, 12 DCLKs, i.e., signal w12 shown in the figure. The second pulse width of the second pulse signal has a width of, for example, 4 DCLKs, i.e., signal w4 shown in the figure.

[0074] and Figure 6 The embodiment shown differs in that Figure 7 In the embodiment shown, the actual number of subframes of the first type of display screen is m, and the actual number of subframes of the second type of display screen is m+1. m≥1 and is an integer, and can be calculated according to the following formula (2):

[0075] (2)

[0076] Where Tf is the preset frame period, i.e., the time interval between two adjacent frame change control signals Vsync. This preset frame period may be determined by the frame rate of the video source. Tr is the row scan period, R is the number of pixel rows on the display panel, INT indicates rounding down, and m is the preset number of subframes in the aforementioned scattering algorithm.

[0077] When obtaining the number of subframes m by referring to the above formula (2), the product of the preset number of subframes and the subframe period is less than the preset frame period. That is, the actual frame period of a single first-category display screen and a second-category display screen is less than the preset frame period. In order to further compensate for the timing deviation in the display, some subframes need to be displayed repeatedly in each second-category display screen. In some embodiments, when allocating subframe row data by binary division, the subframe with the largest subframe number is displayed repeatedly. Preferably, the subframe number decreases with the display order of the subframes, and after m subframes are displayed in sequence, the subframe with the largest subframe number is displayed repeatedly in the last subframe. That is, taking the example of breaking up a frame display screen into m subframes, namely, the 0th subframe, the 1st subframe...the m-1th subframe, in each second-category display screen, the m-1th subframe, the m-2th subframe are displayed in sequence until the 0th subframe is displayed and the m-1th subframe is displayed repeatedly.

[0078] Furthermore, Figure 6 The same embodiment as shown, when the control unit 32 receives the frame change control signal Vsync and the count value of the multiple pulse signals of the line change control signal corresponds to the number of pixel rows, the sub-frame counter 34a is reset and the level of the control selection signal SC is changed. Figure 6 The embodiment shown is different in that, as described above, when the scattering module 34b adopts the binary subframe data allocation method, in order to further improve the uniformity of display, Figure 7 In the embodiment shown, the subframe counter 34a adopts a counting method of reverse counting. Figure 7 In the illustrated embodiment, the reset value of the subframe counter 34a corresponds to the preset number of subframes. Specifically, when the minimum count value of the subframe counter 34a in reverse order is 0, the reset value of the subframe counter 34a is m-1. Each time S line break commands are sent, the subframe counter is decremented by one until the count value of the subframe counter 34a reaches 0, indicating that m subframes have been displayed.

[0079] It should be noted that, in the preferred embodiment described above, where a display frame is broken down into m subframes, namely, the 0th subframe, the 1st subframe, and finally the m-1th subframe, for example, in each second-type display frame, the m-1th subframe and the m-2th subframe are sequentially displayed until the 0th subframe is displayed and then the m-1th subframe is repeatedly displayed. When the current display frame is displayed, the subframe counter 34a decrements from m-1 to 0 and then returns to m-1, at which point the subframe with the largest subframe number is repeatedly displayed. The count value remains at m-1 at the next count value change.

[0080] The present application also provides a chip, for example, including the display driving circuit as described above. The present application also provides a display device, including a display panel and the chip as described above.

[0081] According to the display driver circuit, chip, and display device of the present application, continuous line break instructions are generated based on a line break control signal having a continuous pulse signal, enabling the display panel to continuously scan and display, without being interrupted by whether or not a frame break control signal is received. This avoids the uneven exposure of each pixel row caused by a black screen while waiting for the frame break control signal, thereby eliminating bright and dark ripples during camera shooting and improving the shooting effect. Furthermore, through the coordinated cooperation of the frame break control signal and the line break control signal, the frame break timing can be precisely determined, avoiding display anomalies caused by timing errors.

[0082] Furthermore, when scanning and displaying with a fixed subframe period, the mismatch between the data transmission timing and the display timing of the display screen is compensated by adjusting the number of subframes in part of the display screen, which can avoid display anomalies caused by timing mismatch and help improve display stability.

[0083] Figure 8 Schematic flow chart of the display driving method of the embodiment of the present application is shown. The display driving method provided by the present application can be implemented according to the above-mentioned display driving circuit. Figure 8 , the driving method provided in this application includes:

[0084] Step S11: receiving a line feed control signal, where the line feed control signal includes a plurality of continuous pulse signals.

[0085] Step S12: generating a line break instruction according to the pulse signal of the line break control signal, and displaying the corresponding pixel row according to the line break instruction.

[0086] Because the pulse signals in the line break control signal are continuous, the generated line break commands are also continuous. This means that the generation of line break commands is not interrupted by the receipt of a frame break control signal. The display panel will not display a black screen due to line break command interruptions. This prevents bright and dark ripples and image flickering caused by the overlap of the shutter exposure cycle and the frame interval when shooting with a camera, improving shooting quality.

[0087] In some embodiments, the refresh rate is increased by splitting each frame of display into multiple subframes for display. Accordingly, the display driving method further includes breaking up the display data of each frame of display according to a preset number of subframes. Specifically, the row display data of each pixel row in a frame of display may be broken up to obtain multiple subframe row data, and the subframe row data may be assigned to corresponding subframe sequence numbers. The number of subframe row data is the same as the preset number of subframes, and the assignment method includes a binary search method.

[0088] However, if the number of subframes and the subframe period of each display frame are the same, during the continuous scanning and display process, the data transmission timing and display timing of the display frame will be mismatched, resulting in display anomalies. In order to further solve this problem, in a preferred embodiment, the number of subframes in some display frames can be adjusted to compensate for the mismatch between the data transmission timing and the display timing of the display frame. Specifically, the display frame includes a first type of display frame and a second type of display frame with different numbers of subframes. The actual number of subframes of the first type of display frame is less than the actual number of subframes of the second type of display frame, and at least one first type of display frame is included between two adjacent second type display frames. When the subframe period is fixed, the timing mismatch is compensated by adjusting the number of subframes in some display frames to avoid display anomalies caused by timing mismatch.

[0089] Furthermore, in some embodiments, the actual number of subframes of the first type of display screen is n-1, and the actual number of subframes of the second type of display screen is n. n>1 and is an integer, and can be calculated with reference to the above formula (1). In this case, n is also the preset number of subframes. Accordingly, the counting and resetting of the subframe sequence number and the level control of the selection signal can also refer to the above formula (1). Figure 6 Description.

[0090] In some other embodiments, the actual number of subframes of the first type of display screen is m, and the actual number of subframes of the second type of display screen is m+1. m≥1 and is an integer, and can be calculated with reference to the above formula (2). In this case, m is also the preset number of subframes. Accordingly, the counting and resetting of the subframe sequence number and the level control of the selection signal can also refer to the above formula (2). Figure 7 Description.

[0091] Continuous scanning display will also make the actual frame period of a frame display picture different from the preset frame period. That is to say, the product of the number of subframes actually displayed in each frame display picture and the subframe period is different from the preset frame period. If the frame change instruction is still generated according to the frame change control signal, a forced frame change will occur in the middle of the display, resulting in screen tearing. Therefore, in a preferred embodiment, the multiple pulse signals of the line break control signal Hsync may include a first pulse signal with a first pulse width and a second pulse signal with a second pulse width. The first pulse signal and the second pulse signal indicate different types of line break operations. For example, the first pulse signal is used to indicate the switching of two adjacent frames of display pictures, that is, switching the last pixel row of the current frame display picture to the first pixel row of the next frame display picture. The second pulse signal is used to indicate the switching of pixel rows within the same frame display picture. Accordingly, the display driving method provided in the present application also includes the following steps S13 and S14.

[0092] Step S13: determine whether a frame change control signal is obtained, and execute step S14 when a frame change control signal is obtained.

[0093] In step S14 , a frame change instruction is generated according to the count value of the line change control signal, and a driving signal for the next frame of display image is output according to the frame change instruction.

[0094] Through the coordinated cooperation of the frame change control signal and the line change control signal, the frame change timing can be accurately located, avoiding the screen tearing caused by forced frame change when the frame change control signal arrives during the continuous scanning display process, which is beneficial to improving the display stability.

[0095] For example, when displaying each subframe, the number of pulse signals of the line break control signal may be counted to obtain a count value. After receiving the frame break control signal, a determination is made as to whether the count value equals the number of pixel rows. If the count value equals the number of pixel rows, a frame break instruction is generated. In other words, the frame break instruction is generated after the frame break control signal is detected and the display of the current display image is completed.

[0096] In the above example where a pulse signal count equal to the number of pixel rows is used as one of the conditions for generating a frame change instruction, the count value needs to be reset after each subframe is displayed. Specifically, whenever the count value corresponds to the number of pixel rows, a determination is made as to whether the next pulse signal has been detected, and the count value is reset when the next pulse signal is detected. For example, the count value may be reset upon receiving a frame change control signal and detecting the first pulse signal.

[0097] After detecting the frame change control signal, a frame change instruction is generated by counting the pulse signal. At this time, the first pulse signal can also be used to verify the timing of generating the frame change instruction, thereby further improving the accuracy of the timing.

[0098] According to the display driving method of the present application, continuous line break instructions are generated based on a line break control signal having a continuous pulse signal, enabling the display panel to continuously scan and display, without being interrupted by whether or not a frame break control signal is received. This avoids the uneven exposure of each pixel row caused by a black screen while waiting for the frame break control signal, thereby eliminating bright and dark ripples during camera shooting and improving the shooting effect. At the same time, through the coordinated cooperation of the frame break control signal and the line break control signal, the frame break timing can be accurately determined, avoiding display anomalies caused by timing errors.

[0099] Furthermore, when scanning and displaying with a fixed subframe period, the mismatch between the data transmission timing and the display timing of the display screen is compensated by adjusting the number of subframes in part of the display screen, which can avoid display anomalies caused by timing mismatch and help improve display stability.

[0100] It should be noted that the display driving method provided in the present application can be implemented by the display driving circuit provided in the present application. Although not described in detail, it should be understood that the display driving method provided in the present application can also include relevant steps to control the corresponding structures in the above-mentioned display driving circuit to achieve corresponding functions.

[0101] The embodiments of the present application are as described above, and these embodiments do not describe all details in detail, nor do they limit the present application to specific embodiments. Obviously, based on the above description, many modifications and variations can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The scope of protection of the present application shall be based on the scope defined by the claims of the present application.

Claims

1. A display driving method, wherein: include: receiving a line feed control signal, wherein the line feed control signal includes a plurality of continuous pulse signals; generating a line break instruction according to the pulse signal of the line break control signal, and displaying the corresponding pixel row according to the line break instruction, in, The display driving method further includes: After receiving the frame change control signal, a frame change instruction is generated according to the count value of the plurality of pulse signals of the line change control signal, and a drive signal for the next frame of the display image is output according to the frame change instruction. The display screen includes a first type of display screen and a second type of display screen, The actual number of subframes of the first type of display picture is less than the actual number of subframes of the second type of display picture, There is at least one first-category display screen between two adjacent second-category display screens.

2. The display driving method according to claim 1, wherein: Each frame of the display picture includes multiple sub-frames, The display driving method further includes: The display data of each frame of display image is scattered according to the preset number of sub-frames.

3. The display driving method according to claim 2, wherein: The actual number of subframes of the first type of display picture is n-1, and the actual number of subframes of the second type of display picture is n. ， Tf is the preset frame period, Tr is the row scanning period, R is the number of pixel rows on the display panel, and INT means rounding down. Here, n is also the preset number of subframes, n>1 and is an integer.

4. The display driving method according to claim 2, wherein: The actual number of subframes of the first type of display picture is m, and the actual number of subframes of the second type of display picture is m+1. ， Tf is the preset frame period, Tr is the row scanning period, R is the number of pixel rows on the display panel, and INT means rounding down. Here, m is also the preset number of subframes, m≥1 and is an integer.

5. The display driving method according to claim 3 or 4, wherein: The plurality of pulse signals include a first pulse signal having a first pulse width and a second pulse signal having a second pulse width, wherein the first pulse signal further indicates pixel row switching between frames. The step of generating a frame change instruction according to a count value of the line change control signal after receiving the frame change control signal comprises: When displaying each of the subframes, counting the plurality of pulse signals of the line feed control signal to obtain the count value; and After receiving the frame change control signal, it is determined whether the count value corresponds to the number of pixel rows, and the frame change instruction is generated when the count value corresponds to the number of pixel rows.

6. The display driving method according to claim 5, wherein: The step of obtaining the count value further comprises: determining whether a next pulse signal is detected after the count value corresponds to the number of pixel rows; and The count value is reset after the next pulse signal is detected.

7. The display driving method according to claim 5, wherein: The step of breaking up the display data of each frame of the display image according to the preset number of sub-frames includes: Scattering the row display data of each pixel row in each frame of the display image to obtain the preset number of sub-frame row data; Allocate each subframe row data to a corresponding subframe sequence number.

8. The display driving method according to claim 7, wherein: The method of allocating each subframe row data to the corresponding subframe sequence number includes a binary method, When the product of the preset number of subframes and the subframe period is greater than the preset frame period, in each frame of the display image, the subframe number increases in accordance with the display order of the subframes, and the subframe number is reset when the frame change control signal is received and the count value is equal to the number of pixel rows; When the product of the preset number of subframes and the subframe period is less than the preset frame period, in each frame of the display image, the subframe number decreases with the display order of the subframes, and the subframe number is reset when the frame change control signal is received and the count value is equal to the number of pixel rows.

9. The display driving method according to claim 8, wherein: When the product of the preset number of subframes and the subframe period is greater than the preset frame period, the subframe row data corresponding to the largest subframe sequence number is not displayed in the first type of display image; When the product of the preset number of subframes and the subframe period is less than the preset frame period, in the second type of display image, the subframe row data corresponding to the largest subframe sequence number is repeatedly displayed in two subframes.

10. A display driving circuit, wherein: include: a control unit, configured to receive a line feed control signal and a frame feed control signal, the line feed control signal comprising a plurality of continuous pulse signals, the control unit further configured to generate a line feed instruction according to the pulse signal of the line feed control signal, and to generate a frame feed instruction according to a count value of the line feed control signal after receiving the frame feed control signal; An output unit, configured to drive the corresponding pixel row for display according to the line-change instruction, or output a drive signal for the next frame of display according to the frame-change instruction, The display screen includes a first type of display screen and a second type of display screen. The actual number of subframes of the first type of display picture is less than the actual number of subframes of the second type of display picture, There is at least one first-category display screen between two adjacent second-category display screens.

11. A chip, wherein: comprising the driving circuit as claimed in claim 10.

12. A display device, wherein: include: Display panel; as well as The chip according to claim 11, configured to provide a driving signal for the display panel.

Images