Display control method, circuit, chip, and display device

Abstract

The present application discloses a display control method, circuit, chip, and display device. The display control method includes: obtaining multiple frame change control signals; obtaining a preset frame period based on the time interval between two adjacent frame change control signals; obtaining a preset number of subframes in each frame display image based on the preset frame period; obtaining the actual number of subframes in each frame display image based on the preset number of subframes; and generating a line change control signal based on the frame change control signal and the actual number of subframes in each frame display image, wherein the line change control signal includes multiple continuous pulse signals, each pulse signal is used to control the display of a corresponding pixel row of the display panel, wherein the multiple pulse signals include a first pulse signal with a first pulse width and multiple second pulse signals with a second pulse width located between adjacent first pulse signals, and the first pulse signal is used to indicate the switching of adjacent frame display images. This can eliminate the bright and dark ripples and flickering of the captured image.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display control method, circuit, chip, and display device. Background Art

[0002] At present, LED display panels have become one of the mainstream of modern display technology with their advantages such as high brightness, high resolution, energy saving and high efficiency, unlimited splicing, good viewing angle and high reliability.

[0003] LED display panels consist of pixels arranged in an array. These pixels are scanned row by row during display. During rapid scanning, the human eye's persistence of vision is leveraged to present a complete image. Furthermore, a frame interval is typically set between adjacent frames, creating a period of inactivity. This prevents data conflicts between adjacent frames, thereby ensuring the integrity of the displayed image.

[0004] When photographing an LED display panel, the camera captures pixels that are lit and emitting sufficient light during the exposure time. If the camera's exposure cycle is inconsistent or out of sync with the frame rate of the LED display panel's video source, the exposure cycle and frame interval may overlap, causing bright and dark ripples in the image. Furthermore, as the camera continues to expose, the overlap between the exposure cycle and frame interval may gradually increase, causing a flickering effect in the image and affecting the quality of the shot. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a display control method and circuit, chip, and display device to eliminate the bright and dark ripples and flickering in the captured image.

[0006] According to one aspect of the present application, a display control method is provided, which includes: obtaining multiple frame change control signals; obtaining a preset frame period based on the time interval between two adjacent frame change control signals; obtaining a preset number of subframes in each frame display screen based on the preset frame period; obtaining the actual number of subframes in each frame display screen based on the preset number of subframes; and generating a line break control signal based on the frame change control signal and the actual number of subframes in each frame display screen, the line break control signal including a plurality of continuous pulse signals, each pulse signal being used to control the display of a corresponding pixel row of a display panel, wherein the plurality of pulse signals include a first pulse signal having a first pulse width and a plurality of second pulse signals having a second pulse width located between adjacent first pulse signals, the first pulse signal being used to indicate the switching of adjacent frame display screens.

[0007] Optionally, the display screen includes a first type of display screen and a second type of display screen, the actual number of subframes in the first type of display screen is less than the actual number of subframes in the second type of display screen, and at least one first type of display screen is included between two adjacent second type of display screens.

[0008] Optionally, the actual number of subframes in the first type of display picture is n-1, and the actual number of subframes in the second type of display picture is n.

[0009]

[0010] Tf is the preset frame period, Tr is the row scanning period, R is the number of pixel rows of the display panel, INT represents rounding down, and n is also the preset number of subframes, n>1 and is an integer.

[0011] Optionally, the actual number of the subframes in the first type of display picture is m, and the actual number of the subframes in the second type of display picture is m+1.

[0012]

[0013] Tf is the preset frame period, Tr is the row scanning period, R is the number of pixel rows of the display panel, INT represents rounding down, and m is also the preset number of subframes, m≥1 and is an integer.

[0014] Optionally, the step of generating a line break control signal includes: generating a first first pulse signal based on the first frame break control signal, the first first pulse signal being phase-adapted to the first frame break control signal; after generating the first first pulse signal, generating a second pulse signal after each line scan cycle; and generating the next first pulse signal after counting a first number of the second pulse signals, the first number being one less than the product of the actual number of the subframes in the corresponding display screen and the number of pixel rows.

[0015] Optionally, the display control method further includes: generating a serial decoding input signal according to the number of pulse signals of the line feed control signal and the number of pixel rows, wherein the serial decoding input signal is used to sequentially open the pixel rows.

[0016] Optionally, the serial decoding input signal includes a plurality of continuous third pulse signals, and the step of generating the serial decoding input signal includes: generating the first third pulse signal according to the first line break control signal; after the first third pulse signal, generating the next third pulse signal by counting a second number of the second pulse signals, where the second number is one less than the number of pixel rows.

[0017] Optionally, the multiple frame change control signals are obtained according to a video source, and the step of obtaining the multiple frame change control signals includes: decoding the video source to obtain the frame change control signals; or calculating and obtaining the frame change control signals according to a frame rate of the video source.

[0018] According to another aspect of the present application, a display control circuit is provided, which includes: a frame change control signal acquisition unit for obtaining multiple frame change control signals; a processing unit for obtaining a preset frame period according to the time interval between two adjacent frame change control signals, and obtaining a preset number of subframes in each frame display picture according to the preset frame period, and the processing unit is further used to obtain the actual number of subframes in each frame display picture according to the preset number of subframes; a line break control signal generation unit for generating a line break control signal according to the frame change control signal and the actual number of subframes in each frame display picture, the line break control signal including a plurality of continuous pulse signals, each pulse signal being used to control the display of a corresponding pixel row of the display panel, wherein the plurality of pulse signals include a first pulse signal having a first pulse width and a plurality of second pulse signals having a second pulse width located between adjacent first pulse signals, and the first pulse signal is used to indicate the switching of adjacent frame display pictures.

[0019] According to a third aspect of the present application, a chip is provided, which includes the display control circuit as described above.

[0020] According to a fourth aspect of the present application, a display device is provided, comprising: a display panel; and the display control circuit as described above, for controlling the display of the display panel.

[0021] According to the display control method, circuit, chip, and display device of the present application, the line break control signal has a continuous pulse signal, so that the display panel is continuously scanned and displayed, and the display will not be interrupted by whether the frame break control signal is obtained. This avoids the different exposure levels of each pixel row caused by displaying a black screen while waiting for the frame break control signal, thereby eliminating the bright and dark ripples when the camera is shooting, which is beneficial to improving the shooting effect.

[0022] Furthermore, when scanning and displaying with a fixed subframe period, the mismatch between the data transmission timing and the display timing of the display screen is compensated by adjusting the number of subframes in part of the display screen, which can avoid display anomalies caused by timing mismatch and help improve display stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0024] Figure 1A schematic structural diagram of a display device is shown;

[0025] Figure 2 A schematic timing diagram showing subframe driving;

[0026] Figure 3 A schematic flow chart showing a display control method according to an embodiment of the present application is shown;

[0027] Figure 4 shows a schematic waveform diagram of a line feed control signal in some embodiments of the present application;

[0028] Figure 5 Schematic waveform diagrams of line feed control signals in some other embodiments of the present application are shown;

[0029] Figure 6 A schematic structural diagram of a display control circuit according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0031] Certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different terms to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in their functions.

[0032] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0033] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0034] It should also be noted that, in the various methods and processes of the present application, the size of the step numbers does not mean the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of the present application.

[0035] Figure 1 Schematic diagram of the structure of the display device is shown. Figure 1 The display device is, for example, an LED display device, which includes a receiving card 10 , a scan driving circuit 20 , a data driving circuit 30 and a display panel 40 .

[0036] The receiving card 10 is connected to the scan driver circuit 20 and the data driver circuit 30, respectively. It is configured to provide a first timing signal to the scan driver circuit 20 based on externally provided image data and control signals, and to provide a second timing signal and display data to the data driver circuit 30. The scan driver circuit 20 outputs a scan signal based on the first timing signal, and the data driver circuit 30 converts the display data into a drive signal based on the second timing signal and outputs the result.

[0037] It should be noted that the first and second timing signals described above should be understood as a general term for a class of signals rather than individual signals. For example, the first timing signal may include the line feed control signal DCK, the register clock RCK, and the serial decoder input signal SDI provided to the scan driver circuit 20. The second timing signal may include the reference clock DCLK, the line feed control signal Hsync, and the frame feed control signal Vsync provided to the data driver circuit 30. In a preferred embodiment, the frame feed control signal Vsync is typically transmitted as the command signal LE. Pulses of different pulse widths in the command signal LE may represent, for example, the frame feed control signal Vsync, a data latch instruction, a write register instruction, and the like.

[0038] Furthermore, the line feed control signal DCK sent to the scan driving circuit 20 and the line feed control signal Hsync sent to the data driving circuit 30 should be compatible, so that the scan driving circuit 20 and the data driving circuit 30 work together to achieve progressive scanning driving of the display panel.

[0039] The display panel 40 includes multiple pixel rows, multiple data lines, and multiple scan lines. Each pixel row includes multiple pixels, each of which is connected to the data driver circuit 30 via a corresponding data line and to the scan driver circuit 20 via a corresponding scan line. Each pixel turns on when the scan signal received via the scan line has an active level and displays according to the drive signal received via the data line.

[0040] To increase the refresh rate, a subframe drive method is preferably used to drive the display panel. This involves dividing a display frame into multiple subframes, and then sequentially driving each pixel row within each subframe to display the corresponding subframe row data. Assuming the display panel includes s pixel rows, each display frame contains k subframes. Figure 2 Schematic timing diagram of sub-frame driving is shown in FIG. Figure 2 As shown in the figure, the entire display process of the i-th frame display picture is: the first row of the 1st subframe, the second row of the 1st subframe to the s-th row of the 1st subframe are displayed in sequence, and the luminous brightness of each pixel row in its corresponding row display stage corresponds to the subframe row data of the pixel row in the 1st subframe; then the first row of the 2nd subframe is displayed, the second row of the 2nd subframe... and so on, until the display of all k subframes is completed.

[0041] The present application provides a display control method, which enables a display panel to continuously scan and display by generating a line break control signal including multiple continuous pulse signals, and is not limited by whether the frame break control signal is obtained and the display is interrupted. It avoids the different exposure levels of each pixel row caused by displaying a black screen while waiting for the frame break control signal, thereby eliminating the bright and dark ripples when the camera is shooting, which is beneficial to improving the shooting effect.

[0042] Figure 3 The schematic flow chart of the display control method of the embodiment of the present application is shown. The display control method provided by the present application is implemented, for example, by the receiving card 10. Figure 3 , the display control method provided by this application includes:

[0043] Step S11, obtaining multiple frame change control signals;

[0044] Step S12, obtaining a preset frame period according to the time interval between two adjacent frame change control signals;

[0045] Step S13, obtaining a preset number of subframes in each frame display image according to a preset frame period;

[0046] Step S14, obtaining the actual number of subframes in each display image according to the preset number of subframes;

[0047] Step S15, generating a line change control signal according to the frame change control signal and the actual number of subframes in each frame of the display image;

[0048] Step S16 , generating a serial decoding input signal according to the number of pulse signals of the line feed control signal and the number of pixel rows.

[0049] The above steps are further explained below.

[0050] Step S11 may be to obtain a frame change control signal based on the video source. Specifically, in some embodiments, step S11 may be to obtain the frame change control signal by decoding the video source received by the display device. In still other embodiments, step S11 may also be to obtain the frame change control signal by calculating the frame rate of the video source.

[0051] The duration between two adjacent frame change control signals is the preset frame period obtained in step S12.

[0052] In traditional display control methods, the display of adjacent frames is switched according to the frame change control signal. When each frame is displayed, the number of line change control signals is fixed, corresponding to the number of subframes in the display and the number of pixel rows on the display panel. After generating this fixed number of line change control signals, the generation of line change control signals ceases until the next frame change control signal is received. During the period when no line change control signals are generated, the display panel displays a black screen. This black screen period is usually referred to as the frame interval. When using a camera to capture the display panel, if the shutter exposure period overlaps with the frame interval, it will cause bright and dark ripples in the image, and the screen will flicker when capturing continuous images.

[0053] To address this issue, in an embodiment of the present application, the subsequently generated line break control signal comprises multiple continuous pulse signals. This means that the generation of the line break control signal is not interrupted by the receipt of a frame break control signal, and the display panel will not display a black screen due to an interruption in the line break control signal. This prevents the bright / dark ripples and image flickering caused by the overlap of the shutter exposure cycle and the frame interval when shooting with a camera, thereby improving the shooting quality.

[0054] Furthermore, in step S13, the preset frame period is divided into a preset number of subframes based on the set row scanning period and the number of pixel rows in the display image. In the subframe-driven display method, the row display data of the pixel rows is broken up using a preset breaking up algorithm to obtain a number of subframe row data equal to the preset number of subframes. The subframe row data is then assigned to corresponding subframe numbers using a method such as binary division. The subframe numbers correspond to the display order of the subframes.

[0055] If the number of subframes and the subframe period of each display frame are the same, during the continuous scanning and display process, the data transmission timing and display timing of the display frame will be mismatched, resulting in display anomalies.

[0056] To further address this issue, in step S14, the mismatch between the data transmission timing and the display timing of the display screen is compensated by adjusting the actual number of subframes displayed in a portion of the display screen. Specifically, the display screen includes a first type of display screen and a second type of display screen. The actual number of subframes in the first type of display screen is less than the actual number of subframes in the second type of display screen, and at least one first type of display screen is located between two adjacent second type of display screens. When the subframe period is fixed, the timing mismatch is compensated by adjusting the actual number of subframes in a portion of the display screen, thereby avoiding display anomalies caused by the timing mismatch.

[0057] The actual number of subframes in each display frame can also be calculated based on the preset frame period, row scanning period, and the number of pixel rows on the display panel. The calculation method is described in detail below. When the subframe period is fixed, at least one first-category display image is displayed between two adjacent second-category display images to compensate for any mismatch between the data transmission timing and the display timing of the display images, thus avoiding display anomalies caused by the timing mismatch.

[0058] Continuous scanning can also cause the actual frame period of a displayed frame to differ from the preset frame period, that is, the time interval between two adjacent frame change control signals. If the frame change control signal is still used to indicate the switching of adjacent display frames, a forced frame change will occur mid-display, resulting in screen tearing.

[0059] Therefore, in an embodiment of the present application, the multiple pulse signals of the line feed control signal may include a first pulse signal having a first pulse width and a second pulse signal having a second pulse width located between adjacent first pulse signals. Each pulse signal is used to control the display of a corresponding pixel row of the display panel, and the first pulse signal is also used to indicate the switching of adjacent display images.

[0060] Specifically, step S15 further includes: generating a first first pulse signal according to the first frame change control signal, the first first pulse signal being phase-matched with the first frame change control signal; generating a second pulse signal after each row scan period after the first first pulse signal is generated; and generating a next first pulse signal after counting a first number of second pulse signals. The first number is one less than the product of the actual number of subframes in the corresponding frame display image and the number of pixel rows.

[0061] It should be noted that the first first pulse signal is phase-matched with the first frame change control signal, and the rising edge of the first first pulse signal is aligned with the falling edge of the first frame change control signal, or the rising edge of the first first pulse signal lags behind the falling edge of the first frame change control signal by several clock cycles of the reference clock.

[0062] The line break control command generated by the display control method of the present application can be used to indicate line switching between frames using a first pulse signal, i.e., switching from the last row of pixels displaying the current frame to the first row of pixels displaying the next frame. It is also possible to indicate line switching within a frame using a second pulse signal. Accordingly, the frame break control signal is used to separate the display data of adjacent frames during data transmission.

[0063] Furthermore, since the first pulse signal should lag behind the frame change control signal, in some embodiments, the correctness of the timing can be further verified by the phase relationship between the frame change control signal and the first pulse signal.

[0064] The line feed control signal may include the line feed control signal DCK sent to the scan driving circuit 20 and the line feed control signal Hsync sent to the data driving circuit 30 as described above. The line feed control signal DCK and the line feed control signal Hsync have the same period, and their phase relationship may be advanced, identical, or delayed.

[0065] In some embodiments, the display control method provided herein further includes generating the aforementioned serial decode input signal SDI, which is sent to the scan driver circuit 20, in step S16. The serial decode input signal SDI is used to reset the pixel rows to be displayed. After receiving the serial decode input signal SDI, the scan driver circuit 20 controls the pixel rows to be turned on sequentially, starting with the first row.

[0066] The serial decoding input signal SDI includes a plurality of continuous third pulse signals, and the third pulse signal has, for example, a third pulse width. The steps of generating the serial decoding input signal SDI may include:

[0067] A first third pulse signal is generated according to the first line break control signal. The phase of the first third pulse signal is the same as the phase of the first line break control signal. For example, the rising edge of the first line break control signal may be aligned with the rising edge of the first third pulse signal.

[0068] After generating the first third pulse signal, the next third pulse signal SDI is generated by counting a second number of second pulse signals. The second number is one less than the number of pixel rows. In other words, the phase of the serial decoded input signal is the same as the phase of the first line feed control signal in each subframe.

[0069] Figure 4 Schematic waveform diagram of line feed control signal in some embodiments of the present application is shown. Figure 4 The frame change control signal Vsync, for example, has a width of 3 DCLKs, namely, the w3 signal shown in the figure. The first pulse width of the first pulse signal, for example, has a width of 12 DCLKs, namely, the w12 signal shown in the figure; the second pulse width of the second pulse signal, for example, has a width of 4 DCLKs, namely, the w4 signal shown in the figure; and the third pulse width of the third pulse signal in the serial decoding input signal SDI, for example, has a width of 1 DCLK, namely, the w1 signal shown in the figure. DCLK can be a reference clock in the receiving card. In some embodiments, counting the above-mentioned first and second quantities, that is, the transmission timing of each pulse signal in the above-mentioned line change control signal and serial decoding input signal, can be obtained by counting DCLK. Furthermore, DCLK is obtained by dividing the preset frame period, or it can be independently generated within the receiving card 10.

[0070] In such Figure 4 In the embodiment shown, the actual number of subframes in the first type of display picture is n-1, and the actual number of subframes in the second type of display picture is n. n>1 and is an integer, and can be calculated according to the following formula (1):

[0071] (1)

[0072] Where Tf is the preset frame period, i.e., the time interval between two adjacent frame change control signals; Tr is the row scan period; R is the number of pixel rows on the display panel; and INT indicates rounding down. n is also the preset number of subframes, i.e., the number of subframe rows after each row of display data is broken up.

[0073] When calculating with reference to the above formula (1), the product of n and the subframe period is greater than the preset frame period. That is, the actual frame period of a single second-category display screen is greater than the preset frame period. In order to compensate for this timing deviation, some subframes need to be skipped in each first-category display screen. Preferably, when allocating subframe row data by binary division, the subframe sequence number increases with the display order of the subframes, and the subframe with the largest subframe sequence number is not displayed. For example, Figure 4 As shown, taking the example of breaking up a display frame into n subframes, namely the 1st subframe, the 2nd subframe, ... the nth subframe, in each first type of display frame, the subframe with subframe sequence number n is not displayed.

[0074] Furthermore, the number of first-category display pictures between two adjacent second-category display pictures may be determined according to the difference between an actual frame period of a single second-category display picture and a preset frame period, as well as a sub-frame period.

[0075] The serial decoded input signal SDI has the same phase as the line feed control signal Hsync of the first line of each subframe.

[0076] Figure 5 Schematic waveform diagrams of line feed control signals in some other embodiments of the present application are shown. Figure 5 In, with Figure 4 The embodiment shown is the same, and the frame change control signal Vsync also has a width of 3 DCLKs, the first pulse width of the first pulse signal has a width of 12 DCLKs, and the second pulse width of the second pulse signal has a width of 4 DCLKs as an example. Figure 5 The serial decoder input signal SDI is hidden in the figure.

[0077] and Figure 4 The embodiment shown differs in that Figure 5 In the example, the actual number of subframes in the first type of display screen is m, and the actual number of subframes in the second type of display screen is m+1. m≥1 is an integer and can be calculated according to the following formula (2):

[0078] (2)

[0079] Where Tf is the preset frame period, i.e., the time interval between two adjacent frame change control signals; Tr is the row scan period; R is the number of pixel rows on the display panel; and INT indicates rounding down. m is also the preset number of subframes, i.e., the number of subframe rows after each row of display data is broken up.

[0080] When calculating with reference to the above formula (2), the product of m and the subframe period is less than the preset frame period. That is, the actual frame period of a single first-category display screen and a second-category display screen is less than the preset frame period. In order to further compensate for the timing deviation in the display, some subframes need to be displayed repeatedly in each second-category display screen. In some embodiments, when allocating subframe row data by binary division, the subframe with the largest subframe number is displayed repeatedly. Preferably, referring to Figure 5 The subframe numbers decrease in the order in which the subframes are displayed. After m subframes are displayed in sequence, the subframe with the largest subframe number is repeated as the last subframe. In other words, taking a display frame as an example, where the display is broken up into the 1st, 2nd, ...mth subframes, in each second-type display frame, the mth subframe, then the m-1th subframe are displayed in sequence, until the mth subframe is repeated after the 1st subframe.

[0081] Likewise, the number of first-category display pictures between two adjacent second-category display pictures may be determined according to the difference between the actual frame period of a single second-category display picture and the preset frame period, as well as the sub-frame period.

[0082] According to the display control method of the present application, the line break control signal has a continuous pulse signal, so that the display panel is continuously scanned and displayed, and the display will not be interrupted by whether the frame break control signal is obtained. This avoids the different exposure levels of each pixel row caused by displaying a black screen while waiting for the frame break control signal, thereby eliminating the bright and dark ripples when the camera is shooting, which is beneficial to improving the shooting effect.

[0083] Furthermore, when scanning and displaying with a fixed subframe period, the mismatch between the data transmission timing and the display timing of the display screen is compensated by adjusting the number of subframes in part of the display screen, which can avoid display anomalies caused by timing mismatch and help improve display stability.

[0084] The present application also provides a display control circuit. The display control circuit can implement the above-mentioned display control method. In some embodiments, the display control circuit provided by the present application can be integrated into the receiving card 10. Figure 6 Schematic diagram of the structure of the display control circuit of the embodiment of the present application is shown. Figure 6 , the display control circuit includes:

[0085] The frame change control signal acquisition unit 110 is configured to obtain multiple frame change control signals. In some embodiments, the frame change control signal acquisition unit 110 may obtain the multiple frame change control signals based on the acquired video source by referring to the method corresponding to step S11 described above. The frame change control signals are used to separate display data of adjacent frames during data transmission.

[0086] The processing unit 120 is used to obtain a preset frame period based on the time interval between two adjacent frame change control signals, and obtain a preset number of subframes in each frame display image based on the preset frame period. The processing unit is also used to obtain the actual number of subframes in each frame display image based on the preset number of subframes.

[0087] The display screen includes a first type of display screen and a second type of display screen having different actual numbers of subframes, wherein the actual number of subframes in the first type of display screen is smaller than the actual number of subframes in the second type of display screen, and at least one first type of display screen is included between two adjacent second type of display screens.

[0088] The number of subframes of the first type of display picture and the second type of display picture can be calculated by referring to the above formula (1) or (2).

[0089] The line-change control signal generating unit 130 generates a line-change control signal according to the frame-change control signal and the actual number of subframes in each display frame.

[0090] In an embodiment of the present application, the line feed control signal includes a plurality of continuous pulse signals, each pulse signal being used to control the display of a corresponding pixel row of the display panel. The plurality of pulse signals include a first pulse signal having a first pulse width and a plurality of second pulse signals having a second pulse width located between adjacent first pulse signals. The first pulse signal is further used to indicate the switching of adjacent display frames. The first pulse signal and the second pulse signal can be generated with reference to the above-described display control method.

[0091] In some embodiments, the display control circuit further includes a serial decoding input signal generating module for generating a serial decoding input signal based on the number of pulse signals of the line feed control signal and the number of pixel rows. The serial decoding input signal can also be generated by referring to the above-mentioned display control method.

[0092] The present application also provides a chip and a display device. The chip, for example, includes the display control circuit described above and can be used to implement the display control method provided by the present application. The display device, for example, includes the chip provided by the present application.

[0093] According to the display control circuit, chip, and display device of the present application, the line break control signal has a continuous pulse signal, so that the display panel is continuously scanned and displayed, and the display will not be interrupted by whether the frame break control signal is obtained. This avoids the different exposure levels of each pixel row caused by displaying a black screen while waiting for the frame break control signal, thereby eliminating the bright and dark ripples when the camera is shooting, which is beneficial to improving the shooting effect.

[0094] Furthermore, when scanning and displaying with a fixed subframe period, the mismatch between the data transmission timing and the display timing of the display screen is compensated by adjusting the number of subframes in part of the display screen, which can avoid display anomalies caused by timing mismatch and help improve display stability.

[0095] The embodiments of the present application are as described above, and these embodiments do not describe all details in detail, nor do they limit the present application to specific embodiments. Obviously, based on the above description, many modifications and variations can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The scope of protection of the present application shall be based on the scope defined by the claims of the present application.

Claims

1. A display control method, wherein: include: Obtaining multiple frame change control signals; Obtaining a preset frame period according to a time interval between two adjacent frame change control signals; Obtaining a preset number of subframes in each frame display image according to the preset frame period; Obtaining the actual number of subframes in each frame of the display image according to the preset number of subframes; as well as generating a line-change control signal according to the frame-change control signal and the actual number of the subframes in each frame of the display image, wherein the line-change control signal includes a plurality of continuous pulse signals, each pulse signal being used to control the display of a corresponding pixel row of the display panel; Among them, the multiple pulse signals include a first pulse signal with a first pulse width and a plurality of second pulse signals with a second pulse width located between adjacent first pulse signals. The first pulse signal is used to indicate the switching of adjacent frame display images, and any two adjacent pulse signals among the multiple pulse signals are separated by a line scanning cycle.

2. The display control method according to claim 1, wherein: The display screen includes a first type of display screen and a second type of display screen, The actual number of the subframes in the first type of display picture is less than the actual number of the subframes in the second type of display picture, There is at least one first-category display screen between two adjacent second-category display screens.

3. The display control method according to claim 2, wherein: The actual number of subframes in the first type of display picture is n-1, and the actual number of subframes in the second type of display picture is n. Tf is the preset frame period, Tr is the row scanning period, R is the number of pixel rows of the display panel, INT represents rounding down, and n is also the preset number of subframes, n>1 and is an integer.

4. The display control method according to claim 2, wherein: The actual number of subframes in the first type of display picture is m, and the actual number of subframes in the second type of display picture is m+1. Tf is the preset frame period, Tr is the row scanning period, R is the number of pixel rows of the display panel, INT represents rounding down, m is also the preset number of subframes, m≥1 and is an integer.

5. The display control method according to claim 3 or 4, wherein: The step of generating a line feed control signal comprises: generating a first first pulse signal according to the first frame change control signal, wherein the first first pulse signal is phase-adapted to the first frame change control signal; After generating the first first pulse signal, generating a second pulse signal every time a row scanning period passes; and Each time a first number of the second pulse signals is counted, the next first pulse signal is generated. The first number is one less than a product of an actual number of the subframes in the corresponding display image and the number of pixel rows. The display control method according to claim 1 , wherein: The display control method further includes: A serial decoding input signal is generated according to the number of pulse signals of the line-change control signal and the number of pixel rows, and the serial decoding input signal is used to turn on the pixel rows in sequence.

7. The display control method according to claim 6, wherein: The serial decoding input signal includes a plurality of continuous third pulse signals, The step of generating the serial decoding input signal comprises: generating a first third pulse signal according to the first line feed control signal; After the first third pulse signal, the next third pulse signal is generated by counting a second number of the second pulse signals. The second number is one less than the number of pixel rows.

8. The display control method according to claim 1, wherein: Obtaining the plurality of frame change control signals according to a video source, The step of obtaining a plurality of frame change control signals comprises: Decoding the video source to obtain the frame change control signal; or The frame change control signal is obtained by calculation according to the frame rate of the video source.

9. A display control circuit, wherein: include: A frame change control signal acquisition unit, configured to obtain a plurality of frame change control signals; a processing unit, configured to obtain a preset frame period based on a time interval between two adjacent frame-changing control signals, and to obtain a preset number of subframes in each frame of the display image based on the preset frame period, and further configured to obtain an actual number of subframes in each frame of the display image based on the preset number of subframes; a line break control signal generating unit, which generates a line break control signal according to the frame break control signal and the actual number of the subframes in each frame of the display screen, wherein the line break control signal includes a plurality of continuous pulse signals, each pulse signal is used to control the display of a corresponding pixel row of the display panel, Among them, the multiple pulse signals include a first pulse signal with a first pulse width and a plurality of second pulse signals with a second pulse width located between adjacent first pulse signals. The first pulse signal is used to indicate the switching of adjacent frame display images, and any two adjacent pulse signals among the multiple pulse signals are separated by a line scanning cycle.

10. A chip, wherein: The display control circuit according to claim 9 is included.

11. A display device, wherein: include: Display panel; as well as The display control circuit according to claim 9, configured to control the display of the display panel.

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