Display device

Abstract

The present disclosure relates to a display device capable of improving image quality while reducing power consumption. According to one or more embodiments of the present disclosure, the display device includes a light emitting element connected between a driving voltage line and a common voltage line, a first transistor connected between the driving voltage line and the light emitting element, a second transistor connected between a data line and a source electrode of the first transistor, a third transistor connected between a gate electrode of the first transistor and a drain electrode of the first transistor; and a fourth transistor connected between the drain electrode of the first transistor and the first initialization voltage line, wherein the third transistor and the fourth transistor have the same type.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0192809, filed with the Korean Intellectual Property Office on December 27, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device capable of improving image quality while reducing power consumption. Background art

[0004] Generally, a display device includes a source device and a sink device. In this case, the source device (e.g., a graphics processing unit (GPU)) may send image data to the sink device, and the sink device performs a display operation based on the image data sent from the source device.

[0005] Recently, display devices have allowed the frame rate (or driving time) of image frames constituting image data to be changed in real - time during the display operation according to the characteristics of the image displayed by the display operation. In this case, if the frame rate (or driving time) of the panel driving frames for the display operation does not change, the frame rate of the image frames (e.g., GPU rendering speed) and the frame rate of the panel driving frames do not match, resulting in problems such as tearing (e.g., image corruption) and jitter (e.g., image delay) in the image displayed by the sink device. Therefore, synchronization techniques have been proposed to change the frame rate of the panel driving frames by increasing or decreasing the vertical blanking portion in the panel driving frames as the frame rate of the image frames changes. However, since the driving time of the panel driving frames increases as the frame rate of the panel driving frames decreases, the characteristics of the driving transistors in the pixel circuits included in the display panel may be fixed in one state (e.g., a predetermined state) during the panel driving frames, and thus flicker may occur on the display panel due to hysteresis characteristics. Summary of the invention

[0006] Aspects of the present disclosure provide a display device capable of improving image quality while reducing power consumption.

[0007] According to one or more embodiments of the present disclosure, a display device includes a light - emitting element connected between a driving voltage line and a common voltage line, a first transistor connected between the driving voltage line and the light - emitting element, a second transistor connected between a data line and a source electrode of the first transistor, a third transistor connected between a gate electrode and a drain electrode of the first transistor, and a fourth transistor connected between the drain electrode of the first transistor and a first initialization voltage line, wherein the third transistor and the fourth transistor have the same type.

[0008] The third transistor and the fourth transistor may include n-type transistors.

[0009] The display device may further include a seventh transistor connected between the first electrode of the light-emitting element and the second initialization voltage line.

[0010] The display device may further include a third gate line connected to the gate electrode of the seventh transistor and the gate electrode of the fourth transistor.

[0011] The third transistor, the fourth transistor, and the seventh transistor may be of the same type.

[0012] The third transistor, the fourth transistor, and the seventh transistor may include n-type transistors.

[0013] The display device may further include a fifth transistor connected between the source electrode of the first transistor and the driving voltage line, a sixth transistor connected between the drain electrode of the first transistor and the first electrode of the light-emitting element, an eighth transistor connected between the source electrode of the first transistor and the bias voltage line, and a capacitor connected between the driving voltage line and the gate electrode of the first transistor.

[0014] The display device may further include a first gate line connected to the gate electrode of the second transistor, a second gate line connected to the gate electrode of the third transistor, a third gate line connected to the gate electrodes of the fourth transistor and the seventh transistor, an emission line connected to the gate electrodes of the fifth transistor and the sixth transistor, and a fourth gate line connected to the gate electrode of the eighth transistor.

[0015] The first gate line may be configured to transmit a first gate signal, wherein the second gate line is configured to transmit a second gate signal, wherein the third gate line is configured to transmit a third gate signal, wherein the fourth gate line is configured to transmit a fourth gate signal, and wherein the emission line is configured to transmit an emission signal.

[0016] The first gate signal, the second gate signal, the third gate signal, the fourth gate signal, and the emission signal may have an effective level and an inactive level in the display scan section and the self-scan section.

[0017] The display scan section may include a first bias period, an initialization period, a compensation period, a second bias period, and an emission period.

[0018] During the first bias period of the display scan section, the second gate signal and the fourth gate signal may be configured to have an effective level, and the emission signal, the third gate signal, and the first gate signal may be configured to have an inactive level.

[0019] During the initialization period of the display scan segment, the third gate signal and the second gate signal can be configured to have an active level, and the emission signal, the first gate signal, and the fourth gate signal can be configured to have an inactive level.

[0020] During the compensation period of the display scan segment, the second gate signal and the first gate signal can be configured to have an active level, and the emission signal, the third gate signal, and the fourth gate signal can be configured to have an inactive level.

[0021] The first gate signal can be configured to have an active level during the data writing period of the compensation period.

[0022] The data voltage can be configured to be applied to the data line during the data writing period.

[0023] During the emission period of the display scan segment, the emission signal can be configured to have an active level, and the third gate signal, the second gate signal, the first gate signal, and the fourth gate signal can be configured to have an inactive level.

[0024] The self-scan segment can include a first bias period, an initialization period, and a second bias period.

[0025] During the first bias period of the self-scan segment, the fourth gate signal can be configured to have an active level, and the emission signal, the third gate signal, the second gate signal, and the first gate signal can be configured to have an inactive level.

[0026] During the initialization period of the self-scan segment, the third gate signal can be configured to have an active level, and the emission signal, the second gate signal, the first gate signal, and the fourth gate signal can be configured to have an inactive level.

[0027] During the second bias period of the self-scan segment, the fourth gate signal can be configured to have an active level, and the emission signal, the third gate signal, the second gate signal, and the first gate signal can be configured to have an inactive level.

[0028] The first transistor, the second transistor, the fifth transistor, the sixth transistor, and the eighth transistor can include p-type transistors, where the third transistor, the fourth transistor, and the seventh transistor include n-type transistors.

[0029] According to one or more embodiments of the present disclosure, a display device includes a light-emitting element connected between a driving voltage line and a common voltage line, a first transistor connected between the driving voltage line and the light-emitting element, a second transistor connected between a data line and a source electrode of the first transistor, a third transistor connected between a gate electrode of the first transistor and a drain electrode of the first transistor, a fourth transistor connected between the drain electrode of the first transistor and a first initialization voltage line, and a seventh transistor connected between a first electrode of the light-emitting element and a second initialization voltage line, wherein the third transistor and the seventh transistor have the same type.

[0030] The third transistor and the seventh transistor may include n-type transistors.

[0031] The third transistor, the fourth transistor, and the seventh transistor may have the same type.

[0032] The third transistor, the fourth transistor, and the seventh transistor may include n-type transistors.

[0033] In a display device according to one or more embodiments, leakage current can be reduced or minimized, and the occurrence of spots can be reduced or prevented, thereby improving the image quality of the display device.

[0034] In addition, the magnitude of a gate signal applied to a gate electrode of a transistor can be reduced, thereby reducing the power consumption of the display device.

[0035] Aspects of the present disclosure are not limited to the above aspects, and other aspects not described herein will become apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other aspects of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0037] Figure 1 is a block diagram of a display device according to one or more embodiments;

[0038] Figure 2 is a conceptual diagram showing Figure 1 the driving operation of the display device;

[0039] Figure 3 is an equivalent circuit diagram of a pixel according to one or more embodiments;

[0040] Figure 4 is Figure 3 a timing diagram of a transmission signal, a third gate signal, a second gate signal, a first gate signal, and a fourth gate signal in a display scan section;

[0041] Figure 5 is a conceptual diagram showingFigure 3 A diagram of the operation of the display device during the first bias period of the display scan segment of Figure 4 ;

[0042] Figure 6 A diagram showing Figure 3 the operation of the display device of Figure 4 during the initialization period of the display scan segment;

[0043] Figure 7 A diagram showing Figure 3 the operation of the display device of Figure 4 during the compensation period of the display scan segment;

[0044] Figure 8 A diagram showing Figure 3 the operation of the display device of Figure 4 during the second bias period of the display scan segment;

[0045] Figure 9 A diagram showing Figure 3 the operation of the display device of Figure 4 during the emission period of the display scan segment;

[0046] Figure 10 is Figure 3 a timing diagram of the emission signal, the third gate signal, the second gate signal, the first gate signal, and the fourth gate signal in the self-scan segment;

[0047] Figure 11 A diagram showing Figure 3 the operation of the display device of Figure 10 during the initialization period of the self-scan segment;

[0048] Figures 12 to 16 A cross-sectional view showing the structure of a light-emitting element according to one or more embodiments;

[0049] Figure 17 A diagram showing Figure 15 an example of an organic light-emitting diode;

[0050] Figure 18 A diagram showing Figure 16 an example of an organic light-emitting diode;

[0051] Figure 19 A cross-sectional view showing the structure of a pixel of a display device according to one or more embodiments;

[0052] Figure 20 A perspective view showing a display device according to one or more embodiments; and

[0053] Figure 21is a perspective view showing an extended state of a display device according to one or more embodiments. Detailed embodiments

[0054] Aspects of some embodiments of the present disclosure and methods of implementing the same can be more readily understood by reference to the detailed description of the embodiments and the drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, not relevant to the description of the embodiments, or not necessary for those of ordinary skill in the art to fully understand the aspects of the present disclosure may be omitted. Unless otherwise noted, the same reference numerals, characters, or combinations thereof in the entire drawings and written description indicate the same elements, and thus their repeated description may be omitted.

[0055] The described embodiments can have various modifications and can be implemented in different forms, and should not be construed as being limited only to the embodiments shown herein. The use of "can", "may", or "may not" in the description of the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents, and substitutions within the spirit and scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure can be partially or wholly combined with each other, and various interlocks and drives are technically possible. Each embodiment can be implemented independently of each other, or can be implemented in association with each other.

[0056] In the drawings, for clarity and / or for the purpose of description, the relative dimensions of elements, layers, or regions may be exaggerated. In this document, various embodiments are described with reference to cross-sectional views that are schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Additionally, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are illustrative only. Accordingly, the embodiments disclosed herein should not be construed as being limited to the shapes of the elements, layers, or regions shown, but include deviations in shape resulting from, for example, manufacturing.

[0057] Spatial relative terms such as "beneath", "below", "lower", "lower side", "under", "above", "upper", "upper side" and the like may be used herein for convenience of explanation to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. It should be understood that, in addition to the orientation depicted in the figures, spatial relative terms are intended to also encompass different orientations of the device during use or operation. For example, if the device in the figures is flipped, an element described as "below", "beneath" or "under" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation above and below. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being disposed "on" a second portion, this indicates that the first portion is disposed at the upper side or the lower side of the second portion, and is not limited to the upper side based on the direction of gravity.

[0058] In addition, the phrase "in a schematic cross-sectional view" means a schematic cross-section obtained by vertically cutting a portion of an object when viewed from the side. The terms "overlap" or "overlapped" mean that a first object may be located above or below or on the side of a second object, and vice versa. In addition, the term "overlap" may include stacking, facing or facing each other, extending above, covering or partially covering or any other suitable term as would be appreciated and understood by a person of ordinary skill in the art. The expression "not overlapping" may include meanings such as "separate from", "disposed beside", "offset from" and any other suitable equivalent forms as would be appreciated and understood by a person of ordinary skill in the art. The terms "face" and "facing" may mean that a first object may be directly or indirectly opposite a second object. In a case where a third object is between the first object and the second object, although still facing each other, the first object and the second object may be understood to be indirectly opposite each other.

[0059] It should be understood that when an element, layer, region or component is referred to as being "formed on", "on", "connected to" or "(operatively or communicatively) coupled to" another element, layer, region or component, it can be directly formed on, on another element, layer, region or component, directly connected to or coupled to another element, layer, region or component, or indirectly formed on, on another element, layer, region or component, indirectly connected to or coupled to another element, layer, region or component such that there can be one or more intervening elements, layers, regions or components. Further, this can collectively mean direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or coupled to another layer, region or component, or there can be one or more intervening layers, regions or components. The one or more intervening components can include switches, resistors, capacitors and / or the like. In describing embodiments, unless explicitly described as a direct connection, the expression of connection indicates an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or coupled to another component, or on another component without an intermediate component.

[0060] Further, in this specification, when a part of a layer, film, region, plate or the like is formed on another part, the forming direction is not limited to the upward direction, but includes forming the part on a side surface or the downward direction. Conversely, when a part of a layer, film, region, plate or the like is formed "below" another part, this includes not only the case where the part is "directly below" another part, but also the case where there is yet another part between the part and another part. Meanwhile, other expressions describing the relationship between components such as "between", "immediately between" or "adjacent to", and "directly adjacent to" can be similarly interpreted. It should be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0061] For the purposes of the present disclosure, when a phrase such as "at least one of...", "any one of...", or "one or more of..." appears after a list of elements, it modifies the entire list of elements, rather than individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to mean only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, by way of example, XYZ, XYY, YZ, and ZZ), or any variation thereof. Similarly, the phrase "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the phrase "A and / or B" can include A, B, or A and B. Similarly, when phrases such as "at least one of...", "a plurality of...", "one of...", and other prepositional phrases appear after a list of elements, they modify the entire list of elements, rather than individual elements of the list.

[0062] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions are not to be limited by these terms. These terms do not correspond to a particular order, position, or superiority, and are only used to distinguish one element, member, component, region, area, layer, portion, or part from another element, member, component, region, area, layer, portion, or part. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the spirit and scope of the present disclosure. The description of an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms "first", "second", etc. may respectively represent "first class (or first group)", "second class (or second group)", etc.

[0063] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the present disclosure. Unless otherwise clearly indicated in the context, the singular forms "a" and "an" as used herein are also intended to include the plural forms, and the plural forms are also intended to include the singular forms. It should also be understood that when the terms "comprises", "comprising", "have", "having", "includes" and "including" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0064] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as terms of approximation and not of degree, and are intended to account for the inherent variations of measured or calculated values that would be recognized by a person of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. Taking into account the measurements involved and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein includes the stated value and means within an acceptable variation of the particular value as determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Additionally, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0065] In some embodiments, well-known structures and devices may be described in the drawings in connection with one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuits, individual components, microprocessors, hardwired circuits, memory elements, wire connections, and other electronic circuits. This may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by a microprocessor or other similar hardware may be programmed and controlled using software to perform the various functions discussed herein and may optionally be driven by firmware and / or software. In addition, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs functions different from those of the dedicated hardware. Further, in some embodiments, without departing from the scope of the present disclosure, the blocks, units, and / or modules may be physically separated into two or more interacting individual blocks, units, and / or modules. Additionally, in some embodiments, without departing from the scope of the present disclosure, the blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules.

[0066] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should also be understood that terms such as those defined in a commonly used dictionary should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0067] Figure 1 is a block diagram of a display device 100 according to one or more embodiments. Figure 2 is a conceptual diagram showing Figure 1 the driving operation of the display device.

[0068] Referring to Figure 1, the display device 100 may include a display panel 110, a first gate driver 120-1, a second gate driver 120-2, a first compensation driver 130-1, a second compensation driver 130-2, a bias driver 140, an emission driver 150, a data driver 160, and a timing controller 170. In this case, the display device 100 may display an image at various driving frequencies according to driving conditions. For example, the display device 100 may display an image at various driving frequencies from about 1 Hz to about 120 Hz (e.g., the frame rate of panel driving frames within the range from about 1 Hz to about 120 Hz). Meanwhile, the display device 100 may be an organic light-emitting display device or a quantum dot light-emitting display device, but is not limited thereto.

[0069] The display panel 110 may include a plurality of pixels PX. For example, the plurality of pixels PX may include red pixels, green pixels, and blue pixels. Each of the plurality of pixels PX may be connected to a gate line Sj (where j is an integer greater than or equal to 1 and less than or equal to n) for transmitting a gate signal, a compensation line Cj for transmitting a compensation signal, a bias line Bj for transmitting a bias signal, and an emission line Ej for transmitting an emission signal.

[0070] As Figure 2 shown in the example shown, each of the plurality of pixels PX may perform one display scanning operation (e.g., an operation of receiving a data voltage to allow a light-emitting element to emit light (or turn on)) and at least one self-scanning operation (e.g., an operation of changing the characteristics of a driving transistor (such as a first transistor T1 to be described later)). According to one or more embodiments, each of the plurality of pixels PX may have a so-called 8T-1C structure including eight transistors and one capacitor, but is not limited thereto.

[0071] As Figure 1 shown, the first gate driver 120-1 and the second gate driver 120-2 may be positioned on respective sides of the display panel 110. The first compensation driver 130-1 and the second compensation driver 130-2 may also be respectively positioned on both sides of the display panel 110. The bias driver 140 may be positioned on one side of the display panel 110 (e.g., Figure 1 the left side of the display panel 110 in Figure 1 ). The emission driver 150 may be positioned on one side of the display panel 110 (e.g.,

[0072] The first gate driver 120-1 and the second gate driver 120-2 may be connected to the display panel 110 through gate lines S1 to Sn extending in a first direction. The first gate driver 120-1 and the second gate driver 120-2 may apply gate signals to the display panel 110 through gate lines S1 to Sn extending in a first direction. Since the first gate driver 120-1 and the second gate driver 120-2 are positioned on both sides of the display panel 110 in the first direction and gate signals are applied from both sides of the display panel 110, deviation in the fall time and / or rise time of the gate signals according to the position of the pixels PX in the display panel 110 may not occur. Accordingly, by including the first gate driver 120-1 and the second gate driver 120-2 positioned on the sides of the display panel 110 in the first direction, the display device 100 may reduce or prevent luminance non-uniformity phenomena caused by deviation in the fall time and / or rise time of the gate signals according to the position of the pixels PX in the display panel 110.

[0073] The first compensation driver 130-1 and the second compensation driver 130-2 may be connected to the display panel 110 through compensation lines C1 to Cn extending in a first direction. The first compensation driver 130-1 and the second compensation driver 130-2 may apply compensation signals to the display panel 110 through compensation lines C1 to Cn extending in a first direction. In this case, since the first compensation driver 130-1 and the second compensation driver 130-2 are positioned on the sides of the display panel 110 in the first direction and compensation signals are applied from both sides of the display panel 110, deviation in the fall time and / or rise time of the compensation signals according to the position of the pixels PX in the display panel 110 may not occur. Accordingly, by including the first compensation driver 130-1 and the second compensation driver 130-2 positioned on both sides of the display panel 110 in the first direction, the display device 100 may reduce or prevent luminance non-uniformity phenomena caused by deviation in the fall time and / or rise time of the compensation signals according to the position of the pixels PX in the display panel 110.

[0074] The bias driver 140 may be connected to the display panel 110 through bias lines B1 to Bn extending in a first direction. The bias driver 140 may apply bias signals to the display panel 110 through bias lines B1 to Bn extending in a first direction. In this case, the bias driver 140 may be positioned on one side of the display panel 110 in the first direction (e.g., Figure 1 the left side of the display panel 110 in

[0075] The emission driver 150 may be connected to the display panel 110 through emission lines E1 to En extending in the first direction. The emission driver 150 may apply an emission signal to the display panel 110 through the emission lines E1 to En extending in the first direction. In this case, the emission driver 150 may be positioned on one side of the display panel 110 in the first direction (e.g., Figure 1 the right side of the display panel 110 in

[0076] Generally, the fall time and / or rise time of the gate signal applied to the pixel PX and the fall time and / or rise time of the compensation signal applied to the pixel PX have a relatively large impact on the brightness of the pixel PX. The fall time and / or rise time of the bias signal applied to the pixel PX and the fall time and / or rise time of the emission signal applied to the pixel PX have a relatively small impact on the brightness of the pixel PX. Therefore, the bias driver 140 and the emission driver 150 may be positioned only on the respective sides of the display panel 110. Figure 2 As shown in

[0077] The display panel 110 may be connected to the data driver 160 through data lines D1 to Dm extending in a second direction intersecting the first direction. The data driver 160 may provide a data voltage (or data signal) to the display panel 110 through the data lines D1 to Dm extending in the second direction intersecting the first direction. For example, as Figure 2 shown in Figure 2Execute a display scan segment DSS and at least one self-scan segment SFS at approximately 120 Hz or approximately 60 Hz in . In one or more embodiments, when the driving frequency of the display panel 110 is approximately 120 Hz, one panel driving frame 1F may include one display scan segment DSS and three self-scan segments SFS. When the driving frequency of the display panel 110 is approximately 60 Hz, one panel driving frame 1F may include one display scan segment DSS and seven self-scan segments SFS. In this way, the timing controller 170 can respond to changes in the driving frequency of the display panel 110 (e.g., changes in the frame rate of the panel driving frame or changes in the driving time of the panel driving frame) by adjusting the number of self-scan segments SFS.

[0078] Figure 3 is an equivalent circuit diagram of the pixel PX according to one or more embodiments.

[0079] The pixel PX can be connected to the first gate line GWL, the second gate line GCL, the third gate line GIL, the fourth gate line GBL, the emission line EML, the data line DL, the driving voltage line VDL, the common voltage line VSL, the first initialization voltage line VIL1, the second initialization voltage line VIL2, and the bias voltage line VBL.

[0080] The pixel PX may include a pixel circuit PC and a light-emitting element ED. The pixel circuit PC may include a first transistor T1 (e.g., a driving transistor), a second transistor T2 (e.g., a switching transistor), a third transistor T3 (e.g., a compensating transistor), a fourth transistor T4 (e.g., an initializing transistor), a fifth transistor T5 (e.g., a first light-emitting transistor), a sixth transistor T6 (e.g., a second light-emitting transistor), a seventh transistor T7 (e.g., a reset transistor), an eighth transistor T8 (e.g., a self-scan transistor), and a capacitor Cst (e.g., a storage capacitor).

[0081] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 can control the source-drain current (hereinafter, the driving current) according to the data voltage applied to the gate electrode. The driving current (e.g., Isd) flowing through the channel region of the first transistor T1 may be proportional to the square of the difference between the threshold voltage (e.g., Vth) of the first transistor T1 and the voltage (e.g., Vsg) between the source electrode and the gate electrode of the first transistor T1 (Isd = k × (Vsg - Vth) 2) Here, k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vsg is the source-gate voltage of the first transistor T1, and Vth is the threshold voltage of the first transistor T1. According to one or more embodiments, the first transistor T1 may further include a pair of gate electrodes supplied with a driving voltage ELVDD. The pair of gate electrodes of the first transistor T1 may be positioned opposite to the gate electrode of the first transistor T1 with the active layer therebetween. The pair of gate electrodes of the first transistor T1 may be connected to a driving voltage line VDL. The driving voltage ELVDD applied to the pair of gate electrodes of the first transistor T1 may improve the hysteresis characteristics of the first transistor T1.

[0082] The light-emitting element ED may emit light by receiving a driving current. The light emission amount or luminance of the light-emitting element ED may be proportional to the magnitude of the driving current.

[0083] The light-emitting element ED may be an organic light-emitting diode including a first electrode (e.g., a pixel electrode or an anode electrode), a second electrode (e.g., a common electrode or a cathode electrode), and an organic light-emitting layer positioned between the first electrode and the second electrode. For another example, the light-emitting element ED may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor positioned between the first electrode and the second electrode. For still another example, the light-emitting element ED may be a quantum dot light-emitting element including a first electrode, a second electrode, and a quantum dot light-emitting layer positioned between the first electrode and the second electrode. For still another example, the light-emitting element ED may be a micro light-emitting diode.

[0084] The first electrode of the light-emitting element ED may be electrically connected to the fourth node N4. The first electrode of the light-emitting element ED may be connected to the drain electrode of the sixth transistor T6 and the source electrode of the seventh transistor T7 through the fourth node N4. The second electrode of the light-emitting element ED may be connected to a common voltage line VSL. The second electrode of the light-emitting element ED may receive a common voltage ELVSS (e.g., a low-potential voltage) from the common voltage line VSL.

[0085] The second transistor T2 may be turned on by a first gate signal GW of the first gate line GWL to electrically connect the data line DL to the first node N1 which is the source electrode of the first transistor T1. The second transistor T2 may be turned on based on the first gate signal GW to supply a data voltage VDAT to the first node N1. The gate electrode of the second transistor T2 may be electrically connected to the first gate line GWL, its source electrode may be electrically connected to the data line DL, and its drain electrode may be electrically connected to the first node N1.

[0086] The third transistor T3 can be turned on by the second gate signal GC of the second gate line GCL to electrically connect the second node N2, which is the drain electrode of the first transistor T1, to the third node N3, which is the gate electrode of the first transistor T1. The third transistor T3 can be serially connected between the second node N2 and the third node N3. For example, the gate electrode of the third transistor T3 can be electrically connected to the second gate line GCL, its drain electrode can be electrically connected to the third node N3, and its source electrode can be electrically connected to the second node N2.

[0087] The fourth transistor T4 can be turned on by the third gate signal GI of the third gate line GIL to electrically connect the second node N2, which is the drain electrode of the first transistor T1, to the first initialization voltage line VIL1. The fourth transistor T4 can be serially connected between the second node N2 and the first initialization voltage line VIL1. For example, the gate electrode of the fourth transistor T4 can be electrically connected to the third gate line GIL, its drain electrode can be electrically connected to the second node N2, and its source electrode can be electrically connected to the first initialization voltage line VIL1. The first initialization voltage line VIL1 can transmit the first initialization voltage VINT1. On the other hand, the fourth transistor T4 and the above-mentioned third transistor T3 can be serially connected between the third node N3 and the first initialization voltage line VIL1. Therefore, the leakage current from the third node N3 (e.g., the leakage current generated by the turned-off third transistor T3 and fourth transistor T4) can be reduced or minimized. For example, the third node N3 is a node corresponding to the gate electrode of the first transistor T1 that controls the magnitude of the driving current supplied to the light-emitting element ED, and if there is a leakage path between the third node N3 and the first initialization voltage line VIL1, the voltage of the third node N3 may fluctuate, resulting in deterioration of the image quality of the display device 100. According to one or more embodiments, by serially connecting a plurality of transistors (e.g., the third transistor T3 and the fourth transistor T4) on the leakage path between the third node N3 and the first initialization voltage line VIL1, the leakage current of the above-mentioned third node N3 can be reduced or minimized.

[0088] The fifth transistor T5 can be turned on by the emission signal EM of the emission line EML to electrically connect the driving voltage line VDL to the first node N1, which is the source electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be electrically connected to the emission line EML, its source electrode can be electrically connected to the driving voltage line VDL, and its drain electrode can be electrically connected to the first node N1.

[0089] The sixth transistor T6 can be turned on by the emission signal EM of the emission line EML to electrically connect the second node N2, which is the drain electrode of the first transistor T1, to the fourth node N4, which is the first electrode of the light-emitting element ED. The gate electrode of the sixth transistor T6 can be electrically connected to the emission line EML, its source electrode can be electrically connected to the second node N2, and its drain electrode can be electrically connected to the fourth node N4.

[0090] The seventh transistor T7 can be turned on by the third gate signal GI of the third gate line GIL to electrically connect the fourth node N4, which is the first electrode of the light-emitting element ED, to the second initialization voltage line VIL2. By turning on the seventh transistor T7 based on the third gate signal GI, the first electrode of the light-emitting element ED can be discharged to the second initialization voltage VINT2. The gate electrode of the seventh transistor T7 can be electrically connected to the third gate line GIL, its drain electrode can be electrically connected to the fourth node N4, and its source electrode can be electrically connected to the second initialization voltage line VIL2. The second initialization voltage line VIL2 can send the second initialization voltage VINT2. The seventh transistor T7 and the above-mentioned fourth transistor T4 can be connected to the same third gate line GIL. According to one or more embodiments, the seventh transistor T7 can be an n-type transistor. Therefore, the magnitude of the third gate signal GI for turning on the seventh transistor T7 can be reduced or minimized. For example, a low voltage (e.g., the second initialization voltage VINT2 of negative polarity) can be applied to the source electrode of the seventh transistor T7 to discharge (or initialize) the fourth node N4, so that the effective level of the third gate signal GI can be set to a relatively small positive voltage. Therefore, when the seventh transistor T7 is an n-type transistor, power consumption can be reduced. For the same reason, the fourth transistor T4, which receives the first initialization voltage VINT1 of negative polarity through its source electrode, can also be an n-type transistor.

[0091] The eighth transistor T8 can be turned on by the fourth gate signal GB of the fourth gate line GBL to electrically connect the bias voltage line VBL to the first node N1, which is the source electrode of the first transistor T1. The eighth transistor T8 can be turned on according to the fourth gate signal GB to supply the bias voltage VB to the first node N1. The eighth transistor T8 can improve the hysteresis characteristics of the first transistor T1 by supplying the bias voltage VB to the source electrode of the first transistor T1. The gate electrode of the eighth transistor T8 can be electrically connected to the fourth gate line GBL, its source electrode can be electrically connected to the bias voltage line VBL, and its drain electrode can be electrically connected to the first node N1.

[0092] When all of the above-mentioned fifth transistor T5, first transistor T1, and sixth transistor T6 are turned on, a drive current can be supplied to the light-emitting element ED.

[0093] Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may include a silicon-based active layer. For example, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may be a p-type transistor including an active layer made of low-temperature polycrystalline silicon (LTPS). The active layer made of low-temperature polycrystalline silicon may have a relatively high electron mobility and suitable conduction characteristics. Therefore, in the display device 100, since transistors with suitable conduction characteristics are included, multiple pixels PX can be driven stably and relatively efficiently. Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may output the current flowing into the source electrode to the drain electrode based on a low gate voltage applied to the gate electrode.

[0094] The third transistor T3, the fourth transistor T4, and the seventh transistor T7 may each be an n-type transistor including an oxide-based active layer. The transistor including the oxide-based active layer may have a coplanar structure on which the gate electrode is positioned. The transistor including the oxide-based active layer may output the current flowing into the drain electrode to the source electrode based on a high gate voltage applied to the gate electrode.

[0095] The capacitor Cst may be electrically connected between the third node N3, which is the gate electrode of the first transistor T1, and the driving voltage line VDL. For example, the first electrode of the capacitor Cst may be electrically connected to the third node N3, and the second electrode of the capacitor Cst may be electrically connected to the driving voltage line VDL, so that the potential difference between the driving voltage line VDL and the gate electrode of the first transistor T1 can be maintained.

[0096] The driving voltage ELVDD, the common voltage ELVSS, the first initialization voltage VINT1, the second initialization voltage VINT2, and the bias voltage VB may each be a DC voltage. Here, the driving voltage ELVDD and the bias voltage VB may each be a positive-polarity DC voltage, and the common voltage ELVSS, the first initialization voltage VINT1, and the second initialization voltage VINT2 may each be a negative-polarity voltage. Here, the bias voltage VB may be greater than the driving voltage ELVDD. The driving voltage ELVDD may be greater than the common voltage ELVSS. The first initialization voltage VINT1 and the second initialization voltage VINT2 may have the same magnitude. The second initialization voltage VINT2 may be less than or equal to the common voltage ELVSS.

[0097] Figure 4 is Figure 3 The timing diagram of the emission signal EM, the third gate signal GI, the second gate signal GC, the first gate signal GW, and the fourth gate signal GB in the display scan section DSS.

[0098] Refer toFigure 4 The display scan segment DSS may include a plurality of periods including a first bias period Pd1, an initialization period Pd2, a compensation period Pd3, a second bias period Pd4, and a transmission period Pd5.

[0099] For each period of the display scan segment DSS, the emission signal EM, the third gate signal GI, the second gate signal GC, the first gate signal GW, and the fourth gate signal GB may each have an active level or an inactive level. Here, the active level of each of the above signals may mean a voltage at a level capable of turning on the corresponding transistor to which the corresponding signal is applied. In other words, the active level signal may have a value greater than the threshold voltage of the corresponding transistor. For example, when the corresponding transistor is a p-type transistor, the active level of the signal applied to the gate electrode of the corresponding transistor may mean a low level (e.g., a negative polarity level or a low voltage level).

[0100] Meanwhile, the inactive level of each signal may mean a voltage at a level capable of turning off the corresponding transistor. In other words, the inactive level signal may have a value smaller than the threshold voltage of the corresponding transistor. For example, when the corresponding transistor is a p-type transistor, the inactive level of the signal applied to the gate electrode of the corresponding transistor may mean a high level (e.g., a positive polarity level or a high voltage level).

[0101] Conversely, when the corresponding transistor is an n-type transistor, the active level of the signal applied to the gate electrode of the corresponding transistor may mean a high level (e.g., a positive polarity level or a high voltage level), and the inactive level of the signal applied to the gate electrode of the corresponding transistor may mean a low level (e.g., a negative polarity level or a low voltage level).

[0102] During the first bias period Pd1, the second gate signal GC and the fourth gate signal GB may each have an active level. Meanwhile, during the first bias period Pd1, the emission signal EM, the third gate signal GI, and the first gate signal GW may each have an inactive level.

[0103] During the initialization period Pd2, the third gate signal GI and the second gate signal GC may each have an active level. Meanwhile, during the initialization period Pd2, the emission signal EM, the first gate signal GW, and the fourth gate signal GB may each have an inactive level.

[0104] During the compensation period Pd3, the second gate signal GC and the first gate signal GW may each have an active level. Meanwhile, during the compensation period Pd3, the emission signal EM, the third gate signal GI, and the fourth gate signal GB may each have an inactive level. Here, during the compensation period Pd3, the first gate signal GW may have an active level during a partial period of the compensation period Pd3 (e.g., the data write period Pw). For example, during the compensation period Pd3, the first gate signal GW may have an active level for a partial period starting from the start point of the compensation period Pd3 (e.g., the data write period Pw), and may have an inactive level for the remaining period of the compensation period Pd3 other than this partial period (e.g., other than the data write period Pw). During the data write period Pw, the data voltage VDAT may be applied to the data line DL. Here, during the compensation period Pd3, the time for which the first gate signal GW remains at the active level may be shorter than the time for which the first gate signal GW remains at the inactive level.

[0105] During the second bias period Pd4, the fourth gate signal GB may have an active level. Meanwhile, during the second bias period Pd4, the emission signal EM, the third gate signal GI, the second gate signal GC, and the first gate signal GW may each have an inactive level.

[0106] During the emission period Pd5, the emission signal EM may have an active level. Meanwhile, during the emission period Pd5, the third gate signal GI, the second gate signal GC, the first gate signal GW, and the fourth gate signal GB may each have an inactive level.

[0107] Referring to Figures 5 to 9 , the operation of the display device 100 in the display scan segment DSS according to one or more embodiments will be described as follows. In Figures 5 to 9 , the transistors surrounded by the dashed circles are in the on state, and the transistors other than those surrounded by the dashed circles are in the off state.

[0108] First, referring to Figure 4 and Figure 5 , the operation of the display device 100 during the first bias period Pd1 of the display scan segment DSS will be described as follows.

[0109] Figure 5 is a diagram showing the operation of the display device 100 in Figure 3 during the first bias period Pd1 of the display scan segment DSS in Figure 4 .

[0110] As shown in Figure 4As shown, during the first bias period Pd1, the second gate signal GC and the fourth gate signal GB may each have an active level. At the same time, during the first bias period Pd1, the emission signal EM, the third gate signal GI, and the first gate signal GW may each have an inactive level.

[0111] The second gate signal GC having an active level may be applied to the gate electrode of the third transistor T3 through the second gate line GCL. Accordingly, the third transistor T3 may be turned on.

[0112] The fourth gate signal GB having an active level may be applied to the gate electrode of the eighth transistor T8 through the fourth gate line GBL. Accordingly, the eighth transistor T8 may be turned on.

[0113] The emission signal EM having an inactive level may be applied to each of the gate electrodes of the fifth transistor T5 and the sixth transistor T6 through the emission line EML. Accordingly, the fifth transistor T5 and the sixth transistor T6 may each be turned off.

[0114] The third gate signal GI having an inactive level may be applied to each of the gate electrodes of the fourth transistor T4 and the seventh transistor T7 through the third gate line GIL. Accordingly, the fourth transistor T4 and the seventh transistor T7 may each be turned off.

[0115] The first gate signal GW having an inactive level may be applied to the gate electrode of the second transistor T2 through the first gate line GWL. Accordingly, the second transistor T2 may be turned off.

[0116] When the third transistor T3 is turned on, the gate electrode and the drain electrode of the first transistor T1 may be connected. In addition, the second node N2 may be connected to the capacitor Cst through the turned-on third transistor T3. Accordingly, the voltage of the third node N3 and the voltage of the second node N2 may be initialized (e.g., pre-initialized) by the charge stored in the capacitor Cst. In other words, the voltage of the gate electrode of the first transistor T1 and the voltage of the drain electrode may each be preliminarily initialized (e.g., pre-initialized) by the charge in the capacitor Cst.

[0117] When the eighth transistor T8 is turned on, the bias voltage VB may be applied to the source electrode of the first transistor T1 (e.g., the first node N1) through the turned-on eighth transistor T8. Accordingly, in the first bias period Pd1, the change in the hysteresis characteristic of the first transistor T1 may be reduced or minimized. Accordingly, the flicker phenomenon of the display device 100 may be reduced or prevented, particularly when the display device 100 is driven at a low driving frequency. In addition, the voltage of the first node N1 may be initialized to the bias voltage VB. In other words, the voltage of the source electrode of the first transistor T1 may be initialized to the bias voltage VB.

[0118] Next, refer to Figure 4And Figure 6 ,the operation of the display device 100 during the initialization period Pd2 of the display scan segment DSS will be described as follows.

[0119] Figure 6 is a diagram showing Figure 3 the display device 100 during Figure 4 the operation of the display scan segment DSS during the initialization period Pd2.

[0120] As Figure 4 shown, during the initialization period Pd2, the third gate signal GI and the second gate signal GC may each have an active level. At the same time, during the initialization period Pd2, the emission signal EM, the first gate signal GW, and the fourth gate signal GB may each have an inactive level.

[0121] The third gate signal GI with an active level may be applied to each of the gate electrodes of the fourth transistor T4 and the seventh transistor T7 through the third gate line GIL. Therefore, the fourth transistor T4 and the seventh transistor T7 may each be turned on.

[0122] The second gate signal GC with an active level may be applied to the gate electrode of the third transistor T3 through the second gate line GCL. Therefore, the third transistor T3 may be turned on.

[0123] The emission signal EM with an inactive level may be applied to each of the gate electrodes of the fifth transistor T5 and the sixth transistor T6 through the emission line EML. Therefore, the fifth transistor T5 and the sixth transistor T6 may each be turned off.

[0124] The first gate signal GW with an inactive level may be applied to the gate electrode of the second transistor T2 through the first gate line GWL. Therefore, the second transistor T2 may be turned off.

[0125] The fourth gate signal GB with an inactive level may be applied to the gate electrode of the eighth transistor T8 through the fourth gate line GBL. Therefore, the eighth transistor T8 may be turned off.

[0126] When the third transistor T3 and the fourth transistor T4 are turned on, the voltages of the third node N3 and the second node N2 may be initialized to the first initialization voltage VINT1. In other words, the gate electrode and the drain electrode of the first transistor T1 may each be initialized to the first initialization voltage VINT1. Since the third node N3 and the second node N2 have been preliminarily initialized to a certain voltage in a previous period (e.g., the first bias period Pd1), each of the voltages of the third node N3 and the second node N2 may quickly change to a relatively large initialization voltage (e.g., the first initialization voltage VINT1) during the initialization period Pd2.

[0127] The first initialization voltage VINT1 applied to the third node N3 (e.g., the first initialization voltage VINT1 applied to the gate electrode of the first transistor T1) may be set to a value smaller than the sum of the bias voltage VB of the first node N1 (e.g., the bias voltage VB applied to the source electrode of the first transistor T1) and the threshold voltage of the first transistor T1, so that the p-type first transistor T1 can be turned on during the initialization period Pd2.

[0128] Meanwhile, when the seventh transistor T7 is turned on, the second initialization voltage VINT2 from the second initialization voltage line VIL2 can be applied to the fourth node N4 through the turned-on seventh transistor T7. In other words, the second initialization voltage VINT2 from the second initialization voltage line VIL2 can be applied to the first electrode of the light-emitting element ED. Therefore, the voltage of the first electrode of the light-emitting element ED can be initialized to the second initialization voltage VINT2. For example, the second initialization voltage VINT2 may have a value smaller than the sum of the threshold voltage of the light-emitting element ED and the common voltage ELVSS. Therefore, the light-emitting element ED can be kept in a reverse-biased state during the initialization period Pd2. Therefore, the light-emitting element ED can be kept in a non-light-emitting state during the initialization period Pd2.

[0129] Next, referring to Figure 4 and Figure 7 , the operation of the display device 100 during the compensation period Pd3 of the display scan segment DSS will be described as follows.

[0130] Figure 7 is a diagram showing Figure 3 the operation of the display device 100 during the compensation period Pd3 of Figure 4 the display scan segment DSS.

[0131] As Figure 4 shown, during the compensation period Pd3, the second gate signal GC and the first gate signal GW may each have an active level. Here, during the compensation period Pd3, the first gate signal GW may have an active level during a partial period (e.g., the data write period Pw) of the compensation period Pd3. Meanwhile, during the compensation period Pd3, the emission signal EM, the third gate signal GI, and the fourth gate signal GB may each have an inactive level.

[0132] The second gate signal GC with an active level can be applied to the gate electrode of the third transistor T3 through the second gate line GCL. Therefore, the third transistor T3 can be turned on.

[0133] The first gate signal GW of the effective level can be applied to the gate electrode of the second transistor T2 through the first gate line GWL. Accordingly, the second transistor T2 can be turned on. At the same time, the first gate signal GW can be turned on for a partial period (e.g., the data writing period Pw) of the compensation period Pd3, and then turned off for the remaining period of the compensation period Pd3 except for the data writing period Pw.

[0134] The emission signal EM of the invalid level can be applied to each of the gate electrodes of the fifth transistor T5 and the sixth transistor T6 through the emission line EML. Accordingly, the fifth transistor T5 and the sixth transistor T6 can each be turned off.

[0135] The third gate signal GI of the invalid level can be applied to each of the gate electrodes of the fourth transistor T4 and the seventh transistor T7 through the third gate line GIL. Accordingly, the fourth transistor T4 and the seventh transistor T7 can each be turned off.

[0136] The fourth gate signal GB of the invalid level can be applied to the gate electrode of the eighth transistor T8 through the fourth gate line GBL. Accordingly, the eighth transistor T8 can be turned off.

[0137] When the second transistor T2 is turned on, the data voltage VDAT from the data line DL can be applied to the first node N1 through the turned-on second transistor T2. In other words, the data voltage VDAT from the data line DL can be applied to the source electrode of the first transistor T1. Here, the data voltage VDAT can be a voltage having a corresponding gray scale (or luminance) for displaying an image. The first initialization voltage VINT1 applied to the third node N3 (e.g., the first initialization voltage VINT1 applied to the gate electrode of the first transistor T1) can be set to a value smaller than the sum of the data voltage VDAT of the first node N1 (e.g., the data voltage VDAT applied to the source electrode of the first transistor T1) and the threshold voltage of the first transistor T1, so that the p-type first transistor T1 can be turned on during the compensation period Pd3.

[0138] Meanwhile, when the third transistor T3 is turned on, the third node N3 and the second node N2 can be connected to each other. In other words, since the gate electrode and the drain electrode of the first transistor T1 are electrically connected to each other, the turned-on first transistor T1 can operate as a diode. In this case, current flows from the first node N1 through the turned-on first transistor T1 to the second node N2, and thus, the voltage of the second node N2 and the voltage of the third node N3 connected to the second node N2 start to increase. In other words, the voltage of the drain electrode of the first transistor T1 and the voltage of the gate electrode start to increase. As the voltage of the gate electrode of the first transistor T1 increases, the first transistor T1 can be turned off when the gate-source voltage of the first transistor T1 (e.g., the differential voltage between the voltage of the gate electrode of the first transistor T1 and the voltage of the source electrode of the first transistor T1 (e.g., Vgs)) becomes equal to the threshold voltage of the first transistor T1. When the first transistor T1 is turned off, the threshold voltage of the first transistor T1 can be held by the capacitor Cst. Therefore, the gate-source voltage of the first transistor T1 (e.g., Vgs) can include the data voltage VDAT reflecting the threshold voltage of the first transistor T1. In other words, during the compensation period Pd3, the threshold voltage of the first transistor T1 can be detected, and the detected threshold voltage can be reflected in the data voltage VDAT, thereby compensating the data voltage VDAT.

[0139] Next, referring to Figure 4 and Figure 8 , the operation of the display device 100 during the second bias period Pd4 of the display scan section DSS will be described as follows.

[0140] Figure 8 is a diagram showing Figure 3 the operation of the display device 100 during the second bias period Pd4 of the display scan section DSS of Figure 4 .

[0141] As Figure 4 shown, during the second bias period Pd4, the fourth gate signal GB can have an active level. Meanwhile, during the second bias period Pd4, the emission signal EM, the third gate signal GI, the second gate signal GC, and the first gate signal GW can each have an inactive level.

[0142] The fourth gate signal GB having an active level can be applied to the gate electrode of the eighth transistor T8 through the fourth gate line GBL. Therefore, the eighth transistor T8 can be turned on.

[0143] The emission signal EM having an inactive level can be applied to each of the gate electrodes of the fifth transistor T5 and the sixth transistor T6 through the emission line EML. Therefore, the fifth transistor T5 and the sixth transistor T6 can each be turned off.

[0144] The third gate signal GI of an invalid level can be applied to each of the gate electrodes of the fourth transistor T4 and the seventh transistor T7 through the third gate line GIL. Accordingly, the fourth transistor T4 and the seventh transistor T7 can each be turned off.

[0145] The second gate signal GC of an invalid level can be applied to the gate electrode of the third transistor T3 through the second gate line GCL. Accordingly, the third transistor T3 can be turned off.

[0146] The first gate signal GW of an invalid level can be applied to the gate electrode of the second transistor T2 through the first gate line GWL. Accordingly, the second transistor T2 can be turned off.

[0147] When the eighth transistor T8 is turned on, the bias voltage VB from the bias voltage line VBL can be applied to the first node N1 (e.g., the source electrode of the first transistor T1) through the turned-on eighth transistor T8. Accordingly, the hysteresis characteristics of the first transistor T1 can be stabilized.

[0148] Meanwhile, during the second bias period Pd4, the first transistor T1 can be kept in the off state.

[0149] Next, referring to Figure 4 and Figure 9 , the operation of the display device 100 during the emission period Pd5 of the display scan segment DSS will be described below.

[0150] Figure 9 is a diagram showing Figure 3 of the display device 100 during Figure 4 the emission period Pd5 of the display scan segment DSS.

[0151] As Figure 4 shown, during the emission period Pd5, the emission signal EM can have an effective level. Meanwhile, during the emission period Pd5, the third gate signal GI, the second gate signal GC, the first gate signal GW, and the fourth gate signal GB can each have an invalid level.

[0152] The emission signal EM of an effective level can be applied to each of the gate electrodes of the fifth transistor T5 and the sixth transistor T6 through the emission line EML. Accordingly, the fifth transistor T5 and the sixth transistor T6 can each be turned on.

[0153] The third gate signal GI of an invalid level can be applied to each of the gate electrodes of the fourth transistor T4 and the seventh transistor T7 through the third gate line GIL. Accordingly, the fourth transistor T4 and the seventh transistor T7 can each be turned off.

[0154] The second gate signal GC of the invalid level can be applied to the gate electrode of the third transistor T3 through the second gate line GCL. Therefore, the third transistor T3 can be turned off.

[0155] The first gate signal GW of the invalid level can be applied to the gate electrode of the second transistor T2 through the first gate line GWL. Therefore, the second transistor T2 can be turned off.

[0156] The fourth gate signal GB of the invalid level can be applied to the gate electrode of the eighth transistor T8 through the fourth gate line GBL. Therefore, the eighth transistor T8 can be turned off.

[0157] Meanwhile, in the emission period Pd5, the first transistor T1 can be kept in the on state by the gate-source voltage held by the capacitor Cst.

[0158] When the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned on in the emission period Pd5, the driving voltage ELVDD can be applied to the first electrode (e.g., the fourth node N4) of the light-emitting element ED through the turned-on first transistor T1, fifth transistor T5, and sixth transistor T6. At this time, since the gate-source voltage held by the capacitor Cst includes the threshold voltage of the first transistor T1, the magnitude of the driving current flowing through the turned-on first transistor T1 to the light-emitting element ED can be determined based on the data voltage VDAT and the threshold voltage of the first transistor T1. Therefore, the driving current supplied to the light-emitting element ED can accurately reflect the magnitude of the data voltage VDAT. In other words, the above driving current can have an accurate value in which the threshold voltage of the first transistor T1 is compensated. In this way, the threshold voltages of different values of the first transistor T1 of each pixel PX can be compensated to determine the driving current of each pixel PX, so that the luminance deviation between the pixels PX due to the deviation of the threshold voltages between the first transistors T1 of each pixel PX can be reduced or minimized. Therefore, the image quality of the display device 100 can be improved.

[0159] Figure 10 is Figure 3 a timing diagram of the emission signal EM, the third gate signal GI, the second gate signal GC, the first gate signal GW, and the fourth gate signal GB in the self-scanning section SFS.

[0160] Referring to Figure 10 , the self-scanning section SFS can include a plurality of periods including a first bias period Ps1, an initialization period Ps2, and a second bias period Ps3.

[0161] For each period of the self-scanning section SFS, the emission signal EM, the third gate signal GI, the second gate signal GC, the first gate signal GW, and the fourth gate signal GB may each have an active level or an inactive level. Here, the active level of each of the above signals may mean a voltage at a level capable of turning on the corresponding transistor to which the corresponding signal is applied. In other words, the active level signal may have a value greater than the threshold voltage of the corresponding transistor. For example, when the corresponding transistor is a p-type transistor, the active level of the signal applied to the gate electrode of the corresponding transistor may mean a low level (e.g., a negative polarity level or a low voltage level).

[0162] Meanwhile, the inactive level of each signal may mean a voltage at a level capable of turning off the corresponding transistor. In other words, the inactive level signal may have a value smaller than the threshold voltage of the corresponding transistor. For example, when the corresponding transistor is a p-type transistor, the inactive level of the signal applied to the gate electrode of the corresponding transistor may mean a high level (e.g., a positive polarity level or a high voltage level).

[0163] Conversely, when the corresponding transistor is an n-type transistor, the active level of the signal applied to the gate electrode of the corresponding transistor may mean a high level (e.g., a positive polarity level or a high voltage level), and the inactive level of the signal applied to the gate electrode of the corresponding transistor may mean a low level (e.g., a negative polarity level or a low voltage level).

[0164] During the first bias period Ps1, the fourth gate signal GB may have an active level. Meanwhile, during the first bias period Ps1, the emission signal EM, the third gate signal GI, the second gate signal GC, and the first gate signal GW may each have an inactive level.

[0165] During the initialization period Ps2, the third gate signal GI may have an active level. Meanwhile, during the initialization period Ps2, the emission signal EM, the second gate signal GC, the first gate signal GW, and the fourth gate signal GB may each have an inactive level.

[0166] During the second bias period Ps3, the fourth gate signal GB may have an active level. Meanwhile, during the second bias period Ps3, the emission signal EM, the third gate signal GI, the second gate signal GC, and the first gate signal GW may each have an inactive level.

[0167] Refer to Figure 11 , the operation of the display device 100 according to one or more embodiments in the self-scanning section SFS will be described as follows. In Figure 11 , the transistor surrounded by the dotted circle is in the on state, and the transistors other than the transistor surrounded by the dotted circle are in the off state.

[0168] First, refer toFigure 10 And Figure 8 , the operation of the display device 100 during the first bias period Ps1 of the self-scanning section SFS will be described as follows. The operation of the display device 100 during the first bias period Ps1 of the self-scanning section SFS is the same as the operation of the display device 100 during the second bias period Pd4 of the above-described display scanning section DSS. Therefore, for the description of the operation of the display device 100 during the first bias period Ps1 of the self-scanning section SFS, refer to Figure 8 and the related description.

[0169] Next, refer to Figure 10 and Figure 11 , the operation of the display device 100 during the initialization period Ps2 of the self-scanning section SFS will be described as follows.

[0170] Figure 11 is a diagram showing the operation of the display device 100 of Figure 3 during the initialization period Ps2 of the self-scanning section SFS of Figure 10 .

[0171] During the initialization period Ps2, the third gate signal GI may have an active level. At the same time, during the initialization period Ps2, the emission signal EM, the second gate signal GC, the first gate signal GW, and the fourth gate signal GB may each have an inactive level.

[0172] The third gate signal GI having an active level may be applied through the third gate line GIL to each of the gate electrodes of the fourth transistor T4 and the seventh transistor T7. Therefore, the fourth transistor T4 and the seventh transistor T7 may each be turned on.

[0173] The emission signal EM having an inactive level may be applied through the emission line EML to each of the gate electrodes of the fifth transistor T5 and the sixth transistor T6. Therefore, the fifth transistor T5 and the sixth transistor T6 may each be turned off.

[0174] The second gate signal GC having an inactive level may be applied through the second gate line GCL to the gate electrode of the third transistor T3. Therefore, the third transistor T3 may be turned off.

[0175] The first gate signal GW having an inactive level may be applied through the first gate line GWL to the gate electrode of the second transistor T2. Therefore, the second transistor T2 may be turned off.

[0176] The fourth gate signal GB having an inactive level may be applied through the fourth gate line GBL to the gate electrode of the eighth transistor T8. Therefore, the eighth transistor T8 may be turned off.

[0177] At the same time, during the initialization period Ps2, the first transistor T1 may remain in the off state.

[0178] When the fourth transistor T4 is turned on, the voltage of the second node N2 can be initialized to the first initialization voltage VINT1. In other words, the voltage of the drain electrode of the first transistor T1 can be initialized to the first initialization voltage VINT1. In this way, since the voltage of the drain electrode of the first transistor T1 in the self-scanning section SFS remains at the first initialization voltage VINT1 which can be a known voltage rather than an unknown voltage, spots on the screen of the display device 100 can be reduced or prevented during the above-mentioned emission period Pd5.

[0179] When the seventh transistor T7 is turned on, the voltage of the fourth node N4 can be initialized to the second initialization voltage VINT2. In other words, the voltage of the first electrode of the light-emitting element ED can be initialized to the second initialization voltage VINT2.

[0180] On the other hand, since the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are each turned off, and since a reverse bias voltage is applied to the light-emitting element ED, the light-emitting element ED can remain in the off state during the initialization period Ps2.

[0181] Next, referring to Figure 10 and Figure 8 , the operation of the display device 100 during the second bias period Ps3 of the self-scanning section SFS will be described as follows. The operation of the display device 100 during the second bias period Ps3 of the self-scanning section SFS is the same as the operation of the display device 100 during the second bias period Pd4 of the above-mentioned display scanning section DSS. Therefore, for the description of the operation of the display device 100 during the second bias period Ps3 of the self-scanning section SFS, refer to Figure 8 and the related description.

[0182] Meanwhile, the above-mentioned light-emitting element ED may have a series structure, which will be described with reference to Figures 12 to 19 as follows.

[0183] Figures 12 to 16 is a cross-sectional view showing the structure of the light-emitting element ED according to one or more embodiments.

[0184] Referring to Figure 12 , according to one or more embodiments, a light-emitting element (e.g., an organic light-emitting diode) may include a pixel electrode 201, a common electrode 205, and an intermediate layer 203 between the pixel electrode 201 and the common electrode 205.

[0185] The pixel electrode 201 may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The pixel electrode 201 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. For example, the pixel electrode 201 may have a three-layer structure of ITO / Ag / ITO.

[0186] The common electrode 205 may be positioned on the intermediate layer 203. The common electrode 205 may include a low work function metal, alloy, conductive compound, or any combination thereof. For example, the common electrode 205 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The common electrode 205 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0187] The intermediate layer 203 may include a polymer material or a low molecular weight material that emits light of a color (e.g., a predetermined color). In addition to various organic materials, the intermediate layer 203 may also include compounds containing metals (such as metal organic compounds), inorganic materials (such as quantum dots), and similar materials.

[0188] In one or more embodiments, the intermediate layer 203 may include a single light-emitting layer, and may include a first functional layer and a second functional layer respectively positioned below and above the single light-emitting layer. For example, the first functional layer may include a hole transport layer HTL, or may include a hole transport layer HTL and a hole injection layer HIL. The second functional layer may be a component positioned on the light-emitting layer, and is optional. For example, the intermediate layer 203 may or may not include the second functional layer. The second functional layer may include an electron transport layer ETL and / or an electron injection layer EIL.

[0189] In one or more embodiments, the intermediate layer 203 may include two or more emission units sequentially stacked between the pixel electrode 201 and the common electrode 205, and a charge generation layer CGL positioned between the two emission units. When the intermediate layer 203 includes emission units and a charge generation layer, the light-emitting element (e.g., an organic light-emitting diode) may be a tandem light-emitting element. The light-emitting element (e.g., an organic light-emitting diode) may improve color purity and light-emitting efficiency through a stacked structure having multiple emission units.

[0190] An emission unit may include a light-emitting layer, and may include a first functional layer and a second functional layer positioned below and above the light-emitting layer, respectively. A charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer. The luminous efficiency of an organic light-emitting diode as a tandem light-emitting element having a plurality of light-emitting layers may be further improved by the negative charge generation layer and the positive charge generation layer.

[0191] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metal material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metal material.

[0192] In one or more embodiments, as Figure 13 shown, a light-emitting element (e.g., an organic light-emitting diode) may include a first emission unit EU1 including a first light-emitting layer EL1 and a second emission unit EU2 including a second light-emitting layer EL2, which are sequentially stacked. The charge generation layer CGL may be positioned between the first emission unit EU1 and the second emission unit EU2. For example, a light-emitting element (e.g., an organic light-emitting diode) may include a pixel electrode 201, a first light-emitting layer EL1, a charge generation layer CGL, a second light-emitting layer EL2, and a common electrode 205, which are sequentially stacked. The first functional layer and the second functional layer may be positioned above and below the first light-emitting layer EL1, respectively. The first functional layer and the second functional layer may be positioned below and above the second light-emitting layer EL2, respectively. The first light-emitting layer EL1 may be a blue light-emitting layer, and the second light-emitting layer EL2 may be a yellow light-emitting layer.

[0193] In one or more embodiments, as Figure 14 shown, a light-emitting element (e.g., an organic light-emitting diode) may include a first emission unit EU1 and a third emission unit EU3 both including a first light-emitting layer EL1, and may include a second emission unit EU2 including a second light-emitting layer EL2. A first charge generation layer CGL1 may be positioned between the first emission unit EU1 and the second emission unit EU2, and a second charge generation layer CGL2 may be positioned between the second emission unit EU2 and the third emission unit EU3. For example, a light-emitting element (e.g., an organic light-emitting diode) may include a pixel electrode 201, a first light-emitting layer EL1, a first charge generation layer CGL1, a second light-emitting layer EL2, a second charge generation layer CGL2, a first light-emitting layer EL1, and a common electrode 205, which are sequentially stacked. The first functional layer and the second functional layer may be positioned above and below the first light-emitting layer EL1, respectively. The first functional layer and the second functional layer may be positioned above and below the second light-emitting layer EL2, respectively. The first light-emitting layer EL1 may be a blue light-emitting layer, and the second light-emitting layer EL2 may be a yellow light-emitting layer.

[0194] In one or more embodiments (e.g., see Figure 15 and Figure 16 ), in a light-emitting element (e.g., an organic light-emitting diode), in addition to the second light-emitting layer EL2, the second emission unit EU2 may further include a third light-emitting layer EL3 and / or a fourth light-emitting layer EL4 that are in direct contact with the second light-emitting layer EL2 below and / or above the second light-emitting layer EL2. Here, direct contact may mean that no other layer is positioned between the second light-emitting layer EL2 and the third light-emitting layer EL3 and / or between the second light-emitting layer EL2 and the fourth light-emitting layer EL4. The third light-emitting layer EL3 may be a red light-emitting layer, and the fourth light-emitting layer EL4 may be a green light-emitting layer.

[0195] For example, as shown in Figure 15 , a light-emitting element (e.g., an organic light-emitting diode) may include a pixel electrode 201, a first light-emitting layer EL1, a first charge generation layer CGL1, a third light-emitting layer EL3, a second light-emitting layer EL2, a second charge generation layer CGL2, a first light-emitting layer EL1, and a common electrode 205 that are sequentially stacked. Alternatively, as shown in Figure 16 , a light-emitting element (e.g., an organic light-emitting diode) may include a pixel electrode 201, a first light-emitting layer EL1, a first charge generation layer CGL1, a third light-emitting layer EL3, a second light-emitting layer EL2, a fourth light-emitting layer EL4, a second charge generation layer CGL2, a first light-emitting layer EL1, and a common electrode 205 that are sequentially stacked.

[0196] Figure 17 is a cross-sectional view showing an example of the organic light-emitting diode of Figure 15 , and Figure 18 is a cross-sectional view showing an example of the organic light-emitting diode of Figure 16 .

[0197] Referring to Figure 17 , a light-emitting element (e.g., an organic light-emitting diode) may include a first emission unit EU1, a second emission unit EU2, and a third emission unit EU3 that are sequentially stacked. The first charge generation layer CGL1 may be positioned between the first emission unit EU1 and the second emission unit EU2, and the second charge generation layer CGL2 may be positioned between the second emission unit EU2 and the third emission unit EU3. The first charge generation layer CGL1 and the second charge generation layer CGL2 may each include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0198] The first emission unit EU1 may include a blue emission layer BEML. The first emission unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL between the pixel electrode 201 and the blue emission layer BEML. In one or more embodiments, a p-doped layer may also be included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer may be formed by doping the hole injection layer HIL with a p-type doping material. In one or more embodiments, at least one of a blue light assist layer, an electron blocking layer, and a buffer layer may also be included between the blue emission layer BEML and the hole transport layer HTL. The blue light assist layer may improve the light emission efficiency of the blue emission layer BEML. The blue light assist layer may improve the light emission efficiency of the blue emission layer BEML by adjusting the hole charge balance. The electron blocking layer may reduce or prevent electrons from being injected into the hole transport layer HTL. The buffer layer may compensate for the resonance distance according to the wavelength of the light emitted from the emission layer.

[0199] The second emission unit EU2 may include a yellow emission layer YEML and a red emission layer REML located below the yellow emission layer YEML and in direct contact with the yellow emission layer YEML. The second emission unit EU2 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emission layer REML, and may also include an electron transport layer ETL between the yellow emission layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0200] The third emission unit EU3 may include a blue emission layer BEML. The third emission unit EU3 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue emission layer BEML. The third emission unit EU3 may also include an electron transport layer ETL and an electron injection layer EIL between the blue emission layer BEML and the common electrode 205. The electron transport layer ETL may have a single layer or multiple layers. In one or more embodiments, at least one of a blue light assist layer, an electron blocking layer, and a buffer layer may also be included between the blue emission layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may also be included between the blue emission layer BEML and the electron transport layer ETL. The hole blocking layer may reduce or prevent holes from being injected into the electron transport layer ETL.

[0201] Figure 18 The light-emitting element (e.g., organic light-emitting diode) shown in Figure 17 differs from the light-emitting element (e.g., organic light-emitting diode) shown in Figure 18, the second emission unit EU2 may include a yellow emission layer YEML, a red emission layer REML located below the yellow emission layer YEML and in direct contact with the yellow emission layer YEML, and a green emission layer GEML located above the yellow emission layer YEML and in direct contact with the yellow emission layer YEML. The second emission unit EU2 may further include a hole transport layer HTL located between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emission layer REML, and may further include an electron transport layer ETL located between the green emission layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0202] Figure 19 is a cross-sectional view showing the structure of a pixel of a display device according to one or more embodiments.

[0203] Referring to Figure 19 , the display panel 110 of the display device 100 may include a plurality of pixels. The plurality of pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel electrode 201, a common electrode 205, and an intermediate layer 203. In one or more embodiments, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel.

[0204] The pixel electrode 201 may be independently provided in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0205] The intermediate layer 203 of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first emission unit EU1 and a second emission unit EU2 stacked in sequence, and a charge generation layer CGL located between the first emission unit EU1 and the second emission unit EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0206] The first emission unit EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red emission layer REML, and an electron transport layer ETL that are sequentially stacked on the pixel electrode 201. The first emission unit EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL that are sequentially stacked on the pixel electrode 201. The first emission unit EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue emission layer BEML, and an electron transport layer ETL that are sequentially stacked on the pixel electrode 201. Each of the hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of the first emission unit EU1 may be a common layer that is continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0207] The second emission unit EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red emission layer REML, and an electron transport layer ETL that are sequentially stacked on the charge generation layer CGL. The second emission unit EU2 of the second pixel PX2 may include a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL that are sequentially stacked on the charge generation layer CGL. The second emission unit EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue emission layer BEML, and an electron transport layer ETL that are sequentially stacked on the charge generation layer CGL. Each of the hole transport layer HTL and the electron transport layer ETL of the second emission unit EU2 may be a common layer that is continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3. In one or more embodiments, at least one of a hole blocking layer and a buffer layer may further be included between the emission layer and the electron transport layer ETL in the second emission unit EU2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0208] The thickness H1 of the red emission layer REML, the thickness H2 of the green emission layer GEML, and the thickness H3 of the blue emission layer BEML may be determined according to the resonance distance. The auxiliary layer AXL may be a layer added for adjusting the resonance distance and may include a resonance auxiliary material. For example, the auxiliary layer AXL may include the same material as the material of the hole transport layer HTL.

[0209] In Figure 19 the auxiliary layer AXL may be only located in the first pixel PX1, but the present disclosure is not limited thereto. For example, the auxiliary layer AXL may be located in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to adjust the resonance distance of the corresponding pixel in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0210] The display panel 110 of the display device 100 may further include a cover layer 207 positioned outside the common electrode 205. The cover layer 207 may improve the light emission efficiency through the principle of constructive interference. Accordingly, the light extraction efficiency of a light-emitting element (e.g., an organic light-emitting diode) may be increased, and thus the light emission efficiency of the light-emitting element (e.g., an organic light-emitting diode) may be improved.

[0211] The above-mentioned Figure 3 pixels may also be applied to the Figure 20 and Figure 21 display devices to be described later.

[0212] Figure 20 is a perspective view showing a display device according to one or more embodiments. Figure 21 is a perspective view showing an extended state of a display device according to one or more embodiments.

[0213] In Figure 20 , a first direction DR1, a second direction DR2, and a third direction DR3 are defined. The first direction DR1 and the second direction DR2 may be perpendicular to each other, the first direction DR1 and the third direction DR3 may be perpendicular to each other, and the second direction DR2 and the third direction DR3 may be perpendicular to each other. It can be understood that the first direction DR1 refers to the horizontal direction in the figure, the second direction DR2 refers to the vertical direction in the figure, and the third direction DR3 refers to the up-and-down direction in the figure (e.g., the thickness direction). In the following description, unless otherwise specified, the "direction" may refer to two directions extending along that direction. In addition, when distinguishing two "directions" extending on both sides, one side will be referred to as "one side in that direction", and the other side will be referred to as "the other side in that direction". Refer to Figure 20 , where the direction pointed by the arrow is referred to as one side, and the opposite direction is referred to as the other side.

[0214] Hereinafter, for the sake of simplicity of description, when referring to the surface of the display device 1000 or each component constituting the display device 1000, one surface facing one side in the image display direction (i.e., the third direction DR3) is referred to as the top surface, and the opposite surface of the one surface is referred to as the bottom surface. However, the present disclosure is not limited thereto, and one surface and the other surface of a component may be referred to as the front surface and the rear surface, respectively, or may also be referred to as the first surface or the second surface. In addition, when describing the relative positions of each component of the display device 1000, one side in the third direction DR3 may be referred to as the upper side, and the other side in the third direction DR3 may be referred to as the lower side.

[0215] Refer to Figures 20 to 21, the display device 1000 according to one or more embodiments may be a sliding display device or a slidable display device that can slide in a first direction DR1. The display device 1000 according to one or more embodiments may be a multi-directionally slidable display device that can slide in two directions (e.g., on both sides of the first direction DR1), but is not limited thereto. For example, the display device 1000 may be a unidirectionally slidable display device that can slide only in one direction (e.g., only on one side of the first direction DR1 or only on the other side of the first direction DR1). Hereinafter, the display device 1000 according to one or more embodiments will be mainly described as a multi-directionally slidable display device.

[0216] The display device 1000 may include a display device flat area PA and a display device curved area RA. The display device flat area PA of the display device 1000 substantially overlaps with the area where the display panel PNL of the panel storage container SD to be described later is exposed. The display device curved area RA of the display device 1000 may be formed in the panel storage container SD. The display device curved area RA may be curved with a radius of curvature (e.g., a predetermined radius of curvature) and may be an area where the display panel PNL is curved according to the radius of curvature. The display device curved area RA may be positioned on both sides of the display device flat area PA in the first direction DR1. That is, the first display device curved area RA_1 may be positioned on one side of the display device flat area PA in the first direction DR1, and the second display device curved area RA_2 may be positioned on the other side of the display device flat area PA in the first direction DR1. Meanwhile, as Figure 21 shown, the size of the display device flat area PA may increase as the display device 1000 expands. Therefore, the distance between the first display device curved area RA_1 and the second display device curved area RA_2 may increase.

[0217] Referring to Figure 20 and Figure 21 , the display device 1000 according to one or more embodiments may include a display panel PNL and a panel storage container SD.

[0218] The display panel PNL is a panel for displaying a screen, and any type of display panel such as an organic light-emitting display panel including an organic light-emitting layer, a micro light-emitting diode (LED) display panel using micro light-emitting diodes, a quantum dot light-emitting diode display panel using a quantum dot light-emitting layer, or an inorganic light-emitting display panel using an inorganic light-emitting element including an inorganic semiconductor may be applied to the display panel PNL.

[0219] The display panel PNL can be a flexible panel. As will be described later, the display panel PNL can have flexibility to be partially curled, bent, or folded in the panel storage container SD. The display panel PNL can slide in the first direction DR1.

[0220] The display panel PNL can include an active area and a non-active area. The active area of the display panel PNL can be an area where a plurality of pixels are located. The non-active area of the display panel PNL is an area where no pixels are located. Metal lines such as data / scan lines, touch lines, or power voltage lines can be located in the non-active area. The non-active area can be located to surround the active area.

[0221] The display area DA of the display panel PNL can be an area where a screen is displayed. Depending on whether the display panel PNL slides or the degree of sliding of the display panel PNL, the display area DA can be divided into a first display area DA_1, a second display area DA_2, and a third display area DA_3. The presentation and size of the second display area DA_2 and the third display area DA_3 can change depending on whether the display panel PNL slides or the degree of sliding of the display panel PNL. For example, in the non-sliding state, the display area DA of the display panel PNL includes a first display area DA_1 having a first size. In the sliding state, the display area DA includes, in addition to the first display area DA_1, an extended second display area DA_2 and a third display area DA_3.

[0222] The sizes of the second display area DA_2 and the third display area DA_3 can change depending on the degree of sliding. For example, in a state where the display device 1000 slides to the maximum, the second display area DA_2 can have a second size, the third display area DA_3 can have a third size, and the display area DA can have a fourth size that is the sum of the first size, the second size, and the third size. In this case, the fourth size can be the maximum size that the display area DA can have.

[0223] As Figure 20 and Figure 21 As shown in

[0224] The first storage container SD_1 can connect the second storage container SD_2 and the third storage container SD_3 to each other. For example, the first storage container SD_1 can include a first-first storage container SD_1a and a first-second storage container SD_1b. The first-first storage container SD_1a connects the other side of the second storage container SD_2 in the second direction DR2 and the other side of the third storage container SD_3 in the second direction DR2. The first-second storage container SD_1b connects one side of the second storage container SD_2 in the second direction DR2 and one side of the third storage container SD_3 in the second direction DR2.

[0225] In some embodiments, tracks may be formed in the second storage container SD_2 and the third storage container SD_3 to guide the sliding operation of the display panel PNL, but the present disclosure is not limited thereto.

[0226] At the end of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the embodiments without substantially departing from the aspects of the present disclosure. Therefore, the disclosed embodiments are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: A light-emitting element, wherein the light-emitting element is connected between a driving voltage line and a common voltage line; A first transistor, wherein the first transistor is connected between the driving voltage line and the light-emitting element; A second transistor, wherein the second transistor is connected between a data line and a source electrode of the first transistor; A third transistor, wherein the third transistor is connected between a gate electrode of the first transistor and a drain electrode of the first transistor; And A fourth transistor, wherein the fourth transistor is connected between the drain electrode of the first transistor and a first initialization voltage line, wherein the third transistor and the fourth transistor have the same type.

2. The display device according to claim 1, wherein The third transistor and the fourth transistor comprise n-type transistors.

3. The display device according to claim 1, further comprising: A seventh transistor, wherein the seventh transistor is connected between a first electrode of the light-emitting element and a second initialization voltage line.

4. The display device according to claim 3, further comprising: A third gate line, wherein the third gate line is connected to a gate electrode of the seventh transistor and a gate electrode of the fourth transistor.

5. The display device according to claim 3, wherein, The third transistor, the fourth transistor, and the seventh transistor have the same type.

6. The display device according to claim 5, wherein, The third transistor, the fourth transistor, and the seventh transistor comprise n-type transistors.

7. The display device according to claim 3, further comprising: A fifth transistor, wherein the fifth transistor is connected between the source electrode of the first transistor and the driving voltage line; A sixth transistor, wherein the sixth transistor is connected between the drain electrode of the first transistor and the first electrode of the light-emitting element; An eighth transistor, wherein the eighth transistor is connected between the source electrode of the first transistor and a bias voltage line; And A capacitor, wherein the capacitor is connected between the driving voltage line and the gate electrode of the first transistor.

8. The display device according to claim 7, further comprising: A first gate line, wherein the first gate line is connected to a gate electrode of the second transistor; A second gate line, wherein the second gate line is connected to a gate electrode of the third transistor; A third gate line, wherein the third gate line is connected to a gate electrode of the fourth transistor and a gate electrode of the seventh transistor; An emission line, wherein the emission line is connected to a gate electrode of the fifth transistor and a gate electrode of the sixth transistor; And A fourth gate line, wherein the fourth gate line is connected to a gate electrode of the eighth transistor.

9. The display device according to claim 8, wherein, The first gate line is configured to send a first gate signal, wherein the second gate line is configured to send a second gate signal, wherein the third gate line is configured to send a third gate signal, wherein the fourth gate line is configured to send a fourth gate signal, and wherein the emission line is configured to send an emission signal.

10. The display device according to claim 9, wherein, The first gate signal, the second gate signal, the third gate signal, the fourth gate signal, and the emission signal have effective levels and ineffective levels in a display scan period and a self-scan period.

11. The display device according to claim 10, wherein, The display scan period includes a first bias period, an initialization period, a compensation period, a second bias period, and an emission period.

12. The display device according to claim 11, wherein, During the first bias period of the display scan segment, the second gate signal and the fourth gate signal are configured to have the effective level, and the emission signal, the third gate signal, and the first gate signal are configured to have the invalid level.

13. The display device according to claim 11, wherein, During the initialization period of the display scan segment, the third gate signal and the second gate signal are configured to have the effective level, and the emission signal, the first gate signal, and the fourth gate signal are configured to have the invalid level.

14. The display device according to claim 11, wherein, During the compensation period of the display scan segment, the second gate signal and the first gate signal are configured to have the effective level, and the emission signal, the third gate signal, and the fourth gate signal are configured to have the invalid level.

15. The display device according to claim 14, wherein, The first gate signal is configured to have the effective level during the data writing period of the compensation period.

16. The display device according to claim 15, wherein, The data voltage is configured to be applied to the data line during the data writing period.

17. The display device according to claim 11, wherein, During the emission period of the display scan segment, the emission signal is configured to have the effective level, and the third gate signal, the second gate signal, the first gate signal, and the fourth gate signal are configured to have the invalid level.

18. The display device according to claim 10, wherein, The self-scan segment includes a first bias period, an initialization period, and a second bias period.

19. The display device according to claim 18, wherein, During the first bias period of the self-scan segment, the fourth gate signal is configured to have the effective level, and the emission signal, the third gate signal, the second gate signal, and the first gate signal are configured to have the invalid level.

20. The display device according to claim 18, wherein, During the initialization period of the self-scan segment, the third gate signal is configured to have the effective level, and the emission signal, the second gate signal, the first gate signal, and the fourth gate signal are configured to have the invalid level.

21. The display device according to claim 18, wherein, During the second bias period of the self-scan segment, the fourth gate signal is configured to have the effective level, and the emission signal, the third gate signal, the second gate signal, and the first gate signal are configured to have the invalid level.

22. The display device according to claim 7, wherein, The first transistor, the second transistor, the fifth transistor, the sixth transistor, and the eighth transistor include p-type transistors, and wherein, the third transistor, the fourth transistor, and the seventh transistor include n-type transistors.

23. A display device, comprising: A light-emitting element connected between a driving voltage line and a common voltage line; A first transistor connected between the driving voltage line and the light-emitting element; A second transistor connected between a data line and a source electrode of the first transistor; A third transistor connected between a gate electrode of the first transistor and a drain electrode of the first transistor; A fourth transistor connected between the drain electrode of the first transistor and a first initialization voltage line; And A seventh transistor, the seventh transistor being connected between a first electrode of the light-emitting element and a second initialization voltage line, wherein the third transistor and the seventh transistor have the same type.

24. The display device according to claim 23, wherein, The third transistor and the seventh transistor include n-type transistors.

25. The display device according to claim 23, wherein, The third transistor, the fourth transistor, and the seventh transistor have the same type.

26. The display device according to claim 25, wherein, The third transistor, the fourth transistor, and the seventh transistor include n-type transistors.

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