Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device. In one specific implementation mode, the display panel comprises a substrate, a driving circuit layer, a light emitting device layer, a packaging layer and a light conversion layer, the driving circuit layer, the light emitting device layer, the packaging layer and the light conversion layer are sequentially arranged on the substrate in a stacked mode, the light emitting device layer comprises an anode layer, a pixel defining layer, a light emitting function layer and a cathode layer which are sequentially arranged in a stacked mode, and the display panel comprises a plurality of sub-pixels. The anode layer comprises anodes located in the sub-pixels, the light-emitting function layer comprises a plurality of sub-light-emitting layers which are sequentially arranged in a stacked mode, a charge transmission layer is arranged between every two adjacent sub-light-emitting layers, and the display panel further comprises isolation columns arranged between at least one pair of adjacent sub-pixels. And at least part of the charge transport layer in the light-emitting functional layer is disconnected by the isolation columns. According to the embodiment, crosstalk among the sub-pixels can be avoided, so that the image quality of a display product is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies. More specifically, it relates to a display panel and a display device. Background Art

[0002] Currently, for a quantum dot (QD) display panel with photoluminescence, it is generally designed to use short-wavelength and high-energy excitation lights such as blue light and violet light to excite red, green, and blue quantum dot units, so that the red, green, and blue quantum dot units emit display light, achieving high-gamut full-color display. The quantum dot display panel has advantages such as a wide gamut and relatively high light extraction efficiency. For example, the quantum dot display panel may include an organic light-emitting diode (OLED) light-emitting layer and a light conversion layer (or a quantum dot layer) disposed on the light-emitting side of the excitation light of the OLED light-emitting layer. Such a quantum dot display panel can be called a quantum dot - organic light-emitting diode (QD-OLED) display panel. The inventors have found that crosstalk often occurs between sub-pixels in the QD-OLED display panel, affecting the image quality of the display product. Summary of the Invention

[0003] The purpose of the present disclosure is to provide a display panel and a display device to solve at least one of the problems existing in the prior art.

[0004] To achieve the above object, the present disclosure adopts the following technical solutions:

[0005] In a first aspect of the present disclosure, a display panel is provided, including a substrate, a driving circuit layer, a light-emitting device layer, a packaging layer, and a light conversion layer that are sequentially stacked on the substrate. The light-emitting device layer includes an anode layer, a pixel defining layer, a light-emitting functional layer, and a cathode layer that are sequentially stacked. The display panel includes a plurality of sub-pixels. The anode layer includes an anode located in the sub-pixels. The light-emitting functional layer includes a plurality of sub-light-emitting layers that are sequentially stacked, and a charge transport layer is disposed between adjacent sub-light-emitting layers. Wherein, the display panel further includes an isolation column disposed between at least a pair of adjacent sub-pixels, and the isolation column disconnects at least a part of the charge transport layer in the light-emitting functional layer.

[0006] Optionally, the plurality of sub-pixels include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. The isolation column includes at least one of a first isolation column close to the first sub-pixel, a second isolation column close to the second sub-pixel, and a third isolation column close to the third sub-pixel.

[0007] Optionally, the first isolation pillar has at least one first gap that causes the first isolation pillar to be formed into at least two discontinuous first sub-isolation pillars, the second isolation pillar has at least one second gap that causes the second isolation pillar to be formed into at least two discontinuous second sub-isolation pillars, and the third isolation pillar has at least one third gap that causes the third isolation pillar to be formed into at least two discontinuous third sub-isolation pillars.

[0008] Optionally, the isolation pillars include a first isolation pillar near the first sub-pixel, a second isolation pillar near the second sub-pixel, and a third isolation pillar near the third sub-pixel. A first isolation pillar or a second isolation pillar is disposed between the adjacent first sub-pixel and the second sub-pixel, a first isolation pillar or a third isolation pillar is disposed between the adjacent first sub-pixel and the third sub-pixel, and a second isolation pillar or a third isolation pillar is disposed between the adjacent second sub-pixel and the third sub-pixel.

[0009] Optionally, the isolation pillars include a first isolation pillar near the first sub-pixel, a second isolation pillar near the second sub-pixel, and a third isolation pillar near the third sub-pixel. A first isolation pillar and a second isolation pillar are disposed between the adjacent first sub-pixel and the second sub-pixel, a first isolation pillar and a third isolation pillar are disposed between the adjacent first sub-pixel and the third sub-pixel, and a second isolation pillar and a third isolation pillar are disposed between the adjacent second sub-pixel and the third sub-pixel.

[0010] Optionally, the widths of the first isolation pillar, the second isolation pillar, and the third isolation pillar are respectively a first width.

[0011] Optionally, the first width is 15%-25% of the minimum width of the pixel defining layer between adjacent sub-pixels.

[0012] Optionally, the isolation pillar is located on the side of the pixel defining layer away from the substrate, and the isolation pillar causes the light-emitting functional layer to be disconnected.

[0013] Optionally, the ratio of the thickness of the isolation pillar to the thickness of the light-emitting functional layer is greater than 2.

[0014] Optionally, the light-emitting functional layer includes a plurality of blue photon light-emitting layers stacked in sequence and a green photon light-emitting layer on the side of the plurality of blue photon light-emitting layers away from the substrate. The isolation pillar is located on the side of the plurality of blue photon light-emitting layers away from the substrate, and the isolation pillar causes the green photon light-emitting layer and the first charge transport layer to be disconnected. The first charge transport layer is the charge transport layer between the green photon light-emitting layer and the blue photon light-emitting layer.

[0015] Optionally, the ratio of the thickness of the isolation pillar to the first thickness is greater than 2, where the first thickness is the sum of the thicknesses of the green photon emitting layer and the charge transport layer.

[0016] Optionally, the display panel further includes a color filter layer on a side of the light conversion layer away from the substrate. The light conversion layer includes a first quantum dot layer in a first sub-pixel, a second quantum dot layer in a second sub-pixel, and a third quantum dot layer in a third sub-pixel. The color filter layer includes a first color filter layer in the first sub-pixel, a second color filter layer in the second sub-pixel, and a third color filter layer in the third sub-pixel.

[0017] A second aspect of the present disclosure provides a display device including the display panel provided by the first aspect of the present disclosure.

[0018] The beneficial effects of the present disclosure are as follows:

[0019] In the technical solution of the present disclosure, by providing isolation pillars that cause the charge transport layer to be disconnected, the occurrence of lateral current between adjacent sub-pixels can be effectively avoided, thereby avoiding crosstalk between sub-pixels and improving the picture quality of the display product. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The following further describes in detail the specific embodiments of the present disclosure with reference to the drawings.

[0021] Figure 1 A top view schematic diagram of a partial display area of an OD-OLED display panel provided by an embodiment of the present disclosure is shown.

[0022] Figure 2 Shown Figure 1 A cross-sectional schematic diagram of a partial display area of the OD-OLED display panel shown is shown.

[0023] Figure 3 A cross-sectional schematic diagram of a light-emitting functional layer in a sub-pixel of an OD-OLED display panel provided by an embodiment of the present disclosure is shown.

[0024] Figure 4 Shown Figure 2 An enlarged cross-sectional schematic diagram of the first isolation pillar area shown is shown.

[0025] Figure 5 Shown Figure 1 A comparison diagram of the blue light spectral curves of the OD-OLED display panel provided by an embodiment of the present disclosure and a reference example is shown.

[0026] Figure 6 A top view schematic diagram of another partial display area of an OD-OLED display panel provided by an embodiment of the present disclosure is shown.

[0027] Figure 7Shows a top - view schematic diagram of another partial display area of the OD - OLED display panel provided by the embodiments of the present disclosure.

[0028] Figure 8 Shows a top - view schematic diagram of another partial display area of the OD - OLED display panel provided by the embodiments of the present disclosure.

[0029] Figure 9 Shows Figure 8 A cross - sectional schematic diagram of the partial display area of the OD - OLED display panel shown.

[0030] Figure 10 Shows Figure 1 A cross - sectional schematic diagram of another partial display area of the OD - OLED display panel shown

[0031] Figure 11 Shows a schematic diagram of the generation of lateral current in the charge - transfer layer between adjacent sub - pixels. Detailed implementation manners

[0032] In the present disclosure, the expressions "on...", "formed on...", and "disposed on..." may mean that one layer is directly formed or disposed on another layer, or may mean that one layer is indirectly formed or disposed on another layer, that is, there are other layers between the two layers.

[0033] It should be noted that although terms such as "first", "second", etc. may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as the second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of the present disclosure.

[0034] In the present disclosure, unless otherwise specified, the term "co - layer setting" means that two layers, components, members, elements, or parts can be formed by the same preparation process (such as a patterning process, etc.), and generally, these two layers, components, members, elements, or parts are formed of the same material. For example, the co - layer setting of two or more functional layers means that these co - layer - set functional layers can be formed using the same material layer and the same preparation process, thereby simplifying the preparation process of the display substrate.

[0035] In the present disclosure, unless otherwise specified, the expression "patterning process" generally includes steps such as coating of photoresist, exposure, development, etching, and stripping of photoresist. The expression "one patterning process" means a process of forming a patterned layer, component, member, etc. using one mask.

[0036] In QD-OLED display panels, crosstalk between sub-pixels often occurs. Through analysis, the inventor found that the QD-OLED display panels with crosstalk between sub-pixels are those with a tandem structure for the OLED light-emitting functional layer. After further analysis, although the tandem structure has advantages such as long lifespan, low power consumption, and high light extraction efficiency in the positive viewing angle, on the one hand, its driving voltage is relatively high, and on the other hand, in the multiple sub-light-emitting layers stacked in sequence in the light-emitting functional layer, a charge transport layer (CGL) needs to be provided between adjacent sub-light-emitting layers. In this way, after the OLED light-emitting functional layer, which serves as the backlight source in the QD-OLED display panel, is prepared by, for example, a vacuum evaporation process using an open mask that is open throughout the display area (or the light-emitting area), the OLED light-emitting functional layers in adjacent sub-pixels are common or connected, and it is easy for a lateral current to be generated in the charge transport layer between adjacent sub-pixels, resulting in crosstalk between sub-pixels and affecting the image quality of the display product.

[0037] In view of this, embodiments of the present disclosure provide a QD-OLED display panel, including a substrate, a driving circuit layer, a light-emitting device layer, a packaging layer, and a light conversion layer that are sequentially stacked on the substrate. The light-emitting device layer includes an anode layer, a pixel defining layer, a light-emitting functional layer, and a cathode layer that are sequentially stacked. The display panel includes a plurality of sub-pixels. The anode layer includes an anode in the sub-pixels. The light-emitting functional layer includes a plurality of sub-light-emitting layers that are sequentially stacked, and a charge transport layer is provided between adjacent sub-light-emitting layers. Among them, the display panel further includes isolation pillars provided between at least a pair of adjacent sub-pixels, and the isolation pillars disconnect at least part of the charge transport layer in the light-emitting functional layer.

[0038] The QD-OLED display panel provided in this embodiment can effectively avoid the occurrence of lateral current between adjacent sub-pixels by providing isolation pillars that disconnect the charge transport layer, thereby avoiding crosstalk between sub-pixels and improving the image quality of the display product.

[0039] In a possible implementation manner, the plurality of sub-pixels include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. The isolation pillars include at least one of a first isolation pillar close to the first sub-pixel, a second isolation pillar close to the second sub-pixel, and a third isolation pillar close to the third sub-pixel.

[0040] In a specific example, the QD-OLED display panel provided in the embodiments of the present disclosure, for example Figure 1 and Figure 2As shown, it includes a substrate 201, a driving circuit layer, a light-emitting device layer 203, a packaging layer 204, and a light conversion layer that are sequentially stacked on the substrate 201. The light-emitting device layer 203 includes an anode layer, a pixel definition layer 2032, a light-emitting functional layer 2033, and a cathode layer 2034 that are sequentially stacked.

[0041] The display panel includes a plurality of sub-pixels. The plurality of sub-pixels include a plurality of first sub-pixels 101, a plurality of second sub-pixels 102, and a plurality of third sub-pixels 103. For example, Figure 1 As shown, the plurality of first sub-pixels 101, the plurality of second sub-pixels 102, and the plurality of third sub-pixels 103 are respectively arranged in an array. For example, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, and the third sub-pixel 103 is a blue sub-pixel.

[0042] The driving circuit layer includes a thin-film transistor (TFT) 2021 located in the sub-pixel and a planarization layer 2022 covering the thin-film transistor 2021.

[0043] The anode layer includes an anode 2031 located in the sub-pixel. The anode 2031 is electrically connected to the thin-film transistor 2021 through a via hole formed in the planarization layer 2022. As Figure 2 shown, the anodes 2031 in each sub-pixel are independent. Figure 1 As shown in, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 in are, for example, corresponding to Figure 2 the anode 2031 exposed by the first opening of the pixel definition layer 2032 shown in.

[0044] The light-emitting functional layer 2033 includes a plurality of sub-light-emitting layers that are sequentially stacked, and a charge transport layer is provided between adjacent sub-light-emitting layers.

[0045] For example Figure 1 and Figure 2 As shown in and, the QD-OLED display panel provided in this embodiment further includes spacer columns disposed between each pair of adjacent sub-pixels. The spacer columns cause at least a part of the charge transport layer in the light-emitting functional layer to be disconnected. For example Figure 1 and Figure 2 As shown in and, the spacer columns include a first spacer column 1041 close to the first sub-pixel 101, a second spacer column 1042 close to the second sub-pixel 102, and a third spacer column 1043 close to the third sub-pixel 103.

[0046] For example Figure 1 and Figure 2As shown, the sub-pixel units composed of the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are arranged periodically in the row direction and the column direction. In the sub-pixel unit, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are arranged in a triangular shape. The shapes of the first isolation pillar 1041, the second isolation pillar 1042, and the third isolation pillar 1043 are respectively L-shaped, so as to ensure that an isolation pillar structure that disconnects at least part of the charge transport layer in the light-emitting functional layer 2033 is provided between each pair of adjacent sub-pixels. It should be noted that Figure 1 As shown, the sub-pixels corresponding to the three anodes 2031 from left to right are the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103, respectively, and can Figure 2 be obtained by performing a broken-line intercept on the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 arranged in a triangular shape. If an intercept is performed on the first sub-pixel, the second sub-pixel, and the third sub-pixel arranged in the row direction or the column direction, a straight-line intercept can be used to obtain Figure 1 .

[0047] In a possible implementation manner, the light-emitting functional layer includes a plurality of blue photon light-emitting layers stacked in sequence and a green photon light-emitting layer located on the side of the plurality of blue photon light-emitting layers away from the substrate.

[0048] In a specific example, taking the light-emitting functional layer 2033 including three blue photon light-emitting layers stacked in sequence and one green photon light-emitting layer located on the side of the three blue photon light-emitting layers away from the substrate, that is, a "3B + 1G" Tandem structure as an example, as Figure 3 shown, the light-emitting functional layer 2033 includes a first hole injection layer HIL (with a thickness of, for example, ), a hole transport layer C-HTL (with a thickness of, for example, ), a first organic transition buffer layer B Prime1 (with a thickness of, for example, ), a first blue light-emitting layer BEML1 (with a thickness of, for example, ), a first hole blocking layer HBL1 (with a thickness of, for example, ), a first N-type charge transport layer NCGL1 (with a thickness of, for example, ), a first P-type charge transport layer PCGL1 (with a thickness of, for example, ), a second organic transition buffer layer B Prime2 (with a thickness of, for example, ), a second blue light-emitting layer BEML2 (with a thickness of, for example, ), a second hole blocking layer HBL2 (with a thickness of, for example, ), a second N-type charge transport layer NCGL2 (with a thickness of, for example, ), the second P-type charge transport layer PCGL2 (with a thickness of, for example, ), the third organic transition buffer layer BPrime3 (with a thickness of, for example, ), the third blue light emitting layer BEML3 (with a thickness of, for example, ), the third hole blocking layer HBL3 (with a thickness of, for example, ), the third N-type charge transport layer NCGL3 (with a thickness of, for example, ), the third P-type charge transport layer PCGL3 (with a thickness of, for example, ), the fourth organic transition buffer layer G Prime (with a thickness of, for example, ), the green light emitting layer GEML (with a thickness of, for example, ), the fourth hole blocking layer HBL4 (with a thickness of, for example, ), the electron transport layer ETL:Liq doped with lithium 8-hydroxyquinoline (with a thickness of, for example, ) and the ytterbium layer Yb as the electron injection layer (with a thickness of, for example, ). For example, on the side of the ytterbium layer Yb away from the substrate, a cathode CTD (i.e., Figure 2 the cathode layer 2034 in Figure 2 ), a light extraction layer CPL, a lithium fluoride layer LiF, and a packaging layer TFE (i.e.,

[0049] the packaging layer 204 in Figure 3 ) are sequentially formed.The light-emitting functional layer 2033 shown is divided into the following film layers: the first organic transition buffer layer BPrime1 and the first blue light-emitting layer BEML1 form the first blue photon light-emitting layer 20331, the second organic transition buffer layer BPrime2 and the second blue light-emitting layer BEML2 form the second blue photon light-emitting layer 20332, the third organic transition buffer layer BPrime3 and the third blue light-emitting layer BEML3 form the third blue photon light-emitting layer 20333, the fourth organic transition buffer layer GPrime and the green light-emitting layer GEML form the green photon light-emitting layer 20334. The first blue photon light-emitting layer 20331, the second blue photon light-emitting layer 20332, the third blue photon light-emitting layer 20333, and the green photon light-emitting layer 20334 stacked in sequence form a "3B + 1G" Tandem structure. The first N-type charge transport layer NCGL1 and the first P-type charge transport layer PCGL1 form the first charge transport layer disposed between the first blue photon light-emitting layer 20331 and the second blue photon light-emitting layer 20332, the second N-type charge transport layer NCGL2 and the second P-type charge transport layer PCGL2 form the second charge transport layer disposed between the second blue photon light-emitting layer 20332 and the third blue photon light-emitting layer 20333, and the third N-type charge transport layer NCGL3 and the third P-type charge transport layer PCGL3 form the third charge transport layer disposed between the third blue photon light-emitting layer 20333 and the green photon light-emitting layer 20334.

[0050] In a possible implementation, the OD-OLED display panel provided in this embodiment further includes a color filter layer on the side of the light conversion layer away from the substrate. The light conversion layer includes a first quantum dot layer in the first sub-pixel, a second quantum dot layer in the second sub-pixel, and a third quantum dot layer in the third sub-pixel. The color filter layer includes a first color filter layer in the first sub-pixel, a second color filter layer in the second sub-pixel, and a third color filter layer in the third sub-pixel.

[0051] Exemplarily, referring to Figure 2 , the film layer structures of the OD-OLED display panel provided in this embodiment are, for example:

[0052] The substrate 201 can be a flexible substrate made of materials such as polyimide (PI), polyethylene naphthalate (PEN), and thermoplastic polyester (PET), or a rigid substrate made of materials such as glass and quartz. The OD-OLED display panel may also include a barrier layer and a buffer layer located between the substrate 201 and the driving circuit layer. For example, the barrier layer and the buffer layer can be formed over the entire surface of the substrate. For example, the barrier layer can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, and the buffer layer can also be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The barrier layer is beneficial for blocking water and oxygen from entering the OLED formed later from the bottom. The buffer layer is beneficial for the quality of subsequent material deposition.

[0053] The driving circuit layer, which can also be referred to as the thin film transistor layer, includes an active layer formed by a patterning process on the buffer layer, a gate insulating layer (GI) formed by deposition or the like on the active layer, a gate of the thin film transistor 2021 formed by a patterning process on the gate insulating layer, an interlayer dielectric (ILD) formed by deposition or the like on the gate, a source-drain metal layer formed on the interlayer dielectric, and a planarization layer (PLN) 2022 covering the source-drain metal layer and exposing the interlayer dielectric. The source-drain metal layer forms the source and drain of the thin film transistor 2021. For example, the source is electrically connected to the active layer through a via in the interlayer dielectric. Among them, the active layer can be made of materials such as polysilicon and metal oxides, the gate insulating layer can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, and the interlayer dielectric can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The gate material includes metals or alloy materials such as aluminum, titanium, and cobalt. The planarization layer is an organic material, for example.

[0054] The anode 2031 in each sub-pixel is, for example, a metal oxide such as ITO or IZO, or a metal or its alloy material such as Ag, Al, or Mo. The anode 2031 is electrically connected to the drain of the thin film transistor 2021 through a via opened in the planarization layer 2022, for example.

[0055] The pixel defining layer 2032 can be formed by a patterning process. The pixel defining layer 2032 has a first opening exposing the anode 2031. Exemplarily, the material of the pixel defining layer 2032 can include organic insulating materials such as negative photoresist, polyimide, and epoxy resin.

[0056] The material of the isolation pillar including the first isolation pillar 1041 is, for example, an organic insulating material, such as negative photoresist.

[0057] The light-emitting functional layer 2033 is a common layer in the display area and is formed over the entire surface of the display area, and is disconnected at the position of the isolation pillar.

[0058] The cathode layer 2034 is a common layer in the display area, formed over the entire display area and covering the light-emitting functional layer 2033. The material of the cathode layer 2034 may include metals such as Mg, Ca, Li, or Al, or their alloys, or metal oxides such as IZO or ZTO, or organic materials with conductive properties such as PEDOT / PSS (poly(3,4-ethylenedioxythiophene) / polystyrene sulfonate).

[0059] The encapsulation layer (TFE) 204 is located on the cathode layer 2034. For example, the encapsulation layer 204 includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer that are sequentially stacked. For example, the first inorganic encapsulation layer and the second inorganic encapsulation layer are formed by deposition or the like. The organic encapsulation layer is formed by inkjet printing. For example, the first inorganic encapsulation layer and the second inorganic encapsulation layer may be formed of inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride, and the organic encapsulation layer may be formed of organic materials such as polyimide (PI) or epoxy resin. Thus, the first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer are formed into a composite encapsulation layer, which can provide multiple protections for the OLED device and has a better encapsulation effect.

[0060] For example Figure 1 and Figure 2 As shown, the light conversion layer includes a first quantum dot layer 2051 in the first sub-pixel 101, a second quantum dot layer 2052 in the second sub-pixel 102, and a third quantum dot layer 2053 in the third sub-pixel 103. The color filter layer includes a first color filter layer 2061 in the first sub-pixel 101, a second color filter layer 2062 in the second sub-pixel 102, and a third color filter layer 2063 in the third sub-pixel 103. Taking the first sub-pixel 101 as a red sub-pixel, the second sub-pixel 102 as a green sub-pixel, and the third sub-pixel 103 as a blue sub-pixel as an example, the first quantum dot layer 2051 is a red light quantum dot layer, the second quantum dot layer 2052 is a green light quantum dot layer, the third quantum dot layer 2053 is a blue light quantum dot layer, the first color filter layer 2061 is a red light color filter layer, the second color filter layer 2062 is a green light color filter layer, and the third color filter layer 2063 is a blue light color filter layer.

[0061] Quantum dots, also known as nanocrystals, are nanoparticles composed of II-VI group or III-V group elements. The emission spectrum of quantum dots can be controlled by changing the size of the quantum dots. By changing the size and chemical composition of the quantum dots, their emission spectrum can cover the entire visible light region. Each quantum dot may independently include II-VI group compounds, III-V group compounds, IV-VI group compounds, group IV elements or compounds, and I-III-VI group compounds, II-III-VI group compounds, I-II-IV-VI group compounds, or combinations thereof.

[0062] The red light quantum dot layer can be excited by the excitation light with short wavelength and high energy, such as blue light and violet light, emitted by the corresponding light-emitting functional layer 2033 (i.e., the part of the light-emitting functional layer 2033 whose orthographic projection on the substrate coincides with the red light quantum dot layer), and emit red light. The green light quantum dot layer can be excited by the excitation light with short wavelength and high energy, such as blue light and violet light, emitted by the corresponding light-emitting functional layer 2033, and emit green light. The blue light quantum dot layer can be excited by the excitation light with short wavelength and high energy, such as blue light and violet light, emitted by the corresponding light-emitting functional layer 2033, and emit blue light. In order to enable the quantum dots in the red light quantum dot layer, green light quantum dot layer and blue light quantum dot layer to better absorb the excitation light, scattering particles (which can be called SP, such as titanium dioxide TiO2 particles) can be doped into the materials of the red light quantum dot layer, green light quantum dot layer and blue light quantum dot layer. The size of the scattering particles is usually designed to be larger than the size of the quantum dots. For example, when the backlight emitted by the light-emitting functional layer 2033 as the backlight includes blue light with a wavelength between 445nm and 460nm, the blue light quantum dot layer may not include quantum dots but only include, for example, white ink doped with scattering particles prepared by an inkjet printing process. For example, when adopting the "3B + 1G" Tandem structure of the foregoing example, the blue light quantum dot layer may not include quantum dots but only include, for example, white ink doped with scattering particles prepared by an inkjet printing process. And due to the color film layer provided for preventing ambient light reflection and avoiding color crosstalk, the green light emitted by the green light-emitting layer in the "3B + 1G" Tandem structure cannot pass through the blue light filter layer and will not affect the color of the blue sub-pixels. For example Figure 2 As shown, the light conversion layer further includes a barrier structure 2054 between adjacent quantum dot layers. In addition, a black matrix layer (BM) can also be provided in the color film layer between adjacent filter layers to further ensure its effect of avoiding color crosstalk and the like.

[0063] For example Figure 2 As shown, the QD-OLED display panel further includes a cover plate 207 (such as a glass cover plate CG, etc.) located on the color film layer.

[0064] In a possible implementation manner, the first isolation column, the second isolation column and the third isolation column are respectively continuous structures. For example Figure 1 As shown, the shapes of the first isolation column 1041, the second isolation column 1042 and the third isolation column 1043 are respectively in a continuous L shape. Thus, the effectiveness of the isolation column in disconnecting the charge transport layer can be further ensured.

[0065] In a possible implementation, the widths of the first isolation pillar, the second isolation pillar, and the third isolation pillar are respectively a first width. That is, the widths of the first isolation pillar, the second isolation pillar, and the third isolation pillar are the same. Thus, the disconnection effect of each isolation pillar on the charge transport layer can be ensured, and the preparation process of the isolation pillar is relatively simple. For example Figure 1 , Figure 2 and Figure 4 as shown, the widths of the first isolation pillar 1041, the second isolation pillar 1042, and the third isolation pillar 1043 are respectively b.

[0066] It should be noted that Figure 1 as shown, the cathode layer 2034 is not disconnected at the position of the isolation pillar, or in other words, the isolation pillar does not cause the cathode layer 2034 to be disconnected. Figure 4 As shown, the cathode layer 2034 is disconnected at the position of the first isolation pillar 1041, or in other words, the first isolation pillar 1041 causes the cathode layer 2034 to be disconnected. These two cases respectively show two actual situations, that is, the isolation pillar may cause the cathode layer 2034 to be disconnected.

[0067] In a possible implementation, the first width is 15%-25% of the minimum width of the pixel defining layer between adjacent sub-pixels. Thus, through the width design of the isolation pillar, it is beneficial for the isolation pillar to form a relatively sharp morphology, which is beneficial to ensuring the disconnection effect of each isolation pillar on the charge transport layer.

[0068] For example Figure 1 , Figure 2 and Figure 4 as shown, the widths of the first isolation pillar 1041, the second isolation pillar 1042, and the third isolation pillar 1043 are respectively b, the minimum width of the pixel defining layer 2032 between adjacent sub-pixels is a, the minimum width a of the pixel defining layer 2032 between adjacent sub-pixels is, for example, 19 μm - 22 μm, the width b of the first isolation pillar 1041, the second isolation pillar 1042, and the third isolation pillar 1043 is, for example, 4 μm, and the width b of the first isolation pillar 1041, the second isolation pillar 1042, and the third isolation pillar 1043 is approximately 20% of the minimum width a of the pixel defining layer 2032 between adjacent sub-pixels.

[0069] In a possible implementation, the isolation pillar is located on the side of the pixel defining layer away from the substrate, and the isolation pillar disconnects the light-emitting functional layer.

[0070] In a specific example, for example Figure 2 and Figure 4As shown, the isolation pillars including the first isolation pillar 1041, the second isolation pillar 1042, and the third isolation pillar 1043 are located on the side of the pixel definition layer 2032 away from the substrate 201, and the isolation pillars including the first isolation pillar 1041, the second isolation pillar 1042, and the third isolation pillar 1043 disconnect the light-emitting functional layer 2033.

[0071] In a possible implementation, the ratio of the thickness of the isolation pillar to the thickness of the light-emitting functional layer is greater than 2. Thus, through the design of the thickness of the isolation pillar, especially the combination of the thickness design of the isolation pillar and the width design of the isolation pillar provided by the foregoing implementation, it is beneficial for the isolation pillar to form a relatively sharp morphology, which is beneficial to ensuring the disconnection effect of each isolation pillar on the charge transport layer.

[0072] In a specific example, for example Figure 2 and Figure 4 As shown, the thicknesses of the first isolation pillar 1041, the second isolation pillar 1042, and the third isolation pillar 1043 are respectively c, and the thickness c of the first isolation pillar 1041, the second isolation pillar 1042, and the third isolation pillar 1043 is greater than twice the thickness of the light-emitting functional layer 2033. For example, the thickness c of the first isolation pillar 1041, the second isolation pillar 1042, and the third isolation pillar 1043 is about 1.5 μm.

[0073] Figure 1 and Figure 2 The partial preparation process of the OD-OLED display panel shown, for example, is as follows:

[0074] First, a backplane including a substrate 201 and a driving circuit layer is prepared;

[0075] Then, the anode 2031 is prepared by using a patterning process;

[0076] Then, the pixel definition layer 2032 is prepared by using a patterning process;

[0077] Then, the isolation pillars including the first isolation pillar 1041, the second isolation pillar 1042, and the third isolation pillar 1043 are prepared by using a patterning process;

[0078] Then, a vacuum evaporation process is carried out by using an Open Mask for the display area to prepare the light-emitting functional layer 2033;

[0079] Then, only the cathode layer 2034 is obtained;

[0080] Then, the encapsulation layer 204 is prepared.

[0081] See Figure 5 As shown:

[0082] Taking an OD-OLED display panel with a "3B+1G" Tandem structure without isolation pillars as a reference example, under the test condition of a display brightness of 250 nits, it is actually measured that there is relatively serious 16 gray-scale color crosstalk in the reference. Specifically: there is 3.3% green light crosstalk in the red monochromatic picture, 8.4% green light crosstalk in the blue monochromatic picture, and 4.2% red light crosstalk in the green monochromatic picture. And due to the relatively serious 16 gray-scale color crosstalk, the monochromatic CIE chromaticity drift is also relatively serious. Specifically: the red color coordinate Rx is 0.690→0.630 (the change value from 255 gray scale to 16 gray scale), the green color coordinate Gx is 0.239→0.250 (the change value from 255 gray scale to 16 gray scale), and the blue color coordinate By is 0.057→0.069 (the change value from 255 gray scale to 16 gray scale). The NTSC color gamut changes from 109% to 85%.

[0083] And the OD-OLED display panel provided in this embodiment, such as Figures 1 - 4 shown, with a "3B+1G" Tandem structure and isolation pillars, by making the charge transport layer form a disconnection, effectively avoiding the occurrence of horizontal current between adjacent sub-pixels, can effectively avoid crosstalk between sub-pixels. Under the same test conditions, the monochromatic crosstalk can be controlled at a level less than 1.0%, the monochromatic CIE chromaticity drift amount can be controlled at a level less than 0.001, and the NTSC color gamut can basically be maintained at 109%.

[0084] In a possible implementation manner, the first isolation pillar has at least one first gap that causes the first isolation pillar to be formed into at least two discontinuous first sub-isolation pillars, the second isolation pillar has at least one second gap that causes the second isolation pillar to be formed into at least two discontinuous second sub-isolation pillars, and the third isolation pillar has at least one third gap that causes the third isolation pillar to be formed into at least two discontinuous third sub-isolation pillars.

[0085] In a specific example, different from Figure 1 shown, where the shapes of the first isolation pillar 1041, the second isolation pillar 1042, and the third isolation pillar 1043 are respectively continuous L-shaped, for example Figure 6 shown, the first isolation pillar 1041`, the second isolation pillar 1042`, and the third isolation pillar 1043` respectively have a gap. Taking the first isolation pillar 1041` as an example, it has a gap at the L-shaped corner far from the adjacent sub-pixel, causing the first isolation pillar 1041` to be formed into two discontinuous (i.e., non-continuous) first sub-isolation pillars. The advantages of designing the isolation pillar as a non-continuous morphology include, but are not limited to, ensuring that when the isolation pillar disconnects the cathode layer 2034, the cathode layer 2034 will not form a continuous disconnection over too long a distance, which is beneficial to ensuring the impedance requirements for each position of the cathode layer 2034.

[0086] For another example Figure 7 As shown, the isolation pillars only include a first isolation pillar 1041` close to the first sub-pixel 101 and a second isolation pillar 1042` close to the second sub-pixel 102, and the first isolation pillar 1041` and the second isolation pillar 1042` each have a gap. Figure 7 The structure shown is that an isolation pillar structure is provided between adjacent first sub-pixels 101 and second sub-pixels 102, an isolation pillar structure is provided between adjacent first sub-pixels 101 and third sub-pixels 103, and an isolation pillar structure is provided between adjacent second sub-pixels 102 and third sub-pixels 103, but no isolation pillar structure is provided between two adjacent third sub-pixels 103.

[0087] For example, the designs such as the width and thickness of the first isolation pillar 1041`, the second isolation pillar 1042`, and the third isolation pillar 1043 can be the same as those of the isolation pillars in Figure 1 shown.

[0088] In a possible implementation, a first isolation pillar or a second isolation pillar is provided between the adjacent first sub-pixel and the second sub-pixel, a first isolation pillar or a third isolation pillar is provided between the adjacent first sub-pixel and the third sub-pixel, and a second isolation pillar or a third isolation pillar is provided between the adjacent second sub-pixel and the third sub-pixel. Thus, an isolation pillar is provided between adjacent sub-pixels, causing a break in the charge transport layer between adjacent sub-pixels.

[0089] In a specific example, for example Figure 1 as shown, a first isolation pillar 1041 is provided between adjacent first sub-pixels 101 and second sub-pixels 102, a first isolation pillar 1041 or a third isolation pillar 1043 is provided between adjacent first sub-pixels 101 and third sub-pixels 103, and a second isolation pillar 1042 or a third isolation pillar 1043 is provided between adjacent second sub-pixels 102 and third sub-pixels 103.

[0090] In a possible implementation, a first isolation pillar and a second isolation pillar are provided between the adjacent first sub-pixel and the second sub-pixel, a first isolation pillar and a third isolation pillar are provided between the adjacent first sub-pixel and the third sub-pixel, and a second isolation pillar and a third isolation pillar are provided between the adjacent second sub-pixel and the third sub-pixel. Thus, two isolation pillars are provided between adjacent sub-pixels, causing two breaks in the charge transport layer between adjacent sub-pixels.

[0091] In a specific example, for example Figure 8 and Figure 9As shown, a first isolation pillar 1041`` and a second isolation pillar 1042`` are provided between adjacent first sub-pixels 101 and second sub-pixels 102, a first isolation pillar 1041`` and a third isolation pillar 1043`` are provided between adjacent first sub-pixels 101 and third sub-pixels 103, and a second isolation pillar 1042`` and a third isolation pillar 1043`` are provided between adjacent second sub-pixels 102 and third sub-pixels 103. The designs of the width, thickness, etc. of the first isolation pillar 1041``, the second isolation pillar 1042``, and the third isolation pillar 1043`` can be the same as those of the isolation pillars in Figure 1 shown. The distance between two isolation pillars located adjacent to each other is designed to be less than 10 μm, for example. For example, the distance between the first isolation pillar 1041`` and the second isolation pillar 1042`` provided between adjacent first sub-pixels 101 and second sub-pixels 102 is less than 10 μm.

[0092] It should be noted that since the isolation pillars may cause the cathode layer 2034 to be disconnected, for example Figure 8 when the isolation pillars shown surround the four sides of the rectangular sub-pixels, the first isolation pillar 1041``, the second isolation pillar 1042``, and the third isolation pillar 1043`` can be respectively designed as a discontinuous structure with at least one gap to ensure that the cathode layer 2034 in the sub-pixels does not form an island.

[0093] In a possible implementation manner, the isolation pillars are located on the side of the plurality of blue photon emitting layers away from the substrate, and the isolation pillars disconnect the green photon emitting layer and the first charge transport layer, and the first charge transport layer is the charge transport layer between the green photon emitting layer and the blue photon emitting layer.

[0094] For example Figure 10 、 Figure 1 and Figure 3 shown, the light-emitting functional layer 2033 is a "3B + 1G" Tandem structure, including a first blue photon emitting layer 20331, a second blue photon emitting layer 20332, a third blue photon emitting layer 20333, and a green photon emitting layer 20334 which are sequentially stacked. The isolation pillars including a first isolation pillar 1051, a second isolation pillar 1052, and a third isolation pillar 1053 are located on the side of the third blue photon emitting layer 20333 away from the substrate 201, and specifically can be located on the side of the third hole blocking layer HBL3 away from the substrate 201. The isolation pillars including a first isolation pillar 1051, a second isolation pillar 1052, and a third isolation pillar 1053 disconnect the third charge transport layer (constituted by a third N-type charge transport layer NCGL3 and a third P-type charge transport layer PCGL3) provided between the third blue photon emitting layer 20333 and the green photon emitting layer 20334 in the light-emitting functional layer 2033.

[0095] In a specific example, provided by this implementation mode, such as Figure 10 and Figure 3 the OD-OLED display panel with a "3B + 1G" Tandem structure as shown will include isolation pillars including a first isolation pillar 1051, a second isolation pillar 1052, and a third isolation pillar 1053 disposed on the third blue photon emitting layer 20333 so that the third charge transport layer is formed to be disconnected. Refer to Figure 11 , due to the difference in the material systems of the blue photon emitting layer and the green photon emitting layer, the blue light OLED is a fluorescence system and the green light OLED is a phosphorescence system. Therefore, in a single OLED device structure, the turn-on voltage V b of the blue light OLED is higher than the turn-on voltage V g of the green light OLED. Combining Figure 10 and Figure 3 the "3B + 1G" Tandem structure as shown, such as Figure 11 the equivalent voltage on the right side shown, the device voltage of the Tandem structure ≈ 3 * V b + * V g . Under the test condition of a display brightness of 1000 nit, assuming the aperture ratio of the display area is 29.7%, the device voltage of the "3B + 1G" Tandem structure is about 30 v (in a single OLED device structure, the turn-on voltage or working voltage V b of the blue light OLED is about 7.6 v, and the turn-on voltage or working voltage V b of the green light OLED is about 6.8 v. Combining with the relatively serious 16 gray-scale color crosstalk obtained by actual measurement: there is 3.3% green light crosstalk in the red monochromatic picture, 8.4% green light crosstalk in the blue monochromatic picture, and 4.2% red light crosstalk in the green monochromatic picture. It can be seen that for the red monochromatic picture and the blue monochromatic picture, the degree of green light crosstalk is the largest. For detailed parameters, refer to Table 1. Thus, the inventor found that among adjacent sub-pixels, the topmost green photon emitting layer 20334 of the "3B + 1G" Tandem structure is most affected by the lateral current. Such as Figure 11As shown in the figure, when a voltage is applied to the nth column of sub-pixels on the right to turn them on, a horizontal current appears between adjacent sub-pixels, resulting in crosstalk. The uppermost green photon-emitting layer 20334 in the light-emitting functional layer of the (n + 1)th column of sub-pixels on the left is most easily excited and turned on, thereby exciting the quantum dot layer above to emit light, forming crosstalk between sub-pixels. That is, the horizontal current that appears between adjacent sub-pixels is most affected by the third charge transport layer between the third blue photon-emitting layer 20333 and the green photon-emitting layer 20334. Based on this, in this implementation, an isolation column including a first isolation column 1051, a second isolation column 1052, and a third isolation column 1053 is disposed on the third blue photon-emitting layer 20333 to disconnect the third charge transport layer, preventing the green photon-emitting layer 20334 from being turned on by the influence of the horizontal current, and thus avoiding crosstalk between sub-pixels.

[0096] Table 1

[0097]

[0098] And Figure 2 different from the partial preparation process of the OD-OLED display panel shown in the figure, when preparing Figure 10 the OD-OLED display panel shown in the figure, after preparing the third hole blocking layer HBL3 during the preparation of the light-emitting functional layer 2033, an isolation column including a first isolation column 1051, a second isolation column 1052, and a third isolation column 1053 is prepared by a patterning process, and then the third charge transport layer, the green photon-emitting layer 20334 and other film layers are continuously prepared.

[0099] The design of the isolation column provided in this implementation on the side of the plurality of blue photon-emitting layers away from the substrate, in addition to adopting Figure 1 the isolation column distribution morphology shown in the figure, can also adopt, for example Figure 6 , Figure 7 and Figure 8 the isolation column distribution morphology shown in the figure.

[0100] In a possible implementation, when the isolation posts are located on the side of the plurality of blue photon emitting layers away from the substrate, the ratio of the thickness of the isolation posts to the first thickness is greater than 2, and the first thickness is the sum of the thicknesses of the green photon emitting layer and the charge transport layer. Thus, through the design of the thickness of the isolation posts, especially the combination of the thickness design of the isolation posts with the width design of the isolation posts provided by the foregoing implementation (the width design may also adopt that the widths of the first isolation post, the second isolation post, and the third isolation post are respectively the first width, and the first width is 15%-25% of the minimum width of the pixel defining layer between adjacent sub-pixels), it is beneficial for the isolation posts to form a relatively sharp morphology, and it is beneficial to ensure the disconnection effect of each isolation post on the charge transport layer between the green photon emitting layer and the blue photon emitting layer.

[0101] Another embodiment of the present disclosure provides a QD-OLED display device, including the QD-OLED display panel provided in the foregoing embodiment. Among them, the QD-OLED display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., and this embodiment does not limit this.

[0102] Obviously, the above embodiments of the present disclosure are merely examples for clearly explaining the present disclosure, rather than limiting the implementation manners of the present disclosure. For those of ordinary skill in the art, other different forms of changes or variations can be made on the basis of the above description. It is impossible to enumerate all the implementation manners here. Any obvious changes or variations derived from the technical solutions of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that, It includes a substrate, and a driving circuit layer, a light-emitting device layer, a packaging layer, and a light conversion layer that are sequentially stacked on the substrate. The light-emitting device layer includes an anode layer, a pixel defining layer, a light-emitting functional layer, and a cathode layer that are sequentially stacked. The display panel includes a plurality of sub-pixels. The anode layer includes an anode located in the sub-pixels. The light-emitting functional layer includes a plurality of sub-light-emitting layers that are sequentially stacked, and a charge transport layer is disposed between adjacent sub-light-emitting layers. Wherein, the display panel further includes spacer columns disposed between at least a pair of adjacent sub-pixels, and the spacer columns disconnect at least a part of the charge transport layer in the light-emitting functional layer.

2. The display panel according to claim 1, wherein The plurality of sub-pixels include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. The spacer columns include at least one of a first spacer column close to the first sub-pixel, a second spacer column close to the second sub-pixel, and a third spacer column close to the third sub-pixel.

3. The display panel according to claim 2, characterized in that, The first spacer column has at least one first gap that causes the first spacer column to be formed into at least two discontinuous first sub-spacer columns. The second spacer column has at least one second gap that causes the second spacer column to be formed into at least two discontinuous second sub-spacer columns. The third spacer column has at least one third gap that causes the third spacer column to be formed into at least two discontinuous third sub-spacer columns.

4. The display panel according to claim 2, wherein The spacer columns include a first spacer column close to the first sub-pixel, a second spacer column close to the second sub-pixel, and a third spacer column close to the third sub-pixel. A first spacer column or a second spacer column is disposed between the adjacent first sub-pixel and the second sub-pixel. A first spacer column or a third spacer column is disposed between the adjacent first sub-pixel and the third sub-pixel. A second spacer column or a third spacer column is disposed between the adjacent second sub-pixel and the third sub-pixel.

5. The display panel according to claim 3, wherein The spacer columns include a first spacer column close to the first sub-pixel, a second spacer column close to the second sub-pixel, and a third spacer column close to the third sub-pixel. A first spacer column and a second spacer column are disposed between the adjacent first sub-pixel and the second sub-pixel. A first spacer column and a third spacer column are disposed between the adjacent first sub-pixel and the third sub-pixel. A second spacer column and a third spacer column are disposed between the adjacent second sub-pixel and the third sub-pixel.

6. The display panel according to claim 2, wherein The widths of the first spacer column, the second spacer column, and the third spacer column are respectively a first width.

7. The display panel according to claim 6, wherein The first width is 15%-25% of the minimum width of the pixel defining layer between adjacent sub-pixels.

8. The display panel according to claim 1, wherein The spacer columns are located on the side of the pixel defining layer away from the substrate, and the spacer columns disconnect the light-emitting functional layer.

9. The display panel according to claim 8, wherein The ratio of the thickness of the spacer columns to the thickness of the light-emitting functional layer is greater than 2.

10. The display panel according to claim 1, characterized in that, The light-emitting functional layer includes a plurality of blue photon light-emitting layers stacked in sequence and a green photon light-emitting layer located on the side of the plurality of blue photon light-emitting layers away from the substrate. The isolation pillar is located on the side of the plurality of blue photon light-emitting layers away from the substrate. The isolation pillar disconnects the green photon light-emitting layer and the first charge transport layer, and the first charge transport layer is the charge transport layer between the green photon light-emitting layer and the blue photon light-emitting layer.

11. The display panel according to claim 10, wherein The ratio of the thickness of the isolation pillar to the first thickness is greater than 2, and the first thickness is the sum of the thicknesses of the green photon light-emitting layer and the charge transport layer.

12. The display panel according to claim 2, wherein, The display panel further includes a color filter layer located on the side of the light conversion layer away from the substrate. The light conversion layer includes a first quantum dot layer in a first sub-pixel, a second quantum dot layer in a second sub-pixel, and a third quantum dot layer in a third sub-pixel. The color filter layer includes a first color filter layer in the first sub-pixel, a second color filter layer in the second sub-pixel, and a third color filter layer in the third sub-pixel.

13. A display device, characterized in that, A display panel including the display panel according to any one of claims 1-12.

Images