Display device and electronic device including the same

Abstract

The invention provides a display device and an electronic device including the same. The display device includes a data driving section, a demultiplexer circuit, a wiring hybrid structure, and a display panel. The data driving unit includes first to fourth output amplifiers. The demultiplexer circuit divides the first to fourth output amplifiers into a first output line, a second output line, a third output line, a fourth output line, a fifth output line, a sixth output line, a seventh output line, and an eighth output line through a demultiplexer switch. And the wiring hybrid structure is connected with the demultiplexer circuit. The display panel includes a data line connected to the wiring hybrid structure. And when the sequence of the first data at the input end of the wiring hybrid structure is 1, 2, 3, 4, 5, 6, 7 and 8, the sequence of the second data at the output end of the wiring hybrid structure is 4, 1, 2, 3, 7, 6, 5 and 8.

Description

Technical Field

[0001] The present invention relates to a display device and an electronic device including the same, and more particularly, to a display device including a wiring hybrid structure to improve demultiplexing coupling and prevent data mapping errors, and an electronic device including the same. Background Art

[0002] Generally, a display device includes a display panel and a display panel driving unit. The display panel displays an image based on an input image, and includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. The display panel driving unit includes: a gate driving unit that provides a gate signal to the plurality of gate lines; a data driving unit that provides a data voltage to the data lines; and a driving control unit that controls the gate driving unit and the data driving unit.

[0003] The display panel driving unit may include a demultiplexer circuit that separates R-G data of the data driving unit into R data and G data, and separates B-G data of the data driving unit into B data and G data. In a display device including the demultiplexer circuit, the display quality may be degraded due to coupling between a data line that outputs R data or B data and a data line that outputs G data.

[0004] Moreover, in order to reduce the dead space of the display device, the data driving unit may be formed into a border reduction structure (BRS) capable of cross-outputting a data voltage applied to a data line at the center of the display panel and a data voltage applied to a data line at the edge of the display panel. In this case, a horizontal wiring for transmitting the data voltage to the edge data line may be additionally provided, and the display quality may be degraded due to the coupling between such horizontal wiring and the data line.

[0005] Furthermore, in order to reduce the dead space of the display device, the position of the demultiplexer circuit is moved toward the integrated circuit side of the data driving unit. In this case, the number of floating lines on the display panel further increases, resulting in more coupling and further degrading the display quality.

[0006] Moreover, in the case where the output of the data driving unit of the prior art is directly connected to the data line of the display panel due to the movement of the demultiplexer circuit, data mapping errors may occur in which R data or B data is applied to a G pixel, or G data is applied to an R pixel or a B pixel. Summary of the Invention

[0007] Therefore, the technical problem of the present invention focuses on this, and the object of the present invention is to provide a display device that improves demultiplexing coupling and prevents data mapping errors by including a wiring hybrid structure.

[0008] Another object of the present invention is to provide an electronic device including the display device.

[0009] A display device according to an embodiment for achieving the above object of the present invention includes a data driving unit, a demultiplexer circuit, a wiring hybrid structure, and a display panel. The data driving unit includes a first output amplifier to a fourth output amplifier. The demultiplexer circuit divides the first output amplifier to the fourth output amplifier into a first output line, a second output line, a third output line, a fourth output line, a fifth output line, a sixth output line, a seventh output line, and an eighth output line through demultiplexer switches. The wiring hybrid structure is connected to the demultiplexer circuit. The display panel includes data lines connected to the wiring hybrid structure. When the order of the first data at the input end of the wiring hybrid structure is 1, 2, 3, 4, 5, 6, 7, 8, the order of the second data at the output end of the wiring hybrid structure is 4, 1, 2, 3, 7, 6, 5, 8.

[0010] In an embodiment of the present invention, the display device may further include a bending area disposed between the display panel and the data driving unit. The demultiplexer circuit may be disposed between the integrated circuit area of the data driving unit and the bending area.

[0011] In an embodiment of the present invention, the bending area may include a bending line that bends toward the back surface of the display panel. The display panel may be disposed on a first side of the bending line, and the demultiplexer circuit and the integrated circuit area may be disposed on a second side of the bending line.

[0012] In an embodiment of the present invention, a part of the output data of the data driving unit may be normal data directly applied to the data lines of the display panel. A part of the output data of the data driving unit may be boundary reduction data applied to the data lines of the display panel through boundary reduction horizontal lines.

[0013] In an embodiment of the present invention, when the order of the first data is 1, 2, 3, 4, 5, 6, 7, 8, the first data having the order of 1, 2, 5, 6 may be the normal data, and the first data having the order of 3, 4, 7, 8 may be the boundary reduction data.

[0014] In an embodiment of the present invention, the first output line, the fourth output line, the fifth output line, and the eighth output line of the demultiplexer circuit can be activated by a first switching signal. The second output line, the third output line, the sixth output line, and the seventh output line of the demultiplexer circuit can be activated by a second switching signal.

[0015] In an embodiment of the present invention, the input end of the wiring hybrid structure may include pads numbered 1_1 to 8_1 arranged in sequence, and the output end of the wiring hybrid structure includes pads numbered 1_2 to 8_2 arranged in sequence. The 1_1 pad may be connected to the 2_2 pad. The 2_1 pad may be connected to the 3_2 pad. The 3_1 pad may be connected to the 4_2 pad. The 4_1 pad may be connected to the 1_2 pad. The 5_1 pad may be connected to the 7_2 pad. The 6_1 pad may be connected to the 6_2 pad. The 7_1 pad may be connected to the 5_2 pad. The 8_1 pad may be connected to the 8_2 pad.

[0016] In an embodiment of the present invention, the data driving unit may further include an (N + 1)th output amplifier, an (N + 2)th output amplifier, an (N + 3)th output amplifier, an (N + 4)th output amplifier, an (N + 5)th output amplifier, an (N + 6)th output amplifier, an (N + 7)th output amplifier, and an (N + 8)th output amplifier. The (N + 1)th output amplifier may output data for the (N + 1)_1 data line and the (N + 1)_2 data line. The (N + 2)th output amplifier may output data for the dummy data line, where N is a natural number greater than or equal to 4.

[0017] In an embodiment of the present invention, the (N + 3)th output amplifier, the (N + 4)th output amplifier, and the (N + 5)th output amplifier may not be activated.

[0018] In an embodiment of the present invention, the (N + 6)th output amplifier may output data for the (N + 2)_1 data line and the (N + 2)_2 data line. The (N + 7)th output amplifier may output data for the (N + 3)_1 data line and the (N + 3)_2 data line. The (N + 8)th output amplifier may output data for the (N + 4)_1 data line and the (N + 4)_2 data line.

[0019] In an embodiment of the present invention, the data driving unit may further include an (N + 1)th output amplifier, an (N + 2)th output amplifier, an (N + 3)th output amplifier, an (N + 4)th output amplifier, an (N + 5)th output amplifier, an (N + 6)th output amplifier, an (N + 7)th output amplifier, and an (N + 8)th output amplifier. The (N + 5)th output amplifier may output data for the (N + 1)_1 data line and the (N + 1)_2 data line. The (N + 2)th output amplifier may output data for the dummy data line.

[0020] In an embodiment of the present invention, the (N + 1)th output amplifier, the (N + 3)th output amplifier, and the (N + 4)th output amplifier may not be activated.

[0021] In an embodiment of the present invention, the (N + 6)th output amplifier may output data for the (N + 2)_1 data line and the (N + 2)_2 data line. The (N + 7)th output amplifier may output data for the (N + 3)_1 data line and the (N + 3)_2 data line. The (N + 8)th output amplifier may output data for the (N + 4)_1 data line and the (N + 4)_2 data line.

[0022] In an embodiment of the present invention, the display panel may include a first power supply connection line, a 1_1 data line, a 1_2 data line, a second power supply connection line, a third power supply connection line, a 2_2 data line, a 2_1 data line, and a fourth power supply connection line arranged in sequence. First color data may be applied to the 1_1 data line. Second color data may be applied to the 1_2 data line and the 2_2 data line. Third color data may be applied to the 2_1 data line.

[0023] In an embodiment of the present invention, the display panel may include a first color first light-emitting region, a second color first light-emitting region, a third color first light-emitting region, a second color second light-emitting region, a third color second light-emitting region, a second color third light-emitting region, a first color second light-emitting region, and a second color fourth light-emitting region. The 1_1 data line may be connected to the first color first light-emitting region and the first color second light-emitting region. The 1_2 data line may be connected to the second color first light-emitting region and the second color third light-emitting region. The 2_2 data line may be connected to the second color second light-emitting region and the second color fourth light-emitting region. The 2_1 data line may be connected to the third color first light-emitting region.

[0024] In an embodiment of the present invention, the third color second light-emitting region may be connected to the dummy data line.

[0025] In an embodiment of the present invention, the first light-emitting region of the second color and the second light-emitting region of the second color may be arranged in the 1-1 row. The first light-emitting region of the first color and the first light-emitting region of the third color may be arranged in the 1-2 row adjacent to the 1-1 row. The third light-emitting region of the second color and the fourth light-emitting region of the second color may be arranged in the 2-1 row adjacent to the 1-2 row. The second light-emitting region of the third color and the second light-emitting region of the first color may be arranged in the 2-2 row adjacent to the 2-1 row.

[0026] In an embodiment of the present invention, when the order of the third data at the input end of the demultiplexer circuit is 1, 2, 3, 4, 5, 6, 7, 8, the order of the fourth data at the output end of the demultiplexer circuit may be 1, 2, 4, 3, 5, 6, 8, 7.

[0027] An electronic device according to an embodiment for achieving the above object of the present invention includes a data driving unit, a demultiplexer circuit, a wiring hybrid structure, a display panel, a driving control unit, and a processor. The data driving unit includes a first output amplifier to a fourth output amplifier. The demultiplexer circuit divides the first output amplifier to the fourth output amplifier into a first output line, a second output line, a third output line, a fourth output line, a fifth output line, a sixth output line, a seventh output line, and an eighth output line through a demultiplexer switch. The wiring hybrid structure is connected to the demultiplexer circuit. The display panel includes data lines connected to the wiring hybrid structure. The driving control unit controls the data driving unit. The processor outputs input image data and input control signals to the driving control unit. When the order of the first data at the input end of the wiring hybrid structure is 1, 2, 3, 4, 5, 6, 7, 8, the order of the second data at the output end of the wiring hybrid structure is 4, 1, 2, 3, 7, 6, 5, 8.

[0028] (Advantages of the Invention)

[0029] According to the display device and the electronic device including the same as described above, since it includes a demultiplexer switch structure supporting 4 bundles and a wiring hybrid structure for preventing data mapping errors, demultiplexing coupling can be improved and data mapping errors can be prevented.

[0030] Moreover, without changing the integrated circuit of the data driving unit and the active area of the display panel, a demultiplexer switch structure supporting 4 bundles can be supported.

[0031] Furthermore, since the data driving unit is formed into a boundary reduction structure capable of cross-outputting the data voltages applied to the data lines in the central part of the display panel and the data voltages applied to the data lines at the edge of the display panel, the invalid space of the display device can be reduced.

[0032] Moreover, since the demultiplexer circuit is disposed adjacent to the integrated circuit region on the second side of the bent line, the useless space of the display device can be further reduced.

[0033] Moreover, since the dummy data line includes a structure of a data driver unit for applying dummy data, appropriate data can be applied to the dummy data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0035] Figure 2 is a diagram showing Figure 1 the display panel and a conceptual diagram of the data driver unit.

[0036] Figure 3 is a diagram showing an example of coupling occurring in the demultiplexer switch structure.

[0037] Figure 4 is a diagram showing Figure 1 the output amplifier and a table of data mapping of the data driver unit.

[0038] Figure 5 is a diagram showing Figure 1 the data lines, border reduction horizontal lines, border reduction vertical lines, and power supply access lines of the display panel.

[0039] Figure 6 is a diagram showing Figure 1 the light emitting region of the display panel.

[0040] Figure 7A is a diagram showing Figure 1 a conceptual diagram of the output amplifier, demultiplexer circuit, wiring hybrid structure, and display panel of the data driver unit.

[0041] Figure 7B is a conceptual diagram showing an enlarged view of Figure 7A the wiring hybrid structure.

[0042] Figure 8 is a diagram showing the output amplifier, demultiplexer circuit, and display panel of the data driver unit for outputting dummy data to the dummy data line of the display panel for Figure 1 a conceptual diagram.

[0043] Figure 9 is a conceptual diagram showing the output amplifier, demultiplexer circuit, and display panel of the data driver unit for outputting dummy data to the dummy data line of the display panel of a display device according to an embodiment of the present invention.

[0044] Figure 10 is a block diagram of an electronic device showing an embodiment of the present invention.

[0045] Figure 11 is a diagram showing Figure 10 an example in which the electronic device is implemented by a smartphone.

[0046] Figure 12 is a block diagram of an electronic device showing an embodiment of the present invention.

[0047] Description of Reference Numerals

[0048] 100: Display panel; 200: Drive control unit; 300: Gate drive unit; 400: Gamma reference voltage generation unit; 500: Data drive unit Detailed Description of the Invention

[0049] Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

[0050] Figure 1 is a block diagram of a display device showing an embodiment of the present invention.

[0051] Referring to Figure 1 , the display device includes a display panel 100 and a display panel drive unit. The display panel drive unit includes: a drive control unit 200, a gate drive unit 300, a gamma reference voltage generation unit 400, and a data drive unit 500.

[0052] For example, the drive control unit 200 and the data drive unit 500 may be integrally formed. For example, the drive control unit 200, the gamma reference voltage generation unit 400, and the data drive unit 500 may be integrally formed. A drive module obtained by integrally forming at least the drive control unit 200 and the data drive unit 500 may be referred to as a timing controller embedded data driver (TED).

[0053] The display panel 100 includes: a display unit AA for displaying an image; and a peripheral unit PA disposed adjacent to the display unit AA.

[0054] The display panel 100 includes: a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels P electrically connected to the gate lines GL and the data lines DL, respectively. The gate lines GL may extend in a first direction D1, and the data lines DL extend in a second direction D2 intersecting the first direction D1.

[0055] The driving control unit 200 receives input image data IMG and an input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0056] The driving control unit 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0057] The driving control unit 200 generates the first control signal CONT1 for controlling the operation of the gate driving unit 300 based on the input control signal CONT and outputs it to the gate driving unit 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0058] The driving control unit 200 generates the second control signal CONT2 for controlling the operation of the data driving unit 500 based on the input control signal CONT and outputs it to the data driving unit 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0059] The driving control unit 200 generates a data signal DATA based on the input image data IMG. The driving control unit 200 outputs the data signal DATA to the data driving unit 500.

[0060] The driving control unit 200 generates the third control signal CONT3 for controlling the operation of the gamma reference voltage generation unit 400 based on the input control signal CONT and outputs it to the gamma reference voltage generation unit 400.

[0061] The gate driving unit 300 generates a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving control unit 200. The gate driving unit 300 outputs the gate signal to the gate line GL. For example, the gate driving unit 300 may sequentially output the gate signal to the gate line GL. For example, the gate driving unit 300 may be mounted on the peripheral portion PA of the display panel 100. For example, the gate driving unit 300 may be integrated into the peripheral portion PA of the display panel 100.

[0062] The gamma reference voltage generation unit 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving control unit 200. The gamma reference voltage generation unit 400 provides the gamma reference voltage VGREF to the data driving unit 500. The gamma reference voltage VGREF has a value corresponding to each data signal DATA.

[0063] In an embodiment of the present invention, the gamma reference voltage generation unit 400 may be configured within the driving control unit 200 or within the data driving unit 500.

[0064] The data driving unit 500 receives the second control signal CONT2 and the data signal DATA from the driving control unit 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generation unit 400. The data driving unit 500 transforms the data signal DATA into an analog data voltage by using the gamma reference voltage VGREF. The data driving unit 500 outputs the data voltage to the data line DL.

[0065] Figure 2 is a conceptual diagram showing Figure 1 the display panel 100 and the data driving unit 500.

[0066] Referring to Figure 1 and Figure 2 the display panel 100 may include the display portion AA and the peripheral portion PA. The peripheral portion PA of the display panel 100 may be connected to the bending area BDA. The bending area BDA may include a bending line BL that bends toward the back surface of the display panel 100. The bending area BDA may be configured between the display panel 100 and the data driving unit 500.

[0067] The data driving unit 500 may be formed in the form of a data driving chip DIC. The data driving chip DIC may be configured in the integrated circuit area ICA of the data driving unit 500.

[0068] The display device may further include a demultiplexer circuit DXA. The demultiplexer circuit DXA may be disposed between the integrated circuit area ICA and the bending area BDA.

[0069] The display panel 100 may be disposed on a first side of the bending line BL, and the demultiplexer circuit DXA and the integrated circuit area ICA may be disposed on a second side of the bending line BL. The demultiplexer circuit DXA and the integrated circuit area ICA may be bent toward the back surface of the display panel 100. In this embodiment, since the demultiplexer circuit DXA is bent toward the back surface of the display panel 100, compared with the case where the demultiplexer circuit DXA is disposed in the peripheral area PA of the display panel 100, the invalid space of the display device can be reduced.

[0070] The data driving unit 500 may be formed into a boundary reduction structure capable of cross-outputting data voltages applied to data lines (e.g., DL3, DL4) in the central portion of the display panel 100 and data voltages applied to data lines DL1, DL2 at the edge of the display panel 100. The display panel 100 may further include lateral wirings BRS1, BRS2 for transmitting data voltages to the data lines DL1, DL2 at the edge.

[0071] Figure 3 FIG. is an illustration showing an example where coupling occurs in a demultiplexer switch structure.

[0072] Refer to Figures 1 to 3 , Figure 3 The CLA of may represent a switching signal of a first switch of the demultiplexer circuit DXA, and the CLB represents a switching signal of a second switch of the demultiplexer circuit DXA. In Figure 3 it is illustrated that the CLA outputs data of green pixels and the CLB outputs data of red and blue pixels. Differently, it may also be that the CLA outputs data of red and blue pixels and the CLB outputs data of green pixels.

[0073] According to an embodiment, the timing GW ON of turning on the gate signal may be synchronized with the timing when the CLA remains low level and high level, and may be synchronized with the timing when the CLB changes from high level to low level or from low level to high level. Thus, when the display panel 100 displays a zebra pattern, in the first GW ON timing, the brightness of the green pixels becomes brighter due to coupling (represented by a dotted line), and there may be a problem that the image becomes greenish.

[0074] As described above, when the data output path synchronized with the CLA and the data output path synchronized with the CLB are arranged adjacent to each other, a problem of reduced display quality due to coupling may occur.

[0075] Figure 4 is a table showing Figure 1 the output amplifiers of the data driver unit 500 and data mapping. Figure 5 is a diagram showing Figure 1 the data lines, border reduction horizontal lines, border reduction vertical lines, and power supply connection lines of the display panel 100. Figure 6 is a diagram showing Figure 1 the light-emitting area of the display panel 100.

[0076] Figure 7A is a conceptual diagram showing Figure 1 the output amplifiers, demultiplexer circuit, wiring hybrid structure of the data driver unit 500, and the display panel 100. Figure 7B is a conceptual diagram that magnifies and shows Figure 7A the wiring hybrid structure.

[0077] Referring to Figures 1 to 7B , the display device includes: a data driver unit 500, a demultiplexer circuit DXA, a wiring hybrid structure, and a display panel 100. In this embodiment, a 4-bundle structure in which the demultiplexer switch has a structure of A-A-B-B-B-B-A-A is shown. In Figures 4 to 7B , a case where the CLA corresponds to the data of the red and blue pixels and the CLB corresponds to the data of the green pixels is illustrated. As shown in the PDB region of Figure 7A , the demultiplexer switch structure can be repeated in units of "A-A-B-B-B-B-A-A" (for example, 200A-201A-201B-200B-199B-202B-202A-199A). If a case where the demultiplexer switch structure is repeated more than twice in units of "A-A-B-B-B-B-A-A" is illustrated, the demultiplexer switch structure may be "A-A-B-B-B-B-A-A-A-A-B-B-B-B-A-A…". In this case, if the initial starting part and the terminating part are removed, the data corresponding to the CLA (R data or B data) will be continuously arranged four by four, and the data corresponding to the CLB (G data) will be continuously arranged four by four. Therefore, the possibility of reduced image quality due to coupling between the data corresponding to the CLA and the data corresponding to the CLB is relatively reduced.

[0078] For example, the data driver unit 500 includes first to fourth output amplifiers Y1, Y2, Y3, and Y4.

[0079] The demultiplexer circuit DXA can divide the first to fourth output amplifiers Y1, Y2, Y3, and Y4 into first to eighth output lines through a demultiplexer switch.

[0080] For example, the first, fourth, fifth, and eighth output lines of the demultiplexer circuit DXA can be activated by a first switch signal CLA, and the second, third, sixth, and seventh output lines of the demultiplexer circuit are activated by a second switch signal CLB.

[0081] When configured as described above, Figure 7A data corresponding to CLA will be continuously configured two by two and data corresponding to CLB will be continuously configured two by two (e.g., 201A - 201B - 200B - 200A - 202A - 202B - 199B - 199A). When the order of the third data at the input end of the demultiplexer circuit DXA is 1, 2, 3, 4, 5, 6, 7, 8, the order of the fourth data at the output end of the demultiplexer circuit DXA can be 1, 2, 4, 3, 5, 6, 8, 7.

[0082] The wiring hybrid structure is connected to the demultiplexer circuit DXA. The display panel 100 includes data lines connected to the wiring hybrid structure.

[0083] In this embodiment, when the order of the first data at the input end PDA of the wiring hybrid structure is 1, 2, 3, 4, 5, 6, 7, 8, the order of the second data at the output end PDB of the wiring hybrid structure is 4, 1, 2, 3, 7, 6, 5, 8.

[0084] Referring to Figure 4 , the first output amplifier Y1 can be an amplifier that alternately outputs B data and G data. The second output amplifier Y2 can be an amplifier that alternately outputs R data and G data.

[0085] In Figure 5 , the display panel 100 can include: a dummy area DA, a boundary reduction area BA, a normal - boundary reduction area NBA, and a normal area NA. A dummy data line DM can be configured in the dummy area DA. In this embodiment, although the case where one dummy data line DM is configured in the dummy area DA is illustrated, the present invention is not limited thereto.

[0086] In the boundary reduction area BA, the 1A data line to the 200A data line and the 1B data line to the 200B data line can be configured. In this embodiment, although the case where 400 data lines are configured in the boundary reduction area BA is illustrated, the present invention is not limited thereto.

[0087] The 1st A data line to the 200th A data line and the 1st B data line to the 200th B data line within the boundary reduction region BA can receive data through the boundary reduction horizontal line BRSA and the boundary reduction vertical line BRSB.

[0088] Two power supply access lines EOA can be arranged between two adjacent data lines within the boundary reduction region BA. Also, between two other adjacent data lines within the boundary reduction region BA, the power supply access line EOA may not be arranged. For example, the power supply access line EOA may not be arranged between the 1st A data line and the 1st B data line. On the other hand, two power supply access lines EOA can be arranged between the 1st B data line and the 2nd B data line. The power supply access line EOA can be a wiring for applying a low power supply voltage to the pixel.

[0089] The 201st A data line to the 400th A data line and the 201st B data line to the 400th B data line can be arranged in the normal-boundary reduction region NBA. In this embodiment, although the case where 400 data lines are arranged in the normal-boundary reduction region NBA is illustrated, the present invention is not limited thereto. The data lines within the normal-boundary reduction region NBA can receive data directly from the data driving unit 500 without passing through the boundary reduction horizontal line BRSA and the boundary reduction vertical line BRSB. The boundary reduction horizontal line BRSA is arranged within the normal-boundary reduction region NBA, so that data can be transmitted to the boundary reduction region BA through the boundary reduction vertical line BRSB.

[0090] In the normal-boundary reduction region NBA, a part of the power supply access line EOA can be used as the boundary reduction horizontal line BRSA. When a part of the power supply access line EOA is used as the boundary reduction horizontal line BRSA, the part of the power supply access line EOA used as the boundary reduction horizontal line BRSA and the part of the power supply access line EOA not used as the boundary reduction horizontal line BRSA can be insulated from each other. The part of the power supply access line EOA used as the boundary reduction horizontal line BRSA cannot function to apply a low power supply voltage to the pixel, and the part of the power supply access line EOA not used as the boundary reduction horizontal line BRSA can function to apply a low power supply voltage to the pixel.

[0091] In the normal region NA, the 401A data line to the 540A data line and the 401B data line to the 540B data line can be configured. In this embodiment, although a case where 280 data lines are configured in the normal region NA is illustrated, the present invention is not limited thereto. The data lines in the normal region NA can directly receive data from the data driving unit 500 without passing through the boundary reduction horizontal line BRSA and the boundary reduction vertical line BRSB. And, the boundary reduction horizontal line BRSA may not be configured in the normal region NA. That is, in the normal region NA, the power supply access line EOA can only be used to apply the low power supply voltage.

[0092] Figure 5 The display panel 100 shown in [reference] can correspond to half of the entire display area, and the display panel 100 can be line-symmetric with respect to the center line CL.

[0093] Refer to Figure 5 , the display panel 100 can include a first power supply access line, a 1A data line 1A, a 1B data line 1B, a second power supply access line, a third power supply access line, a 2B data line 2B, a 2A data line 2A, and a fourth power supply access line, which are arranged in sequence.

[0094] First color data can be applied to the 1A data line 1A, second color data can be applied to the 1B data line 1B and the 2B data line 2B, and third color data can be applied to the 2A data line 2A. For example, the first color data can be blue data, the second color data is green data, and the third color data is red data.

[0095] As Figure 6 shown, the display panel 100 can include: a first color first light-emitting region B11, a second color first light-emitting region G11, a third color first light-emitting region R11, a second color second light-emitting region G12, a third color second light-emitting region R21, a second color third light-emitting region G21, a first color second light-emitting region B21, and a second color fourth light-emitting region G22.

[0096] Refer to together Figure 6 and Figure 7A , Figure 7A The 1A data line 1A of [reference] can be a line for applying first color data (for example, blue data), which is connected to Figure 6 the first color first light-emitting region B11 of [reference] and Figure 6 the first color second light-emitting region B21 of [reference]. Figure 7A The 1B data line 1B of [reference] can be a line for applying second color data (for example, green data), which is connected to Figure 6 the second color first light-emitting region G11 of [reference] andFigure 6 is connected to the second-color third light-emitting region G21. Figure 7A The 2B data line 2B can be a line for applying second-color data (e.g., green data), which is connected to Figure 6 the second-color second light-emitting region G12 and Figure 6 the second-color fourth light-emitting region G22. Figure 7A The 2A data line 2A can be a line for applying third-color data (e.g., red data), which is connected to Figure 6 the third-color first light-emitting region R11 and Figure 6 the third-color third light-emitting region R22.

[0097] Although not shown, Figure 6 the first-color third light-emitting region B12 can be arranged adjacent to Figure 7A the 2A data line 2A, and is connected to the 3A data line for applying first-color data (e.g., blue data).

[0098] And, Figure 6 the third-color second light-emitting region R21 can be connected to Figure 7A the dummy data line DM.

[0099] For example, the second-color first light-emitting region G11 and the second-color second light-emitting region G12 can be arranged in the 1-1 row, the first-color first light-emitting region B11 and the third-color first light-emitting region R11 are arranged in the 1-2 row adjacent to the 1-1 row, the second-color third light-emitting region G21 and the second-color fourth light-emitting region G22 are arranged in the 2-1 row adjacent to the 1-2 row, and the third-color second light-emitting region R21 and the first-color second light-emitting region B21 are arranged in the 2-2 row adjacent to the 2-1 row.

[0100] Among them, four pixels of G11, B11, G21, and R11 can be arranged in a diamond shape. Similarly, four pixels of G12, R11, G22, and B12 can also be arranged in a diamond shape. Similarly, four pixels of R11, G21, B21, and G22 can also be arranged in a diamond shape.

[0101] A part of the output data of the data driving unit 500 can be normal data NORMAL directly applied to the data line DL of the display panel 100, and a part of the output data of the data driving unit 500 is boundary reduction data BRS applied to the data line DL of the display panel 100 through the boundary reduction vertical line BRSB.

[0102] For example, when the order of the first data of the input end PDA of the wiring hybrid structure is 1, 2, 3, 4, 5, 6, 7, 8, the first data with the order of 1, 2, 5, 6 (e.g., Figure 7A 201A, 201B, 202A, 202B) can be the normal data NORMAL, and the first data with the order of 3, 4, 7, 8 (e.g., Figure 7A 200B, 200A, 199B, 199A) is the boundary reduction data BRS.

[0103] In this embodiment, the data corresponding to the 1st to 200th data lines can be the boundary reduction data BRS. On the other hand, the data corresponding to the 201st to 540th data lines is the normal data NORMAL.

[0104] As Figure 7B shown, the input end PDA of the wiring hybrid structure may include the 1st to 8th A pads A1 to A8 arranged in sequence, and the output end PDB of the wiring hybrid structure includes the 1st to 8th B pads B1 to B8 arranged in sequence.

[0105] Among them, the 1st A pad A1 can be connected to the 2nd B pad B2, the 2nd A pad A2 is connected to the 3rd B pad B3, the 3rd A pad A3 is connected to the 4th B pad B4, the 4th A pad A4 is connected to the 1st B pad B1, the 5th A pad A5 is connected to the 7th B pad B7, the 6th A pad A6 is connected to the 6th B pad B6, the 7th A pad A7 is connected to the 5th B pad B5, and the 8th A pad A8 is connected to the 8th B pad B8. Through the wiring hybrid structure as described above, when the order of the first data of the input end PDA of the wiring hybrid structure is 1, 2, 3, 4, 5, 6, 7, 8, the order of the second data of the output end PDB of the wiring hybrid structure can be 4, 1, 2, 3, 7, 6, 5, 8.

[0106] Previously, the data corresponding to CLA was continuously configured in two and the data corresponding to CLB was continuously configured in two (201A - 201B - 200B - 200A - 202A - 202B - 199B - 199A). However, through the wiring hybrid structure, from Figure 7A it can be changed to the data corresponding to CLA being continuously configured in four and the data corresponding to CLB being continuously configured in four (200A - 201A - 201B - 200B - 199B - 202B - 202A - 199A). That is, the 4 - bundle structure can be implemented by using the wiring hybrid structure, and the data mapping error in the 4 - bundle structure can be prevented by using the wiring hybrid structure.

[0107] Figure 8 It is a conceptual diagram of an output amplifier, a demultiplexer circuit, and a display panel 100 of a data driver unit 500 that outputs dummy data to a dummy data line DM of the display panel 100 for Figure 1 .

[0108] Referring to Figures 1 to 8 , the data driver unit 500 may further include: an (N + 1)th output amplifier (for example, Y401), an (N + 2)th output amplifier (for example, Y402), an (N + 3)th output amplifier (for example, Y403), an (N + 4)th output amplifier (for example, Y404), an (N + 5)th output amplifier (for example, Y405), an (N + 6)th output amplifier (for example, Y406), an (N + 7)th output amplifier (for example, Y407), and an (N + 8)th output amplifier (for example, Y408). Among them, the (N + 1)th output amplifier (for example, Y401) may be an output amplifier that outputs blue data and green data, the (N + 2)th output amplifier (for example, Y402) is an output amplifier that outputs red data and green data, the (N + 3)th output amplifier (for example, Y403) is an output amplifier that outputs red data and green data, the (N + 4)th output amplifier (for example, Y404) is an output amplifier that outputs blue data and green data, the (N + 5)th output amplifier (for example, Y405) is an output amplifier that outputs blue data and green data, the (N + 6)th output amplifier (for example, Y406) is an output amplifier that outputs red data and green data, the (N + 7)th output amplifier (for example, Y407) is an output amplifier that outputs red data and green data, and the (N + 8)th output amplifier (for example, Y408) is an output amplifier that outputs blue data and green data.

[0109] For example, in the normal area NA, a 401A data line to a 540A data line and a 401B data line to a 540B data line may be arranged.

[0110] For example, the (N + 1)th output amplifier (for example, Y401) may output data for the (N + 1)A data line (for example, the 401A data line) and the (N + 1)B data line (for example, the 401B data line), and the (N + 2)th output amplifier (for example, Y402) may output data for the dummy data line DM.

[0111] That is, the (N + 1)th output amplifier (for example, Y401) may be used for outputting normal data to the normal area NA, and the (N + 2)th output amplifier (for example, Y402) is used for outputting data of the dummy data line DM.

[0112] Moreover, the (N + 3)th output amplifier (e.g., Y403), the (N + 4)th output amplifier (e.g., Y404), and the (N + 5)th output amplifier (e.g., Y405) may not be activated. In this embodiment, the dummy data line DM is connected to the red pixels and corresponds to the boundary reduction data BRS. Therefore, in order to output the boundary reduction data BRS of the red color to the dummy data line DM, an output amplifier group with four units can be used (including a first amplifier for outputting blue normal data and green normal data, a second amplifier for outputting red boundary reduction data and green boundary reduction data, a third amplifier for outputting red normal data and green normal data, and a fourth amplifier for outputting blue boundary reduction data and green boundary reduction data). Thus, in order to output the red boundary reduction data to the dummy data line DM connected to the red pixels, the (N + 2)th output amplifier (e.g., Y402) is activated. On the other hand, the (N + 3)th output amplifier (e.g., Y403), the (N + 4)th output amplifier (e.g., Y404), and the (N + 5)th output amplifier (e.g., Y405) may not be activated.

[0113] The dummy data can be applied to the dummy data line DM via a boundary reduction vertical line configured between the 400A data line and the 401A data line and a boundary reduction horizontal line connected thereto.

[0114] Moreover, the (N + 6)th output amplifier (e.g., Y406) can output the data of the (N + 2)A data line (e.g., the 402A data line) and the (N + 2)B data line (e.g., the 402B data line), the (N + 7)th output amplifier (e.g., Y407) outputs the data of the (N + 3)A data line (e.g., the 403A data line) and the (N + 3)B data line (e.g., the 403B data line), and the (N + 8)th output amplifier (e.g., Y408) outputs the data of the (N + 4)A data line (e.g., the 404A data line) and the (N + 4)B data line (e.g., the 404B data line). The (N + 6)th output amplifier (e.g., Y406), the (N + 7)th output amplifier (e.g., Y407), and the (N + 8)th output amplifier (e.g., Y408) can all output normal data.

[0115] According to this embodiment, since it includes a demultiplexer switch structure supporting 4-wire bundles and a wiring mixing structure for preventing data mapping errors, the demultiplexing coupling can be improved and data mapping errors can be prevented.

[0116] Moreover, in the case of an integrated circuit without a data driving unit 500 and a change in the active area of the display panel 100, a demultiplexer switch structure supporting 4-wire bundles can be supported.

[0117] Moreover, since the data driving unit 500 is configured to have a boundary reduction structure that can cross-output the data voltages applied to the data lines in the central portion of the display panel 100 and the data voltages applied to the data lines at the edges of the display panel, the invalid space of the display device can be reduced.

[0118] Moreover, since the demultiplexer circuit is disposed adjacent to the integrated circuit region on the second side of the curved line, the invalid space of the display device can be further reduced.

[0119] Moreover, by including the configuration of the data driving unit 500 for applying dummy data to the dummy data line DM, appropriate data can be applied to the dummy data line.

[0120] Figure 9 FIG. is a conceptual diagram showing an output amplifier, a demultiplexer circuit, and the display panel 100 of the data driving unit 500 for outputting dummy data to the dummy data line DM of the display panel 100 of a display device according to an embodiment of the present invention.

[0121] The display device according to the present embodiment is substantially the same as the display device Figures 1 to 8 except for the output amplifier, the demultiplexer circuit, and the structure of the display panel of the data driving unit for outputting dummy data. Therefore, the same reference numerals will be used for the same or similar parts, and redundant descriptions will be omitted.

[0122] Refer to Figures 1 to 7B and Figure 9 , the display device includes: a data driving unit 500, a demultiplexer circuit DXA, a wiring hybrid structure, and a display panel 100. In the present embodiment, a 4-bundle structure in which the demultiplexer switch has a structure of A-A-B-B-B-B-A-A is shown. Figures 4 to 7B illustrates a case where CLA corresponds to the data of red and blue pixels, and CLB corresponds to the data of green pixels. As Figure 7AAs shown in the PDB region, the demultiplexer switch structure can be repeated in units of "A-A-B-B-B-B-A-A" (e.g., 200A-201A-201B-200B-199B-202B-202A-199A). If the illustrated demultiplexer switch structure is repeated more than twice in units of "A-A-B-B-B-B-A-A", then the demultiplexer switch structure can be "A-A-B-B-B-B-A-A-A-A-B-B-B-B-A-A…". In this case, if the initial starting part and the terminating part are removed, four data corresponding to CLA (R data or B data) are continuously configured, and four data corresponding to CLB (G data) are continuously configured. Therefore, the possibility of image quality degradation caused by coupling between the data corresponding to CLA and the data corresponding to CLB is relatively reduced.

[0123] For example, the data driver unit 500 includes first to fourth output amplifiers Y1, Y2, Y3, and Y4.

[0124] The demultiplexer circuit DXA can distribute the first to fourth output amplifiers Y1, Y2, Y3, and Y4 to first to eighth output lines through a demultiplexer switch.

[0125] For example, the first, fourth, fifth, and eighth output lines of the demultiplexer circuit DXA are activated by a first switch signal CLA, and the second, third, sixth, and seventh output lines of the demultiplexer circuit are activated by a second switch signal CLB.

[0126] When configured as described above, Figure 7A two data corresponding to CLA and two data corresponding to CLB are continuously configured (e.g., 201A-201B-200B-200A-202A-202B-199B-199A). When the order of the third data at the input end of the demultiplexer circuit DXA is 1, 2, 3, 4, 5, 6, 7, 8, the order of the fourth data at the output end of the demultiplexer circuit DXA can be 1, 2, 4, 3, 5, 6, 8, 7.

[0127] The wiring hybrid structure is connected to the demultiplexer circuit DXA. The display panel 100 includes data lines connected to the wiring hybrid structure.

[0128] In this embodiment, when the order of the first data at the input end PDA of the wiring hybrid structure is 1, 2, 3, 4, 5, 6, 7, 8, the order of the second data at the output end PDB of the wiring hybrid structure is 4, 1, 2, 3, 7, 6, 5, 8.

[0129] The data driving unit 500 may further include: an (N + 1)th output amplifier (e.g., Y401), an (N + 2)th output amplifier (e.g., Y402), an (N + 3)th output amplifier (e.g., Y403), an (N + 4)th output amplifier (e.g., Y404), an (N + 5)th output amplifier (e.g., Y405), an (N + 6)th output amplifier (e.g., Y406), an (N + 7)th output amplifier (e.g., Y407), and an (N + 8)th output amplifier (e.g., Y408). Among them, the (N + 1)th output amplifier (e.g., Y401) may be an output amplifier that outputs blue data and green data, the (N + 2)th output amplifier (e.g., Y402) is an output amplifier that outputs red data and green data, the (N + 3)th output amplifier (e.g., Y403) is an output amplifier that outputs red data and green data, the (N + 4)th output amplifier (e.g., Y404) is an output amplifier that outputs blue data and green data, the (N + 5)th output amplifier (e.g., Y405) is an output amplifier that outputs blue data and green data, the (N + 6)th output amplifier (e.g., Y406) is an output amplifier that outputs red data and green data, the (N + 7)th output amplifier (e.g., Y407) is an output amplifier that outputs red data and green data, and the (N + 8)th output amplifier (e.g., Y408) is an output amplifier that outputs blue data and green data.

[0130] For example, in the normal region NA, a 401A data line to a 540A data line and a 401B to a 540B data line may be configured.

[0131] For example, the (N + 5)th output amplifier (e.g., Y405) may output data for the (N + 1)A data line (e.g., the 401A data line) and the (N + 1)B data line (e.g., the 401B data line), and the (N + 2)th output amplifier (e.g., Y402) may output data for the dummy data line DM.

[0132] That is, the (N + 5)th output amplifier (e.g., Y405) may be used for outputting normal data to the normal region NA, and the (N + 2)th output amplifier (e.g., Y402) is used for outputting data of the dummy data line DM.

[0133] Moreover, the (N + 1)th output amplifier (e.g., Y401), the (N + 3)th output amplifier (e.g., Y403), and the (N + 4)th output amplifier (e.g., Y404) may not be activated. In this embodiment, the dummy data line DM is connected to the red pixels and corresponds to the boundary reduction data BRS. Therefore, in order to output the boundary reduction data BRS of the red color to the dummy data line DM, an output amplifier group with four units can be used (including a first amplifier for outputting blue normal data and green normal data, a second amplifier for outputting red boundary reduction data and green boundary reduction data, a third amplifier for outputting red normal data and green normal data, and a fourth amplifier for outputting blue boundary reduction data and green boundary reduction data). Thus, in order to output the red boundary reduction data to the dummy data line DM connected to the red pixels, the (N + 2)th output amplifier (e.g., Y402) is activated, while on the other hand, the (N + 1)th output amplifier (e.g., Y401), the (N + 3)th output amplifier (e.g., Y403), and the (N + 4)th output amplifier (e.g., Y404) may not be activated.

[0134] The dummy data can be applied to the dummy data line DM via a boundary reduction vertical line configured between the 400A data line and the 401A data line and a boundary reduction horizontal line connected thereto.

[0135] Moreover, the (N + 6)th output amplifier (e.g., Y406) can output the data of the (N + 2)A data line (e.g., the 402A data line) and the (N + 2)B data line (e.g., the 402B data line), the (N + 7)th output amplifier (e.g., Y407) outputs the data of the (N + 3)A data line (e.g., the 403A data line) and the (N + 3)B data line (e.g., the 403B data line), and the (N + 8)th output amplifier (e.g., Y408) outputs the data of the (N + 4)A data line (e.g., the 404A data line) and the (N + 4)B data line (e.g., the 404B data line). The (N + 6)th output amplifier (e.g., Y406), the (N + 7)th output amplifier (e.g., Y407), and the (N + 8)th output amplifier (e.g., Y408) can all output normal data.

[0136] According to this embodiment, since it includes a demultiplexer switch structure that supports 4-wire bundles and a wiring mixing structure for preventing data mapping errors, the demultiplexing coupling can be improved and data mapping errors can be prevented.

[0137] Moreover, without changing the integrated circuit of the data driving unit 500 and the active area of the display panel 100, a demultiplexer switch structure that supports 4-wire bundles can be supported.

[0138] In addition, since the data driving unit 500 is configured to have a boundary reduction structure that can cross-output the data voltage applied to the data lines in the central portion of the display panel 100 and the data voltage applied to the data lines at the edge of the display panel, the ineffective space of the display device can be reduced.

[0139] In addition, since the demultiplexer circuit is disposed adjacent to the integrated circuit region on the second side of the curved line, the ineffective space of the display device can be further reduced.

[0140] In addition, by including a configuration of the data driving unit 500 for applying dummy data to the dummy data lines DM, appropriate data can be applied to the dummy data lines.

[0141] Figure 10 is a block diagram of an electronic device showing an embodiment of the present invention. Figure 11 shows Figure 10 An example in which the electronic device is implemented by a smartphone.

[0142] Referring to Figure 10 and Figure 11 , the electronic device 1000 may include: a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply device 1050, and a display device 1060. At this time, the display device 1060 may be Figure 1 the display device. In addition, the electronic device 1000 may further include various ports that can communicate with a graphics card, a sound card, a memory card, a USB device, etc., or communicate with other systems.

[0143] According to an embodiment, as Figure 11 shown, the electronic device 1000 may be implemented by a smartphone. However, this is merely illustrative, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a mobile phone, a video phone, a smart tablet, a smart watch, a tablet PC, a vehicle navigation, a computer monitor, a notebook, a head-mounted display device, etc.

[0144] The processor 1010 may perform specific calculations or tasks. According to an embodiment, the processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 may be connected to other components through an address bus, a control bus, a data bus, etc. According to an embodiment, the processor 1010 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0145] The processor 1010 may output the input image data IMG and the input control signal CONT to Figure 1 the driving control unit 200 thereof.

[0146] The memory device 1020 may store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices such as an Erasable Programmable Read-Only Memory (EPROM) device, an Electrically Erasable Programmable Read-Only Memory (EEPROM) device, a flash memory device, a Phase Change Random Access Memory (PRAM) device, a Resistance Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a Polymer Random Access Memory (PoRAM) device, a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM) device, etc. and / or volatile memory devices such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a mobile DRAM device, etc.

[0147] The storage device 1030 may include a Solid State Drive (SSD), a Hard Disk Drive (HDD), a CD-ROM, etc. The input / output device 1040 may include input means such as a keyboard, a keypad, a touchpad, a touch screen, a mouse, etc. and output means such as a speaker, a printer, etc. According to an embodiment, the display device 1060 may also be included in the input / output device 1040. The power supply device 1050 may supply power required for the operation of the electronic device 1000. The display device 1060 may be connected to other components via the bus or other communication links.

[0148] Figure 12 is a block diagram of an electronic device 101 showing an embodiment of the present invention.

[0149] Refer toFigures 1 to 12 The electronic device 101 outputs various information through the display module 140 within the operating system. When the processor 110 runs the application programs stored in the memory 120, the display module 140 provides the application program information to the user through the display panel 141.

[0150] The processor 110 obtains external inputs through the input module 130 or the sensing module 161 and runs the application programs corresponding to the external inputs. For example, in the case where the user selects the camera icon displayed on the display panel 141, the processor 110 obtains the user input through the input sensor 161-2 and activates the camera module 171. The processor 110 transfers the video data corresponding to the captured image obtained through the camera module 171 to the display module 140. The display module 140 may display the image corresponding to the captured image through the display panel 141.

[0151] As another example, in the case where personal information authentication is performed in the display module 140, the fingerprint sensor 161-1 obtains the input fingerprint information as input data. The processor 110 compares the input data obtained through the fingerprint sensor 161-1 with the authentication data stored in the memory 120 and runs the application program according to the comparison result. The display module 140 may display the information that runs according to the logic of the application program through the display panel 141.

[0152] As another example, in the case where the music stream icon displayed on the display module 140 is selected, the processor 110 obtains the user input through the input sensor 161-2 and activates the music stream application program stored in the memory 120. When a music execution instruction is input in the music stream application program, the processor 110 activates the audio output module 163 and provides the audio information corresponding to the music execution instruction to the user.

[0153] Above, the operation of the electronic device 101 has been briefly described. Hereinafter, the structure of the electronic device 101 will be described in detail. A part of the structure of the electronic device 101 described later may be integrated and provided as one structure, and one structure may also be separated into two or more structures for provision.

[0154] The electronic device 101 may communicate with an external electronic device 102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to an embodiment, the electronic device 101 may include: a processor 110, a memory 120, an input module 130, a display module 140, a power module 150, a built-in module 160, and an external module 170. According to an embodiment, in the electronic device 101, at least one of the above-described components may be omitted, or one or more other components may be added. According to an embodiment, some of the above-described components (e.g., a sensing module 161, an antenna module 162, or an audio output module 163) may be integrated into another component (e.g., the display module 140).

[0155] The processor 110 may control at least one other component (e.g., a hardware or software component) of the electronic device 101 connected to the processor 110 by running software, and may perform various data processing or operations. According to an embodiment, as at least a part of the data processing or operations, the processor 110 may store instructions or data received from other components (e.g., the input module 130, the sensing module 161, or the communication module 173) in the volatile memory 121, process the instructions or data stored in the volatile memory 121, and store the result data in the non-volatile memory 122.

[0156] The processor 110 may include a main processor 111 and an auxiliary processor 112. The main processor 111 may include one or more of a central processing unit 111-1 (CPU) or an application processor (AP). The main processor 111 may also include one or more of a graphic processing unit 111-2 (GPU), a communication processor (CP), and an image signal processor (ISP). The main processor 111 may also include a neural network processing unit 111-3 (NPU). The neural network processing unit 111-3 is a processor dedicated to processing artificial intelligence models, and the artificial intelligence models may be generated through machine learning. The artificial intelligence models may include multiple artificial neural network layers. The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network, a recurrent neural network (RNN), a restricted boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), deep Q-networks, or a combination of two or more of the foregoing, but is not limited to the foregoing examples. In addition to the hardware structure, the artificial intelligence models may additionally or alternatively include a software structure. At least two of the above-mentioned processing units and processors may be implemented by an integrated structure (e.g., a single chip) or separately in independent structures (e.g., multiple chips).

[0157] The auxiliary processor 112 may include a controller. The controller may include an interface conversion circuit and a timing control circuit. The controller receives an image signal from the main processor 111, converts the data format of the image signal in a manner matching the interface specification of the display module 140, and outputs the image data. The controller may output various control signals required for driving the display module 140.

[0158] The auxiliary processor 112 may also include a data conversion circuit 112-2, a gamma correction circuit 112-3, a rendering circuit 112-4, etc. The data conversion circuit 112-2 may receive image data from the controller and compensate the image data according to the characteristics of the electronic device 101 or user settings, etc., to display the image at a desired brightness, or transform the image data to reduce power consumption or compensate for afterimages, etc. The gamma correction circuit 112-3 may transform the image data or gamma reference voltage, etc., so that the image displayed on the electronic device 101 has the desired gamma characteristics. The rendering circuit 112-4 may receive image data from the controller and render the image data in consideration of the pixel arrangement of the display panel 141 employed in the electronic device 101, etc. At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 may be integrated into other components (e.g., the main processor 111 or the controller). At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 may also be integrated into the data driver 143 described later.

[0159] The memory 120 may store various data used by at least one component of the electronic device 101 (e.g., the processor 110 or the sensing module 161) and input data or output data of instructions associated therewith. The memory 120 may include one or more of a volatile memory 121 and a non-volatile memory 122.

[0160] The input module 130 may receive instructions or data to be used in components of the electronic device 101 (e.g., the processor 110, the sensing module 161, or the audio output module 163) from the outside of the electronic device 101 (e.g., a user or an external electronic device 102).

[0161] The input module 130 may include: a first input module 131 for a user to input instructions or data; and a second input module 132 for an external electronic device 102 to input instructions or data. The first input module 131 may include a microphone, a mouse, a keyboard, a key (e.g., a button), or a pen (e.g., a passive pen or an active pen). The second input module 132 may support a specified protocol to be able to connect to the external electronic device 102 in a wired or wireless manner. According to an embodiment, the second input module 132 may include an HDMI (high definition multimedia interface), a USB (universal serial bus) interface, an SD card interface, or an audio interface. The second input module 132 may include a connector capable of physically connecting to the external electronic device 102, e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0162] The display module 140 visually provides information to the user. The display module 140 may include: a display panel 141, a scan driver 142, and a data driver 143. The display module 140 may further include a window, a chassis, and a bracket for protecting the display panel 141.

[0163] The display panel 141 may include a liquid crystal display panel, an organic light emitting display panel, or an inorganic light emitting display panel, and there is no particular limitation on the type of the display panel 141. The display panel 141 may be of a rigid type or a flexible type that can be curled or folded. The display module 140 may further include a support or a heat dissipation member for supporting the display panel 141, etc.

[0164] The scan driver 142 may be mounted on the display panel 141 as a driving chip. And the scan driver 142 may be integrated into the display panel 141. For example, the scan driver 142 may include an amorphous silicon TFT gate driver circuit (ASG), a low temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (OSG) built into the display panel 141. The scan driver 142 receives a control signal from the controller and outputs a scan signal to the display panel 141 in response to the control signal.

[0165] The display module 140 may further include a light emitting driver. The light emitting driver outputs a light emission control signal to the display panel 141 in response to a control signal received from the controller. The light emitting driver may be formed separately from the scan driver 142 or integrated into the scan driver 142.

[0166] The data driver 143 receives a control signal from the controller, converts image data into an analog voltage (e.g., a data voltage) in response to the control signal, and then outputs the data voltage to the display panel 141.

[0167] The data driver 143 may be integrated into other components (e.g., the controller). The functions of the interface conversion circuit and the timing control circuit of the above-mentioned controller may also be integrated into the data driver 143.

[0168] The display module 140 may further include a voltage generation circuit. The voltage generation circuit may output various voltages required for driving the display panel 141.

[0169] The power module 150 supplies power to the components of the electronic device 101. The power module 150 may include a battery that supplies a power voltage. The battery may include a primary battery that cannot be recharged, a secondary battery that can be recharged, or a fuel cell. The power module 150 may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to the above-mentioned modules and the modules described later respectively. The power module 150 may include a wireless power transceiver component electrically connected to the battery. The wireless power transceiver component may include a plurality of antenna radiators in the form of coils.

[0170] The electronic device 101 may further include an in-built module 160 and an external module 170. The in-built module 160 may include: a sensing module 161, an antenna module 162, and an audio output module 163. The external module 170 may include: a camera module 171, a lighting module 172, and a communication module 173.

[0171] The sensing module 161 may sense an input from the user's body or an input from a pen in the first input module 131, and generate an electrical signal or data value corresponding to the input. The sensing module 161 may include one or more of a fingerprint sensor 161-1, an input sensor 161-2, and a digitizer 161-3.

[0172] The fingerprint sensor 161-1 may generate a data value corresponding to the user's fingerprint. The fingerprint sensor 161-1 may include one of an optical or capacitive fingerprint sensor.

[0173] The input sensor 161-2 may generate a data value corresponding to the relevant coordinate information when an input is made with the user's body or a pen. The input sensor 161-2 generates the amount of capacitance change caused by the input as a data value. The input sensor 161-2 may sense the input of a passive pen or communicate with an active pen.

[0174] The input sensor 161-2 may also measure biometric signals such as blood pressure, moisture, or body fat. For example, when a part of the user's body touches the sensing layer or sensing panel and does not move for a certain period of time, based on the change in the electric field caused by a part of the body, the input sensor 161-2 may sense the biometric signal and output the information required by the user to the display module 140.

[0175] The digitizer 161-3 may generate a data value corresponding to the relevant coordinate information when an input is made with a pen. The digitizer 161-3 generates the amount of electromagnetic change caused by the input as a data value. The digitizer 161-3 may sense the input of a passive pen or communicate with an active pen.

[0176] At least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may also be implemented as a sensing layer formed on the display panel 141 through a continuous process. The fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be disposed on the upper side of the display panel 141, and one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3, for example, the digitizer 161-3 may be disposed on the lower side of the display panel 141.

[0177] Two or more of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be integrally formed on one sensing panel through the same process. In the case of being integrated into one sensing panel, the sensing panel may be disposed between the display panel 141 and a window disposed on the upper side of the display panel 141. According to an embodiment, the sensing panel may also be disposed on the window, and the position of the sensing panel is not particularly limited.

[0178] At least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be built in the display panel 141. That is, at least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be formed simultaneously with the display panel 141 through the process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 141.

[0179] In addition to this, the sensing module 161 may generate an electrical signal or a data value corresponding to an internal state or an external state of the electronic device 101. The sensing module 161 may further include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0180] The antenna module 162 may include one or more antennas for transmitting a signal or power to the outside or receiving a signal or power from the outside. According to an embodiment, the communication module 173 may transmit a signal to an external electronic device or receive a signal from an external electronic device through an antenna suitable for a communication method. The antenna pattern of the antenna module 162 may also be integrated into one component (e.g., the display panel 141) of the display module 140 or the input sensor 161-2, etc.

[0181] The audio output module 163 is a device for outputting an audio signal to the outside of the electronic device 101, and may include, for example, a speaker used for general purposes such as multimedia playback or recording playback and a receiver used exclusively for telephone reception. According to one embodiment, the receiver may be formed integrally with the speaker or separately. The audio output pattern of the audio output module 163 may also be integrated into the display module 140.

[0182] The camera module 171 can capture still images and dynamic images. According to one embodiment, the camera module 171 may include one or more lenses, image sensors or image signal processors. The camera module 171 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, the user's line of sight, etc.

[0183] The lighting module 172 may provide light. The lighting module 172 may include a light emitting diode or a xenon lamp. The lighting module 172 may work in conjunction with the camera module 171 or independently.

[0184] The communication module 173 can support the construction of a wired or wireless communication channel between the electronic device 101 and the external electronic device 102 and the communication execution based on the constructed communication channel. The communication module 173 may include a cellular communication module, a short-range wireless communication module or a wireless communication module such as a global navigation satellite system (GNSS) communication module and a wired communication module such as a local area network (LAN) communication module or a power line communication module, or include all of them. The communication module 173 can communicate with the external electronic device 102 through a short-range communication network such as Bluetooth, WiFi direct or infrared communication (infrared data association, IrDA) or a long-range communication network such as a cellular network, the Internet or a computer network (for example, LAN or WAN). The above-mentioned multiple types of communication modules 173 can be implemented by one chip or by separate chips respectively.

[0185] The input module 130 , the sensor module 161 , the camera module 171 , etc. may be applied to work in conjunction with the processor 110 and control the operation of the display module 140 .

[0186] The processor 110 outputs instructions or data to the display module 140, the audio output module 163, the camera module 171, or the lighting module 172 according to the input data received from the input module 130. For example, the processor 110 may generate image data corresponding to the input data applied by a mouse or an active pen, etc., and output it to the display module 140, or generate instruction data corresponding to the input data and output it to the camera module 171 or the lighting module 172. If the processor 110 does not receive input data from the input module 130 for a certain period of time, the operating mode of the electronic device 101 may be switched to a low power mode or a sleep mode, thereby reducing the power consumed in the electronic device 101.

[0187] The processor 110 may output instructions or data to the display module 140, the audio output module 163, the camera module 171, or the lighting module 172 according to the sensing data received from the sensing module 161. For example, the processor 110 may compare the authentication data applied by the fingerprint sensor 161-1 with the authentication data stored in the memory 120, and then run an application according to the comparison result. The processor 110 may execute instructions or output corresponding image data to the display module 140 according to the sensing data sensed by the input sensor 161-2 or the digitizer 161-3. In the case where a temperature sensor is included in the sensing module 161, the processor 110 may receive temperature data related to the temperature measured by the sensing module 161, and further perform brightness correction, etc. on the image data according to the temperature data.

[0188] The processor 110 may receive measurement data related to the presence or absence of a user, the user's position, the user's line of sight, etc. from the camera module 171. The processor 110 may further perform brightness correction, etc. on the image data according to the measurement data. For example, the processor 110 that determines the presence or absence of a user based on the input of the camera module 171 may output the image data whose brightness is corrected through the data conversion circuit 112-2 or the gamma correction circuit 112-3 to the display module 140.

[0189] Some of the constituent elements can be connected to each other via an inter-peripheral communication method, such as a bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industry processor interface (MIPI), or Ultrapath interconnect (UPI) link, so as to exchange signals (e.g., instructions or data) with each other. The processor 110 can communicate with the display module 140 using an interface agreed upon by each other. For example, it can use one of the above-mentioned communication methods, but is not limited to the above-mentioned communication methods.

[0190] The electronic device 101 of various embodiments disclosed in this specification can be various types of devices. The electronic device 101 can include, for example, at least one of a portable communication device (e.g., a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance device. The electronic device 101 of the embodiments of this specification is not limited to the aforementioned devices.

[0191] For example, Figure 1 The display panel 100 of can correspond to Figure 12 The display panel 141 of. For example, Figure 1 The drive control unit 200 of can correspond to Figure 12 The controller of the auxiliary processor 112 of. For example, Figure 1 The gate drive unit 300 of can correspond to Figure 12 The scan driver 142 of. For example, Figure 1 The data drive unit 500 of can correspond to Figure 12 The data driver 143 of.

[0192] Industrial applicability

[0193] According to the display device of the present invention described above, it is possible to improve demultiplexing coupling and prevent data mapping errors.

[0194] Although the above has been described with reference to the embodiments, those of ordinary skill in the relevant technical field should understand that various modifications and variations can be made to the present invention without departing from the spirit and scope of the present invention described in the appended claims.

Claims

1. A display device, characterized in that, Comprising: A data driving unit, including a first output amplifier to a fourth output amplifier, A demultiplexer circuit, which divides the first output amplifier to the fourth output amplifier into a first output line, a second output line, a third output line, a fourth output line, a fifth output line, a sixth output line, a seventh output line and an eighth output line through demultiplexer switches, A wiring hybrid structure, connected to the demultiplexer circuit, and A display panel, including data lines connected to the wiring hybrid structure; When the order of the first data at the input end of the wiring hybrid structure is 1, 2, 3, 4, 5, 6, 7, 8, the order of the second data at the output end of the wiring hybrid structure is 4, 1, 2, 3, 7, 6, 5, 8.

2. The display device according to claim 1, characterized in that, It further includes a bending area arranged between the display panel and the data driving unit, The demultiplexer circuit is arranged between the integrated circuit area of the data driving unit and the bending area.

3. The display device according to claim 2, characterized in that, The bending area includes a bending line bent towards the back surface of the display panel, The display panel is arranged on the first side of the bending line, and the demultiplexer circuit and the integrated circuit area are arranged on the second side of the bending line.

4. The display device according to claim 1, characterized in that, A part of the output data of the data driving unit is normal data directly applied to the data lines of the display panel, A part of the output data of the data driving unit is boundary reduction data applied to the data lines of the display panel through boundary reduction horizontal lines.

5. The display device according to claim 1, characterized in that, The first output line, the fourth output line, the fifth output line and the eighth output line of the demultiplexer circuit are activated by a first switch signal, The second output line, the third output line, the sixth output line and the seventh output line of the demultiplexer circuit are activated by a second switch signal.

6. The display device according to claim 1, characterized in that, The data driving unit further includes an (N + 1)th output amplifier, an (N + 2)th output amplifier, an (N + 3)th output amplifier, an (N + 4)th output amplifier, an (N + 5)th output amplifier, an (N + 6)th output amplifier, an (N + 7)th output amplifier and an (N + 8)th output amplifier, The (N + 1)th output amplifier outputs data for the (N + 1)_1 data line and the (N + 1)_2 data line, The (N + 2)th output amplifier outputs data for dummy data lines, where N is a natural number greater than or equal to 4.

7. The display device according to claim 1, characterized in that, The display panel includes a first power supply access line, a 1_1 data line, a 1_2 data line, a second power supply access line, a third power supply access line, a 2_2 data line, a 2_1 data line and a fourth power supply access line arranged in sequence, First color data is applied to the 1_1 data line, Apply second-color data to the 1_2 data line and the 2_2 data line. Apply third-color data to the 2_1 data line.

8. The display device according to claim 7, wherein the display panel includes a first-color first light-emitting region, a second-color first light-emitting region, a third-color first light-emitting region, a second-color second light-emitting region, a third-color second light-emitting region, a second-color third light-emitting region, a first-color second light-emitting region, and a second-color fourth light-emitting region. The 1_1 data line is connected to the first-color first light-emitting region and the first-color second light-emitting region. The 1_2 data line is connected to the second-color first light-emitting region and the second-color third light-emitting region. The 2_2 data line is connected to the second-color second light-emitting region and the second-color fourth light-emitting region. The 2_1 data line is connected to the third-color first light-emitting region.

9. The display device according to claim 1, wherein when the order of the third data at the input end of the demultiplexer circuit is 1, 2, 3, 4, 5, 6, 7, 8, the order of the fourth data at the output end of the demultiplexer circuit is 1, 2, 4, 3, 5, 6, 8, 7.

10. An electronic device, wherein it includes: a data driving unit including a first output amplifier to a fourth output amplifier, a demultiplexer circuit that divides the first output amplifier to the fourth output amplifier into a first output line, a second output line, a third output line, a fourth output line, a fifth output line, a sixth output line, a seventh output line, and an eighth output line through demultiplexer switches, a wiring hybrid structure connected to the demultiplexer circuit, a display panel including data lines connected to the wiring hybrid structure, a driving control unit that controls the data driving unit, and a processor that outputs input image data and input control signals to the driving control unit; when the order of the first data at the input end of the wiring hybrid structure is 1, 2, 3, 4, 5, 6, 7, 8, the order of the second data at the output end of the wiring hybrid structure is 4, 1, 2, 3, 7, 6, 5, 8.

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