Data processing apparatus, data driving apparatus, and display apparatus including same

Abstract

Provided are a data processing device, a data driving device, and a display device including the same, which transmit setting data in a low-speed communication mode, change steps to a high-speed communication mode after the low-speed communication mode, and transmit control data and video data, and in a process of operating in the high-speed communication mode, change steps to the high-speed communication mode. If a lock failure signal is received, the clock training mode is retransmitted while maintaining the high-speed communication mode.

Description

Technical Field

[0001] The embodiment relates to a driving technique of a display device. Background Art

[0002] A display panel is composed of a plurality of pixels arranged in a matrix form. Each pixel may have colors such as red (R), green (G), and blue (B), and emits light according to a greyscale based on video data to display an image on the display panel.

[0003] Video data is sent from a data processing device such as a timing controller to a data driving device such as a source driver. The video data is sent as a digital value, and the data driving device converts the video data into an analog voltage and drives each pixel.

[0004] The video data individually or independently indicates the gradient value of each pixel. Therefore, the amount of video data increases as the number of pixels provided in the display panel increases. Moreover, as the frame rate increases, the amount of video data that needs to be sent per unit time also increases.

[0005] Recently, as the resolution of the display panel increases, both the number of pixels provided in the display panel and the frame rate have increased. In order to process the amount of video data that increases with the increase in high resolution, the data communication of the display device has gradually become faster.

[0006] When such a high-speed communication interface is subjected to external noise such as noise or ESD of a transmission channel, signal distortion will occur, and the data driving device can recover abnormal data. Therefore, the data processing device needs to quickly recover the communication state in order to achieve normal data communication. Summary of the Invention

[0007] Technical Problem

[0008] One embodiment provides a data processing device, a data driving device, and a display device including the same that can quickly recover the communication state in the case of a lock failure.

[0009] The object of the present invention is not limited to the above-mentioned object, and those of ordinary skill in the technical field to which the present invention pertains can clearly understand other objects not mentioned through the following description.

[0010] Technical Solution

[0011] A data processing device according to a feature of the present invention sends set data in a low-speed communication mode, and after the low-speed communication mode, changes the step to a high-speed communication mode and sends control data and video data. During the operation through the high-speed communication mode, if a lock failure signal is received, the clock training mode is retransmitted while maintaining the state of the high-speed communication mode.

[0012] After the low-speed communication mode, in order to enter the high-speed communication mode, a clock training mode is transmitted. After receiving a lock signal indicating that the training of the clock training mode has been completed, in the step of transmitting image data, if a lock failure signal is received, the clock training mode can be retransmitted while maintaining the state of the high-speed communication mode.

[0013] If a lock signal related to the retransmitted clock training mode is not received within a predetermined time, the low-speed communication mode can be executed again.

[0014] In the case of executing the low-speed communication mode again, the preamble mode can be retransmitted.

[0015] Before retransmitting the clock training mode, a repair start signal is transmitted, and the repair start signal can be a signal formed by repeating a high level and a low level.

[0016] Before retransmitting the clock training mode, a repair start signal is transmitted, and the repair start signal can be a direct current (DC) signal of a high level or a low level.

[0017] If power is supplied, the low-speed communication mode is activated to send the preamble mode and then send the set data. If a lock signal related to the preamble mode is received, the set data is sent. If a lock signal is continuously received, the high-speed communication mode can be activated.

[0018] If a lock signal related to the clock training mode is received, the link training mode can be transmitted.

[0019] A data driving device according to a feature of the present invention receives set data in the low-speed communication mode, receives control data and image data in the high-speed communication mode after the low-speed communication mode, and during the operation through the high-speed communication mode, if a lock failure is detected, a lock failure signal is sent to the data processing device, and a repair start signal and a clock training mode can be received while maintaining the state of the high-speed communication mode to perform training.

[0020] There are a plurality of the data driving devices, and each data driving device may include a lock detection unit.

[0021] A display device according to a feature of the present invention may include: a data processing device that sends set data in the low-speed communication mode, sends control data and image data in the high-speed communication mode after the low-speed communication mode, and during the operation through the high-speed communication mode, if a lock failure signal is received, the repair start signal and the clock training mode are retransmitted while maintaining the state of the high-speed communication mode; and a data driving device that receives the repair start signal and the clock training mode to perform training.

[0022] Effects of the Invention

[0023] According to the embodiment, the communication state can be quickly restored when a lock failure occurs in the data driving device.

[0024] According to the embodiment, the best communication state restoration method can be applied according to the time point when a lock failure occurs in the data driving device to quickly restore the communication state.

[0025] The effects of the present invention are not limited to the above-mentioned effects, and those of ordinary skill in the technical field to which the present invention pertains can clearly understand other effects not mentioned from the content recorded in the scope of the invention claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a conceptual diagram of a display device according to an embodiment of the present invention.

[0027] Figure 2 It is a structural diagram of a data processing device and a data driving device according to an embodiment of the present invention.

[0028] Figure 3 It is a diagram showing main communication and auxiliary communication between a data processing device and a data driving device according to an embodiment of the present invention.

[0029] Figure 4 It is a diagram showing main communication and auxiliary communication between a data processing device and a data driving device according to another embodiment of the present invention.

[0030] Figure 5 It is a diagram showing a sequence of a transmission signal according to an embodiment of the present invention.

[0031] Figure 6 It is a diagram showing a clock repair sequence according to an embodiment of the present invention.

[0032] Figure 7 It is a diagram showing a first clock repair sequence in a display mode according to an embodiment of the present invention.

[0033] Figure 8 For Figure 7 a variant of

[0034] Figure 9 It is a diagram showing a second clock repair sequence when a lock failure occurs in a setting mode according to an embodiment of the present invention.

[0035] Figure 10 It is a diagram showing a second clock repair sequence when a lock failure occurs in a display mode according to an embodiment of the present invention.

[0036] Figure 11A diagram showing the locking monitoring structure of a data driving device according to an embodiment of the present invention.

[0037] Figure 12 A diagram showing the process of a data driving device with a monitoring function quickly detecting a locking failure.

[0038] Figure 13 A diagram showing the process of a data driving device without a locking monitoring function detecting a locking failure.

[0039] Figure 14 A diagram showing the main communication and auxiliary communication between a data processing device and a data driving device according to another embodiment of the present invention.

[0040] Figure 15 A diagram showing the data flow of a data processing device and a data driving device according to another embodiment of the present invention.

[0041] Figure 16 A diagram showing the first clock repair sequence when a locking failure occurs in the display mode according to another embodiment of the present invention.

[0042] Figure 17 A diagram showing the second clock repair sequence when a locking failure occurs in the setting mode according to another embodiment of the present invention.

[0043] Figure 18 A diagram showing the first clock repair sequence when a locking failure occurs in the display mode according to another embodiment of the present invention.

[0044] Description of reference numerals

[0045] 110: Data processing device 120: Data driving device Detailed description of the preferred embodiments

[0046] The advantages, features, and implementation methods of the present invention can be made clear by referring to the embodiments described in conjunction with the accompanying Figure 1 drawings and described in detail. The present invention is not limited to the embodiments disclosed below and can be implemented in different ways. The multiple embodiments are only used to make the disclosure of the present invention complete so that those of ordinary skill in the technical field to which the present invention pertains can fully understand the scope of the present invention. The present invention should be defined based on the scope of the claims.

[0047] To illustrate the embodiments of the present invention, the shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings are only examples, and the present invention is not limited to the matters shown in the drawings. Throughout the content of this specification, the same reference numerals actually designate the same structural elements. Also, in the process of describing the present invention, when it is determined that a detailed description of related well-known technologies may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

[0048] Part or all of the following embodiments can be combined or combined with each other, and various linkages and drives can be achieved at the technical level. Each embodiment can be implemented independently or together based on the relevant relationship.

[0049] Hereinafter, multiple embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 It is a conceptual diagram of a display device according to an embodiment of the present invention.

[0051] Refer to Figure 1 , the display device 100 may include a data processing device 110, a data driving device 120, a display panel 130, a gate driving device 140, etc.

[0052] The data processing device 110 can receive image data from other devices. Other devices, as devices for generating image data, refer to the host.

[0053] The data processing device 110 processes the image data received from other devices to be suitable for the data driving device 120, and can send the processed image data to the data driving device 120. The data processing device 110 can perform digital gamma correction on the gradient values of each pixel included in the image data, and can also perform correction processing to suit the characteristics of each pixel.

[0054] The data driving device 120 receives image data from the data processing device 110, and can generate a data voltage VD based on the gradient values of the pixels included in the image data and supply the data voltage VD to the pixel P.

[0055] A plurality of pixels P can be provided on the display panel 130. Moreover, each pixel P is connected to the data driving device 120 through a data line DL, and can be connected to the gate driving device 140 through a gate line GL.

[0056] The display panel 130 can be a panel of a flat panel display device such as a liquid crystal display device (LCD, Liquid Crystal Display), a field emission display device (FED, Field Emission Display), a plasma display panel (PDP, Plasma Display Panel), an organic light emitting display device (OLED, Organic Light Emitting Display), a non-organic light emitting display device (Non-Organic Light Emitting Display), etc.

[0057] A transistor may be provided for each pixel P. The gate terminal of the transistor is connected to the gate line GL, and the source terminal may be connected to the data line DL. When the gate driving device 140 supplies a scan signal SCN through the gate line GL, the transistor is turned on, and the data line DL is connected to the pixel P. After the data line DL is connected to the pixel P, the data voltage VD supplied by the data driving device 120 is transmitted to the pixel P.

[0058] To match the timings of the gate driving device 140 and the data driving device 120, the data processing device 110 may send timing control signals to the gate driving device 140 and the data driving device 120.

[0059] The data processing device 110 may send a gate control signal to the gate driving device 140. The gate control signal may include the timing control signal. The gate driving device 140 may generate a scan signal SCN based on the gate control signal and supply the scan signal SCN to the pixel P through the gate line GL.

[0060] Between the data processing device 110 and the data driving device 120, at least two communication lines LN1 and LN2 may be provided. The data processing device 110 may send a first communication signal MDT through the first communication line LN1 and may send and receive a second communication signal LCK through the second communication line LN2.

[0061] The first communication line LN1 may be defined as the main communication line, and the second communication line LN2 may be defined as the auxiliary communication line. Moreover, the first communication signal MDT may be defined as the main communication signal, and the second communication signal LCK may be defined as the auxiliary communication signal.

[0062] The data processing device 110 may send image data and timing control signals to the data driving device 120 through the main communication signal MDT, and the data driving device 120 may send status information to the data processing device 110 through the auxiliary communication signal LCK.

[0063] Figure 2 It is a structural diagram of the data processing device and the data driving device according to an embodiment of the present invention.

[0064] Refer to Figure 2 The data processing device 110 may include a first main communication circuit 410 and a first auxiliary communication circuit 420, and the data driving device 120 may include a second main communication circuit 610 and a second auxiliary communication circuit 620. The first main communication circuit 410 may communicate with the second main communication circuit 610, and the first auxiliary communication circuit 420 may communicate with the second auxiliary communication circuit 620.

[0065] The first main communication circuit 410 can send a main communication signal MDT to the data driving device 120 through the first communication line LN1. The first main communication circuit 410 can send image data and first control data during an active period through the first communication line LN1, and can send second control data during a blanking period.

[0066] The data driving device 120 can drive the pixels of the display panel according to the image data. The first control data can include control values used for line units or pixel units of the display panel, and the second control data can include control values used for a longer period than line units or pixel units or control values used for frame units.

[0067] The first main communication circuit 410 can send setting data through the first communication line LN1 at a first data rate. Subsequently, the first main communication circuit 410 can send image data, first control data, and second control data through the first communication line LN1 at a second data rate higher than the first data rate. The mode of performing communication at the first data rate can be defined as a low-speed communication mode, and the mode of performing communication at the second data rate can be defined as a high-speed communication mode.

[0068] The first main communication circuit 410 receives image data, control data, and setting data, and the received image data, control data, and setting data can be output after being converted by different encoding methods. The first main communication circuit 410 can include: a first data conversion unit 411 for converting image data and control data; and a second data conversion unit 412 for converting setting data. The first data conversion unit 411 and the second data conversion unit 4112 can also be respectively defined as a first data conversion circuit and a second data conversion circuit.

[0069] The first data conversion unit 411 receives image data and control data, and the received image data and control data can be output after being converted by different encoding methods. The first data conversion unit 411 can include a first data packer 413A, a second data packer 413B, a scrambler 414, a first encoder 415A, and a second encoder 415B.

[0070] The first data packer 413A can receive image data from the data processing circuit 10. The data processing circuit 10 can be an external host or an application processor (AP), however, the embodiments of the present invention are not limited thereto. For example, the data processing circuit can also be a part of the data processing device 110 that receives data from a host.

[0071] The first data packer 413A and the second data packer 413B are respectively connected to the data processing circuit 10 through additional lines and can receive data separately. The data processing circuit 10 can transmit data to the first data packer 413A and / or the second data packer 413B according to a predetermined time line. However, the embodiments of the present invention are not limited thereto. The first data packer 413A and the second data packer 413B are connected to the data processing circuit 10 through one line and can receive data according to a predetermined time line.

[0072] The first data packer 413A receives video data in the form of a continuous bit stream from the data processing circuit 10 and generates video packets with a predetermined number of bits. The second data packer 413B can receive first control data and / or second control data from the data processing circuit 10 and generate control packets with a predetermined number of bits. The video packets can be referred to as first data packets, video data packets, video packet data, etc., and the control packets can be referred to as second data packets, control data packets, control packet data, etc.

[0073] The video packets encapsulated by the first data packer 413A and the control packets encapsulated by the second data packer 413B can have different numbers of bits. For example, a video packet is encapsulated as 12 bits, while a control packet can be encapsulated as 3 bits or 4 bits. However, the embodiments of the present invention are not limited thereto. For example, the video packets and the control packets can also be encapsulated with the same number of bits.

[0074] The scrambler 414 can scramble the data of the video packets. Scrambling can prevent the same bits from being continuously configured more than K times (K is a natural number greater than or equal to 2) in the data transmission stream by confusing each bit of the transmitted data. The scrambling is performed according to a predetermined agreement, and the data driving device 120 can restore the stream of scrambled bits to the original state data according to a predetermined protocol.

[0075] The first encoder 415A and the second encoder 415B can encode data according to a predetermined method. The first encoder 415A can encode video data. The first encoder 415A can encode the boundary bits of adjacent data packets to have different polarities. For example, if the last bit of the first data packet and the first bit of the second data packet are both "0", the first bit of the second data packet can be encoded as "1". Therefore, transitions often occur at the boundaries of the data packets, and a predetermined run length can be satisfied. However, the embodiments of the present invention are not limited to the prediction. For example, the first encoder 415A can also be encoded by a line coding method such as 8B10B.

[0076] The second encoder 415B can encode control data. The second encoder 415B can encode the original bits of a data packet into multiple redundant bits with the same polarity and jump bits with different polarities. For example, if the bits of a data packet are "110", the second encoder 415B can encode them with three redundant bits such as "1110 1110 0001" and one jump bit. Therefore, the control data can increase the number of bits through encoding. However, the embodiments of the present invention are not limited thereto. For example, the second encoder 415B can also be encoded in various ways to simplify the sampling of the clock data recovery unit.

[0077] The second data conversion unit 412 may include a third data packer 413C and a third encoder 415C. The third data packer 413C can receive setting data from the data processing circuit 10 and generate a setting packet according to a predetermined number of bits. The setting packet can be referred to as a third data packet, a setting data packet, setting packet data, etc.

[0078] As data sent at a low speed, the setting data may include setting values required by the data driving device 120 before high-speed communication. For example, the setting data may include circuit setting values for the data driving device 120 to perform high-speed communication.

[0079] The third encoder 415C can encode the setting packet encapsulated by the third data packer 413C in a predetermined manner. The third encoder 415C can encode the setting packet through a DC balance code. For example, the third encoder 415C can encode the setting packet through a Manchester code or an 8B10B code. However, the embodiments of the present invention are not limited thereto.

[0080] The first data output circuit 416 receives data packets from the first encoder 415A, the second encoder 415B, and the third encoder 415C respectively, and can transmit data conforming to the pattern to the serializer 417. For example, the first data output circuit 416 can transmit setting data to the serializer 417 in a setting mode, and can transmit image data and control data to the serializer 417 in a display mode.

[0081] The data transmitted in parallel from the first data output circuit 416 can be converted into serial by the serializer 417. The serializer 417 can send the transmitted data converted into serial to the data driving device 120. In this case, a series of data transmitted in serial can form a transmission stream, and can be formed into the form of a main communication signal MDT at the signal level. The first data output circuit 416 and the serializer 417 can constitute a transmission unit. The transmission unit can be referred to as a transmission circuit or transmission logic, etc.

[0082] The main communication signal MDT can be an embedded clock signal. Since the main communication signal embeds a clock, the data driving device 120 needs to perform clock training in the initial interval of communication.

[0083] The data processing device 110 includes a first auxiliary communication circuit 420, and the first auxiliary communication circuit 420 may include a first auxiliary control circuit 421 and a first auxiliary signal processing circuit 422.

[0084] The first auxiliary signal processing circuit 422 may receive an auxiliary communication signal LCK from a second communication line LN2 or transmit the auxiliary communication signal LCK to the second communication line LN2.

[0085] The first auxiliary control circuit 421 confirms the auxiliary communication signal LCK received from the second communication line LN2, and when the auxiliary communication signal LCK indicates an abnormality of the data driving device 120, it may transmit a signal having the same form as the auxiliary communication signal LCK to the second communication line LN2.

[0086] The data driving device 120 may include a second main communication circuit 610 and a second auxiliary communication circuit 620.

[0087] The second main communication circuit 610 may receive a main communication signal MDT through a first communication line LN1. The second main communication circuit 610 may receive image data and first control data during an active period through the first communication line LN1, and may receive second control data during a blanking period. The data driving circuit 20 may drive pixels of a display panel according to the image data and the control data.

[0088] The second main communication circuit 610 may receive setting data through the first communication line LN1 at a first data rate. Moreover, the second main communication circuit 610 may receive image data, first control data, and second control data through the first communication line LN1 at a second data rate higher than the first data rate.

[0089] The second main communication circuit 610 may include a deserializer 617, a second data output circuit 616, a third data conversion unit 611, and a fourth data conversion unit 612. The deserializer 617 and the second data output circuit 616 may constitute a receiving unit or a receiving circuit.

[0090] The deserializer 617 may parallelize the main communication signal MDT serially received through the first communication line LN1 in units of bytes or symbols.

[0091] The deserializer 617 may include an RX receiving unit 617A, a clock data recovery unit 617B, and a parallelization unit 617C. The RX receiving unit 617A may adjust a signal received from the data processing device. The RX receiving unit 617A may transmit a signal through the first communication line LN1 to the clock data recovery unit 617B.

[0092] The signal passing through the first communication line LN1 may be distorted, and high-frequency component attenuation and inter-symbol interference (ISI) may occur in the signal passing through the first communication line LN1. The RX receiving unit 617A can reproduce high-frequency components, thereby reducing inter-symbol interference.

[0093] The clock data recovery unit 617B can perform clock training on a signal including a training pattern. The clock data recovery unit 617B can recover a clock through clock training. The clock data recovery unit 617B recovers data based on the recovered clock, and if the recovered data matches the standard data, the recovered clock can be used for communication with the data processing device.

[0094] The clock data recovery unit 617B generates an output by receiving a clock training pattern signal. When the phase and frequency of the output are the same as the input clock, after converting the lock signal from a low logic level to a high logic level, it can generate a multi-phase internal clock by recovering the clock. The clock data recovery unit 617B can be a phase-locked loop (PLL) method, or it can use a delay-locked loop (DLL) to output a multi-phase internal clock.

[0095] The clock data recovery unit 617B can synchronize the rising edge of the multi-phase internal clock with each bit of the control data packet and the video data packet to recover the bits of the control / video data.

[0096] The parallelization unit 617C can convert serial data into parallel data. The parallelization unit 617C receives the clock recovered by the clock data recovery unit 617B, and can parallelize the data received from the data processing device 110 through the recovered clock.

[0097] The second data output circuit 616 can transmit the parallel data converted by the deserialiser 617 to the third data conversion unit 611 and the fourth data conversion unit 612 according to a mode. For example, in the case of a setting mode, setting data can be transmitted to the third decoder 615C, and in the display mode, video data can be transmitted to the first decoder 615A or control data can be transmitted to the second decoder 615B.

[0098] The third data conversion unit 611 can include a first decoder 615A, a second decoder 615B, a descrambler 614, a first data unpacker 613A, and a second data unpacker 613B.

[0099] The first decoder 615A can decode video data, and the second decoder 615B can decode control data. The first decoder 615A can perform decoding in the reverse order of encoding the video data by the first encoder 415A. The second decoder 615B can perform decoding in the reverse order of encoding the video data by the second encoder 415B. For example, the second decoder 615B can extract the second bit of every 4 bits from each control packet. For example, when the bits of the control packet are [111011100001], only the second bit of every 4 bits can be extracted and decoded as

[110] .

[0100] The descrambler 614 can restore the scrambled data to its original state according to a predetermined protocol. The descrambler 614 can be synchronized with the scrambler 414 and restore the scrambled data.

[0101] The first data unpacker 613A can arrange the video data in pixel units and transmit the video data of each pixel to the data driving circuit 20. The second data unpacker 613B can restore the control data to its original form and transmit it to the data driving circuit 20.

[0102] The fourth data conversion unit 612 can include a third decoder 615C and a third data unpacker 613C. The third decoder 615C can restore the set data encoded by Manchester code. The third data unpacker 613C receives the set data and can transmit the set value included in the set data to the data driving circuit.

[0103] The second auxiliary communication circuit 620 can include a second auxiliary control circuit 621 and a second auxiliary signal processing circuit 622.

[0104] The second auxiliary control circuit 621 can confirm the abnormal state of the main communication signal MDT, the abnormal state of the main communication circuit, and / or the abnormal state of other structures and generate a status signal.

[0105] The second auxiliary signal processing circuit 622 can generate an auxiliary communication signal LCK using the status signal or the feedback signal and send the auxiliary communication signal LCK to the second communication line LN2.

[0106] The data driving device 120 according to an embodiment of the present invention can include a main control circuit 430. The main control circuit 430 can receive a control signal from the data processing circuit 10 to control the first data conversion unit 411, the second data conversion unit 412, the first data output circuit 416, etc. However, the embodiments of the present invention are not limited thereto.

[0107] Figure 3 A diagram showing the main communication and auxiliary communication between the data processing device and the data driving device according to an embodiment of the present invention. Figure 4A diagram showing the main communication and auxiliary communication between a data processing device and a data driving device according to another embodiment of the present invention.

[0108] Referring to Figure 3 , the data driving device may be composed of a plurality of data driving devices 120a, 120b, 120c, and 120d. The plurality of data driving devices 120a, 120b, 120c, and 120d may be source drivers or data driving integrated circuits. The data processing device 110 may communicate with the plurality of data driving devices 120a, 120b, 120c, and 120d through a first communication line LN1. The first communication line LN1 may be connected to each of the data driving devices 120a, 120b, 120c, and 120d in a one-to-one manner.

[0109] Each of the first communication lines LN1 may be composed of m (m is a natural number) electrically insulated lines. Moreover, every two of the m lines form a pair, and each pair may perform low voltage differential (LVDS, Low Voltage Differential Signaling) communication. However, this embodiment is not limited thereto. When the data driving device can receive transmission data through the low voltage differential (LVDS) method, the data processing device may transmit data through the low voltage differential method. When the data driving device can receive data through the current mode logic (CML) method, it may output transmission data through the current mode logic method.

[0110] The data processing device 110 and the plurality of data driving devices 120a, 120b, 120c, and 120d may transmit and receive information through a second communication line LN2.

[0111] Among the plurality of data driving devices 120a, 120b, 120c, and 120d, the second communication line LN2 may be connected in a cascaded form forming a plurality of locked lines. The first data driving device 120a may receive a signal from the data processing device 110 through a first locked line LN2a. The first data driving device 120a and the second driving processing device 120b may be connected through a second locked line LN2b. The second data driving device 120b and the third data driving device 120c may be connected through a third locked line LN2c. The third data driving device 120c and the fourth data driving device 120d may be connected through a fourth locked line LN2d. The fourth data driving device 120d may be connected to the data processing device 110 through a feedback line LN2e.

[0112] The first data driving device 120a to the fourth data driving device 120d can transmit a lock signal by using a lock line. The lock signal is a signal indicating whether clock training is completed. When the lock signal is at a high level (or a low level), it can be regarded that the clock training has been completed. When the lock signal is at a low level (or a high level), it can be regarded that the clock training has not been completed. Lock failure means that the clock training is not completed or the link between the data processing device 110 and the data driving device 120 is broken.

[0113] The fourth data driving device 120d can transmit a lock signal to the data processing device 110. The lock signal can indicate the communication state of at least one of the first data driving device 120a to the fourth data driving device 120d. When lock failure occurs in at least one of the first data driving device 120a to the fourth data driving device 120d, the lock signal can be converted into a value indicating a communication abnormal state.

[0114] Refer to Figure 4 , the data processing device 110 can also be connected to the plurality of data driving devices 120 in a one-to-one manner through a plurality of first communication lines LN1. Moreover, the data processing device 110 and the plurality of data driving devices 120 can be connected through a second communication line LN2 that constitutes a common bus.

[0115] The second communication line LN2 can be a single signal line driven by open-drain. The second communication line LN2 is connected to a pull-up resistor Rqu. One side of the pull-up resistor Rqu is connected to the second communication line LN2, and the other side can provide a driving voltage VCC.

[0116] The second communication line LN2 is connected to the plurality of data driving devices 120a, 120b, 120c, 120d, and a multi-drop architecture can be achieved through this connection.

[0117] The data processing device 110 can send video data with a built-in clock to the data driving device 120 through the first communication line LN1. Moreover, the data processing device 110 and the data driving device 120 can send and receive various information through the second communication line LN2.

[0118] Figure 5 It is a diagram showing the sequence of transmission signals according to an embodiment of the present invention.

[0119] Refer to Figure 5 , the driving voltage VCC initially maintains a low-level voltage, and the waveform can become a high-level voltage at a specified time point. The time point when the driving voltage VCC becomes a high-level voltage can be the driving time point of the display driving device.

[0120] After the driving time point, the data processing device 110 and the data driving device 120 can operate according to the set mode (CFGmode) T101. After completing the operation in the set mode T101, the data processing device 110 and the data driving device 120 can operate in the display mode T102.

[0121] In the set mode T101, the data processing device 110 can send the preamble packet P710 and the set packet P720 through the main communication signal MDT.

[0122] The data processing device 110 can change the voltage of the second communication line from low level to high level while sending the preamble packet P710. According to this voltage change, it can be notified that the data processing device 110 sends the preamble packet P710 to the data driving device 120.

[0123] The data driving device 120 can use the preamble packet P710 composed of the clock training mode to train the low-speed communication clock for receiving the set packet P720. The preamble packet can be defined as the low-speed clock training mode or the first clock training mode.

[0124] The data processing device 110 can send the preamble packet P710 and the set packet P720 at the relatively low first data rate. The low-speed communication clock is the first data rate, and the data driving device 120 can use the preamble packet P710 to train the low-speed communication clock.

[0125] If the low-speed communication clock is trained within the predetermined time TCFG_LOCK, the data driving device 120 can notify the digital processing device 110 of the clock training status through the auxiliary communication signal. For example, if the low-speed communication clock is trained, the data driving device 120 can change the voltage of the auxiliary communication signal from low level to high level. After the data processing device 110 confirms through the auxiliary communication signal that the data driving device 120 has trained the low-speed communication clock, it can send the set packet P720.

[0126] The set packet P720 can be composed of a start bit (CFGS) P721, header data P722, body data P723, and an end bit (CFGE) P724. Data for detecting transmission data errors such as check data can be additionally included as needed.

[0127] In the header data P722, parameter values such as data type, mode, identification identifier (ID) of the receiving end, data length, and the set register address of the receiving end. The body data P723 can include the set information for message sending and receiving.

[0128] The start bit P721 and the end bit P724 can be composed of different data bits. For example, if the start bit P721 is a data bit corresponding to the binary number "0", the end bit P724 can be a data bit corresponding to the binary number "1".

[0129] After the data driving device 120 identifies the end bit P724 through the first communication signal MDT, if the first communication signal MDT is maintained at a level that can be identified by the binary number "0" or "1", it can be determined that the setting mode T101 has ended and the display mode T102 is entered. However, the embodiments of the present invention are not limited thereto. In addition to the level that can be identified by the binary number "0" or "1", even in the case of a high level or a low level, it can be determined that the setting mode has ended.

[0130] After the setting mode T101 ends, the data processing device 110 and the data driving device 120 can enter the display mode T102. The display mode T102 can be composed of a clock training period T103 and a frame period T104. In the clock training period T103, if the high-speed communication clock P730 is trained, the frame period T104 will appear repeatedly thereafter.

[0131] In the clock training period T103, the data processing device 110 can send the clock training mode P730 to the data driving device 120 at the second data rate. The data driving device 120 can train the high-speed communication clock corresponding to the second data rate in the clock training mode P730. Among them, the second data rate can have a frequency higher than the first data rate.

[0132] In the clock training period T103, if the data driving device 120 fails to train the high-speed communication clock, the data driving device 120 can send a clock training failure signal through the auxiliary communication signal. For example, as the voltage of the auxiliary communication signal drops from a high level to a low level, the data driving device 120 can notify the data processing device 110 of the clock training failure.

[0133] When the clock training of the high-speed communication clock fails, the data processing device 110 can additionally send the clock training mode or return to the setting mode T101.

[0134] If the clock training of the high-speed communication clock is completed, the data processing device 110 and the data driving device 120 can enter the frame period T104.

[0135] The frame period T104 can include an active period T106 and a blanking period T105. The active period T106 is the period for sending image data and control data by line unit, and the blanking period T105 can be the period for not sending image data by line unit. The blanking period T105 can be divided into a horizontal blanking period and a vertical blanking period.

[0136] Figure 6 A diagram showing the clock repair sequence of an embodiment of the present invention.

[0137] Referring to Figure 6 , the clock repair modes of the embodiment may include: a first lock repair mode LRC1, when the lock fails in the display mode T102, performing clock training again; and a second lock repair mode LRC2, when the lock fails, returning to the setting mode T101. The first lock repair mode LRC1 performs clock training again while maintaining the state of the current mode. Therefore, it has the advantage of being able to quickly repair the communication state.

[0138] Generally, when performing lock repair, if it always returns to the setting mode T101 and is executed again, the lock repair may consume a large amount of time. The embodiment discloses various lock repair methods. Thus, it is possible to return to the setting mode T101 and select the second lock repair mode LRC2 that retrains through the preamble mode P710 and the first lock repair mode LRC1 that retrains through the clock training mode P730.

[0139] In particular, when the first lock repair mode LRC1 is executed, since it does not return to the starting point of the sequence, not only can the communication device be quickly repaired, but also the time required to normally receive data can be shortened.

[0140] In a display system with a 60Hz resolution, it takes about 16.6 milliseconds (ms) to output 1 frame to the screen. In the second lock repair mode LRC2, adding the low-speed data transmission time, the operation conversion time of the high-speed mode, and the high-speed data transmission time, it takes several milliseconds (ms) to dozens of milliseconds (ms) to normally drive the screen, which may result in the loss of several frames of video data.

[0141] However, the first lock repair mode LRC1 takes hundreds of microseconds (μs), which is faster than the second lock repair mode LRC2. Therefore, it has the advantage of being able to normally drive the screen within multi-line video data.

[0142] According to the embodiment, in the setting mode, if the transmission lock fails, retraining starts from the preamble mode. In the display mode, if the lock fails, the preamble mode of the setting mode or the clock training mode of the display mode can be selectively trained. In the display mode, the first lock repair mode LRC1 and the second lock repair mode LRC2 can be selectively executed according to the error condition.

[0143] For example, in the display mode, when a lock failure occurs in the clock data recovery unit, if symbol errors such as 8B / 10B code errors or data transmission errors caused by watchdog timeouts occur, the first lock repair mode can quickly perform lock repair through clock training. On the contrary, when a cyclic redundancy check (CRC) error or a set CRC error occurs in the frame data or line data, the second lock repair mode can be preferentially executed. If an error message is received, the data processing device 110 can determine the error type and determine whether to preferentially execute the first lock repair mode or the second lock repair mode according to the error type.

[0144] The AUTO Compensation Mode T107 can be a preparation mode executed before entering the display mode. In the auto compensation mode, the display device can optimize the initial conditions of the main link. In the auto compensation mode, the display device can set the internal circuit of the data driver device to operate at a frequency capable of achieving high-speed data communication between the data processing device and the data driver device. Also, the display device can set an equalizer for improving signal quality. The auto compensation mode can also be referred to as the AUTO Training Mode.

[0145] Figure 7 A diagram showing the first clock repair sequence in the display mode according to an embodiment of the present invention. Figure 8 For Figure 7 a modified example of

[0146] Referring to Figure 7 , the data processing device 110 can transmit control data and image data at high speed in the display mode T102. In this case, external noise such as ESD can cause a lock failure. In the case of a lock failure, the data driver device 120 can change the lock signal to a low level.

[0147] If the lock signal changes to a low level, the data processing device 110 stops transmitting image data. After a predetermined time T RE_LAT has elapsed, a repair start signal P740 can be transmitted within a specified time T RE . The repair start signal P740 can be a low-level DC signal or a bit signal equivalent to the binary number "0". However, the embodiments of the present invention are not limited thereto. When a lock failure occurs, the data processing device 110 can also transmit a high-level DC signal.

[0148] After transmitting a bit signal equivalent to the binary number "0", the data processing device 110 can return to the clock training mode and transmit the clock training mode P730 for a predetermined time T DM_CTIn this case, the clock training mode P730 can be the same mode as the high-speed clock training mode transmitted when the first display mode T102 starts to be displayed.

[0149] If a low-level DC signal or a bit equivalent to the binary number "0" is transmitted through the first communication line, the data driving device 120 can perform training using the subsequently transmitted clock training mode P730.

[0150] If the clock training is completed, the data driving device 120 can change the lock signal to a high level. If the lock signal is changed to a high level, the data processing device 110 can re-transmit the video data.

[0151] According to an embodiment, during the operation in the high-speed display mode T102, when a lock failure occurs, the clock training mode P730 can be executed again in the state of maintaining the display mode T102 to restore the communication state without returning to the set mode T101.

[0152] According to an embodiment, after the clock training is completed in the high-speed display mode T102 and the frame interval T104 is entered, when a lock failure occurs, it operates according to the first lock repair mode LRC1. In the case of a lock failure during the clock training, it can enter the set mode T101 again to execute the second lock repair mode LRC2.

[0153] The case where a lock failure occurs in the clock training interval T103 can be regarded as a state where the clock data recovery unit cannot recover the clock. Since it is necessary to change the clock data conversion unit and / or the equalizer option (EQ Option), it is necessary to execute the second lock repair mode LRC2. The equalizer option (EQ Option) is set to a low value for low-speed data, and then, when a lock failure occurs, it can be changed by increasing the option, but it is not limited thereto. For example, the equalizer option can also be changed from a high value to a low value.

[0154] The case where a lock failure occurs in the link training interval T107 can be regarded as a state where the transmission mode cannot be recovered (for example, the RX PHY Margin (receiver physical layer margin) is insufficient), and it is necessary to change the clock data conversion unit and / or the equalizer option (EQ Option). After the data driving device 120 completes the clock training, link training can be additionally performed to detect the symbol boundary and lock the symbol clock. The link training can also be omitted.

[0155] On the contrary, the lock failure that occurs in the frame interval T104 is caused by the loss of the input signal due to the inflow of external noise (signal level that cannot be recovered by RX), and has nothing to do with the working characteristics of the PHY (Physical Layer). Therefore, when a lock failure occurs in the clock training interval T103 or the link training interval T107 after entering the display mode T102, the setting mode T101 is entered again. When a lock failure occurs in the frame interval T104, since there is no need to set the state again, clock training can be performed without changing the mode. However, after operating according to the first lock repair mode LRC1 and transmitting the clock training mode P730, if the lock signal does not change to the high level within a predetermined time, the second lock repair mode LRC2 can be executed.

[0156] According to an embodiment, the first communication line is composed of differential signals, and data sequence differences can be generated according to the presence or absence of AC (alternating current) coupling.

[0157] Refer to Figure 8 , when there is an AC coupling capacitor in the differential signal of the first communication line LN1, if the lock signal changes to the low level due to a lock failure, the data processing device 110 can transmit a switching pattern P741 in which the high level and the low level alternate. This switching pattern can be confirmed without a clock data recovery unit or an equalizer.

[0158] That is, when there is no AC coupling capacitor in the first communication line LN1, the binary number "0" is transmitted through the recovery start signal. When there is an AC coupling capacitor in the first communication line LN1, the switching pattern P741 can be transmitted through the recovery start signal for a predetermined time T RE TIP .

[0159] Figure 9 FIG. for showing the second clock repair sequence when a lock failure occurs in the setting mode according to an embodiment of the present invention. Figure 10 FIG. for showing the second clock repair sequence when a lock failure occurs in the display mode according to an embodiment of the present invention.

[0160] Refer to Figure 9 , if a lock failure occurs in the setting mode T101 or a CRC error is detected during the setting mode T101, the data driving device 120 can change the lock signal to the low level.

[0161] The data processing device 110 recognizes the lock signal as the low level state, and after a predetermined delay time T RE_LAT later, a bit equivalent to the binary number 1 of the high level (DC Level) signal can be output to the first communication line. If the first communication line is in a predetermined time T RE_WAIT (T RE_等待) If it receives a high-level signal or bit 1 within, the data driving device 120 can recognize the restart of the setting mode T101.

[0162] Starting from the setting mode T101 again, the data processing device 110 can transmit the preamble pattern P710 to the data driving device 120. The data driving device can train the preamble pattern P710. Within a specified time T CFG_RELOCK (T CFG_重新锁定 ) If the training is completed within, the data driving device can change the lock signal to high level.

[0163] Refer to Figure 10 , when a lock failure occurs in the display mode T102, the data processing device 110 can change the lock signal to low level.

[0164] After confirming that the lock signal is low level and after a predetermined delay time T RE_LAT , the data processing device 110 can transmit a high-level (DC Level) signal or a bit equivalent to binary number 1 to the first communication line LN1. If the first communication line LN1 receives a high-level signal within a predetermined time T RE_等待 within, the data driving device 120 can recognize the restart of the setting mode T101.

[0165] That is, if a low-level signal (or a bit equivalent to binary number 0) is received through the first communication line LN1 within the specified time, the data driving device 120 operates according to the first lock repair mode LRC1. If a high-level signal (or a bit equivalent to binary number 1) is received within the specified time, it can be determined that it operates according to the second lock repair mode LRC2.

[0166] Starting from the setting mode T101 again, the data processing device 110 can transmit the preamble pattern P710 to the data driving device 120. The data driving device can train the preamble pattern P710. If the clock is restored within a predetermined time T CFG_重新锁定 within, the data driving device can change the lock signal to high level.

[0167] Figure 11 It is a diagram showing the lock monitoring structure of the data driving device according to an embodiment of the present invention. Figure 12 It is a diagram showing the process of a data driving device with a monitoring function quickly detecting a lock failure. Figure 13 It is a diagram showing the process of a data driving device without a lock monitoring function detecting a lock failure.

[0168] Refer to Figure 11, the lock monitoring technology in the Multi-drop Topology can be applied, enabling status synchronization based on the lock signals between multiple data driving devices and rapid identification of lock failures.

[0169] In the Multi-drop Topology, multiple data driving devices 120 control the lock line through an Open-drain LOCK circuit. Meanwhile, the status of the external lock line can be confirmed through lock monitoring. The data driving device 120 can detect the level of the second communication line LN2 through the status receiving unit 129a and change the level of the second communication line LN2 through the status sending unit 129b.

[0170] After confirming that its own lock signal is at a high level, the data driving device 120 performs lock monitoring. In this case, if the lock signal is in a low-level state, it can be recognized as a lock failure. Subsequently, the data driving device 120 that determines a lock failure can convert to a lock repair sequence.

[0171] In the absence of a lock monitoring function, additional mode receiving and identification steps are required, and a specified time is needed to determine whether there is a lock abnormality. However, according to the embodiment, this problem can be solved when each data driving device 120 has a lock monitoring function.

[0172] Refer to Figure 12 , in the case of applying the Multi-drop Topology, the present invention can accurately and quickly perform lock repair work through the lock monitoring technology.

[0173] According to the lock monitoring technology of the embodiment, when one of the second communication line and its own lock signal is at a low level, the data driving device 120 can determine a lock failure without transmitting a specific mode. Therefore, it has the advantage that the timing for identifying lock failures and the timing for performing lock repair between the data driving devices 120 are relatively fast.

[0174] Moreover, due to the characteristics of the Multi-drop Topology, the data processing device 110 can also quickly identify lock failures, so it has the advantage of being able to quickly restore the communication state.

[0175] According to an embodiment, among a plurality of data driving devices 120, if a locking failure occurs in the first data driving device 120a, the second data driving device 120b and the third data driving device 120c can recognize the locking failure in real time and can convert their own locking signals to a low level. When the locking failure of the first data driving device 120a occurs in the display mode T102 and the first locking repair mode is executed, the second data driving device 120b and the third data driving device 120c can also execute the first locking repair mode.

[0176] When the locking failure of the first data driving device 120a occurs in the setting mode T101 and the second locking repair mode is executed, the second data driving device 120b and the third data driving device 120c can also execute the second locking repair mode.

[0177] According to an embodiment, when a locking failure occurs in any one of the data driving devices 120 and the first locking repair mode or the second locking repair mode is executed, the remaining data driving devices 120 can also execute the same locking repair mode.

[0178] Refer to Figure 13 , if the data driving device 120 does not have a locking monitoring structure, the data processing device 110 recognizes the locking failure and synchronizes the data driving device 120 by transmitting a specific mode training clock. However, this method has a problem that the synchronization may be slow due to different timings of recognizing the locking failure among the data driving devices 120. Therefore, the locking repair of some of the data driving devices 120 may be slowed down.

[0179] Figure 14 FIG. is a diagram of a communication line between a data processing device and a data driving device according to another embodiment of the present invention.

[0180] Refer to Figure 14 , the communication line between the data processing device 110 and the data driving device 120 may include a first communication line LN1, a second communication line LN2, and a third communication line LN3. The third communication line LN3 can be a hot plug detect (HPD) line. The hot plug detect line can be a signal line for the data processing device 110 to detect the interface connection with the data driving device 120. For example, if the data processing device 110 and the data driving device 120 are connected through the hot plug detect line, the data processing device 110 detects the interface connection with the data driving device 120 and can prepare the communication protocol with the data driving device 120.

[0181] The second communication line LN2 can transmit and receive various setting information required for communication between the data processing device 110 and the data driving device 120. Also, based on the information detected through the second communication line LN2, the data driving device 120 can determine whether it is in a state capable of communication.

[0182] Figure 15 FIG. showing the data flow of the data processing device and the data driving device according to another embodiment of the present invention.

[0183] Figure 16 FIG. showing the first clock repair sequence in the case of a lock failure in the setting mode according to another embodiment of the present invention.

[0184] Refer to Figure 15 , if the power supplies of the data processing device 110 and the data driving device 120 are turned on, the data driving device 120 can change the hot plug detection signal to a high level and transmit it through the third communication line LN3 (step S110). Then, the data processing device 110 transmits the preamble pattern P710 (step S120). If the training of the preamble pattern P710 is completed, the data driving device 120 can change the second communication line to a high level (step S130).

[0185] If the second communication line is changed to a high level, the data processing device 110 transmits a setting packet (step S140), and the data driving device 120 can complete the setting based on the setting packet.

[0186] Subsequently, in the display mode T102, the data processing device 110 can transmit the clock training pattern P730 (step S150). If the training of the clock training pattern P730 is completed, the data processing device 110 can maintain the lock signal at a high level (step S160).

[0187] Then, the data processing device 110 can transmit the link training pattern (step S170). If the training of the link training pattern is completed, the data driving device 120 can maintain the lock signal at a high level.

[0188] Refer to Figure 16 , control data and image data can be transmitted in the high-speed display mode T102. In this case, external noise such as ESD can cause a lock failure. In the case of a lock failure, the data driving device 120 can maintain the hot plug detection signal at a high level and change the lock signal to a low level.

[0189] As the hot-plug detection signal is detected to be maintained at a high level and the lock signal is changed to a low level, after transmitting the ESD-based error data IVD, the data processing device 110 may transmit the clock training mode P730. In this case, the clock training mode P730 may be the same mode as the high-speed clock training mode P730 transmitted when the display mode T102 was first started.

[0190] The data driving device 120 may perform training using the clock training mode P730. If the clock training is completed within a predetermined period T CER_LOCK (T CER_锁定 ), the data driving device 120 may change the lock signal to a high level. If the lock signal is changed to a high level, the data processing device 110 may re-transmit the image data.

[0191] Figure 17 FIG. showing the second clock repair sequence when locking fails in the setting mode according to another embodiment of the present invention. Figure 18 FIG. showing the first clock repair sequence when locking fails in the display mode according to another embodiment of the present invention.

[0192] Referring to Figure 17 , in the setting mode T101, if the data driving device 120 detects a cyclic redundancy check (CRC) error or identifies a locking failure, the data driving device 120 may change the hot-plug detection signal and the lock signal to a low level (t1). As the hot-plug detection signal is changed to a low level, after a predetermined delay time T HPD_RELOCK (T HPD_重新锁定 ), the data driving device 120 may change it back to a high level.

[0193] The data processing device 110 identifies the hot-plug detection signal and the lock signal as being in a low level state, and after a predetermined delay time, may transmit the preamble mode P710 to the data driving device 120. The data driving device may perform training work using the preamble mode P710.

[0194] If the training is completed within a predetermined time T CFG_重新锁定 , the data driving device may change the lock signal to a high level (t2).

[0195] Referring to Figure 18 , in the display mode T102, when a locking failure is caused by external noise or various reasons, the data processing device 110 may change the hot-plug detection signal and the lock signal to a low level (t3).

[0196] According to an embodiment, in display mode T102, if symbol errors such as 8B / 10B code errors occur, or data transmission errors due to watchdog timeouts occur, as Figure 16 shown, the first lock repair mode can quickly perform lock repair through clock training. Conversely, when cyclic redundancy check (CRC) errors or set CRC errors occur in frame data or line data, as Figure 18 shown, the second lock repair mode can be preferentially executed.

[0197] After recognizing the hot plug detection signal and the lock signal as low level states and outputting a high level signal within a specified period, the data processing device 110 can start setting mode T101 again.

[0198] After a delay time T HPD_重新锁定 has passed, the data driving device 120 can change the hot plug detection signal from low level to high level. The data processing device 110 can recognize that the level of the hot plug detection signal has changed and perform the operation again. The data processing device 110 re-transmits the preamble pattern P710, and the data driving device 120 can train the preamble pattern P710.

[0199] If the training of the preamble pattern P710 is completed, the data driving device 120 can change the lock signal to high level. Then, the AUTO Compensation Mode T107 can be selectively executed. The AUTO Compensation Mode is executed at the initial stage after power supply and is not executed in the subsequent lock repair mode sequence.

[0200] The advantage of the embodiment is that, in abnormal working conditions, when lock repair work needs to be performed, it is possible to choose whether to re-train the preamble pattern P710 in setting mode T101 or re-train the clock training mode P730 in display mode T102. And, the existing hot plug detection line and lock line can be used for selection without additional lines.

[0201] In the above specification, the content recorded in the technical problem, technical solution, and invention effect does not specify the basic features of the claims. Therefore, the protection scope of the claims is not limited to the matters recorded in the specification content.

[0202] As mentioned above, although the embodiments of the present invention have been further described in detail with reference to the accompanying drawings, the present invention is not limited to such embodiments and can be variously modified without departing from the technical idea of the present invention. Therefore, the embodiments disclosed in the present invention are only for illustration and do not limit the technical idea of the present invention. The scope of the technical idea of the present invention is not limited to such embodiments. Therefore, the embodiments described above are only examples in all aspects and should not be construed as having a limiting meaning.

Claims

1. A data processing device, characterized in that, it sends set data in a low-speed communication mode, after the low-speed communication mode, it changes the step to a high-speed communication mode and sends control data and image data, during the process of working through the high-speed communication mode, if a lock failure signal is received, it re-transmits the clock training mode while maintaining the state of the high-speed communication mode.

2. The data processing device according to claim 1, characterized in that, after the low-speed communication mode, in order to enter the high-speed communication mode, it transmits the clock training mode, after receiving a lock signal indicating that the training of the clock training mode has been completed, in the step of transmitting image data, if a lock failure signal is received, it re-transmits the clock training mode while maintaining the state of the high-speed communication mode.

3. The data processing device according to claim 2, wherein If a lock signal related to the re-transmitted clock training mode is not received within a predetermined time, the low-speed communication mode is executed again.

4. The data processing device according to claim 3, characterized in that, In the case of executing the low-speed communication mode again, it re-transmits the preamble mode.

5. The data processing device according to claim 1, characterized in that, before re-transmitting the clock training mode, it transmits a repair start signal, the repair start signal is a signal formed by repeating high level and low level.

6. The data processing device according to claim 1, characterized in that, before re-transmitting the clock training mode, it transmits a repair start signal, the repair start signal is a DC signal of high level or low level.

7. The data processing device according to claim 1, characterized in that, if power is supplied, it activates the low-speed communication mode to send the preamble mode and then sends the set data, if a lock signal related to the preamble mode is received, it sends the set data, if a lock signal is continuously received, it activates the high-speed communication mode.

8. The data processing device according to claim 1, wherein, if a lock signal related to the clock training mode is received, it transmits the link training mode.

9. A data driving device, characterized in that, it receives set data in a low-speed communication mode, after the low-speed communication mode, it receives control data and image data in a high-speed communication mode, during the process of working through the high-speed communication mode, if a lock failure is detected, it sends a lock failure signal to the data processing device, and receives a repair start signal and a clock training mode to perform training while maintaining the state of the high-speed communication mode.

10. The data driving device according to claim 9, characterized in that, There are multiple data driving devices, and each data driving device includes a lock detection unit.

11. A display device, characterized in that, It includes: a data processing device that sends set data in a low-speed communication mode, after the low-speed communication mode, sends control data and image data in a high-speed communication mode, and during the process of working through the high-speed communication mode, if a lock failure signal is received, it re-transmits a repair start signal and a clock training mode while maintaining the state of the high-speed communication mode; and a data driving device that receives the repair start signal and the clock training mode to perform training.

12. The display device according to claim 11, characterized in that, After the low-speed communication mode, the data processing device transmits a clock training mode to enter the high-speed communication mode. After receiving a lock signal indicating that the training of the clock training mode has been completed, in the step of transmitting image data, if a lock failure signal is received, the clock training mode is re-transmitted while maintaining the state of the high-speed communication mode.

13. The display device according to claim 12, wherein: Comprising: A first communication line for transmitting the image data; A second communication line for transmitting and receiving the lock signal; and A third communication line for detecting the interface connection between the data processing device and the data driving device. During operation in the high-speed communication mode, if a lock failure signal is received, the data driving device changes the signal level of at least one of the third communication line and the second communication line.

14. The display device according to claim 13, wherein During operation in the high-speed communication mode, if a lock failure signal is received, the data driving device maintains the signal level of the third communication line at a high level and changes the signal level of the second communication line to a low level.

15. The display device according to claim 13, characterized in that, During operation in the high-speed communication mode, if a lock failure signal is received, the data driving device changes the signal levels of the third communication line and the second communication line to low levels.

16. The display device according to claim 13, wherein During operation in the low-speed communication mode, if a lock failure signal is received, the data driving device changes the signal levels of the third communication line and the second communication line to low levels.

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