Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display, in the display panel, a first pixel circuit is electrically connected with a first light-emitting element, a second pixel circuit is electrically connected with a second light-emitting element, and a third pixel circuit is electrically connected with a third light-emitting element. The first reference voltage line provides a first reference voltage signal for the first light-emitting element and the third light-emitting element through the first pixel circuit and the third pixel circuit, and the second reference voltage line provides a second reference voltage signal for the second light-emitting element through the second pixel circuit. The voltage values of the first reference voltage signal and the second reference voltage signal are different. The first reference voltage line comprises a first sub-reference voltage line and a second sub-reference voltage line which are electrically connected, and the second reference voltage line comprises a third sub-reference voltage line and a fourth sub-reference voltage line which are electrically connected. Therefore, the possible problems of heating color cast and poor low-gray-scale visual effect of the display panel can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablet computers, laptop computers, and smart wearable devices, etc., are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable important tool for people today.

[0003] Organic light-emitting diode display technology has been widely used in the field of consumer electronics due to its advantages such as self-luminescence, high contrast ratio, wide color gamut, thin and flexible. However, organic light-emitting diode displays still face some challenges in actual use, especially the display quality still needs to be improved. Summary of the Invention

[0004] To solve the above technical problems, the present disclosure provides a display panel and a display device, aiming to improve the problems of heating color shift and poor low gray-level visual effect that may occur in the display panel, thereby improving the display quality.

[0005] In a first aspect, the present disclosure provides a display panel, including a light-emitting element and a pixel circuit connected to the light-emitting element. The light-emitting element includes a first light-emitting element, a second light-emitting element, and a third light-emitting element, and the first light-emitting element, the second light-emitting element, and the third light-emitting element have different light-emitting colors; the pixel circuit includes a first pixel circuit, a second pixel circuit, and a third pixel circuit. The first pixel circuit is electrically connected to the first light-emitting element, the second pixel circuit is electrically connected to the second light-emitting element, and the third pixel circuit is electrically connected to the third light-emitting element;

[0006] The display panel further includes a first reference voltage line and a second reference voltage line. The first reference voltage line is configured to provide a first reference voltage signal to the first light-emitting element and the third light-emitting element respectively through the first pixel circuit and the third pixel circuit, and the second reference voltage line is configured to provide a second reference voltage signal to the second light-emitting element through the second pixel circuit; the voltage value of the first reference voltage signal is different from the voltage value of the second reference voltage signal;

[0007] The first reference voltage line includes a first sub-reference voltage line extending in a first direction and a second sub-reference voltage line extending in a second direction, and the first sub-reference voltage line and the second sub-reference voltage line are electrically connected;

[0008] The second reference voltage line includes a third sub-reference voltage line extending in a first direction and a fourth sub-reference voltage line extending in a second direction, and the third sub-reference voltage line and the fourth sub-reference voltage line are electrically connected; the first direction and the second direction intersect.

[0009] In a second aspect, based on the same inventive concept, the present disclosure also provides a display device, including the display panel provided in the first aspect of the present disclosure.

[0010] The technical solutions provided by the embodiments of the present disclosure have the following advantages compared with the prior art:

[0011] In the display panel and the display device provided by the embodiments of the present disclosure, considering that light-emitting elements of at least two different light-emitting colors have different sensitivities to temperature due to different material characteristics, a first reference voltage line and a second reference voltage line are respectively introduced. The first reference voltage signal and the second reference voltage signal can be respectively provided through the first reference voltage line and the second reference voltage line to reset the anodes of different light-emitting elements. In this way, the initial states of different light-emitting elements before light emission can be controlled more precisely. For example, the reference voltage corresponding to the light-emitting element that is more sensitive to temperature can be adjusted to ensure a more stable starting point at different temperatures, thereby reducing the brightness drift caused by temperature changes, ultimately reducing the offset of white balance, and improving the problem of heating color cast. Moreover, by differentiating the design of the first reference voltage signal and the second reference voltage signal, more appropriate initial conditions can be provided specifically for light-emitting elements with large differences in material characteristics during the anode reset stage, so that the subsequent driving voltage can more accurately control the brightness output of each color sub-pixel, thereby better maintaining the target color ratio and reducing the color deviation caused by temperature.

[0012] In addition, considering that during low gray-scale display, the driving voltage applied to the light-emitting element is very close to the turn-on voltage of the light-emitting element, and a slight voltage difference may cause obvious brightness changes or unevenness. The present disclosure provides optimized reference voltage signals (such as more accurate anode reset voltages) for different light-emitting elements through the first reference voltage line and the second reference voltage line, which can ensure that different light-emitting elements have predictable starting states during low gray-scale, can more precisely control the output of different light-emitting elements at low brightness, ensure that the light-emitting elements can accurately respond to slight driving voltage changes, thereby facilitating the reduction of the problem of low gray-scale color cast, precisely controlling the starting states of different light-emitting elements at low brightness, and at the same time avoiding the problem of light stealing caused by signal interference between different light-emitting elements during monochromatic picture display of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure.

[0014] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0015] Figure 1 Shown is a planar structure diagram of a display panel provided by an embodiment of the present disclosure;

[0016] Figure 2 Shown is a connection schematic diagram of a light-emitting element, a pixel circuit, a first reference voltage line, and a second reference voltage line;

[0017] Figure 3 Shown is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0018] Figure 4 Shown is another circuit schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0019] Figure 5 Shown is Figure 3 a timing diagram of the pixel circuit in

[0020] Figure 6 Shown is an arrangement schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0021] Figure 7 Shown is an arrangement schematic diagram of light-emitting elements in a display panel;

[0022] Figure 8 Shown is another connection schematic diagram of a light-emitting element, a pixel circuit, a first reference voltage line, and a second reference voltage line;

[0023] Figure 9 Shown is a film layer schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0024] Figure 10 Shown is a layout schematic diagram of a circuit column group where a second sub-reference voltage line and a fourth sub-reference voltage line are located;

[0025] Figure 11 Shown is another layout schematic diagram of a circuit column group where a second sub-reference voltage line and a fourth sub-reference voltage line are located;

[0026] Figure 12 Shown is another layout schematic diagram of a circuit column group where a second sub-reference voltage line and a fourth sub-reference voltage line are located;

[0027] Figure 13 Shown is another layout schematic diagram of the circuit column group where the second sub-reference voltage line and the fourth sub-reference voltage line are located;

[0028] Figure 14 Shown is another layout schematic diagram of the circuit column group where the second sub-reference voltage line and the fourth sub-reference voltage line are located;

[0029] Figure 15 Shown is another layout schematic diagram of the circuit column group where the second sub-reference voltage line and the fourth sub-reference voltage line are located;

[0030] Figure 16 Shown is another layout schematic diagram of the circuit column group where the second sub-reference voltage line and the fourth sub-reference voltage line are located;

[0031] Figure 17 Shown is a wiring schematic diagram of the first reference voltage line and the second reference voltage line in the display panel;

[0032] Figure 18 Shown is another wiring schematic diagram of the first reference voltage line and the second reference voltage line in the display panel;

[0033] Figure 19 Shown is an arrangement schematic diagram of the second sub-reference voltage line, the fourth sub-reference voltage line, the third reference voltage line, and the fourth reference voltage line;

[0034] Figure 20 Shown is a connection schematic diagram of the reference voltage line in the display panel and the signal line in the border area;

[0035] Figure 21 Shown is a structural schematic diagram of the display device provided by the embodiment of the present disclosure. Detailed implementation manners

[0036] In order to be able to more clearly understand the above-mentioned objects, features, and advantages of the present disclosure, the solution of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0037] Many specific details are set forth in the following description in order to fully understand the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0038] Organic Light-Emitting Diode (OLED) display technology has been widely used in the consumer electronics field due to its advantages such as self-luminescence, high contrast ratio, wide color gamut, thinness, flexibility, etc. However, OLED displays still face some challenges in actual use, especially in terms of the stability of display quality. Two significant problems are heating-induced color shift and poor visual effects in low gray levels. Heating-induced color shift refers to the phenomenon that when the OLED display screen works for a long time or the ambient temperature changes, due to the difference in temperature sensitivity of different color sub-pixels (red, green, blue), the white balance of the screen drifts, resulting in color deviation and affecting the viewing experience. Poor visual effects in low gray levels are manifested as problems such as uneven brightness or even flickering on the screen when displaying low-brightness images, which is related to the characteristics of the driving circuit itself (such as threshold voltage drift).

[0039] Based on this, the present disclosure provides a display panel and a display device, aiming to improve the problems of heating-induced color shift and poor visual effects in low gray levels that may occur in the display panel, thereby enhancing the display quality.

[0040] Figure 1 Shown is a planar structure diagram of a display panel provided by an embodiment of the present disclosure. Figure 2 Shown is a schematic connection diagram of a light-emitting element, a pixel circuit, a first reference voltage line, and a second reference voltage line. It should be noted that Figure 1 only a display panel with a rectangular structure is taken as an example for illustration, and the actual shape of the display panel is not limited. In some other embodiments of the present disclosure, the display panel may also be embodied in other feasible shapes such as circular, rounded rectangular, etc. Optionally, the display panel provided in this embodiment may be an organic light-emitting display panel, and the corresponding light-emitting element is an organic light-emitting element. Of course, in some other embodiments of the present disclosure, the display panel may also adopt a display panel using inorganic light-emitting diode display technology, such as a Micro LED display panel, or a Mini LED display panel, etc., and the present disclosure does not limit this.

[0041] Figure 1 and Figure 2 only a block diagram is used to represent the pixel circuit. In specific implementation, the structure of the pixel circuit may include a circuit structure of multiple electrically connected transistors and capacitors. Figure 3 Shown is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure, with Figure 3For example, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. Among them, the third transistor T3 is a driving transistor for providing a driving current to the light-emitting element D0. The gate, the first pole, and the second pole of the driving transistor are respectively connected to the first node N1, the third node N3, and the second node N2. The first pole and the second pole of the fifth transistor T5 are respectively connected to the gate reset signal terminal Vref1 and the first node N1, and the gate is connected to the first control signal terminal S1N for receiving a reset control signal. The fifth transistor T5 is used to provide the gate reset signal Vref1 to the first node N1. The first pole and the second pole of the second transistor T2 are respectively connected to the data voltage signal terminal Vdata and the second node N2, and the gate receives the control signal SP. The second transistor T2 is used to transmit the data voltage signal Vdata to the second node N2. It should be noted that in the embodiments of the present disclosure, the signal terminals and the signals transmitted by the signal terminals are represented by the same reference numerals. The first pole and the second pole of the fourth transistor T4 are respectively connected to the third node N3 and the first node N1, and the gate is connected to the second control signal terminal S2N for receiving the control signal S2N. The fourth transistor T4 is used to perform threshold compensation on the third transistor T3. The first pole and the second pole of the seventh transistor T7 are respectively connected to the anode reset signal terminal Vref2 and the first pole of the light-emitting element D0, and the gate is connected to the control signal terminal SPX. The seventh transistor T7 is used to reset the first pole (e.g., the anode) of the light-emitting element D0. The first pole and the second pole of the eighth transistor T8 are respectively connected to the bias adjustment signal terminal DVH and the second node N2, and the gate is connected to the control signal terminal SPX. The first pole and the second pole of the first transistor T1 are respectively connected to the first power supply signal terminal PVDD and the second node N2, and the gate is connected to the light emission control signal terminal Emit. The first pole and the second pole of the sixth transistor T6 are respectively connected to the third node N3 and the first pole of the light-emitting element D0, and the gate is connected to the light emission control signal terminal Emit for transmitting the driving current to the light-emitting element D0. The second pole of the light-emitting element D0 receives the second power supply signal PVEE. It should be noted that in the embodiments of the present disclosure, only the case where the gates of the seventh transistor T7 and the eighth transistor T8 are both connected to the control signal terminal SPX is taken as an example for illustration, but the present disclosure is not limited thereto.

[0042] It should also be noted that Figure 3 the pixel circuit in Figure 3In the embodiment, the fourth transistor T4 and the fifth transistor T5 connected to the first node N1 are N-type transistors. The N-type transistor can be an oxide transistor. The signals for controlling the fourth transistor T4 and the fifth transistor T5 to conduct are high-potential signals, and the other transistors are all P-type transistors. In this embodiment, when the fourth transistor T4 and the fifth transistor T5 are N-type transistors and the N-type transistor is an oxide transistor, it is beneficial to reduce the leakage current of the fourth transistor T4 and the fifth transistor T5 to the first node N1, thereby facilitating the maintenance of the stability of the potential of the gate of the driving transistor connected to the first node N1. In some other embodiments, the pixel circuit may also be embodied in other structures. For example, please refer to Figure 4 , Figure 4 shows another circuit schematic diagram of the pixel circuit provided by the embodiment of the present disclosure. The connection relationship and working principle are the same as Figure 3 , and the difference from Figure 3 is only that the fourth transistor T4 and the fifth transistor T5 are P-type transistors, and the P-type transistor conducts under the control of a low-potential signal. Figure 4 When all the transistors in the embodiment shown in

[0043] are P-type transistors, it is beneficial to simplify the manufacturing process of the pixel circuit. Figure 5 below will be combined with Figure 3 to illustrate the working principle of Figure 4 . The working principle of the pixel circuit in Figure 5 shows a timing diagram of the pixel circuit in Figure 3 . Please combine Figure 3 and Figure 5 . The specific working process of the pixel circuit P includes an initialization stage t1, a data writing and threshold compensation stage t2, a bias stage t3, and a light-emitting stage t4.

[0044] In the initialization stage t1, the high-potential signal of the first control signal S1N controls the fifth transistor T5 to conduct, and transmits the gate reset signal Vref1 to the control end of the third transistor T3 for initialization, so as to eliminate the residual charge of the previous frame of the picture and improve the display effect of the display panel. In the present disclosure, in a partial time period of the initialization stage t1, the effective levels of the first control signal S1N and the second control signal S2N have an overlapping time, which is beneficial to improving the hysteresis problem of the driving transistor during the initialization stage.

[0045] In the data writing and threshold compensation stage t2, the fifth transistor T5 is turned off, the control signal SP controls the second transistor T2 to be turned on, the second control signal S2N controls the fourth transistor T4 to be turned on, the data voltage signal Vdata is written into the third transistor T3 through the second transistor T2, and the fourth transistor T4 is connected between the gate and the first pole of the third transistor T3, and can capture the threshold voltage of the third transistor T3 to the gate of the third transistor T3, realizing the compensation of the threshold voltage and self-compensating the deviation of the threshold voltage of the driving transistor.

[0046] In the bias stage t3, the control signal SPX controls the eighth transistor T8 to be turned on, and the bias adjustment signal DVH is transmitted to the second pole (i.e., the second node N2) of the driving transistor through the eighth transistor T8 to adjust the bias state of the driving transistor. At the same time, the control signal SPX controls the seventh transistor T7 to be turned on, and the anode reset signal Vref2 is transmitted to the anode of the light-emitting element D0 through the seventh transistor T7 to reset the light-emitting element D0.

[0047] In the light-emitting stage t4, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are all turned off, the first transistor T1, the third transistor T3, and the sixth transistor T6 are all turned on, and the driving current is transmitted to the first pole of the light-emitting element D0, and the light-emitting element D0 emits light. It should be noted that Figure 5 the timing diagram is only for illustration and is not limited thereto. In some other embodiments of the present disclosure, pixel circuits with different structures may correspond to different timings.

[0048] In this embodiment, the stage of resetting the anode of the light-emitting element D0 is carried out simultaneously with the bias stage, but it is not limited thereto. In some other embodiments of the present disclosure, the stage of resetting the anode of the light-emitting element D0 may also be carried out in the initialization stage.

[0049] In practical applications, when resetting the anode of the light-emitting element D0, the anode reset signal Vref2 can be transmitted to the anode of the light-emitting element D0 through the seventh transistor T7, so as to reduce the anode voltage to a low potential or zero potential to eliminate the residual charge or leakage current that may cause the light-emitting element to emit light accidentally. In addition, considering that there may be slight differences in the threshold voltages of the light-emitting elements with different emission colors on the display panel and the driving transistors, resetting the anode of the light-emitting element to a known state before each frame helps to minimize the impact of the change in the threshold voltage on the initial state of the pixel, so as to achieve more uniform brightness and color on the entire screen, especially at low gray levels.

[0050] Please refer to Figure 1 and Figure 2, embodiments of the present disclosure provide a display panel, including a light-emitting element D0 and a pixel circuit P connected to the light-emitting element D0. For the specific structure of the pixel circuit P, reference can be made to Figure 3 and Figure 4 , the light-emitting element D0 includes a first light-emitting element D01, a second light-emitting element D02, and a third light-emitting element D03, and the first light-emitting element D01, the second light-emitting element D02, and the third light-emitting element D03 have different light-emitting colors; the pixel circuit P includes a first pixel circuit P1, a second pixel circuit P2, and a third pixel circuit P3. The first pixel circuit P1 is electrically connected to the first light-emitting element D01, the second pixel circuit P2 is electrically connected to the second light-emitting element D02, and the third pixel circuit P3 is electrically connected to the third light-emitting element D03.

[0051] The display panel further includes a first reference voltage line 10 and a second reference voltage line 20. The first reference voltage line 10 is configured to provide a first reference voltage signal to the first light-emitting element D01 and the third light-emitting element D03 respectively through the first pixel circuit P1 and the third pixel circuit P3, and the second reference voltage line 20 is configured to provide a second reference voltage signal to the second light-emitting element D02 through the second pixel circuit P2; the voltage value of the first reference voltage signal is different from the voltage value of the second reference voltage signal. It should be noted that the first reference voltage signal and the second reference voltage signal are anode reset signals transmitted to the corresponding light-emitting elements.

[0052] The first reference voltage line 10 includes a first sub-reference voltage line Vref2-RG1 extending along a first direction D1 and a second sub-reference voltage line Vref2-RG2 extending along a second direction D2, and the first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2 are electrically connected. The second reference voltage line 20 includes a third sub-reference voltage line Vref2-B1 extending along the first direction D1 and a fourth sub-reference voltage line Vref2-B2 extending along the second direction D2, and the third sub-reference voltage line Vref2-B1 and the fourth sub-reference voltage line Vref2-B2 are electrically connected; the first direction D1 and the second direction D2 intersect.

[0053] The first reference voltage line 10 mentioned in the embodiments of the present disclosure can be configured to provide a first reference voltage signal to the anodes of the first light-emitting element D01 and the third light-emitting element D03 to realize the reset of the anodes of the first light-emitting element D01 and the third light-emitting element D03; the second reference voltage line 20 can be configured to provide a second reference voltage signal to the anode of the second light-emitting element D02 to realize the reset of the anode of the second light-emitting element D02.

[0054] In the display panel provided by the embodiments of the present disclosure, considering that light-emitting elements of at least two different light-emitting colors have different sensitivities to temperature due to different material characteristics, the first reference voltage line 10 and the second reference voltage line 20 are respectively introduced. Independent first reference voltage signals and second reference voltage signals can be provided through the first reference voltage line 10 and the second reference voltage line 20 to reset the anodes of different light-emitting elements. In this way, the initial states of different light-emitting elements before light emission can be controlled more precisely. For example, the reference voltage corresponding to the light-emitting element that is more sensitive to temperature can be adjusted to ensure a more stable starting point at different temperatures, thereby reducing the brightness drift caused by temperature changes, ultimately reducing the offset of white balance, and improving the problem of heating color cast. Moreover, by differentiating the design of the first reference voltage signal and the second reference voltage signal, more suitable initial conditions can be provided specifically for light-emitting elements with large material property differences during the anode reset stage, enabling the subsequent driving voltage to more accurately control the brightness output of each color sub-pixel, thereby better maintaining the target color ratio and reducing the color deviation caused by temperature.

[0055] In addition, considering that during low gray-scale display, the driving voltage applied to the light-emitting element is very close to the turn-on voltage of the light-emitting element, and a slight voltage difference may cause obvious brightness changes or unevenness. The present disclosure provides optimized reference voltage signals (such as more accurate reset voltages) for different light-emitting elements through the first reference voltage line 10 and the second reference voltage line 20, which can ensure that different light-emitting elements have predictable starting states during low gray-scale display, can more precisely control the output of different light-emitting elements at low brightness, ensure that the light-emitting elements can accurately respond to slight driving voltage changes, thereby helping to reduce the problem of low gray-scale color cast, precisely controlling the starting states of different light-emitting elements at low brightness, and also avoiding the problem of light stealing caused by signal interference between different light-emitting elements during monochromatic picture display due to different turn-on voltages of the light-emitting elements.

[0056] Moreover, the first reference voltage line 10 in the present disclosure includes a first sub-reference voltage line Vref2-RG1 and a second sub-reference voltage line Vref2-RG2 that are electrically connected and have different extending directions. The second reference voltage line 20 includes a third sub-reference voltage line Vref2-B1 and a fourth sub-reference voltage line Vref2-B2 that are electrically connected and have different extending directions. The first reference voltage line 10 and the second reference voltage line 20 can respectively form a mesh wiring structure in the display panel. This is beneficial to reducing the overall impedance of the first reference voltage line 10 and reducing the overall impedance of the second reference voltage line 20, thereby being beneficial to reducing the voltage difference during the transmission of the reference voltage signal, being beneficial to balancing the consistency of the reference voltage signals received by light-emitting elements of the same light-emitting color at different positions, and thus being beneficial to improving the display uniformity of the display panel.

[0057] Please continue to refer to Figure 1 and Figure 2 In an alternative embodiment of the present disclosure, the turn-on voltages of the first light-emitting element D01 and the third light-emitting element D03 are both less than the turn-on voltage of the second light-emitting element D02, and the voltage value of the first reference voltage signal is less than the voltage value of the second reference voltage signal.

[0058] During the manufacturing process of the display panel, in order to save costs and reduce the manufacturing process, the same mask is used to simultaneously evaporate some film layers of light-emitting elements of different colors, resulting in at least one common film layer in different light-emitting elements. The common film layer can be, for example, at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0059] Considering that the turn-on voltages of light-emitting elements may vary due to differences in light-emitting materials. For example, in the present disclosure, the turn-on voltages of the first light-emitting element D01 and the third light-emitting element D03 are close and both are relatively small, while the turn-on voltage of the second light-emitting element D02 is relatively large. In the low gray-scale visual effect, when it is necessary to turn on the second light-emitting element D02 for pure-color screen display, due to the existence of the aforementioned common film layer, the relatively large driving current corresponding to the second light-emitting element D02 may leak through the common film layer to other light-emitting elements, resulting in the problem of accidental lighting of the first light-emitting element D01 or the third light-emitting element D03 that should not originally emit light. Therefore, in this embodiment, when the turn-on voltages of the first light-emitting element D01 and the third light-emitting element D03 are less than the turn-on voltage of the second light-emitting element D02, it is set that the voltage value of the first reference voltage signal provided for the first light-emitting element D01 and the third light-emitting element D03 is less than the voltage value of the second reference voltage provided for the second light-emitting element D02, that is, the potential of the first reference voltage corresponding to the first light-emitting element D01 and the second light-emitting element D02 is lower. When the light-emitting elements in the display panel emit light, they are charged from the initial reference voltage to the target turn-on voltage (the voltage difference between the reference voltage and the turn-on voltage can be regarded as the cross-voltage value), and the light-emitting elements will naturally be turned on. It can be understood that there is a charging process in the early stage of the light-emitting element being turned on. The potential is charged from the reference voltage signal transmitted from the reference voltage line until it reaches a turn-on voltage value, and then the light-emitting element will emit light. In this embodiment, the voltage value of the anode reset signal of the first light-emitting element D01 and the third light-emitting element D03 with relatively small turn-on voltages is pulled down (that is, the voltage value of the first reference voltage signal is smaller and the potential is lower). When the second light-emitting element D02 is turned on to achieve monochromatic screen display, the first light-emitting element D01 and the third light-emitting element D03 are less likely to reach the corresponding cross-voltage value compared with the second light-emitting element D02. Therefore, the first light-emitting element D01 and the third light-emitting element D03 will not be easily affected by leakage current, which is beneficial to avoiding the problem of accidental lighting of the light-emitting elements, and thus beneficial to improving the display quality.

[0060] Please continue to refer to Figure 1 and Figure 2 , in an alternative embodiment of the present disclosure, the first light-emitting element D01 is one of a red light-emitting element and a blue light-emitting element, the second light-emitting element D02 is the other of the red light-emitting element and the blue light-emitting element, and the third light-emitting element D03 is a green light-emitting element. It should be noted that Figure 1 and Figure 2 only the case where the first light-emitting element D01 is a red light-emitting element and the second light-emitting element D02 is a blue light-emitting element is taken as an example for illustration, but it is not limited thereto.

[0061] Optionally, the first light-emitting element D01 is a red light-emitting element, the second light-emitting element D02 is a blue light-emitting element, and the third light-emitting element D03 is a green light-emitting element. When the light-emitting element mentioned in the embodiment of the present disclosure is an organic light-emitting diode, the turn-on voltage of the red light-emitting element is less than the turn-on voltage of the blue light-emitting element, and the turn-on voltage of the green light-emitting element is less than the turn-on voltage of the blue light-emitting element. Therefore, when lighting the second light-emitting element D02 with a blue light-emitting color, since its turn-on voltage is larger than that of the red light-emitting element and the green light-emitting element, there will be a sneak light of red and / or green in the blue screen, affecting the display quality of the display screen. In this embodiment, the second light-emitting element D02 is set as a blue light-emitting element with a larger turn-on voltage, and the first light-emitting element D01 and the third light-emitting element D03 are red light-emitting elements and green light-emitting elements with smaller turn-on voltages. At this time, the voltage values of the first reference voltage signals corresponding to the red light-emitting element and the green light-emitting element are pulled down. When lighting the blue light-emitting element to realize the blue screen display, even if the anodes of the red light-emitting element and the green light-emitting element are charged due to the influence of the common film layer, due to the large cross-voltage value, it is not easy to be turned on, which is beneficial to improving the problem of sneak light of the red light-emitting element and / or the green light-emitting element in the blue screen.

[0062] Considering that different color light-emitting materials have different energy level structures and electron transition characteristics, which directly affect the turn-on voltage of the corresponding light-emitting element. Besides the differences in the light-emitting materials, the specific turn-on voltage value is also affected by various factors such as the manufacturer and the device structure. Therefore, only the case where the first light-emitting element D01 is a red light-emitting element, the second light-emitting element D02 is a blue light-emitting element, and the third light-emitting element D03 is a green light-emitting element is taken as an example for illustration in this embodiment. In some other embodiments of the present disclosure, the first light-emitting element D01 may also be embodied as a blue light-emitting element, the second light-emitting element D02 may also be embodied as a red light-emitting element, and the third light-emitting element D03 may also be embodied as a green light-emitting element. At this time, the red light-emitting element has a higher turn-on voltage, and the blue light-emitting element and the green light-emitting element have lower turn-on voltages, which is also applicable to the content of the present disclosure.

[0063] Figure 6The following is a schematic layout diagram of the pixel circuit provided by the embodiments of the present disclosure. Please refer to Figure 6 , in an alternative embodiment of the present disclosure, the display panel includes a plurality of first circuit columns L1 and second circuit columns L2 alternately arranged along a first direction D1. Among them, the first circuit columns L1 include a first pixel circuit P1 and a second pixel circuit P2 alternately arranged along a second direction D2, and the second circuit columns L2 include a plurality of third pixel circuits P3 arranged along the second direction D2. The display panel includes a plurality of circuit column groups Z0 arranged along the first direction D1. A circuit column group Z0 includes a first circuit column L1 and a second circuit column L2 adjacent to each other along the first direction D1; a second sub-reference voltage line Vref2-RG2 and a fourth sub-reference voltage line Vref2-B2 are respectively arranged corresponding to different circuit column groups Z0.

[0064] It should be noted that, for clearly showing the overall layout of the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 in the display panel, Figure 6 only the different pixel circuits in the circuit column group Z0 are schematically shown in the form of boxes, and the first pixel circuit P1, the second pixel circuit P2, and the third pixel circuit P3 are distinguished by R, B, and G respectively. It should also be noted that, Figure 6 only the arrangement of the pixel circuits in the display panel is shown, and the arrangement of the light-emitting elements is not limited. In practical applications, the light-emitting elements can be arranged according to actual situations. For example, please refer to Figure 7 , Figure 7 The following is a schematic layout diagram of the light-emitting elements in the display panel. Similar to the arrangement of the pixel circuits, the light-emitting elements include a first element column L01 and a second element column L02 alternately arranged along the first direction D1. The first element column L01 includes a first light-emitting element D01 and a second light-emitting element D02 alternately arranged along the second direction D2, and the second element column L02 includes a plurality of third light-emitting elements D03 arranged along the second direction D2. However, the present disclosure is not limited thereto. It should be noted that, Figure 7 the shapes and sizes of the shown light-emitting elements are only for illustration, and the present disclosure does not limit this.

[0065] In this embodiment, the first pixel circuit P1 and the second pixel circuit P2 in the first type of circuit column L1 are respectively used to drive the first light-emitting element D01 and the second light-emitting element D02, and the third pixel circuit P3 in the second type of circuit column L2 is used to drive the third light-emitting element D03. Optionally, the third light-emitting element D03 is a green light-emitting element, and one of the first light-emitting element D01 and the second light-emitting element D02 is a red light-emitting element, and the other is a blue light-emitting element. Optionally, the arrangement rule of the light-emitting elements is adapted to the arrangement rule of the corresponding pixel circuits. That is to say, in the display panel, when the first pixel circuit P1 and the second pixel circuit P2 in the first type of circuit column L1 are alternately arranged along the second direction D2, the corresponding first light-emitting element D01 and the second light-emitting element D02 are also alternately arranged along the second direction D2; when multiple third pixel circuits P3 in the second type of circuit column L2 are arranged along the second direction D2, multiple third light-emitting elements D03 in the display panel are also arranged along the second direction D2. Considering that green contributes the most to the perceived brightness of the human eye, in the embodiments of the present disclosure, a second type of circuit column L2 is separately provided to drive the corresponding green light-emitting element, which is beneficial to improving the overall brightness of the display panel.

[0066] The circuit column group Z0 mentioned in this embodiment includes a first type of circuit column L1 and a second type of circuit column L2 that are adjacent to each other along the first direction D1. Different circuit column groups Z0 correspond to different circuit columns. That is to say, different circuit column groups Z0 do not share the first type of circuit column L1 or the second type of circuit column L2. The second sub-reference voltage line Vref2-RG2 in the first reference voltage line 10 and the fourth sub-reference voltage line Vref2-B2 in the second reference voltage line 20 both extend along the second direction D2. At this time, the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 are respectively set corresponding to different circuit column groups Z0, which is beneficial to improving the overall wiring uniformity of the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 in the display panel.

[0067] Please refer to Figure 2 , in an alternative embodiment of the present disclosure, in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, at least one of the first pixel circuit P1 and the third pixel circuit P3 is electrically connected to the second sub-reference voltage line Vref2-RG2, and the second pixel circuit P2 is electrically connected to the third sub-reference voltage line Vref2-B1.

[0068] The circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 mentioned in this embodiment is located refers to the circuit column group that is provided with the second sub-reference voltage line Vref2-RG2 but not provided with the fourth sub-reference voltage line Vref2-B2. Since the second sub-reference voltage line Vref2-RG2 is part of the first reference voltage line 10, and the first reference voltage line 10 is used to provide the first reference voltage signal to the first light-emitting element D01 and the third light-emitting element D03 through the first pixel circuit P1 and the third pixel circuit P3 respectively. Therefore, in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, at least one of the first pixel circuit P1 and the third pixel circuit P3 can be electrically connected to the second sub-reference voltage line Vref2-RG2 to obtain the first reference voltage signal from the second sub-reference voltage line Vref2-RG2. It should be noted that Figure 2 In the embodiment, only the scheme where only the third pixel circuit P3 is electrically connected to the second sub-reference voltage line Vref2-RG2 in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located is shown. Of course, in some other embodiments of the present disclosure, only the first pixel circuit P1 can be electrically connected to the second sub-reference voltage line Vref2-RG2, or both the first pixel circuit P1 and the third pixel circuit P3 are electrically connected to the second sub-reference voltage line Vref2-RG2, which will be described in subsequent embodiments.

[0069] For the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, since the fourth sub-reference voltage line Vref2-B2 extending along the second direction D2 is not provided, the second pixel circuit P2 can be electrically connected to the third sub-reference voltage line Vref2-B1 extending along the first direction D1 to obtain the second reference voltage signal through the third sub-reference voltage line Vref2-B1.

[0070] In the embodiment of the present disclosure, the first reference voltage line 10 includes a first sub-reference voltage line Vref2-RG1 extending along the first direction D1 and a second sub-reference voltage line Vref2-RG2 extending along the second direction D2, and the second reference voltage line 20 includes a third sub-reference voltage line Vref2-B1 extending along the first direction D1 and a fourth sub-reference voltage line Vref2-B2 extending along the second direction D2. When the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 extending along the second direction D2 are respectively corresponding to different circuit column groups Z0, the first pixel circuit P1, the second pixel circuit P2, and the third pixel circuit P3 can be electrically connected to the corresponding sub-reference voltage lines in a way of connecting nearby, so as to simplify the wiring difficulty of the display panel. The specific connection manner between the pixel circuit and the sub-reference voltage line will be further described in subsequent embodiments.

[0071] Please continue to refer to Figure 2 In an alternative embodiment of the present disclosure, in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, the first pixel circuit P1 is electrically connected to the first sub-reference voltage line Vref2-RG1 extending along the first direction D1, and the third pixel circuit P3 is electrically connected to the second sub-reference voltage line Vref2-RG2 extending along the second direction D2.

[0072] In the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, the first pixel circuit P1 is located in the first type of circuit column L1. In the first type of circuit column L1, the first pixel circuit P1 and the second pixel circuit P2 are alternately arranged along the second direction D2. Among them, the first pixel circuit P1 is electrically connected to the first sub-reference voltage line Vref2-RG1 extending along the first direction D1, and the second pixel circuit P2 is electrically connected to the third sub-reference voltage line Vref2-B1 extending along the first direction D1. In the second type of circuit column L2, each third pixel circuit P3 is electrically connected to the second sub-reference voltage line Vref2-RG2 extending along the second direction D2. In this embodiment, in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, connecting the first pixel circuit P1 to the first sub-reference voltage line Vref2-RG1 extending along the first direction D1 and connecting the third pixel circuit P3 to the second sub-reference voltage line Vref2-RG2 extending along the second direction D2 is beneficial to balancing the loads corresponding to the first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2, thereby facilitating improving the transmission quality of the first reference voltage signal on the first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2.

[0073] In addition, considering that both the first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2 need to obtain signals from the bonding area (for electrically connecting to the control chip) of the display panel. Assuming that the bonding area is located in the extending direction of the second sub-reference voltage line Vref2-RG2, the signal transmission distance between the second sub-reference voltage line Vref2-RG2 and the bonding area is relatively short. Compared with the first sub-reference voltage line Vref2-RG1, the second sub-reference voltage line Vref2-RG2 can transmit the first reference voltage signal more quickly. When the third light-emitting element D03 corresponding to the third pixel circuit P3 is a green light-emitting element, since the green light-emitting element contributes the most to the human eye's brightness perception, when the third pixel circuit P3 is connected to the second sub-reference voltage line Vref2-RG2 extending along the second direction D2, the anode reset of the third light-emitting element D03 corresponding to the third pixel circuit P3 can be achieved more quickly, thereby facilitating reducing the smear and blurring of the overall picture.

[0074] Figure 8 Shown is another connection schematic diagram of a light-emitting element, a pixel circuit, a first reference voltage line, and a second reference voltage line. Different from the Figure 2 embodiment, in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, the first pixel circuit P1 is electrically connected to the second sub-reference voltage line Vref2-RG2.

[0075] Please refer to Figure 8 , in an alternative embodiment of the present disclosure, in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, both the first pixel circuit P1 and the third pixel circuit P3 are electrically connected to the second sub-reference voltage line Vref2-RG2.

[0076] This embodiment shows a scheme in which, in the circuit column group Z0 where the second sub-reference voltage line Vref2-RG2 is located, both the first pixel circuit P1 and the third pixel circuit P3 are connected to the second sub-reference voltage line Vref2-RG2 extending along the second direction D2. In this way, for the first pixel circuit P1 and the third pixel circuit P3 in the same row, both of them will be able to receive the anode reset signal simultaneously, realizing the synchronous reset of the first light-emitting element D01 and the third light-emitting element D03.

[0077] In addition, considering that both the first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2 need to obtain signals from the bonding area of the display panel. Assuming that the bonding area is located in the extending direction of the second sub-reference voltage line Vref2-RG2, the second sub-reference voltage line Vref2-RG2 can transmit the first reference voltage signal more quickly compared to the first sub-reference voltage line Vref2-RG1. Therefore, in this embodiment, when both the first pixel circuit P1 and the third pixel circuit P3 are connected to the second sub-reference voltage line Vref2-RG2 extending along the second direction D2, since the distance for the bonding area to transmit signals to the second sub-reference voltage line Vref2-RG2 is shorter and the signal attenuation is small, it is beneficial to realize the rapid reset of the first light-emitting element D01 and the third light-emitting element D03 corresponding to the first pixel circuit P1 and the third pixel circuit P3, and helps to quickly clear the residual charges to prepare for the display of the next frame.

[0078] Please continue to refer to Figure 8 , in an alternative embodiment of the present disclosure, in the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, the second pixel circuit P2 is electrically connected to the fourth sub-reference voltage line Vref2-B2, and the first pixel circuit P1 and the third pixel circuit P3 are electrically connected to the first sub-reference voltage line Vref2-RG1.

[0079] In the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, the fourth sub-reference voltage line Vref2-B2 extends along the second direction D2. When the second pixel circuit P2 is electrically connected to the fourth sub-reference voltage line Vref2-B2, the second pixel circuit P2 can obtain the second reference voltage signal through the fourth sub-reference voltage line Vref2-B2. Considering that both the third sub-reference voltage line Vref2-B1 and the fourth sub-reference voltage line Vref2-B2 in the second reference voltage line 20 need to obtain signals from the bonding area of the display panel, assuming that the bonding area is located in the extension direction of the fourth sub-reference voltage line Vref2-B2, the fourth sub-reference voltage line Vref2-B2 can transmit the second reference voltage signal more quickly than the third sub-reference voltage line Vref2-B1. Therefore, in this embodiment, when the second pixel circuit P2 is connected to the fourth sub-reference voltage line Vref2-B2 extending along the second direction D2, due to the shorter signal transmission distance from the bonding area to the fourth sub-reference voltage line Vref2-B2 and the smaller signal attenuation, it is beneficial to quickly reset the second light-emitting element D02 corresponding to the second pixel circuit P2, which helps to quickly clear the residual charges and prepare for the display of the next frame.

[0080] It should be noted that in the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, since the second sub-reference voltage line Vref2-RG2 extending along the second direction D2 is not provided, the first pixel circuit P1 and the third pixel circuit P3 are both electrically connected to the first sub-reference voltage line Vref2-RG1 extending along the first direction D1 to obtain the first reference voltage signal, avoiding the problem of complex wiring caused by connecting to the second sub-reference voltage line Vref2-RG2 with a longer distance.

[0081] It should be noted that Figure 2 and Figure 8 This embodiment only takes the example that the circuit column group Z0 where the second sub-reference voltage line Vref2-RG2 is located and the circuit column group Z0 where the fourth sub-reference voltage line Vref2-B2 is located are adjacent, but the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the circuit column group Z0 where the second sub-reference voltage line Vref2-RG2 is located and the circuit column group Z0 where the fourth sub-reference voltage line Vref2-B2 is located may not be adjacent.

[0082] It should be noted that Figure 2 and Figure 8 Only the connection schematic of the first reference voltage line 10 and the second reference voltage line 20 with the pixel circuit is shown, and the specific film layers of these signal lines are not limited. The film layer structure of the display panel will be introduced below.

[0083] Figure 9The following is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure. Taking the display panel as an OLED display panel as an example for illustration, it should be noted that this embodiment only takes the transistors in the pixel circuit as P-type transistors as an example for illustration, but is not limited thereto. Please refer to Figure 9 , the basic structure of the light-emitting element D0 includes an anode 301, a light-emitting material layer 302, and a cathode 303. When a suitable voltage is supplied by the power supply, the holes generated by the anode 301 and the electrons generated by the cathode 303 will combine in the light-emitting material layer 302 to generate bright light. Optionally, the display panel includes a substrate 00, a driving layer 40, and a display layer 30. Among them, the display layer 30 includes a pixel definition layer 19, and the pixel definition layer 19 defines a plurality of pixel openings K; the light-emitting material layer 302 is at least located in the pixel openings K. Along the direction perpendicular to the substrate 00, the anode 301 and the cathode 303 are respectively located on both sides of the light-emitting material layer 302, and the anode 301 is located on the side of the cathode 303 facing the substrate 00. Optionally, a packaging layer 50 is further provided on the side of the cathode 303 away from the anode 301. Optionally, the packaging layer 50 includes a first inorganic layer 51, an organic layer 52, and a second inorganic layer 53 arranged in a stacked manner. The aforementioned pixel circuit is provided in the driving layer 40 for providing a driving voltage to the light-emitting element D0 to drive the light-emitting element to emit light. The pixel circuit includes a plurality of transistors T. Optionally, in the driving layer 40, the gate of the transistor is provided on the first metal layer m1, and the source and drain of the transistor are provided on the second metal layer m2. Optionally, the array substrate 10 further includes an active layer poly provided on the side of the first metal layer m1 facing the substrate 00 and an auxiliary metal layer m0 provided on the side of the active layer poly facing the substrate 00. Along the direction perpendicular to the plane where the substrate 00 is located, both the first metal layer m1 and the auxiliary metal layer m0 overlap with the active layer poly, and the auxiliary metal layer m0 has a light-shielding effect to avoid the influence of light on the active layer poly. Optionally, a capacitive metal layer mc is further included between the first metal layer m1 and the second metal layer m2, and the capacitive metal layer mc can form a capacitive structure with the second metal layer m2 or the first metal layer m1. Optionally, a third metal layer m3 is further included on the side of the second metal layer m2 away from the substrate 00, and additional metal layers can be provided on the side of the third metal layer m3 away from the substrate according to actual needs. The present disclosure does not specifically limit this, and signal lines can be arranged on each metal layer.

[0084] The first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1 mentioned in the embodiments of the present disclosure can be disposed on the aforementioned first metal layer m1 or the capacitor metal layer mc, or other feasible film layers. The two can be disposed on the same layer or on different layers, and the present disclosure does not specifically limit this. The second reference voltage line 20 and the fourth reference voltage line DVH can be disposed on the aforementioned second metal layer m2 or the capacitor metal layer mc, or other feasible film layers. The two can be disposed on the same layer or on different layers, and the present disclosure does not specifically limit this.

[0085] Figure 10 Shown is a layout schematic diagram of a circuit column group where the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 are located. This embodiment shows a scheme where the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located and the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located are adjacent, but the present disclosure is not limited thereto. Please refer to Figure 4 and Figure 10 , in an alternative embodiment of the present disclosure, the pixel circuit includes a first reset transistor T7 (corresponding to Figure 4 the seventh transistor T7 in the embodiment), a first end of the first reset transistor T7 is connected to the first reference voltage line 10 or the second reference voltage line 20, and a second end of the first reset transistor T7 is connected to an anode of the light-emitting element; in the second type of circuit column L2, the first reset transistors T7 corresponding to the third pixel circuits P3 adjacent along the second direction D2 are respectively a first sub-transistor T7-G1 and a second sub-transistor T7-G2; in the circuit column group Z0, along the first direction D1, the first sub-transistor T7-G1 is adjacent to the first reset transistor T7-R in the first pixel circuit P1; the second sub-transistor T7-G2 is adjacent to the first reset transistor T7-B in the second pixel circuit P2.

[0086] It should be noted that for convenience of description, in this embodiment, the first reset transistors T7 corresponding to the adjacent third pixel circuits P3 in the second type of circuit column L2 are respectively defined as the first sub-transistor T7-G1 and the second sub-transistor T7-G2, but there is no distinction made between the structures or performances of the first sub-transistor T7-G1 and the second sub-transistor T7-G2. In fact, the first sub-transistor T7-G1 and the second sub-transistor T7-G2 can have the same structure and play the same role in different third pixel circuits P3. In the circuit column group Z1 where the second reference voltage line 20 is located, and in the circuit column group Z2 where the fourth reference voltage line DVH is located, the first sub-transistor T7-G1 can be regarded as a transistor adjacent to the first reset transistor T7-R in the first pixel circuit P1, and the second sub-transistor T7-G2 can be regarded as a transistor adjacent to the first reset transistor T7-B in the second pixel circuit P2.

[0087] In this embodiment, in the same circuit column group Z0, the first reset transistors T7 corresponding to two adjacent pixel circuits along the first direction D1 are arranged adjacent to each other, so that the adjacent first reset transistors T7 have closer electrical characteristics (such as threshold voltage, mobility). For the first pixel circuit P1 and the third pixel circuit P3 receiving the same first reference voltage signal, the first reference voltage signals transmitted by the corresponding two first reset transistors T7 are more uniform or consistent, which is beneficial to reset the anodes of the light-emitting elements corresponding to the first pixel circuit P1 and the third pixel circuit P3 to a more stable initial state, thereby reducing the brightness drift caused by temperature change, and finally reducing the offset of white balance and improving the problem of heating color cast.

[0088] In addition, in the same circuit column group Z0, the first reset transistors T7 corresponding to two adjacent pixel circuits along the first direction D1 are arranged adjacent to each other, which makes it possible for at least some adjacent first reset transistors T7 to share the second sub-reference voltage line Vref2-RG2 or the fourth sub-reference voltage line Vref2-B2 extending along the second direction D2. This is beneficial to simplifying the connection complexity between the first reset transistor T7 and the corresponding second sub-reference voltage line Vref2-RG2 or the fourth sub-reference voltage line Vref2-B2. At the same time, in the same circuit column group Z0, the first reset transistors T7 corresponding to two adjacent pixel circuits along the first direction D1 are arranged adjacent to each other, which also helps to achieve a more compact pixel arrangement, thereby being beneficial to achieving a higher pixel density under the same physical size, and being beneficial to improving the display resolution and fineness.

[0089] Please continue to refer to Figure 10 , in an alternative embodiment of the present disclosure, in the circuit column group Z1 corresponding to the second sub-reference voltage line Vref2-RG2, the first reset transistors T7-R / T7-B and the adjacent first sub-transistor T7-G1 or the second sub-transistor T7-G2 are respectively located on both sides of the second sub-reference voltage line Vref2-RG2; in the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, the first reset transistors T7-R / T7-B and the adjacent first sub-transistor T7-G1 or the second sub-transistor T7-G2 are respectively located on both sides of the fourth sub-reference voltage line Vref2-B2.

[0090] Among the pixel circuits corresponding to two adjacent pixel circuits in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, when the first reset transistors T7 are arranged adjacent to each other along the first direction D1, the second reference voltage line 20 is located between the two adjacent first reset transistors T7 along the first direction D1, that is, between the first sub-transistor T7-G1 and the first reset transistor T7-R in the adjacent first pixel circuit P1, and between the second sub-transistor T7-G2 and the first reset transistor T7-B in the adjacent second pixel circuit P2. In this way, in the circuit column group Z1, at least one of the first sub-transistor T7-G1 and the first reset transistor T7-R adjacent thereto can be electrically connected to the second sub-reference voltage line Vref2-RG2 in the vicinity. At the same time, the second sub-transistor T7-G2 can also be electrically connected to the second sub-reference voltage line Vref2-RG2 in the vicinity, which is beneficial to simplifying the connection wiring difficulty of the second sub-reference voltage line Vref2-RG2 and the transistors connected thereto. In addition, when the bonding area of the display panel is located in the extension direction of the second sub-reference voltage line Vref2-RG2, the second sub-reference voltage line Vref2-RG2 can obtain the first reference voltage signal from the bonding area more quickly, and can quickly transmit the first reference voltage signal to the first reset transistor T7 connected thereto, so as to more quickly realize the anode reset of the light-emitting elements corresponding to these first reset transistors T7, which is beneficial to reducing the smear and blurring of the overall picture.

[0091] In the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, when the first reset transistors T7 corresponding to two adjacent pixel circuits along the first direction D1 are arranged adjacent to each other, the fourth reference voltage line DVH is located between the two adjacent first reset transistors T7 along the first direction D1, that is, between the first sub-transistor T7-G1 and the first reset transistor T7-R in the first pixel circuit P1 adjacent thereto, and between the second sub-transistor T7-G2 and the first reset transistor T7-B in the second pixel circuit P2 adjacent thereto. In this way, in the circuit column group Z2 where it is located, the first reset transistor T7-B in the second pixel circuit P2 can be connected to the fourth sub-reference voltage line Vref2-B2 in close proximity, which helps to simplify the connection difficulty between the fourth sub-reference voltage line Vref2-B2 and the first reset transistor T7-B connected thereto. At the same time, when the bonding area of the display panel is in the extending direction of the fourth sub-reference voltage line Vref2-B2, the fourth sub-reference voltage line Vref2-B2 can obtain the second reference voltage signal from the bonding area more quickly, and can quickly transmit the second reference voltage signal to the first reset transistor T7-B connected thereto, so as to more quickly achieve the anode reset of the second light-emitting element D02 corresponding to these first reset transistors T7-B, which helps to reduce the smear and blurring of the overall picture.

[0092] Figure 11 Another layout schematic diagram of the circuit column group where the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 are located is shown. Please refer to Figure 11 In an alternative embodiment of the present disclosure, in the circuit column group Z0, the first end of the first sub-transistor T7-G1 and the first end of the first reset transistor T7-R adjacent to the first sub-transistor T7-G1 are electrically connected through a connection portion B0.

[0093] Considering that the first reset transistors T7 in the first pixel circuit P1 and the third pixel circuit P3 are both electrically connected to the first reference voltage line 10 to obtain the first reference voltage signal, in the circuit column group Z0 of this embodiment, when the first end of the first sub-transistor T7-G1 corresponding to the third pixel circuit P3 and the first end of the first reset transistor T7-R adjacent to the first sub-transistor T7-G1 are electrically connected through the connection portion B0, the first sub-transistor T7-G1 and the first reset transistor T7-R adjacent thereto can be connected to the same sub-reference voltage line through the connection portion B0. For example, for the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, the first sub-transistor T7-G1 and the first reset transistor T7-R adjacent thereto can be connected to the second sub-reference voltage line Vref2-RG2 or the first sub-reference voltage line Vref2-RG1 through the connection portion B0 ( Figure 11The scheme of connecting the connection part B0 to the first sub-reference voltage line Vref2-RG1 is shown. For the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, the first sub-transistor T7-G1 and the adjacent first reset transistor T7-R can be connected to the first sub-reference voltage line Vref2-RG1 through the aforementioned connection part B0. In this way, there is no need to introduce different connection parts for the first sub-transistor T7-G1 and the adjacent first reset transistor T7-R respectively and realize the connection with the corresponding sub-reference voltage line through two via processes, which is beneficial to reducing the connection difficulty between the first reset transistor T7 and the reference voltage line in the display panel and simplifying the connection process.

[0094] It should be noted that when the first ends of the first sub-transistor T7-G1 and the first reset transistor T7-R adjacent to the first sub-transistor T7-G1 are electrically connected through the connection part B0, the connection part B0 can be located in the active layer poly, for example, to realize their electrical connection in the active layer poly. In this way, it does not occupy the metal layer in the display panel. In integrated circuit manufacturing, the metal layer is usually used for long-distance signal and power wiring. In a local area, especially inside the pixel circuit, arranging the connection part B0 in the active layer poly can reduce the demand for the metal wiring layer. Reducing the use of the metal layer may also reduce the required lithography steps, thus simplifying the layout design and reducing the manufacturing complexity and cost. In addition, if two transistors are very close physically, using the connection part B0 located in the active layer to directly connect their first ends can avoid auxiliary connection through metal vias and the metal layer. Each additional metal via will introduce additional resistance, while directly using the connection part B0 located in the active layer for connection can reduce these contact resistances, thereby reducing the overall connection resistance and being beneficial to improving the performance and efficiency of the circuit.

[0095] Figure 12 Shown is another layout schematic diagram of the circuit column group where the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 are located. The difference from Figure 11 the embodiment is that in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, the sub-reference voltage signal line connected by the connection part B0 is different. Please refer to Figure 12 , in an optional implementation manner of the present disclosure, in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, the connection part B0 is electrically connected to the second sub-reference voltage line Vref2-RG2 through the connection hole K0.

[0096] When the first ends of the first sub-transistor T7-G1 and the adjacent first reset transistor T7-R are electrically connected through the connection part B0, in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, the connection part B0 is further electrically connected to the second sub-reference voltage line Vref2-RG2 extending along the second direction D2, and a first reference voltage signal is obtained through the second sub-reference voltage line Vref2-RG2. When the bonding area is located in the extending direction of the second sub-reference voltage line Vref2-RG2, the signal transmission distance between the second sub-reference voltage line Vref2-RG2 and the bonding area is relatively short, that is, the signal transmission distance from the bonding area to the second sub-reference voltage line Vref2-RG2 is short, and the signal attenuation is small. Therefore, it is beneficial to quickly reset the first light-emitting element and the third light-emitting element corresponding to the first pixel circuit P1 and the third pixel circuit P3, which helps to quickly clear the residual charges and prepare for the display of the next frame.

[0097] Moreover, when the first ends of the first sub-transistor T7-G1 and the adjacent first reset transistor T7-R are electrically connected through the connection part B0, only one punching process is required to electrically connect the first sub-transistor T7-G1, the adjacent first reset transistor T7-R and the second sub-reference voltage line Vref2-RG2. Therefore, it is also beneficial to simplify the manufacturing process of the display panel.

[0098] Figure 13 Shown is another layout schematic diagram of the circuit column group Z0 where the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 are located. Different from Figure 12 is that Figure 13 it further shows the connection of the first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2.

[0099] Please refer to Figure 13, in an alternative embodiment of the present disclosure, in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, the connecting portion B0 is also electrically connected to the first sub-reference voltage line Vref2-RG1 through the connection hole K0. The first reference voltage line 10 in the embodiment of the present disclosure includes a first sub-reference voltage line Vref2-RG1 extending along the first direction D1 and a second sub-reference voltage line Vref2-RG2 extending along the second direction D2. The first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2 are located in different film layers, and the two can be electrically connected through the connection hole. In this embodiment, when the connecting portion B0 is electrically connected to the second sub-reference voltage line Vref2-RG2 extending along the second direction D2 through the connection hole K0, it is further electrically connected to the first sub-reference voltage line Vref2-RG1 extending along the first direction D1 through the same connection hole K0. In this way, the electrical connection of the connecting portion B0, the first sub-reference voltage line Vref2-RG1, and the second sub-reference voltage line Vref2-RG2 can be achieved through one connection hole K0, without separately introducing a new connection hole for the connection between the first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2. Therefore, it is beneficial to simplify the connection process of the signal lines in the display panel and improve the production efficiency of the display panel.

[0100] Please refer to Figure 12 and Figure 13 , in an alternative embodiment of the present disclosure, in the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, the connecting portion B0 is electrically connected to the first sub-reference voltage line Vref2-RG1. Since the second sub-reference voltage line Vref2-RG2 extending along the second direction D2 is not provided in the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, the first reset transistor T7-R in the first pixel circuit P1 and the third pixel circuit P3 in the circuit column group Z0 can be connected to the first sub-reference voltage line Vref2-RG1 through the connecting portion B0, and the first reference voltage signal can be obtained through the first sub-reference voltage line Vref2-RG1. By connecting to the first sub-reference voltage line Vref2-RG1 through the same connecting portion B0, there is no need to separately introduce different connecting portions and two drilling processes for the first transistor T7-G1 and the first reset transistor T7-R connected thereto. Therefore, it is beneficial to simplify the manufacturing difficulty of the panel and simplify the manufacturing process.

[0101] The above embodiments illustrate a solution in which the first sub-transistor T7-G1 and the adjacent first reset transistor T7-R are connected through the connection part B0 and then connected to the first reference voltage line 10. In some other embodiments of the present disclosure, the first sub-transistor T7-G1 and the adjacent first reset transistor T7-R may also be electrically connected to the first reference voltage line 10 respectively. For example, please refer to Figure 10 , in an alternative embodiment of the present disclosure, in the circuit column group Z0, the first sub-transistor T7-G1 and the adjacent first reset transistor T7-R are electrically connected to the first reference voltage line 10 respectively. It can be understood that the first sub-transistor T7-G1 and the adjacent first reset transistor T7 can be respectively connected to different points on the first reference voltage line 10. For example, please refer to Figure 10 , when both the first sub-transistor T7-G1 and the adjacent first reset transistor T7-R are connected to the first sub-reference voltage line Vref2-RG1 extending along the first direction D1, for example, in the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, the first sub-transistor T7-G1 is electrically connected to the first sub-reference voltage line Vref2-RG1 through a connection hole K01, and the first reset transistor T7-R adjacent to the first sub-transistor T7-G1 is electrically connected to the first sub-reference voltage line Vref2-RG1 through another connection hole K02. The two connection holes are connected to different positions on the first sub-reference voltage line Vref2-RG1. In this way, the electrical connection between the first sub-transistor T7-G1 and the adjacent first reset transistor T7-R and the first reference voltage line 10 can also be realized. Of course, in some other embodiments of the present disclosure, the first sub-transistor T7-G1 and the adjacent first reset transistor T7 may also be respectively connected to the first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2, which will be described in subsequent embodiments.

[0102] Please continue to refer to Figure 10 , in an alternative embodiment of the present disclosure, in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, the first sub-transistor T7-G1 is electrically connected to the second sub-reference voltage line Vref2-RG2, and the first reset transistor T7-R adjacent to the first sub-transistor T7-G1 is electrically connected to the first sub-reference voltage line Vref2-RG1.

[0103] For the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, due to the corresponding setting of the second sub-reference voltage line Vref2-RG2, when the first sub-transistor T7-G1 and the first reset transistor T7-R adjacent to it are respectively electrically connected to the first reference voltage line 10, one of the first sub-transistor T7-G1 and the first reset transistor T7-R adjacent to it can be connected to the second sub-reference voltage line Vref2-RG2, and the other can be connected to the first sub-reference voltage line Vref2-RG1. In this way, the loads of the first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2 can be balanced, which is beneficial to improving the transmission quality of the first reference voltage signal on the first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2.

[0104] It should be noted that Figure 10 The embodiment only shows that in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, the first sub-transistor T7-G1 is electrically connected to the second sub-reference voltage line Vref2-RG2, and the first reset transistor T7-R adjacent to the first sub-transistor T7-G1 is electrically connected to the first sub-reference voltage line Vref2-RG1. In some other embodiments of the present disclosure, it can also be embodied as Figure 14 As shown schematically, the first sub-transistor T7-G1 is electrically connected to the first sub-reference voltage line Vref2-RG1, and the first reset transistor T7-R adjacent to the first sub-transistor T7-G1 is electrically connected to the second sub-reference voltage line Vref2-RG2. The present disclosure does not specifically limit this. Among them, Figure 14 Shown is another layout schematic diagram of the circuit column group where the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 are located.

[0105] Please continue to refer to Figure 13 and Figure 14 In an alternative embodiment of the present disclosure, in the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, the second sub-transistor T7-G2 is electrically connected to the second sub-reference voltage line Vref2-RG2, and the first reset transistor T7-B adjacent to the second sub-transistor T7-G2 is electrically connected to the third sub-reference voltage line Vref2-B1.

[0106] In this embodiment, the second sub-transistor T7-G2 is the first reset transistor T7 in the third pixel circuit P3 corresponding to the third light-emitting element D03 (e.g., a green light-emitting element). The second sub-transistor T7-G2 is adjacent to the first reset transistor T7-B in the second pixel circuit P2 corresponding to the second light-emitting element D02 (e.g., a blue light-emitting element). In the circuit column group Z1 where the second sub-reference voltage line Vref2-RG2 is located, since there is a second sub-reference voltage line Vref2-RG2 extending along the second direction D2, the second sub-transistor T7-G2 can be electrically connected to the second sub-reference voltage line Vref2-RG2 to achieve rapid reset of the third light-emitting element. In addition, since there is no fourth sub-reference voltage line Vref2-B2 extending along the second direction D2 in this circuit column group Z0, the first reset transistor T7-B adjacent to the second sub-transistor T7-G2 can be electrically connected to the third sub-reference voltage line Vref2-B1 extending along the first direction D1, and obtain the second reference voltage signal through the third sub-reference voltage line Vref2-B1. The method of connecting the first reset transistor T7 to the third sub-reference voltage line Vref2-B1 in the vicinity is beneficial to simplifying the overall wiring complexity of the display panel.

[0107] Please continue to refer to Figure 13 and Figure 14 , in an alternative embodiment of the present disclosure, in the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, the second sub-transistor T7-G2 is electrically connected to the first sub-reference voltage line Vref2-RG1, and the first reset transistor T7-B adjacent to the second sub-transistor T7-G2 is electrically connected to the fourth sub-reference voltage line Vref2-B2.

[0108] In this embodiment, the second sub-transistor T7-G2 is the first reset transistor T7 in the third pixel circuit P3 corresponding to the third light-emitting element (e.g., a green light-emitting element). The second sub-transistor T7-G2 is adjacent to the first reset transistor T7-B in the second pixel circuit P2 corresponding to the second light-emitting element (e.g., a blue light-emitting element). In the circuit column group Z0 where the fourth sub-reference voltage line Vref2-B2 is located, since the second sub-reference voltage line Vref2-RG2 extending along the second direction D2 is not provided, the second sub-transistor T7-G2 can be electrically connected to the first sub-reference voltage line Vref2-RG1 extending along the first direction D1, and the first reference voltage signal can be obtained through the first sub-reference voltage line Vref2-RG1. In this circuit column group Z0, in the circuit column group Z0 where the fourth sub-reference voltage line Vref2-B2 is located, the first reset transistor T7 adjacent to the second sub-transistor T7-G2 can be electrically connected to the fourth sub-reference voltage line Vref2-B2 extending along the second direction D2, so as to realize the faster transmission of the second reference voltage signal and realize the fast reset of the second light-emitting element. Of course, in some other embodiments of the present disclosure, the first reset transistor T7 adjacent to the second sub-transistor T7-G2 can be electrically connected to the third sub-reference voltage line Vref2-B1 extending along the first direction D1, and the second reference voltage signal can also be obtained through the third sub-reference voltage line Vref2-B1.

[0109] Figure 15 Shown is another layout schematic diagram of the circuit column group Z2 where the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 are located. In this embodiment, the connection between the third sub-reference voltage line Vref2-B1 and the fourth sub-reference voltage line Vref2-B2 in the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located is illustrated. Please refer to Figure 15 , in an alternative embodiment of the present disclosure, in the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, on the side of the fourth sub-reference voltage line Vref2-B2 away from the first sub-transistor T7-G1, the fourth sub-reference voltage line Vref2-B2 is electrically connected to the third sub-reference voltage line Vref2-B1.

[0110] In the present disclosure, the second reference voltage line 20 includes a third sub-reference voltage line Vref2-B1 extending along a first direction D1 and a fourth sub-reference voltage line Vref2-B2 extending along a second direction D2. The third sub-reference voltage line Vref2-B1 and the fourth sub-reference voltage line Vref2-B2 are electrically connected. Optionally, the third sub-reference voltage line Vref2-B1 and the fourth sub-reference voltage line Vref2-B2 are respectively located in different metal layers, and they can be electrically connected through a connection hole K1. In this embodiment, the connection position of the third sub-reference voltage line Vref2-B1 and the fourth sub-reference voltage line Vref2-B2 is described. In the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, the connection position of the third sub-reference voltage line Vref2-B1 and the fourth sub-reference voltage line Vref2-B2 (such as the position where the connection hole K1 is located) is on the side of the fourth sub-reference voltage line Vref2-B2 away from the first sub-transistor T7-G1. When the first sub-transistor T7-G1 and the adjacent first reset transistor T7 are electrically connected through a connection portion B0, the connection position of the connection portion B0 and the first sub-reference voltage line Vref2-RG1 (such as the position where the connection hole K0 is located) can be set on the side of the fourth sub-reference voltage line Vref2-B2 facing the first sub-transistor T7-G1. Thus, in the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, the connection hole K0 between the first sub-transistor T7-G1 and the first reference voltage line 10, and the connection hole K1 between the third sub-reference voltage line Vref2-B1 and the fourth sub-reference voltage line Vref2-B2 can be respectively arranged on both sides of the fourth sub-reference voltage line Vref2-B2 along the first direction D1. At the same time, the connection hole K2 between the second sub-transistor T7-G2 and the first reference voltage line 10, and the connection hole K3 between the first reset transistor T7-B adjacent to the second sub-transistor T7-G2 and the second reference voltage line 20 can also be respectively arranged on both sides of the fourth sub-reference voltage line Vref2-B2 along the first direction D1. Thus, it is beneficial to improve the overall hole distribution uniformity in the display panel, and thus beneficial to improve the overall display uniformity of the display panel.

[0111] Figure 16Shown is another layout schematic diagram of the circuit column group Z0 where the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 are located. In this embodiment, another connection of the third sub-reference voltage line Vref2-B1 and the fourth sub-reference voltage line Vref2-B2 in the circuit column group Z0 where the fourth sub-reference voltage line Vref2-B2 is located is schematically shown. In the circuit column group Z2 where the fourth sub-reference voltage line Vref2-B2 is located, the first reset transistor T7-B adjacent to the second sub-transistor T7-G2 can be electrically connected to the fourth sub-reference voltage line Vref2-B2 through the via hole K3. At the same time, the via hole K3 can further be electrically connected to the third sub-reference voltage line Vref2-B1. In this way, the electrical connection of the third sub-reference voltage line Vref2-B1, the fourth sub-reference voltage line Vref2-B2, and the first reset transistor T7-B can be achieved through one via hole K3, which is beneficial to simplifying the connection process in the display panel.

[0112] Please refer to Figure 14 , in an alternative embodiment of the present disclosure, the display panel includes a plurality of pixel circuit rows H0 arranged along the second direction D2. The pixel circuit rows H0 include a plurality of pixel circuits arranged along the first direction D1; the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1 are correspondingly provided for the pixel circuit rows H0. In one row of pixel circuit rows H0, along the second direction D2, the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1 are respectively located on both sides of the first end of the first reset transistor T7. The first end of the first reset transistor T7 is the end connected to the first reference voltage line 10 or the second reference voltage line 20. Taking Figure 14 the layout diagram as an example, the first end of the first reset transistor T7 is the upper end in the first reset transistor T7 indicated by the dashed box.

[0113] In the present disclosure, the first reference voltage line 10 includes a first sub-reference voltage line Vref2-RG1 and a second sub-reference voltage line Vref2-RG2 extending along the first direction D1, and the second reference voltage line 20 includes a third sub-reference voltage line Vref2-B1 and a fourth sub-reference voltage line Vref2-B2 extending along the first direction D1. For the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1 extending along the first direction D1, they can be correspondingly arranged with the pixel circuit row H0. That is to say, each pixel circuit row H0 is correspondingly provided with the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1. In this way, it is convenient for the electrical connection between some of the first reset transistors T7 (the first reset transistor T7-B corresponding to the second pixel circuit P2) in the circuit column group Z0 where the second sub-reference voltage line Vref2-RG2 is located and the third sub-reference voltage line Vref2-B1, and at the same time, it is convenient for the electrical connection between the first sub-transistor T7-G1 and some of the first reset transistors T7 (the first reset transistor T7-R corresponding to the third pixel circuit P3) in the circuit column group Z0 where the fourth sub-reference voltage line Vref2-B2 is located and the first sub-reference voltage line Vref2-RG1, so as to realize the reliable reset of the anode of the light-emitting element. At the same time, when each pixel circuit row is correspondingly provided with the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1, it is beneficial to realize the overall wiring uniformity of the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1 in the display panel.

[0114] In the present disclosure, the first end of the first reset transistor T7 is the end connected to the first reference voltage line 10 or the second reference voltage line 20. In this embodiment, it is further defined that in a row of pixel circuit rows H0, the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1 are respectively arranged on both sides of the first end of the first reset transistor T7. In this way, the nearby connection between different first reset transistors T7 and the first sub-reference voltage line Vref2-RG1 or the third sub-reference voltage line Vref2-B1 can be realized, which is beneficial to simplifying the connection difficulty between the first reset transistor T7 and the corresponding reference voltage line.

[0115] Please continue to refer to Figure 14, in an alternative embodiment of the present disclosure, the display panel further includes a plurality of driving control lines S2N / Emit. The driving control lines S2N / Emit extend along a first direction D1 and are arranged along a second direction D2. The driving control lines S2N / Emit are configured to provide control signals to the pixel circuits; at least some of the driving control lines S2N / Emit are disposed in a different layer from the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1; along a direction perpendicular to the plane of the display panel, at least one of the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1 overlaps with the driving control lines S2N / Emit.

[0116] The driving control lines mentioned in the present disclosure can be, for example, control lines that provide control signals to the control terminals of transistors in the pixel circuits, such as Figure 3 in the embodiment, the control signal line S2N that provides a control signal to the gate of the fourth transistor T4, the control signal line Emit that provides a light-emitting control signal to the gates of the first transistor T1 and the sixth transistor T1, etc. It should be noted that only some of the driving control lines are schematically shown in the layout diagram of the present disclosure.

[0117] In the present disclosure, the driving control lines S2N / Emit extend along the first direction D1. When the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1 that extend along the first direction D1 are introduced into the display panel, in order to achieve a reasonable layout of the signal lines extending along the first direction D1, the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1 can be disposed in the same layer and in a different layer from at least some of the driving control lines S2N / Emit. At this time, for the driving control lines and the sub-reference voltage lines disposed in different layers, along a direction perpendicular to the plane of the display panel, at least one of the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1 can overlap with the driving control lines S2N / Emit. In this way, it is beneficial to reduce the space occupied by the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1 and the driving control lines in the second direction D2 in the display panel as a whole, which helps to achieve a more compact pixel arrangement, and thus is beneficial to achieving a higher pixel density under the same physical size, and is beneficial to improving the display resolution and fineness. It should be noted that Figure 14 the embodiment shows a scheme in which the second sub-reference voltage line Vref2-RG1 overlaps with the driving control line S2N, but it is only for illustration and is not limited thereto.

[0118] Figure 17 Shown is a wiring schematic diagram of the first reference voltage line 10 and the second reference voltage line 20 in the display panel. Please refer to Figure 17, in an alternative embodiment of the present disclosure, the first sub-reference voltage line Vref2-RG1 includes a plurality of first sub-voltage lines Vref2-RG11 and a plurality of second sub-voltage lines Vref2-RG12 arranged alternately along the second direction D2; at least one second sub-reference voltage line Vref2-RG2 is electrically connected to the first sub-voltage line Vref2-RG11, and at least one second sub-reference voltage line Vref2-RG2 is electrically connected to the second sub-voltage line Vref2-RG12.

[0119] This embodiment further illustrates the wiring and connection manner of the first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2 in the first reference voltage line 10. Specifically, the first sub-reference voltage line Vref2-RG1 extending along the first direction D1 includes the first sub-voltage lines Vref2-RG11 and the second sub-voltage lines Vref2-RG12 arranged alternately along the second direction D2. For example, the first sub-voltage lines Vref2-RG11 correspond to the pixel circuits in odd rows, and the second sub-voltage lines Vref2-RG12 correspond to the pixel circuits in even rows. Of course, in some other embodiments of the present disclosure, the first sub-voltage lines Vref2-RG11 may also correspond to the pixel circuits in even rows, and the second sub-voltage lines Vref2-RG12 correspond to the pixel circuits in odd rows. Both the first sub-voltage lines Vref2-RG11 and the second sub-voltage lines Vref2-RG12 in the first sub-reference voltage line Vref2-RG1 are used to transmit the first reference voltage signal. Optionally, the first sub-voltage lines Vref2-RG11 and the second sub-voltage lines Vref2-RG12 in the first sub-reference voltage line Vref2-RG1 are arranged on the same layer to simplify the number of film layers in the display panel. Of course, in some other embodiments of the present disclosure, the first sub-voltage lines Vref2-RG11 and the second sub-voltage lines Vref2-RG12 in the first sub-reference voltage line Vref2-RG1 may also be arranged on different layers, and the present disclosure does not specifically limit this.

[0120] In this embodiment, among the second sub-reference voltage lines Vref2-RG2 extending along the second direction D2, at least one second sub-reference voltage line Vref2-RG2 is used to be electrically connected to the first sub-voltage line Vref2-RG11, forming a mesh wiring structure with the first sub-voltage line Vref2-RG11; at least one second sub-reference voltage line Vref2-RG2 is used to be electrically connected to the second sub-voltage line Vref2-RG12, forming another mesh wiring structure with the second sub-voltage line Vref2-RG12, so that the second sub-reference voltage lines Vref2-RG2, the first sub-voltage lines Vref2-RG11, and the second sub-voltage lines Vref2-RG12 in the first reference voltage line 10 form two mesh wiring structures as a whole. In this way, it helps to disperse the current, reduce the voltage drop caused by the line resistance, and thus ensure that relatively stable and uniform first reference voltage signals can be obtained in different regions of the display panel. Moreover, the form of the two mesh wiring structures further enhances the uniformity of the voltage distribution. This design can effectively average the voltage differences on different lines and avoid the situation of too high or too low local voltage. In addition, in the two mesh wiring structures, multiple reference voltage lines and interconnection structures provide redundant power supply paths. If a local fault or interference occurs in a certain line, the current can be compensated through other paths, thereby improving the reliability and anti-interference ability of the entire reference voltage network.

[0121] Figure 18 Shown is another wiring schematic diagram of the first reference voltage line 10 and the second reference voltage line 20 in the display panel. Please refer to Figure 18 , in an alternative embodiment of the present disclosure, the first sub-reference voltage line Vref2-RG1 includes multiple first sub-voltage lines Vref2-RG11 and multiple second sub-voltage lines Vref2-RG12 arranged alternately along the second direction D2; at least one second sub-reference voltage line Vref2-RG2 is electrically connected to both the first sub-voltage line Vref2-RG11 and the second sub-voltage line Vref2-RG12.

[0122] This embodiment further illustrates the wiring and another connection method of the first sub-reference voltage line Vref2-RG1 and the second sub-reference voltage line Vref2-RG2 in the first reference voltage line 10. The difference from Figure 17 is that the sub-voltage lines connected by the second sub-reference voltage line Vref2-RG2 are different, and the same parts will not be repeated. Figure 18In the illustrated embodiment, at least one second sub-reference voltage line Vref2-RG2 is electrically connected to the first sub-voltage line Vref2-RG11 and the second sub-voltage line Vref2-RG12 simultaneously. In this embodiment, it is taken as an example that each second sub-reference voltage line Vref2-RG2 is respectively connected to the first sub-voltage line Vref2-RG11 and the second sub-voltage line Vref2-RG12. In this embodiment, the second sub-reference voltage line Vref2-RG2 extending along the second direction D2 serves as a connection bridge to connect the first sub-voltage line Vref2-RG11 and the second sub-voltage line Vref2-RG12 in different lateral directions. This means that any local voltage fluctuations can be more quickly diffused and averaged along the second sub-reference voltage line Vref2-RG2 extending along the second direction D2 to the circuit, making the voltage distribution and current distribution of the entire reference voltage network more uniform. Especially on large-size or high-resolution panels, this effect is more significant. A more uniform current distribution can also reduce the current density on local circuits, thereby reducing the voltage drop caused by resistance heating and avoiding the formation of local hot spots, improving the reliability and lifespan of the display panel. In addition, each lateral first sub-voltage line Vref2-RG11 and second sub-voltage line Vref2-RG12 is connected to other lateral sub-voltage lines through multiple second sub-reference voltage lines Vref2-RG2 extending along the second direction D2. If a connection point or a certain lateral / longitudinal circuit fails, the current can still flow through other paths, ensuring that the supply of the reference voltage will not be interrupted, thereby improving the fault tolerance and reliability of the entire system. In this embodiment, the connection points between the second sub-reference voltage line Vref2-RG2 and the lateral sub-voltage lines are increased. More interconnection circuits are equivalent to increasing the parallel resistance paths, thereby reducing the equivalent impedance of the entire reference voltage network. Lower impedance helps to stabilize the voltage more quickly and reduce the transient voltage fluctuations.

[0123] Please continue to refer to Figure 17 , in an alternative embodiment of the present disclosure, the third sub-reference voltage line Vref2-B1 includes a plurality of third sub-voltage lines Vref2-B11 and a plurality of fourth sub-voltage lines Vref2-B12 arranged alternately along the second direction D2; at least one fourth sub-reference voltage line Vref2-B2 is electrically connected to the third sub-voltage line Vref2-B11, and at least one fourth sub-reference voltage line Vref2-B2 is electrically connected to the fourth sub-voltage line Vref2-B12.

[0124] This embodiment further illustrates the wiring and connection manner of the third sub-reference voltage line Vref2-B1 and the fourth sub-reference voltage line Vref2-B2 in the second reference voltage line 20. Specifically, the third sub-reference voltage line Vref2-B1 extending along the first direction D1 includes third sub-voltage lines Vref2-B11 and fourth sub-voltage lines Vref2-B12 arranged alternately along the second direction D2. For example, the third sub-voltage lines Vref2-B11 correspond to the pixel circuits in odd rows, and the fourth sub-voltage lines Vref2-B12 correspond to the pixel circuits in even rows. Of course, in some other embodiments of the present disclosure, the third sub-voltage lines Vref2-B11 may also correspond to the pixel circuits in even rows, and the fourth sub-voltage lines Vref2-B12 correspond to the pixel circuits in odd rows. Both the third sub-voltage lines Vref2-B11 and the fourth sub-voltage lines Vref2-B12 in the third sub-reference voltage line Vref2-B1 are used to transmit the second reference voltage signal. Optionally, the third sub-voltage lines Vref2-B11 and the fourth sub-voltage lines Vref2-B12 in the third sub-reference voltage line Vref2-B1 are arranged on the same layer to simplify the number of film layers in the display panel. Of course, in some other embodiments of the present disclosure, the third sub-voltage lines Vref2-B11 and the fourth sub-voltage lines Vref2-B12 in the third sub-reference voltage line Vref2-B1 may also be arranged on different layers, and the present disclosure does not specifically limit this.

[0125] In this embodiment, in the fourth sub-reference voltage line Vref2-B2 extending along the second direction D2, at least one fourth sub-reference voltage line Vref2-B2 is used to be electrically connected to the third sub-voltage line Vref2-B11 to form a mesh wiring structure with the third sub-voltage line Vref2-B11; at least one fourth sub-reference voltage line Vref2-B2 is used to be electrically connected to the fourth sub-voltage line Vref2-B12 to form another mesh wiring structure with the fourth sub-voltage line Vref2-B12, so that the fourth sub-reference voltage line Vref2-B2, the third sub-voltage line Vref2-B11, and the fourth sub-voltage line Vref2-B12 in the second reference voltage line 20 as a whole form two mesh wiring structures. In this way, it helps to disperse the current, reduce the voltage drop caused by the line resistance, and thus ensure that relatively stable and uniform second reference voltage signals can be obtained in different regions of the display panel. Moreover, the form of the two mesh wiring structures further enhances the uniformity of the voltage distribution. This design can effectively average the voltage differences on different lines and avoid the situation of too high or too low local voltage. In addition, in the two mesh wiring structures, multiple reference voltage lines and interconnection structures provide redundant power supply paths. If a local fault or interference occurs in a certain line, the current can be compensated through other paths, thereby improving the reliability and anti-interference ability of the entire reference voltage network.

[0126] Please continue to refer to Figure 18 , in an alternative embodiment of the present disclosure, the third sub-reference voltage line Vref2-B1 includes a plurality of third sub-voltage lines Vref2-B11 and a plurality of fourth sub-voltage lines Vref2-B12 that are alternately arranged along the second direction D2; at least one fourth sub-reference voltage line Vref2-B2 is electrically connected to both the third sub-voltage line Vref2-B11 and the fourth sub-voltage line Vref2-B12.

[0127] This embodiment further illustrates the wiring and another connection method of the third sub-reference voltage line Vref2-B1 and the fourth sub-reference voltage line Vref2-B2 in the second reference voltage line 20. The difference from Figure 17 is that the sub-voltage lines connected by the fourth sub-reference voltage line Vref2-B2 are different, and the same parts will not be repeated. Figure 18 In the illustrated embodiment, at least one fourth sub-reference voltage line Vref2-B2 is electrically connected to both the third sub-voltage line Vref2-B11 and the fourth sub-voltage line Vref2-B12. In this embodiment, each fourth sub-reference voltage line Vref2-B2 is respectively connected to the third sub-voltage line Vref2-B11 and the fourth sub-voltage line Vref2-B12 as an example for illustration. In this embodiment, the fourth sub-reference voltage line Vref2-B2 extending along the second direction D2 serves as a connection bridge to connect the third sub-voltage lines Vref2-B11 and the fourth sub-voltage lines Vref2-B12 in different lateral directions. This means that any local voltage fluctuations can spread and be averaged along the fourth sub-reference voltage line Vref2-B2 extending along the second direction D2 to the circuit more quickly, making the voltage distribution and current distribution of the entire reference voltage network more uniform. Especially on large-size or high-resolution panels, this effect is more significant. A more uniform current distribution can also reduce the current density on local circuits, thereby reducing the voltage drop caused by resistive heating and avoiding the formation of local hot spots, improving the reliability and lifespan of the display panel. In addition, each lateral third sub-voltage line Vref2-B11 and fourth sub-voltage line Vref2-B12 is connected to other lateral sub-voltage lines through a plurality of fourth sub-reference voltage lines Vref2-B2 extending along the second direction D2. If a connection point or a certain lateral / longitudinal circuit fails, the current can still flow through other paths, ensuring that the supply of the reference voltage will not be interrupted, thereby improving the fault tolerance and reliability of the entire system. In this embodiment, the connection points of the fourth sub-reference voltage line Vref2-B2 and the lateral sub-voltage lines are increased. More interconnection lines are equivalent to increasing the parallel resistance paths, thereby reducing the equivalent impedance of the entire reference voltage network. Lower impedance helps to stabilize the voltage more quickly and reduce the transient voltage fluctuations.

[0128] Figure 17 In the illustrated embodiment, a second sub-reference voltage line Vref2-RG2 is only connected to one of a first sub-voltage line Vref2-RG11 and a second sub-voltage line Vref2-RG12 to form two mesh wiring structures. A fourth sub-reference voltage line Vref2-B2 is only connected to one of a third sub-voltage line Vref2-B11 and a fourth sub-voltage line Vref2-B12 to form two mesh wiring structures. That is, a first reference voltage line 10 is a double-mesh wiring structure, and a second reference voltage line 20 is also a double-mesh wiring structure. Thus, it is beneficial to achieve uniform arrangement of connection holes in the display panel and improve the overall display uniformity of the display panel.

[0129] Figure 18 In the illustrated embodiment, a second sub-reference voltage line Vref2-RG2 is electrically connected to both a first sub-voltage line Vref2-RG11 and a second sub-voltage line Vref2-RG12 to form a mesh wiring structure. A fourth sub-reference voltage line Vref2-B2 is electrically connected to both a third sub-voltage line Vref2-B11 and a fourth sub-voltage line Vref2-B12 to form a mesh wiring structure. That is, both the first reference voltage line 10 and the second reference voltage line 20 are single-mesh wiring structures. Thus, the uniform arrangement of connection holes in the display panel can also be achieved, and the overall display uniformity of the display panel can be improved.

[0130] In some other alternative embodiments of the present disclosure, when the first reference voltage line 10 adopts a double-mesh wiring structure, the second reference voltage line 20 may also adopt a single-mesh wiring structure. When the second reference voltage line 20 adopts a double-mesh wiring structure, the first reference voltage line 10 may also adopt a single-mesh wiring structure. The present disclosure does not make specific limitations thereto.

[0131] Figure 19 Shown is a schematic layout diagram of a second sub-reference voltage line Vref2-RG2, a fourth sub-reference voltage line Vref2-B2, a third reference voltage line Vref1, and a fourth reference voltage line DVH. It should be noted that, for clearly showing a sub-line and a second sub-line Vref1-2 in the third reference voltage line Vref1 and a third sub-line DVH1 and a fourth sub-line DVH2 in the fourth reference voltage line DVH, Figure 19 in the illustrated embodiment, a first sub-reference voltage line Vref2-RG1 extending along a first direction D1 in the first reference voltage line 10 is not shown, nor is a third sub-reference voltage line Vref2-B1 extending along the first direction D1 in the second reference voltage line 20. For the layout of the first sub-reference voltage line Vref2-RG1 and the third sub-reference voltage line Vref2-B1, reference can be made to Figure 17 and Figure 18 .

[0132] Please refer to Figure 19 , in an alternative embodiment of the present disclosure, the display panel further includes a third reference voltage line Vref1 and a fourth reference voltage line DVH. The third reference voltage line Vref1 is configured to provide a gate reset signal to the gate of the driving transistor in the pixel circuit, and the fourth reference voltage line DVH is configured to provide a bias signal to the first or second pole of the driving transistor in the pixel circuit. The third reference voltage line Vref1 includes a first sub-line Vref1-1 extending along a first direction D1 and a second sub-line Vref1-2 extending along a second direction D2, and the first sub-line Vref1-1 and the second sub-line Vref1-2 are electrically connected; the fourth reference voltage line DVH includes a third sub-line DVH1 extending along the first direction D1 and a fourth sub-line DVH2 extending along the second direction D2, and the third sub-line DVH1 and the fourth sub-line DVH2 are electrically connected. The second sub-reference voltage line Vref2-RG2, the fourth sub-reference voltage line Vref2-B2, the second sub-line Vref1-2, and the fourth sub-line DVH2 respectively correspond to different circuit column groups Z0.

[0133] In this embodiment, the first sub-line Vref1-1 extending along the first direction D1 and the second sub-line Vref1-2 extending along the second direction D2 in the third reference voltage line Vref1 form a mesh wiring structure, and the third sub-line DVH1 extending along the first direction D1 and the fourth sub-line DVH2 extending along the second direction D2 in the fourth reference voltage line DVH form another mesh wiring structure. Adopting the form of the mesh wiring structure is beneficial to reducing the overall impedance of the third reference voltage line Vref1 and the fourth reference voltage line DVH, helps to disperse the current, and reduces the voltage drop caused by the line resistance, so as to ensure that relatively stable and uniform gate reset signals and bias signals can be obtained in different regions of the display panel. When the first reference voltage line 10, the second reference voltage line 20, the third reference voltage line Vref1, and the fourth reference voltage line DVH all adopt the mesh wiring structure, it is also beneficial to improve the overall wiring uniformity of the display panel, thereby being beneficial to improving the display uniformity of the display panel.

[0134] When the first reference voltage line 10, the second reference voltage line 20, the third reference voltage line Vref1, and the fourth reference voltage line DVH all adopt a mesh wiring structure, the first reference voltage line 10 includes a second sub-reference voltage line Vref2-RG2 extending along the second direction D2, the second reference voltage line 20 includes a fourth sub-reference voltage line Vref2-B2 extending along the second direction D2, the third reference voltage line Vref1 includes a second sub-line Vref1-2 extending along the second direction D2, and the fourth reference voltage line DVH includes a fourth sub-line DVH2 extending along the second direction D2. At this time, corresponding the second sub-reference voltage line Vref2-RG2, the fourth sub-reference voltage line Vref2-B2, the second sub-line Vref1-2, and the fourth sub-line DVH2 to different circuit column groups Z0 respectively is beneficial to improving the wiring uniformity of the traces extending along the second direction D2 of the display panel, thereby being beneficial to improving the overall display uniformity of the display panel. At the same time, arranging the signal lines transmitting different reference voltage signals separately in different circuit column groups Z0 can reduce the capacitive coupling and electromagnetic interference between these signal lines and reduce the risk of signal crosstalk.

[0135] Please refer to Figure 17 and Figure 18 , Figure 17 shown in the figure is another layout schematic diagram of the second sub-reference voltage line Vref2-RG2, the fourth sub-reference voltage line Vref2-B2, the third reference voltage line Vref1, and the fourth reference voltage line DVH. In an optional implementation manner of the present disclosure, the display panel includes a plurality of reference line groups A0 arranged along the first direction D1, and the reference line group A0 includes four reference voltage lines, namely the second sub-reference voltage line Vref2-RG2, the fourth sub-reference voltage line Vref2-B2, the second sub-line Vref1-2, and the fourth sub-line DVH2.

[0136] Please refer to Figure 18 , in different reference line groups A0, the arrangement order of the four reference voltage lines is the same. For example, the arrangement of the four reference voltage lines is shown as the fourth sub-reference voltage line Vref2-B2, the second sub-line Vref1-2, the second sub-reference voltage line Vref2-RG2, and the fourth sub-line DVH2 arranged in sequence. Of course, the arrangement manner here is only for illustration and does not limit the arrangement order of the four reference voltage lines. When the four reference voltage lines are arranged in a fixed arrangement order in different reference line groups A0, it is beneficial to facilitate the driving chip to output and control these signals according to a specific timing and simplify the design of the driving control logic. Of course, Figure 18 the arrangement manner of the four reference voltage lines shown in the reference line group A0 is only for illustration, and the present disclosure does not specifically limit this. In some other embodiments, the arrangement manner of the four reference voltage lines can also be selected as others.

[0137] In some other embodiments of the present disclosure, please refer to Figure 17 , in the adjacent reference line groups A1 and A2, the arrangement positions of the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 are interchanged, and the arrangement positions of the second sub-line Vref1-2 and the fourth sub-line DVH2 are the same. For example, in two adjacent reference line groups A0, in one of the reference line groups A1, the arrangement of the four reference voltage lines is shown as the fourth sub-reference voltage line Vref2-B2, the second sub-reference voltage line Vref2-RG2, the second sub-line Vref1-2, and the fourth sub-line DVH2 arranged in sequence. In the other reference line group A2, the arrangement of the four reference voltage lines is shown as the second sub-reference voltage line Vref2-RG2, the fourth sub-reference voltage line Vref2-B2, the second sub-line Vref1-2, and the fourth sub-line DVH2 arranged in sequence. This is equivalent to interchanging the arrangement positions of the fourth sub-reference voltage line Vref2-B2 and the second sub-reference voltage line Vref2-RG2 on the basis of the previous reference line group A0, while keeping the arrangement positions of the second sub-line Vref1-2 and the fourth sub-line DVH2 unchanged. Of course, Figure 17 The arrangement of the four reference voltage lines shown in the reference line group A0 is only for illustration, and the present disclosure does not specifically limit this. In some other embodiments, the arrangement of the four reference voltage lines can also be selected as others.

[0138] Considering that in the first reference voltage signal and the second reference voltage signal provided to the light-emitting element, even a slight difference in the signals may affect the initial state of the light-emitting element, thereby having a subtle impact on the final brightness output and color performance. In this embodiment, the arrangement positions of the second sub-reference voltage line Vref2-RG2 and the fourth sub-reference voltage line Vref2-B2 in the adjacent reference line groups A0 are interchanged, and the regular position interchange can be used to achieve a more uniform or desired color performance macroscopically.

[0139] Figure 20 The figure shows a schematic connection diagram of the reference voltage lines in the display panel and the signal lines in the border area. Please refer to Figure 20, in an alternative embodiment of the present disclosure, the display panel includes a display area AA, a first border area NA1, and a second border area NA2. The first border area NA1 is located on both sides of the display area AA along the first direction D1, and the second border area NA2 is located on one side of the display area along the second direction D2. The display panel includes a first main line 01, a second main line 02, a third main line 03, and a fourth main line 04. The first main line 01 is electrically connected to the first reference voltage line 10, the second main line 02 is electrically connected to the second reference voltage line 20, the third main line 03 is electrically connected to the third reference voltage line Vref1, and the fourth main line 04 is electrically connected to the fourth reference voltage line DVH; at least two of the first main line 01, the second main line 02, the third main line 03, and the fourth main line 04 are located in the first border area NA1, and the other two are located in the second border area NA2.

[0140] Considering that the first reference voltage line 10, the second reference voltage line 20, the third reference voltage line Vref1, and the fourth reference voltage line DVH in the display panel all need to obtain corresponding reference voltage signals through a driving chip, therefore, these reference voltage lines ultimately need to be electrically connected to the driving chip. Optionally, the driving chip may be located in the bonding area of the display panel. Since the number of reference voltage lines is large and the reference voltage lines are all in a mesh wiring structure, the four reference voltage lines can be respectively electrically connected to the signal lines in the border area and then connected to the bonding area through the corresponding signal lines. For example, the first main line 01 and the second main line 02 respectively connected to the first reference voltage line 10 and the second reference voltage line 20 can be arranged in the second border area NA2 of the display panel, and the third main line 03 and the fourth main line 04 respectively connected to the third reference voltage line Vref1 and the fourth reference voltage line DVH can be arranged in the first border area NA1, so that each main line is reasonably distributed in the border area of the display panel, avoiding concentration in a certain border area and causing some borders to be too wide and affecting the narrow border design. Therefore, the method of separately arranging different fixed main lines in the first border area NA1 and the second border area NA2 is beneficial to realizing the narrow border design of the display panel.

[0141] It should be noted that when two main lines are set in the second border area NA2 of the display panel and the bonding area is also located in the second border area NA2, the signal transmission distance between the main lines and the bonding area in the second border area NA2 is relatively small, which is conducive to realizing the fast and effective transmission of corresponding signals. When two main lines are set in the first border area NA1 of the display panel, since the signal transmission distance between the first border area NA1 and the bonding area is relatively large, two corresponding main lines can be respectively set in the two first border areas NA1. For example, the third main line 03 is set in the left first border area NA1 and the right first border area NA1 at the same time, and both of the two third main lines 03 can be electrically connected to the bonding area. At the same time, the fourth main line 04 is set in the left first border area NA1 and the right first border area NA1 at the same time, and both of the two fourth main lines 04 can be electrically connected to the bonding area. In this way, the corresponding reference voltage signal is transmitted to the third reference voltage line Vref1 through the two third main lines 03, and the corresponding reference voltage signal is transmitted to the fourth reference voltage line DVH through the two fourth main lines 04, which is also conducive to improving the signal transmission rate of the third main line 03 and the fourth main line 04 to the corresponding third reference voltage line Vref1 and the fourth reference voltage line DVH.

[0142] It should also be noted that this embodiment only shows the scheme in which the first main line 01 and the second main line 02 are located in the second border area NA2, and the third main line 03 and the fourth main line 04 are located in the first border area NA1. In some other embodiments of the present disclosure, the positions of the four main lines can be flexibly adjusted. For example, the first main line 01 and the second main line 02 are set in the first border area NA1, and the third main line 03 and the fourth main line 04 are set in the second border area NA2, etc. The present disclosure does not limit this.

[0143] Based on the same inventive concept, the present disclosure also provides a display device. Figure 21 Shown is a schematic structural diagram of a display device 200 provided by an embodiment of the present disclosure. Please refer to Figure 21 , the display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided by the embodiment of the present disclosure can be any electronic device with a display function such as a touch display screen, a mobile phone, a tablet computer, a laptop computer, an e-reader or a television. The display device 200 provided by the embodiment of the present disclosure has the beneficial effects of the display panel provided by the embodiment of the present disclosure. Specifically, reference can be made to the specific descriptions of the display panel in the above embodiments, and details are not described herein again.

[0144] It can be understood that Figure 21 only the shape of the display device 200 is schematically shown by taking a rectangular structure as an example. In some other embodiments of the present disclosure, the display device 200 can also be embodied as a circular shape, an oval shape or any other feasible shape. The present disclosure does not specifically limit this.

[0145] In summary, the technical solutions provided by the embodiments of the present disclosure have the following advantages:

[0146] In the display panel and the display device provided by the embodiments of the present disclosure, considering that light-emitting elements of at least two different light-emitting colors have different sensitivities to temperature due to different material characteristics, a first reference voltage line and a second reference voltage line are respectively introduced. The first reference voltage signal and the second reference voltage signal can be respectively provided through the first reference voltage line and the second reference voltage line to reset the anodes of different light-emitting elements. In this way, the initial states of different light-emitting elements before light emission can be controlled more precisely. For example, the reference voltage corresponding to the light-emitting element that is more sensitive to temperature can be adjusted to ensure a more stable starting point at different temperatures, thereby reducing the brightness drift caused by temperature changes, ultimately reducing the offset of white balance, and improving the problem of heating color cast. Moreover, by differentiating the design of the first reference voltage signal and the second reference voltage signal, more appropriate initial conditions can be provided specifically for light-emitting elements with large differences in material characteristics during the anode reset stage, so that the subsequent driving voltage can more accurately control the brightness output of each color sub-pixel, thereby better maintaining the target color ratio and reducing the color deviation caused by temperature.

[0147] In addition, considering that when displaying low gray levels, the driving voltage applied to the light-emitting element is very close to the turn-on voltage of the light-emitting element, and a tiny voltage difference may cause obvious brightness changes or unevenness. The present disclosure provides optimized reference voltage signals (such as more accurate reset voltages) for different light-emitting elements through the first reference voltage line and the second reference voltage line, which can ensure that different light-emitting elements have predictable starting states at low gray levels, can more precisely control the output of different light-emitting elements at low brightness, ensure that the light-emitting elements can accurately respond to tiny driving voltage changes, thereby helping to reduce the problem of low gray level color cast, precisely control the starting states of different light-emitting elements at low brightness, and avoid the problem of light stealing caused by signal interference between different light-emitting elements when the display panel displays a monochromatic picture.

[0148] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0149] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, It includes a light-emitting element and a pixel circuit connected to the light-emitting element. The light-emitting element includes a first light-emitting element, a second light-emitting element, and a third light-emitting element, and the first light-emitting element, the second light-emitting element, and the third light-emitting element have different light-emitting colors; The pixel circuit includes a first pixel circuit, a second pixel circuit, and a third pixel circuit. The first pixel circuit is electrically connected to the first light-emitting element, the second pixel circuit is electrically connected to the second light-emitting element, and the third pixel circuit is electrically connected to the third light-emitting element; The display panel further includes a first reference voltage line and a second reference voltage line. The first reference voltage line is configured to provide a first reference voltage signal to the first light-emitting element and the third light-emitting element respectively through the first pixel circuit and the third pixel circuit, and the second reference voltage line is configured to provide a second reference voltage signal to the second light-emitting element through the second pixel circuit; The voltage value of the first reference voltage signal is different from the voltage value of the second reference voltage signal; The first reference voltage line includes a first sub-reference voltage line extending in a first direction and a second sub-reference voltage line extending in a second direction, and the first sub-reference voltage line and the second sub-reference voltage line are electrically connected; The second reference voltage line includes a third sub-reference voltage line extending in the first direction and a fourth sub-reference voltage line extending in the second direction, and the third sub-reference voltage line and the fourth sub-reference voltage line are electrically connected; the first direction and the second direction intersect.

2. The display panel according to claim 1, wherein The turn-on voltages of the first light-emitting element and the third light-emitting element are both smaller than the turn-on voltage of the second light-emitting element, and the voltage value of the first reference voltage signal is smaller than the voltage value of the second reference voltage signal.

3. The display panel according to claim 2, wherein The first light-emitting element is one of a red light-emitting element and a blue light-emitting element, the second light-emitting element is the other of the red light-emitting element and the blue light-emitting element, and the third light-emitting element is a green light-emitting element.

4. The display panel according to claim 1, wherein The display panel includes a plurality of first-type circuit columns and second-type circuit columns alternately arranged in the first direction. Among them, the first-type circuit columns include the first pixel circuit and the second pixel circuit alternately arranged in the second direction, and the second-type circuit columns include a plurality of the third pixel circuits arranged in the second direction; The display panel includes a plurality of circuit column groups arranged in the first direction. One circuit column group includes one first-type circuit column and one second-type circuit column adjacent to each other in the first direction; the second sub-reference voltage line and the fourth sub-reference voltage line are respectively arranged corresponding to different circuit column groups.

5. The display panel according to claim 4, wherein In the circuit column group where the second sub-reference voltage line is located, at least one of the first pixel circuit and the third pixel circuit is electrically connected to the second sub-reference voltage line, and the second pixel circuit is electrically connected to the third sub-reference voltage line.

6. The display panel according to claim 5, characterized in that, In the circuit column group where the second sub-reference voltage line is located, the first pixel circuit is electrically connected to the first sub-reference voltage line, and the third pixel circuit is electrically connected to the second sub-reference voltage line.

7. The display panel according to claim 5, wherein In the circuit column group where the second sub-reference voltage line is located, both the first pixel circuit and the third pixel circuit are electrically connected to the second sub-reference voltage line.

8. The display panel according to claim 4, wherein In the circuit column group where the fourth sub-reference voltage line is located, the second pixel circuit is electrically connected to the fourth sub-reference voltage line, and the first pixel circuit and the third pixel circuit are electrically connected to the first sub-reference voltage line.

9. The display panel according to claim 4, wherein, The pixel circuit includes a first reset transistor. A first end of the first reset transistor is connected to the first reference voltage line or the second reference voltage line, and a second end of the first reset transistor is connected to an anode of the light-emitting element. In the second type of circuit column, the first reset transistors corresponding to the third pixel circuits adjacent along the second direction are a first sub-transistor and a second sub-transistor respectively. In the circuit column group, along the first direction, the first sub-transistor is adjacent to the first reset transistor in the first pixel circuit; the second sub-transistor is adjacent to the first reset transistor in the second pixel circuit.

10. The display panel according to claim 9, wherein In the circuit column group corresponding to the second sub-reference voltage line, the first reset transistor and the adjacent first sub-transistor or second sub-transistor are respectively located on two sides of the second sub-reference voltage line. In the circuit column group where the fourth sub-reference voltage line is located, the first reset transistor and the adjacent first sub-transistor or second sub-transistor are respectively located on two sides of the fourth sub-reference voltage line.

11. The display panel according to claim 9, wherein In the circuit column group, a first end of the first sub-transistor and a first end of the first reset transistor adjacent to the first sub-transistor are electrically connected through a connection part.

12. The display panel according to claim 11, wherein In the circuit column group where the second sub-reference voltage line is located, the connection part is electrically connected to the second sub-reference voltage line through a connection hole.

13. The display panel according to claim 12, wherein The connection part is also electrically connected to the first sub-reference voltage line through the connection hole.

14. The display panel according to claim 11, wherein, In the circuit column group where the fourth sub-reference voltage line is located, the connection part is electrically connected to the first sub-reference voltage line.

15. The display panel according to claim 9, characterized in that, In the circuit column group, the first sub-transistor and the first reset transistor adjacent to the first sub-transistor are respectively electrically connected to the first reference voltage line.

16. The display panel according to claim 9, wherein In the circuit column group where the second sub-reference voltage line is located, the first sub-transistor is electrically connected to the second sub-reference voltage line, and the first reset transistor adjacent to the first sub-transistor is electrically connected to the first sub-reference voltage line.

17. The display panel according to claim 9, wherein In the circuit column group where the second sub-reference voltage line is located, the second sub-transistor is electrically connected to the second sub-reference voltage line, and the first reset transistor adjacent to the second sub-transistor is electrically connected to the third sub-reference voltage line.

18. The display panel according to claim 9, characterized in that, In the circuit column group where the fourth sub-reference voltage line is located, the second sub-transistor is electrically connected to the first sub-reference voltage line, and the first reset transistor adjacent to the second sub-transistor is electrically connected to the fourth sub-reference voltage line.

19. The display panel according to claim 9, wherein In the circuit column group where the fourth sub-reference voltage line is located, on a side of the fourth sub-reference voltage line away from the first sub-transistor, the fourth sub-reference voltage line is electrically connected to the third sub-reference voltage line.

20. The display panel according to claim 9, wherein The display panel includes a plurality of pixel circuit rows arranged along the second direction, and the pixel circuit rows include a plurality of the pixel circuits arranged along the first direction; The first sub-reference voltage line and the third sub-reference voltage line are correspondingly arranged for the pixel circuit rows. In one pixel circuit row, along the second direction, the first sub-reference voltage line and the third sub-reference voltage line are respectively located on both sides of the first end of the first reset transistor.

21. The display panel according to claim 1, wherein The first sub-reference voltage line includes a plurality of first sub-voltage lines and a plurality of second sub-voltage lines alternately arranged along the second direction; At least one of the second sub-reference voltage lines is electrically connected to the first sub-voltage line, and at least one of the second sub-reference voltage lines is electrically connected to the second sub-voltage line.

22. The display panel according to claim 1, wherein, The first sub-reference voltage line includes a plurality of first sub-voltage lines and a plurality of second sub-voltage lines alternately arranged along the second direction; At least one of the second sub-reference voltage lines is electrically connected to both the first sub-voltage line and the second sub-voltage line.

23. The display panel according to claim 1, wherein The third sub-reference voltage line includes a plurality of third sub-voltage lines and a plurality of fourth sub-voltage lines alternately arranged along the second direction; At least one of the fourth sub-reference voltage lines is electrically connected to the third sub-voltage line, and at least one of the fourth sub-reference voltage lines is electrically connected to the fourth sub-voltage line.

24. The display panel according to claim 1, wherein, The third sub-reference voltage line includes a plurality of third sub-voltage lines and a plurality of fourth sub-voltage lines alternately arranged along the second direction; At least one of the fourth sub-reference voltage lines is electrically connected to both the third sub-voltage line and the fourth sub-voltage line.

25. The display panel according to claim 1, wherein The display panel further includes a plurality of driving control lines, the driving control lines extend along the first direction and are arranged along the second direction, and the driving control lines are configured to provide control signals to the pixel circuits; At least part of the driving control lines are arranged in a different layer from the first sub-reference voltage line and the third sub-reference voltage line; along the direction perpendicular to the plane where the display panel is located, at least one of the first sub-reference voltage line and the third sub-reference voltage line overlaps with the driving control lines.

26. The display panel according to claim 4, wherein, The display panel further includes a third reference voltage line and a fourth reference voltage line, the third reference voltage line is configured to provide a gate reset signal to the gate of the driving transistor in the pixel circuit, and the fourth reference voltage line is configured to provide a bias signal to the first pole or the second pole of the driving transistor in the pixel circuit; The third reference voltage line includes a first sub-line extending along the first direction and a second sub-line extending along the second direction, and the first sub-line and the second sub-line are electrically connected; the fourth reference voltage line includes a third sub-line extending along the first direction and a fourth sub-line extending along the second direction, and the third sub-line and the fourth sub-line are electrically connected; The second sub-reference voltage line, the fourth sub-reference voltage line, the second sub-line and the fourth sub-line respectively correspond to different circuit column groups.

27. The display panel according to claim 26, wherein, The display panel includes a plurality of reference line groups arranged along the first direction, and each reference line group includes four reference voltage lines, namely the second sub-reference voltage line, the fourth sub-reference voltage line, the second sub-line, and the fourth sub-line; In different reference line groups, the arrangement order of the four reference voltage lines is the same; alternatively, in adjacent reference line groups, the arrangement positions of the second sub-reference voltage line and the fourth sub-reference voltage line are interchanged, and the arrangement positions of the second sub-line and the fourth sub-line are the same.

28. The display panel according to claim 26, wherein It includes a display area, a first border area, and a second border area. The first border area is located on both sides of the display area along the first direction, and the second border area is located on one side of the display area along the second direction; The display panel includes a first main line, a second main line, a third main line, and a fourth main line. The first main line is electrically connected to the first reference voltage line, the second main line is electrically connected to the second reference voltage line, the third main line is electrically connected to the third reference voltage line, and the fourth main line is electrically connected to the fourth reference voltage line; At least two of the first main line, the second main line, the third main line, and the fourth main line are located in the first border area, and the other two are located in the second border area.

29. A display device, characterized in that, It includes the display panel according to any one of claims 1 to 28.

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