Semiconductor devices and methods of using conductive layer stacks with graphene core shells and interconnecting semiconductor assemblies

Abstract

Semiconductor devices and methods of using a conductive layer stack having a graphene core shell and interconnecting semiconductor assemblies are disclosed. A semiconductor device has a plurality of stacked semiconductor components. Each semiconductor assembly has a first electrical component and an electrical connector disposed adjacent to the first electrical component. A conductive layer having a graphene core shell is formed between the first electrical component and the electrical connector. The graphene core shell has a copper core or a silver core. The conductive layer has a plurality of cores covered by graphene, and the graphene is interconnected within the conductive layer to form an electrical path. The conductive layer has a matrix of the type of thermoset or polymer or composite epoxy resin. The second electrical component is disposed adjacent a side of the electrical connector opposite the first electrical component. An encapsulant is deposited around the first electrical component, the second electrical component, and the electrical connector. A conductive layer is formed over the encapsulant between the second electrical component and the electrical connector.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly, to semiconductor devices and methods of stacking and interconnecting semiconductor components using a conductive layer and electrical connectors having a graphene core-shell. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communication, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

[0003] Semiconductor devices, especially in high-frequency applications such as radio frequency (RF) wireless communication, often include one or more integrated passive devices (IPDs) to perform necessary electrical functions. Multiple semiconductor dies and IPDs can be integrated into a system-in-package (SiP) module for higher density and extended electrical functionality in a small space. Within the SIP module, the semiconductor dies and IPDs are deployed on a substrate for structural support and electrical connection through vertical and horizontal interconnect structures. An encapsulant is deposited over the semiconductor dies, IPDs, and substrate.

[0004] SiP modules can be stacked for higher device integration and functionality. The stacked modules need to be interconnected. Common interconnect structures use multiple conductive layers sintered by heating. However, thermal sintering is time-consuming and reduces manufacturing productivity and device yield. Brief Description of the Drawings

[0005] Figures 1a to 1c Illustrates a semiconductor wafer having multiple semiconductor dies separated by saw tracks;

[0006] Figures 2a to 2n Illustrates a process of stacking and interconnecting semiconductor components using a conductive layer and electrical connectors having a graphene core-shell;

[0007] Figures 3a to 3b Illustrates further details of the graphene core-shell within the conductive layer;

[0008] Figures 4a to 4c Illustrates a process of forming the graphene core-shell;

[0009] Figures 5a to 5c Illustrates further details of stacking and interconnecting semiconductor components using a conductive layer and electrical connectors having a graphene core-shell;

[0010] Figures 6a to 6fIllustrated is another process of stacking and interconnecting semiconductor components using a conductive layer and an electrical connector having a graphene core-shell;

[0011] Figure 7 Illustrated is stacking and interconnecting a semiconductor component from Figures 5a to 5c with a semiconductor package from Figures 2a to 2n ;

[0012] Figures 8a to 8b Illustrated are further details of stacking and interconnecting a semiconductor component from Figure 7 with an interconnect substrate;

[0013] Figures 9a to 9b Illustrated is depositing a conductive material on an encapsulant using EHD jet printing;

[0014] Figure 10 Illustrated is depositing a conductive material on an encapsulant using aerosol jet printing; and

[0015] Figure 11 Illustrated is a printed circuit board (PCB) having different types of packages deployed on a surface of the PCB. DETAILED DESCRIPTION

[0016] In the following description, the present invention is described in one or more embodiments with reference to the figures, in which like numerals represent the same or similar elements throughout. Although the present invention is described in terms of the best mode contemplated for carrying out the present invention, those skilled in the art will appreciate that the present invention is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the drawings. The features shown in the figures are not necessarily drawn to scale. Elements having similar functions in the figures are assigned the same reference numerals. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word and can thus refer to both a single semiconductor device and multiple semiconductor devices.

[0017] Generally, two complex manufacturing processes are used to fabricate semiconductor devices: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors create the relationships between voltage and current required to perform circuit functions.

[0018] Backend manufacturing refers to cutting or singulating a finished wafer into individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor die, the wafer is scribed and broken along non-functional regions of the wafer, known as saw streets or scribe lines. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor die are placed on a package substrate, which includes pins or contact pads for interconnection with other system components. Then, the contact pads formed on the semiconductor die are connected to the contact pads within the package. The electrical connection can be made using conductive layers, bumps, pillar bumps, conductive solder paste, or wire bonding. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. Then, the finished package is inserted into an electrical system and the functionality of the semiconductor device is made available to other system components.

[0019] Figure 1a A semiconductor wafer 100 having a substrate base material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support, is shown. A plurality of semiconductor die or electrical components 104 are formed on the wafer 100 and separated by non-active inter-die wafer regions or saw streets 106. The saw streets 106 provide a cutting area to singulate the semiconductor wafer 100 into individual semiconductor die 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100 - 450 millimeters (mm). Alternatively, the wafer 100 can be a molded surface, organic or inorganic substrate, or a target substrate suitable for graphene transfer.

[0020] Figure 1b A cross-sectional view of a portion of the semiconductor wafer 100 is shown. Each semiconductor die 104 has a backside or non-active surface 108 and an active surface 110, which contains analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and functionality of the die. For example, the circuitry can include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement an analog or digital circuit, such as a digital signal processor (DSP), application specific integrated circuit (ASIC), memory, or other signal processing circuit. In one embodiment, the semiconductor die 104 can be a memory or a memory controller. The semiconductor die 104 can also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0021] The conductive layer 112 is formed on the active surface 110 by physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper, tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 operates as a contact pad for a circuit electrically connected to the active surface 110. In one embodiment, each semiconductor die 104 has conductive layers 112a, 112b, 112c, and 112d.

[0022] In Figure 1c , the semiconductor wafer 100 is singulated into individual semiconductor dies 104 by a saw blade or a laser cutting tool 118 through the saw streets 106. The individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies or known good units (KGD / KGU) after singulation.

[0023] Figures 2a to 2n Illustrated is a process of stacking and interconnecting semiconductor components using a conductive layer and an electrical connector having a graphene core-shell. Figure 2a Illustrated is a temporary substrate or wafer 120 that includes a sacrificial material 122, such as silicon, a polymer, beryllium oxide, glass, or other suitable low-cost rigid materials for structural support. In one embodiment, the temporary substrate 120 is a carrier tape. Alternatively, the substrate 120 can be silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support. The substrate 120 has a major surface 126 and a major surface 128 opposite the surface 126. A temporary bonding layer 129 is formed on the surface 126 of the substrate 120. The temporary bonding layer 129 can be a sacrificial layer or an etch stop layer made of aluminum arsenide (AlAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), or aluminum indium phosphide (AlInP).

[0024] In Figure 2b , electrical components 130a - 130b are deployed on the surface 126 of the substrate 120. The electrical components 130a - 130b can be similar to or made to be similar to the semiconductor dies 104 from Figure 1c , having a conductive layer 112 oriented away from the surface 126 of the substrate 120. Alternatively, the electrical components 130a - 130b can include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPD).

[0025] The electrical components 130a - 130b are positioned on the substrate 120 using pick - and - place operations. The electrical components 130a - 130b are brought into contact with the bonding layer 129 and are fixed in place by the bonding layer 129. Figure 2b Illustrated are the electrical components 130a - 130b bonded to the substrate 120. Figure 2c Is a top view of the electrical components 130a - 130d bonded to the substrate 120. The electrical components 130c and 130d can be similar to the electrical components 130a and 130b.

[0026] In Figure 2d , an electrical connector 140 is deployed on the surface 126 of the substrate 120. The electrical connector 140 includes a base insulating material 142 and conductive vias 144 extending through the base insulating material. The electrical connector 140 is positioned on the substrate 120 between the electrical components 130a and 130b using pick - and - place operations. The electrical connector 140 is brought into contact with the bonding layer 129 adjacent to the electrical components 130a - 130b and is fixed in place by the bonding layer 129. Figure 2e Illustrated is the electrical connector 140 bonded to the substrate 120 between the electrical components 130a and 130b and bonded to the substrate 120 adjacent to the electrical components 130a and 130b. Figure 2f Is a top view of electrical connectors 140a and 140b respectively bonded to the substrate 120 between the electrical components 130a and 130b and between the electrical components 130c and 130d. The electrical connector 140b can be similar to the electrical connector 140a and are collectively referred to as the electrical connector 140.

[0027] In Figure 2g , an encapsulant or molding compound 146 is deposited over and around the electrical components 130a - 130d, the electrical connectors 140, and the substrate 120 using solder paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulant 146 can be a liquid or particulate polymer composite, such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with appropriate fillers. The encapsulant 146 is non - conductive, provides structural support, and environmentally protects the semiconductor device from external factors and contaminants. The combination of the electrical components 130a - 130d, the electrical connectors 140a - 140b, the encapsulant 146, and the substrate 120 constitutes the semiconductor assembly 148.

[0028] In Figure 2hIn it, the conductive layer or material 150 is deposited, printed, or otherwise formed on the surface 147 of the encapsulant 146 and the active surface 110 of the electrical components 130a - 130b, including on the conductive layer 112, to provide a horizontal electrical interconnect structure across the encapsulant between the electrical components 130a - 130d and the electrical connectors 140a - 140b, above the encapsulant between the electrical components 130a - 130d and the electrical connectors 140a - 140b, or through the encapsulant between the electrical components 130a - 130d and the electrical connectors 140a - 140b. The conductive layer 150 is electrically connected between the conductive layer 112 of the electrical component 130 and the conductive vias 144 in the electrical connector 140. More specifically, the conductive layer 150a is electrically connected between the conductive layer 112d of the electrical component 130a and the conductive via 144a in the electrical connector 140a. The conductive layer 150b is electrically connected between the conductive layer 112a of the electrical component 130b and the conductive via 144b in the electrical connector 140a. In one embodiment, the conductive layer or materials 150a - 150b, collectively referred to as the conductive layer 150, are printed or dispensed onto the surfaces 110 and 147 by a printer or dispenser 149. Further details of forming the conductive layer 150 are in Figures 3a to 3b , Figures 4a to 4c , Figures 9a to 9b and Figure 10 are described. The conductive layer 150 can be a matrix of one or more layers, such as a thermosetting material or a polymer, in which graphene - coated core - shells are embedded. Alternatively, the electrical layer 150 is deposited onto the surfaces 110 and 147 using evaporation, electroplating, electroless plating, ball drop, screen - printing process, injector, or electrohydrodynamic (EHD) jet printing to provide a horizontal electrical interconnect structure across the encapsulant 146 between the electrical components 130a - 130d and the electrical connectors 140a - 140b. The conductive layer 150 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials.

[0029] Figure 3a shows from Figure 2hFurther details of the region or cartridge 151. The conductive layer or material 150a is deployed on the conductive vias 144a of the electrical connector 140a and on the surfaces 147 of the substrate insulating material 142 and encapsulant 146. In one embodiment, the conductive layer or material 150a includes a matrix 154 and a plurality of nuclei 156 having a graphene coating 157, designated as graphene core - shell 158 embedded within the matrix. The matrix 154 can be a thermosetting material such as an epoxy resin or an adhesive with fillers, the fillers including alumina, Al, aluminum - zinc oxide, or other materials with good heat transfer and conductive properties. The matrix 154 can be a thermal paste such as silicon or a polymer type, the polymer type such as polymethyl methacrylate (PMMA) or polyethylene terephthalate (PET). In one embodiment, the nuclei 156 are Ag, Cu, Ni, phase - change material (PCM), or other suitable metals or similar materials. The nuclei 156 are arranged within the matrix 154 such that most, if not all, of the graphene coating 157 covering the nuclei contacts at least one adjacent graphene coating to form a continuous and connected conductive path 159 through the conductive material 150a. A first graphene coating 157 contacts an adjacent second graphene coating, which in turn contacts an adjacent third graphene coating, and so on, to form a continuous and connected conductive path 159 between the conductive via 144a and the conductive layer 112d. The nuclei 156 have a sufficient density such that most, if not all, of the graphene coating surrounding the nuclei contacts at least one graphene coating surrounding an adjacent nucleus and typically contacts the graphene coatings of multiple adjacent nuclei.

[0030] In another embodiment, the matrix 154 is a polymer or composite epoxy resin having graphene, carbon nanotubes, conductive polymers, and the like dispersed therein. For example, the matrix 154 can be an Ag - ink epoxy resin for the conductive layer or material 150a.

[0031] Figure 3b Shows another embodiment of the region or cartridge 151 from Figure 2h In this case, the matrix 160 is a solder containing one or more elements of Sn, lead (Pb), or indium (In). Components having similar functions are assigned the same reference numerals. Again, the nuclei 156 can be Cu, Ni, PCM, or other suitable metals or similar materials. Each nucleus 156 embedded within the matrix 160 is surrounded or covered by a graphene coating or shell 157. In one embodiment, a graphene solder paste or ink is formed around a Cu or Ag nucleus, designated as graphene core - shell 158.

[0032] The core 156 is disposed within the matrix 160 such that the graphene coating 157 covering most (if not all) of the core contacts at least one adjacent graphene coating to form a continuous and connected conductive path 161 through the conductive layer or material 150a of the graphene coating. The graphene coating 157 of each core 156 contacts the graphene coating of an adjacent core. The first graphene coating 157 contacts the adjacent second graphene coating, which in turn contacts the adjacent third graphene coating, and so on, to form a continuous and connected conductive path 161. The cores 156 have a sufficient density such that the graphene coating surrounding most (if not all) of the core contacts at least one graphene coating surrounding an adjacent core and typically contacts the graphene coatings of multiple adjacent cores.

[0033] Figures 4a to 4c Further details of the core 156, the graphene coating 157, and the graphene core shell 158 are illustrated. In one embodiment, the core 156 is Cu, Ni, PCM, or other suitable metal or similar material. Figure 4b Illustrated is the graphene coating 157 formed on and surrounding the surface 162 of the core 156. Figure 4c Further details of the graphene coating 157 are illustrated. The graphene coating 157 is formed as a network around the surface 162 of the core 156, collectively referred to as the graphene core shell 158. The graphene coating 157 is an allotrope of carbon having one or more layers of carbon atoms, each carbon atom being arranged in a two-dimensional (2D) honeycomb lattice. The graphene coating 157 can be formed by CVD. The core 156 is placed in a chamber heated to 900 - 1080 °C. A gas mixture of CH4 / H2 / Ar is introduced into the chamber to initiate the CVD reaction. When the CVD reaction separates carbon atoms from hydrogen atoms, the carbon source decomposes in the high-temperature reaction chamber, leaving the graphene coating 157 on the surface 162 of the core 156. The release of carbon atoms on the core 156 forms a continuous sheet of the graphene coating 157. Additional information related to forming the graphene coating by CVD is disclosed in U.S. Patent 8,535,553 and is incorporated herein by reference.

[0034] The core 156 is a PCM capable of undergoing a phase change from solid phase to liquid phase or from liquid phase to solid phase within the operating temperature range of a semiconductor chip (e.g., 20 - 200 °C). The first coating 164 is formed around the PCM core 156, as in Figure 4bAs shown, and discussed in the published Korean application KR101465616B1. The first coating 164 may be a polymer interlayer. The second coating 157 is formed on the first coating 164. The substrates 154 and 160 with graphene-coated nuclei are further disclosed in U.S. Patent 10,421,123 and are all incorporated herein by reference.

[0035] The properties of graphene are summarized in Table 1 below:

[0036] Parameter

[0037]

[0038]

[0039] Table 1 - Properties of graphene.

[0040] The graphene coating 157 has a conductivity 100 times that of Cu. The graphene coating 157 enables the epoxy resin to exhibit a conductivity similar to that of Ag while reducing or eliminating oxidation. Compared with sputtering, the core-shell 158 with Cu or Ag and graphene epoxy resin is low-cost. The graphene coating 157 has low moisture permeability and a high thermal conductivity of 4000 - 5000 W m -1 K -1 which is 10 times that of Cu at room temperature. Since carbon also has good solderability and wettability to solder paste. The graphene coating 157 exhibits a high degree of flexibility and resists warping to maintain stability. The conductive material 150a with a graphene Cu or Ag shell 158 improves the conductivity while reducing the manufacturing cost. The conductive layer or material 150b follows a similar formation and functionality.

[0041] Return Figure 2i , the conductive layers 150a - 150b are subjected to intense pulsed light (IPL) irradiation treatment using a radiation source 166 to anneal the conductive layers. Figure 2j Further details of the radiation source 166 and the IPL irradiation treatment are shown. The semiconductor component 148 with the conductive layers 150a - 150b is placed below the radiation source 166. The reflector 167 is supported by the bracket 168. The xenon lamp 169 transmits the pulsed light 170 to the conductive layers 150a - 150b through the ultraviolet (UV) filter 171. The distance D1 from the radiation source 166 to the conductive layers 150a - 150b is approximately 14.0 mm. The radiation source 166 emits pulsed light within several milliseconds and can be applied to a large-area substrate 120 to anneal the conductive layer 150.

[0042] In Figure 2kIn [description], an insulating layer 172 is formed on a semiconductor component 148 and a conductive layer 150. The insulating layer 172 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder mask, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials having similar insulating and structural properties. The insulating layer 172 can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), printing, lamination, spin coating, sputter coating, sintering, or thermal oxidation.

[0043] In Figure 2l [description], a portion of the insulating layer 172 is removed using an etching process or laser direct ablation (LDA) with a laser 173 to form an opening 174 that extends to and exposes the conductive layer or materials 150a and 150b.

[0044] In Figure 2m [description], a conductive bump material is deposited into the opening 174 on the conductive layers 150a and 150b using evaporation, electroplating, electroless plating, ball drop, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is joined to the conductive layer 150 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 175. In one embodiment, the bump 175 is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. The bump 175 can also be compression bonded or thermocompression bonded to the conductive layer 150. In one embodiment, the bump 175 is a copper-core bump for durability and maintaining its height. The bump 175 represents a type of interconnect structure that can be formed above the conductive layer 150. The interconnect structure can also use bonding wires, conductive solder paste, pillar bumps, micro-bumps, or other electrical interconnections. The combination of the semiconductor component 148, the conductive layer 150, the insulating layer 172, and the bump 175 constitutes a semiconductor component 176.

[0045] In Figure 2n [description], the substrate 120 and the bonding layer 129 are removed from the semiconductor component 176 by chemical mechanical polishing (CMP), mechanical peeling, mechanical grinding, thermal baking, UV light, or wet stripping, leaving a semiconductor component 177.

[0046] In Figure 5a, the semiconductor component 177a is disposed over the semiconductor component 176. The semiconductor component 177a is mounted to the semiconductor component 176, wherein the bumps 175 on the semiconductor component 176 contact the conductive vias 144a and 144b of the electrical connector 140 on the semiconductor component 177a. Figure 5b A semiconductor component 177a is shown mounted to a semiconductor component 176. In particular, an electrical signal conduction path from a conductive layer 112d on an electrical component 130a in the semiconductor component 176 is routed through a conductive layer 150a in the semiconductor component 176, a bump 175 in the semiconductor component 176, a conductive via 144a of an electrical connector 140 in the semiconductor component 177a, and a conductive layer 150a in the semiconductor component 177a to a conductive layer 112d in an electrical component 130a in the semiconductor component 177a. An electrical signal conduction path from a conductive layer 112a on an electrical component 130b in the semiconductor component 176 is routed through a conductive layer 150b in the semiconductor component 176, a bump 175 in the semiconductor component 176, a conductive via 144b of an electrical connector 140 in the semiconductor component 177a, and a conductive layer 150b in the semiconductor component 177a to a conductive layer 112a in an electrical component 130b in the semiconductor component 177a.

[0047] exist Figure 5c In the embodiment, the semiconductor component 177b is connected with Figures 5a to 5b The semiconductor component 177a is similarly disposed above and mounted on the semiconductor component 177a. The semiconductor component 177b is mounted to the semiconductor component 177a, wherein the bump 175 on the semiconductor component 177a contacts the conductive through holes 144a and 144b of the electrical connector 140 on the semiconductor component 177b. The electrical signal conduction path from the conductive layer 112d on the electrical component 130a in the semiconductor component 177a is routed through the conductive layer 150a in the semiconductor component 177a, the bump 175 in the semiconductor component 177a, the conductive through hole 144a of the electrical connector 140 in the semiconductor component 177b, and the conductive layer 150a in the semiconductor component 177b to the conductive layer 112d in the electrical component 130a in the semiconductor component 177b. An electrical signal conduction path starting from the conductive layer 112a on the electrical component 130b in the semiconductor component 177a is routed through the conductive layer 150b in the semiconductor component 177a, the bump 175 in the semiconductor component 177a, the conductive through hole 144b of the electrical connector 140 in the semiconductor component 177b, and the conductive layer 150b in the semiconductor component 177b to the conductive layer 112a in the electrical component 130b in the semiconductor component 177b.

[0048] The combination of semiconductor components 176, 177a, and 177b constitutes a SiP or semiconductor package 178, which can electrically connect the electrical components 130a - 130b in each of the semiconductor components 176, 177a, and 177b through electrical connectors 140, bumps 175, and a conductive layer or material 150. The conductive layer or material 150 includes a graphene core - shell for improved conductivity with low resistivity and high thermal conductivity. The SiP 178 including the electrical connector 140 and the conductive layer 150 provides a higher - density semiconductor die in a smaller space with extended electrical functionality. In particular, the conductive layer 150 with a graphene core - shell improves signal transmission and reduces propagation delay. IPL irradiation performs annealing in a shorter time than thermal sintering.

[0049] In another embodiment, starting from Figure 2g Continuing, a conductive layer or material 180 is deposited, printed, or otherwise formed on the surface 147 of the encapsulant 146 and the active surfaces 110 of the electrical components 130a - 130b, including the conductive layer 112, as shown in Figure 6a The conductive layer or material 180 provides a horizontal electrical interconnection structure across the encapsulant between the electrical components 130a - 130d and the electrical connectors 140a - 140b, above the encapsulant between the electrical components 130a - 130d and the electrical connectors 140a - 140b, or through the encapsulant between the electrical components 130a - 130d and the electrical connectors 140a - 140b. Components with similar functions are assigned the same reference numerals. The conductive layer 180 is electrically connected to the conductive layer 112 of the electrical component 130. More specifically, the conductive layer 180a is electrically connected to the conductive layer 112a of the electrical component 130a, and the conductive layer 180b is electrically connected to the conductive layer 112b of the electrical component 130a. The conductive layer 180c is electrically connected between the conductive layer 112d of the electrical component 130a and the conductive via 144a in the electrical connector 140a. The conductive layer 180d is electrically connected between the conductive layer 112a of the electrical component 130b and the conductive via 144b in the electrical connector 140a. The conductive layer 180e is electrically connected to the conductive layer 112c of the electrical component 130b, and the conductive layer 180f is electrically connected to the conductive layer 112d of the electrical component 130b. In one embodiment, the conductive layer or material 180a - 180f, collectively referred to as the conductive layer 180, is printed or spread onto the surfaces 110 and 147 by a printer or spreader 179, as described in Figures 9a to 9b and Figure 10 The conductive layer 180 follows a formation and function similar to that of the conductive layer 150 in Figures 3a to 3b and Figures 4a to 4c

[0050] InFigure 6b in which the conductive layers 180a - 180f are subjected to IPL irradiation treatment using the radiation source 181, similar to Figure 2j similar.

[0051] In Figure 6c in which an insulating layer 182 is formed over the semiconductor component 148 and the conductive layer 180. The insulating layer 182 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder mask, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. The insulating layer 182 can be formed using PVD, CVD, printing, lamination, spin coating, sputter coating, sintering, or thermal oxidation.

[0052] In Figure 6d in which a portion of the insulating layer 182 is removed using LDA or an etching process utilizing the laser 183 to form an opening 184 and expose the conductive layer or materials 180a - 180f.

[0053] In Figure 6e in which a conductive bump material is deposited into the opening 184 over the conductive layers 180a - 180f using evaporation, electroplating, electroless plating, ball drop, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high - lead solder, or lead - free solder. The bump material is joined to the conductive layer 180 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 186. In one embodiment, the bump 186 is formed over a UBM having a wetting layer, a barrier layer, and an adhesive layer. The bump 186 can also be compression - bonded or thermocompression - bonded to the conductive layer 180. In one embodiment, the bump 186 is a copper - core bump for durability and maintaining its height. The bump 186 represents one type of interconnect structure that can be formed on the conductive layer 180. Interconnect structures can also use bonding wires, conductive solder paste, columnar bumps, micro - bumps, or other electrical interconnections.

[0054] In Figure 6f in which the substrate 120 and the bonding layer 129 are removed by CMP, mechanical peeling, mechanical grinding, thermal baking, UV light, or wet stripping, leaving the semiconductor component 190.

[0055] In Figure 7 in which the semiconductor component 190 is deployed in a manner similar to Figures 5a to 5b from Figure 5cabove and mounted to semiconductor component 177b. In particular, the electrical signal conduction path starting from the conductive layer 112d on the electrical component 130a in semiconductor component 177b is routed through the conductive layer 150a in semiconductor component 177b, the bump 175 in semiconductor component 177b, the conductive via 144a of the electrical connector 140 in semiconductor component 190, and the conductive layer 180c in semiconductor component 190 to the conductive layer 112d in the electrical component 130a in semiconductor component 190. The electrical signal conduction path starting from the conductive layer 112a on the electrical component 130b in semiconductor component 177b is routed through the conductive layer 150b in semiconductor component 177b, the bump 175 in semiconductor component 177b, the conductive via 144b of the electrical connector 140 in semiconductor component 190, and the conductive layer 180d in semiconductor component 190 to the conductive layer 112a in the electrical component 130b in semiconductor component 190. The electrical components 130a - 130b in semiconductor components 176, 177a, and 177b can be electrically connected to the electrical components 130a - 130b in semiconductor component 190 and the external bumps 186 through the conductive layers 150, the electrical connector 140, and the conductive layers 180a - 180f. The combination of semiconductor components 176, 177a, 177b, and 190 constitutes semiconductor component 192.

[0056] In Figure 8a it, the substrate 120 and the bonding layer 129 are removed from the semiconductor component 176 by CMP, mechanical peeling, mechanical grinding, thermal baking, UV light, or wet stripping. A cross-sectional view of a multi-layer interconnect substrate 200 including a conductive layer 202 and an insulating layer 204 is shown. The conductive layer 202 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer can be formed using PVD, CVD, electroplating, electroless plating processes, or other suitable metal deposition processes. The conductive layer 202 provides horizontal electrical interconnections across the substrate 200 and vertical electrical interconnections between the top surface 206 and the bottom surface 208 of the substrate 200. Depending on the design and function of the semiconductor die 104 and other electrical components, portions of the conductive layer 202 can be electrically common or electrically isolated. The insulating layer 204 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder mask, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. The insulating layer can be formed using PVD, CVD, printing, lamination, spin coating, sputter coating, sintering, or thermal oxidation. The insulating layer 204 provides isolation between the conductive layers 202.

[0057] The semiconductor component 192 is deployed on the surface 206 of the interconnect substrate 200 and is electrically and mechanically connected to the conductive layer 202. The bumps 186 of the semiconductor component 190 are brought into contact with the conductive layer 202 on the surface 206 of the substrate 200. The semiconductor component 192 is electrically and mechanically connected to the conductive layer 202 by reflowing the bumps 186. Figure 8b Illustrated is a semiconductor component 192 that is electrically and mechanically connected to the conductive layer 202 of the substrate 200 and is designated as a SiP or semiconductor package 210. The SiP 210 provides a semiconductor stacking method and structure using electrical connectors and graphene core-shells to improve interconnectivity, electrical conductivity, thermal conductivity, and performance while reducing resistivity. The SiP 210 including the electrical connectors 140 and the conductive layers 150 and 180 provides a higher density of semiconductor dies in a smaller space with extended electrical functionality. In particular, the conductive layers 150 and 180 with graphene core-shells improve signal transmission and reduce propagation delay. IPL irradiation performs annealing in a shorter time than thermal sintering.

[0058] Figures 9a to 9b and Figure 10 Illustrated are further details of the dispensers 149 and 179. Figure 9a Shown is the deposition of the conductive layer 150 on the surface 147 of the encapsulant 146 and the active surface 110 (including the conductive layer 112) of the electrical component 130 in the semiconductor components 176, 177a, 177b, and 190 using EHD jet printing. For example, the semiconductor component 176 is placed on a substrate 220 capable of three-dimensional (x, y, z directions) movement to control the distribution of the conductive material 150 on the surfaces 110 and 147. A pneumatic regulator 222 with a pressure gauge applies pressure to an injection pump 224 containing the conductive material 150. A tapered section 226 narrows the ink path to the injection nozzle 228, which deposits the conductive material 150 on the surfaces 110 and 147 in a controlled manner. More specifically, the injection nozzle 228 performs jetting through the pressure and electric field between the nozzle and the substrate. In Figure 9b this case, pressure is applied from the pneumatic regulator 222. A voltage source induces an electric field shown as negative charges 232 and positive charges 234. The printing liquid is driven by the electric field to achieve direct patterning and high-resolution printing of the conductive layer 150.

[0059] Figure 10shows the deposition of a conductive layer 150 on the surface 147 of the encapsulant 146 and the active surface 110 of the electrical component 130 in semiconductor components 176, 177a, 177b, and 190 using aerosol jet printing. The dispenser 240 includes a channel 242 for the flow of the conductive material 150 and a channel 244 for the flow of a gas such as nitrogen. The conductive material is mixed with the gas and deposited as an aerosol jet of the material from the nozzle or head 250 onto the surfaces 110 and 147. The printing liquid, i.e., the conductive layer 150, is dispensed as an aerosol jet focused by a sheath gas at the end of the head 250. In Figures 9a to 9b and Figure 10 the above description for the conductive layer or material 150 and 180 applies.

[0060] Figure 11 illustrates an electrical device 400 having a chip carrier substrate or PCB 402, where a plurality of semiconductor packages are deployed on the surface of the PCB 402, including SiP 178 and 210. Depending on the application, the electrical device 400 may have one type of semiconductor package, or multiple types of semiconductor packages.

[0061] The electrical device 400 may be an independent system that performs one or more electrical functions using semiconductor packages. Alternatively, the electrical device 400 may be a sub-component of a larger system. For example, the electrical device 400 may be part of a tablet computer, cellular phone, digital camera, communication system, or other electrical device. Alternatively, the electrical device 400 may be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package may include a microprocessor, memory, ASIC, logic circuit, analog circuit, RF circuit, discrete device, or other semiconductor die or electrical component. Miniaturization and weight reduction are essential for the product to be accepted in the market. The distance between semiconductor devices can be reduced to achieve higher density.

[0062] In Figure 11 , the PCB 402 provides a common substrate for the structural support and electrical interconnection of semiconductor packages deployed on the PCB. Conductive signal traces 404 are formed on the surface or within the layers of the PCB 402 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces 404 provide electrical connectivity between each of the semiconductor packages, mounted components, and other external system components. The traces 404 also provide power and ground connections for each of the semiconductor packages.

[0063] In some embodiments, a semiconductor device has two packaging levels. The first-level packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may only have the first-level packaging, where the die is mechanically and electrically deployed directly on the PCB. For illustrative purposes, several types of first-level packaging are shown on the PCB 402, including a wirebond package 406 and a flip chip 408. Additionally, several types of second-level packaging, including a ball grid array (BGA) 410, a bump chip carrier (BCC) 412, a land grid array (LGA) 416, a multi-chip module (MCM) or a SIP module 418, a quad flat no-lead package (QFN) 420, a small flat package 422, an embedded wafer-level ball grid array (eWLB) 424, and a wafer-level chip scale package (WLCSP) 426, are shown as being deployed on the PCB 402. In one embodiment, the eWLB 424 is a fan-out wafer-level package (Fo-WLP) and the WLCSP 426 is a fan-in wafer-level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages configured with any combination of first- and second-level packaging types, as well as other electrical components, can be connected to the PCB 402. In some embodiments, the electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, a manufacturer can incorporate prefabricated components into electrical devices and systems. Because semiconductor packages include complex functionality, electrical devices can be manufactured using less expensive components and pipelined manufacturing processes. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs for consumers.

[0064] While one or more embodiments of the invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A semiconductor device, comprising: A first electrical component; An electrical connector disposed adjacent to the first electrical component; and A conductive layer including a graphene core - shell formed between the first electrical component and the electrical connector.

2. The semiconductor device according to claim 1, further comprising: A second electrical component disposed adjacent to a side of the electrical connector opposite to the first electrical component; and An encapsulant deposited around the first electrical component, the second electrical component, and the electrical connector, wherein the conductive layer including the graphene core - shell is formed between the second electrical component and the electrical connector above the encapsulant.

3. The semiconductor device according to claim 1, wherein the graphene core - shell comprises a copper core or a silver core.

4. The semiconductor device according to claim 1, wherein the conductive layer comprises a plurality of cores covered by graphene, and the graphene is interconnected within the conductive layer to form a conductive path.

5. The semiconductor device according to claim 1, wherein the conductive layer comprises a matrix of a thermosetting material or a polymer or a composite epoxy resin type, and the graphene core - shell is embedded within the thermosetting material or the polymer or the composite epoxy resin type matrix.

6. A semiconductor device, comprising a plurality of stacked semiconductor components, each semiconductor component comprising: A first electrical component; An electrical connector disposed adjacent to the first electrical component; And A conductive layer including a graphene core - shell formed between the first electrical component and the electrical connector.

7. The semiconductor device according to claim 6, further comprising: A second electrical component disposed adjacent to a side of the electrical connector opposite to the first electrical component; and An encapsulant deposited around the first electrical component, the second electrical component, and the electrical connector, wherein the conductive layer including the graphene core - shell is formed between the second electrical component and the electrical connector above the encapsulant.

8. The semiconductor device according to claim 6, wherein the graphene core - shell comprises a copper core or a silver core.

9. The semiconductor device according to claim 6, wherein the conductive layer comprises a plurality of cores covered by graphene, and the graphene is interconnected within the conductive layer to form a conductive path.

10. The semiconductor device according to claim 6, wherein the conductive layer comprises a matrix of a thermosetting material or a polymer or a composite epoxy resin type, and the graphene core - shell is embedded within the thermosetting material or the polymer or the composite epoxy resin type matrix.

11. A method of manufacturing a semiconductor device, comprising: Providing a first electrical component; Disposing an electrical connector adjacent to the first electrical component; and Forming a conductive layer including a graphene core - shell between the first electrical component and the electrical connector.

12. The method according to claim 11, further comprising: Disposing a second electrical component adjacent to a side of the electrical connector opposite to the first electrical component; and Depositing an encapsulant around the first electrical component, the second electrical component, and the electrical connector, wherein the conductive layer including the graphene core - shell is formed between the second electrical component and the electrical connector above the encapsulant.

13. The method according to claim 11, wherein the graphene core - shell comprises a copper core or a silver core.

14. The method according to claim 11, wherein the conductive layer comprises a plurality of cores covered by graphene, and the graphene is interconnected within the conductive layer to form a conductive path.

15. The method according to claim 11, wherein the conductive layer comprises a matrix of a thermosetting material or a polymer or a composite epoxy resin type, and the graphene core-shell is embedded within the matrix of the thermosetting material or the polymer or the composite epoxy resin type.

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