Data transmission device and display device including the same

Abstract

The embodiment discloses a data transmission device and a display device including the same. The data transmission device includes: a first transmission device that scrambles digital video data using a scrambling key and transmits the scrambled video data; and a second transmission device that restores the video data by descrambling the scrambled video data using a descrambling key, the second transmission device restores the descrambling key using predetermined pattern data input during a horizontal blanking period when synchronization with the first transmission device is released.

Description

Technical Field

[0001] Embodiments of the present invention relate to a data transmission device and a display device including the same. Background Art

[0002] With the development of the information society, there is an increasing demand for various forms of display devices for displaying images. Recently, various types of display devices such as liquid crystal display devices (LCDs) or organic light emitting display devices (OLEDs) are being applied.

[0003] A display device includes: a display panel including a plurality of pixels; a data driving unit for supplying a data voltage to the display panel; a gate driving unit for supplying a gate signal to the display panel; and a timing controller for controlling the data driving unit and the gate driving unit.

[0004] The timing controller scrambles and transmits digital video data, and the data driving unit descrambles the transmitted video data to restore it to the original video data, converts the restored video data into an analog data voltage, and supplies it to each pixel.

[0005] In this case, it is necessary to achieve scrambling synchronization between the transmitting end of the timing controller and the receiving end of the data driving unit. The scrambling synchronization can be achieved by transmitting a special symbol or packet control information for scrambling reset from the transmitting end and recognizing it at the receiving end.

[0006] However, in a specific situation, whenever the scrambling synchronization cannot be achieved normally, it is necessary to re-transmit the scrambling reset information from the transmitting end to the receiving end in order to enable the data driver to normally restore the video data.

[0007] Therefore, there is a current need for a solution that can achieve scrambling re-synchronization without re-transmitting the scrambling reset information. Summary of the Invention

[0008] Technical Problem

[0009] Embodiments of the present invention provide a data transmission device and a display device including the same.

[0010] The object of the present invention is not limited to the above object, and other objects not mentioned can be clearly understood by those of ordinary skill in the technical field to which the present invention belongs through the following description.

[0011] Technical Solution

[0012] The data transmission device according to an embodiment of the present invention includes: a first transmission device that scrambles digital video data using a scrambling key and transmits the scrambled video data; and a second transmission device that descrambles the scrambled video data using a descrambling key to restore the video data. In a case where synchronization with the first transmission device is released, the second transmission device can restore the descrambling key using predetermined pattern data input during a horizontal blanking period.

[0013] The first transmission device transmits the scrambled video data during a horizontal active period, and after the horizontal active period, during a horizontal blanking period, can scramble pattern data consisting of "0" using the scrambling key and transmit the scrambled pattern data.

[0014] The second transmission device may include: a linear feedback shift register (LFSR) estimation unit that estimates a scrambling key using data input from the first transmission device; a multiplexer that outputs the scrambling key estimated by the linear feedback shift register estimation unit during the horizontal blanking period; a linear feedback shift register engine unit that restores the descrambling key using the scrambling key output from the multiplexer and outputs it; and a combining unit that restores the video data by performing a logical operation on the data input from the first transmission device and the descrambling key output from the linear feedback shift register engine unit.

[0015] The linear feedback shift register estimation unit estimates the scrambling key using the Nth data and the (N + 1)th data input from the first transmission device, where N is a natural number.

[0016] The combining unit may be an exclusive OR (XOR) gate that performs an XOR operation on the input data and the descrambling key.

[0017] The multiplexer receives the descrambling key output from the linear feedback shift register engine unit as feedback during the horizontal active period and can output the feedback descrambling key to the linear feedback shift register engine unit.

[0018] The second transmission device may further include a data comparison unit that selects the output of the multiplexer using the descrambled data output from the combining unit and a signal indicating the horizontal blanking period.

[0019] The data comparison unit may include: a determination unit that outputs "1" when the descrambled data output from the combining unit is not "0"; and an AND gate that outputs a signal for controlling the output of the multiplexer by performing a logical operation on the output of the determination unit and a signal indicating the horizontal blanking period.

[0020] The display device according to an embodiment of the present invention includes: a display panel, in which a plurality of pixels are provided in an area where a plurality of gate lines and a plurality of data lines intersect; a gate driving unit that outputs a gate signal through the gate lines; a data driving unit that outputs a data voltage through the data lines; and a timing controller that controls the gate driving unit and the data driving unit. The timing controller includes a first transmission device that scrambles digital video data using a scrambling key and transmits the scrambled video data. The data driving unit includes a second transmission device that descrambles the scrambled video data using a descrambling key to restore the video data. In a case where synchronization with the first transmission device is released, the second transmission device can restore the descrambling key using predetermined pattern data input during a horizontal blanking period.

[0021] The second transmission device includes: a multiplexer that outputs data input during the horizontal blanking period; a linear feedback shift register engine unit that restores the descrambling key using the data output by the multiplexer and outputs it; and a combining unit that restores the video data by performing a logical operation on the data input by the first transmission device and the descrambling key output by the linear feedback shift register engine unit.

[0022] The multiplexer receives the descrambling key output by the linear feedback shift register engine unit as feedback during the horizontal active period and outputs the feedback descrambling key to the linear feedback shift register engine unit.

[0023] Effects of the Invention

[0024] According to an embodiment of the present invention, when a receiving device cannot normally achieve data scrambling synchronization under specific conditions, it is possible to restore the descrambling key using data input during the horizontal blanking period to quickly perform data scrambling resynchronization without receiving scrambling reset information from a transmitting device again.

[0025] The effects of the present invention are not limited to the above-mentioned effects. Those of ordinary skill in the technical field to which the present invention pertains can clearly understand other effects not mentioned through the content recorded in the scope of the invention claimed. Brief Description of the Drawings

[0026] Figure 1 A diagram showing a display device according to an embodiment of the present invention.

[0027] Figure 2 To show an application to Figure 1 a data transmission device.

[0028] Figure 3 To illustrate Figure 2 the structure and working principle of the scrambler shown.

[0029] Figure 4 It is a diagram for explaining the descrambling principle of the embodiments of the present invention.

[0030] Figure 5 For showing Figure 2 It is a structural diagram of the descrambler of the first embodiment shown.

[0031] Figures 6 to 7 It is a diagram for explaining the principle of estimating the scrambling key of the embodiment.

[0032] Figure 8 For showing Figure 5 It is a diagram of scrambling resynchronization.

[0033] Figure 9 For showing Figure 5 It is a diagram of the modified structure of the descrambler.

[0034] Figure 10 For showing Figure 2 It is a structural diagram of the descrambler of the second embodiment shown.

[0035] Figure 11 For showing Figure 10 It is a diagram of scrambling resynchronization.

[0036] Figure 12 It is a diagram for comparing and explaining the scrambling resynchronization results of the comparative example and the embodiment.

[0037] Explanation of reference numerals

[0038] 110: Display panel 120: Gate driving unit

[0039] 130: Data driving unit 140: Timing controller

[0040] 150: Host system 210: First transmission device

[0041] 220: Second transmission device Detailed description of the specific embodiments

[0042] Hereinafter, multiple embodiments of the present invention will be described in detail with reference to the drawings.

[0043] Figure 1 It is a diagram of the display device of the embodiment of the present invention.

[0044] Referring to Figure 1 , the display device 100 of the embodiment of the present invention may include a display panel 110, a gate driving unit 120, a data driving unit 130, and a timing controller 140. The display device 100 may further include a host system 150 that supplies various timing signals to the timing controller 140.

[0045] The display panel 110 may include: a plurality of gate lines G1 to Gm and a plurality of data lines D1 to Dn, which are arranged to cross each other to form a plurality of pixel regions; and pixels P, which are respectively disposed in the plurality of pixel regions. Each pixel P may include a red sub-pixel R that emits red light, a green sub-pixel G that emits green light, and a blue sub-pixel B that emits blue light.

[0046] The gate driving unit 120 is disposed on one side of the display panel 110. For example, it may be disposed on the left side. However, it may be disposed on one side and the other side of the display panel 110 facing each other according to circumstances. For example, it may also be disposed on both the left side and the right side. The gate driving unit 120 may include a plurality of gate driver integrated circuits (ICs, Gate Driver Integrated Circuits; not shown).

[0047] The gate driving unit 120 may be implemented in the form of a tape carrier package (TCP) mounted with a gate driver integrated circuit (IC), but is not limited thereto. The gate driver integrated circuit may also be directly mounted on the display panel 110.

[0048] The data driving unit 130 converts the digital video signal transmitted from the timing controller 140 into an analog source signal and outputs it to the display panel 110. Specifically, the data driving unit 130 outputs an analog source signal through the data lines D1 to Dn in response to a data control signal (DCS, Data Control Signal) transmitted from the timing controller 140.

[0049] The data driving unit 130 is disposed on one side of the display panel 110. For example, it may be disposed on the upper side. However, it may be disposed on one side and the other side of the display panel 110 facing each other according to circumstances. For example, it may also be disposed on both the upper side and the lower side. Moreover, the data driving unit 130 may be implemented in the form of a tape carrier package (TCP) mounted with a gate driver integrated circuit, but is not limited thereto.

[0050] The timing controller 140 may receive various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable (DE, Data Enable) signal, a clock signal CLK, etc. from the host system 150 to generate a data control signal DCS for controlling the data driving unit 130 and a gate control signal GCS for controlling the gate driving unit 120. Also, the timing controller 140 may receive the video data RGB from the host system 150, convert it into a form that the data driving unit 130 can process, and output the video data RGB'.

[0051] The data control signal DCS may include a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), etc., and the gate control signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), etc.

[0052] The host system 150 may be implemented by one of a navigation system, a set-top box, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, a broadcast receiver, and a phone system.

[0053] The host system 150 includes a system-on-chip (SoC) with an embedded scaler. The digital image data RGB of the input image can be converted into a format suitable for display on the display panel 110. The host system 150 can transmit the digital image data RGB and timing information to the timing controller 140.

[0054] In an embodiment, although the case of transmitting image data between the timing controller and the data driver unit is illustrated as an example, it is not limited thereto. For example, it can also be applied to the case of transmitting image data between the host system and the timing controller.

[0055] Figure 2 To show the Figure 1 figure of the data transmission device applied to Figure 3 To illustrate the Figure 2 figure of the structure and working principle of the scrambler shown.

[0056] Among them, the data transmission device includes Figure 1 the timing controller 140 and the data driver unit 130 of , the timing controller 140 includes a first transmission device 210, and the data driver unit 130 includes a second transmission device 220, but it is not limited thereto.

[0057] Referring to Figure 2 According to the data transmission device of the embodiment of the present invention, it may include a first transmission device 210 and a second transmission device 220. The first transmission device 210 receives data from the Figure 1 host system and can transmit the received data (for example, image data) to the second transmission device 220. The first transmission device 210 may be referred to as a transmitting device, and the second transmission device 220 may be referred to as a receiving device.

[0058] The first transmission device 210 may include a scrambler 211. The scrambler 211 may scramble the input digital video data. As Figure 3 shown, the scrambler 211 may include a Linear Feedback Shift Register (LFSR) 211a and a combining unit 211b.

[0059] The Linear Feedback Shift Register 211a is a predetermined polynomial and can generate a random bit sequence or a scrambling key for data scrambling. Such data scrambling not only encrypts the data, but also, in the case of high-speed communication, can randomly generate repeated data sequences, which can improve EMI noise and maximize coding efficiency.

[0060] The combining unit 211b may perform a logical operation on the digital video data and the random bit sequence generated from the Linear Feedback Shift Register 211a and mix them to output scrambled data. For example, the combining unit 211b may be an exclusive-OR gate, but is not limited thereto.

[0061] The second transmission device 220 receives the scrambled data from the first transmission device 210 and may descramble the received scrambled data to recover the video data.

[0062] In an embodiment, when the receiving device cannot normally achieve data scrambling synchronization due to a specific state, the data input during the horizontal blanking period can be used to recover the descrambling key without receiving the scrambling reset information from the transmitting device again.

[0063] Figure 4 It is a diagram for explaining the descrambling principle of an embodiment of the present invention.

[0064] Referring to Figure 2 and Figure 4 , the first transmission device 210 receives video data from the host system and is configured to include a Start of Line (SOL), digital video data, an End of Line (EOL), and mode data based on the received video data. The data configured in this way is input to the scrambler 211.

[0065] The scrambler 211 of the first transmission device 210 scrambles the input digital video data using a random bit sequence, transmits the scrambled data during the horizontal active period, scrambles the data composed of "0", and transmits the scrambled mode data during the horizontal blanking period.

[0066] In this case, special symbols such as the start of line (SOL) and the end of line (EOL) have fixed values and are not scrambled to maintain these fixed values. Among them, although symbols such as the start of line and the end of line can be used, other symbols can also be used according to the interface protocol.

[0067] The descrambler 212 of the second transmission device 220 generates a descrambling key using the scrambled pattern data received during the horizontal blanking period, and can use the generated descrambling key to descramble the received scrambled data to restore digital video data.

[0068] Among them, the scrambled pattern data transmitted during the horizontal blanking period refers to data scrambled using the scrambling key being used by the first transmission device 210 at the transmitting end.

[0069] Specifically, the pattern data refers to data composed of "0". The first transmission device 210 generates scrambled pattern data by performing an exclusive OR operation on the pattern data composed of "0" and the scrambling key. The generated scrambled pattern data has the same value as the scrambling key. This is because if an exclusive OR operation is performed on each bit of data composed of "0" and "0", it becomes "0", and if an exclusive OR operation is performed on each bit of data composed of "0" and "1", it becomes "1". Therefore, the second transmission device 220 can generate a descrambling key using the scrambled pattern data without transmitting the scrambling reset information again.

[0070] Thus, in the embodiment, by utilizing the characteristics of the scrambled pattern data transmitted from a specific interval such as the horizontal blanking period, even if the scrambling reset information cannot be received again from the transmitting end, the scrambling resynchronization can be achieved independently.

[0071] In the first embodiment, as an example, a case where the number of bits of the data input to the descrambler is different from the number of bits of the data processed by the descrambler is illustrated.

[0072] Figure 5 To show Figure 2 the structural diagram of the descrambler of the first embodiment shown, Figures 6 to 7 is a diagram for explaining the principle of estimating the scrambling key of the embodiment.

[0073] Referring to Figure 5 , the descrambler 221 of the first embodiment may include a linear feedback shift register estimation unit 221a, a multiplexer 221b, a linear feedback shift register engine unit 221c, a combining unit 221d, and a data comparison unit 221e.

[0074] During the horizontal active period, the input data is directly input to the junction 221d, but is not transmitted to the linear feedback shift register engine unit 221c through the linear feedback shift register estimation unit 221a. During the horizontal blanking period, the input data is directly input to the junction 221d and is transmitted to the linear feedback shift register engine unit 221c through the linear feedback shift register estimation unit 221a.

[0075] The linear feedback shift register estimation unit 221a estimates the scrambling key having the number of bits that can be processed by the linear feedback shift register engine unit 221c by using the data input during the horizontal blanking period, and can transmit the estimated scrambling key to the linear feedback shift register engine unit 221c through the multiplexer 221b.

[0076] For example, as Figure 6 shown, when the number of input data bits is 8 bits and the number of bits processed by the linear feedback shift register engine unit 221c is 16 bits, the linear feedback shift register estimation unit 221a uses the Nth 8-bit key and the (N + 1)th 8-bit key to estimate the scrambling key (EST Key), and can estimate the (N + 1)th 16-bit scrambling key (Key(N + 1)).

[0077] Among them, the Nth 8-bit key and the (N + 1)th 8-bit key constitute a 16-bit key. Therefore, the Nth 8-bit key is the high-order key including the most significant bit (MSB, Most Significant Bit), and the (N + 1)th 8-bit key can be the low-order key including the least significant bit (LSB, Least Significant Bit).

[0078] Specifically, as Figure 7 shown, the linear feedback shift register estimation unit 221a predicts the next (N + 1)th 8-bit key from the input Nth 8-bit key by using a predetermined polynomial, and can predict the next (N + 2)th 8-bit key from the input (N + 1)th 8-bit key. The linear feedback shift register estimation unit 221a can estimate the (N + 1)th 16-bit key as the scrambling key by combining the predicted (N + 1)th 8-bit key with the input (N + 1)th 8-bit key.

[0079] In this case, the predicted (N + 2)th 8-bit key can be used to estimate the next scrambling key.

[0080] The first input terminal of the multiplexer 221b is connected to the output terminal of the linear feedback shift register estimation unit 221a, and the second input terminal is connected to the output terminal of the linear feedback shift register engine unit 221c. The multiplexer 221b transmits the scrambling key estimated by the linear feedback shift register estimation unit 221a to the linear feedback shift register engine unit 221c according to the high logic level of the enable signal output from the data comparison unit 221e. Conversely, the multiplexer 221b receives the descrambling key output from the linear feedback shift register engine unit 221c as feedback according to the low logic level of the enable signal output from the data comparison unit 221e and transmits it.

[0081] The linear feedback shift register engine unit 221c uses the scrambling key estimated during the horizontal blanking period to generate a descrambling key and outputs the descrambling key output in the previous cycle during the horizontal active period. The linear feedback shift register engine unit 221c is implemented as a predetermined polynomial. Therefore, the descrambling key can be generated using the predetermined polynomial.

[0082] In this case, the descrambling key generated by the linear feedback shift register engine unit 221c using the estimated scrambling key is 16 bits. In order to descramble the input 8-bit data, only an 8-bit descrambling key is required. Therefore, the linear feedback shift register engine unit 221c can extract the upper 8-bit descrambling key from the generated 16-bit descrambling key and output it.

[0083] In this case, the linear feedback shift register engine unit 221c generates the (N + 1)-th 16-bit descrambling key, and in the next clock, outputs an 8-bit descrambling key from the (N + 2)-th 16-bit descrambling key.

[0084] In the embodiment, although it is illustrated as an example that the linear feedback shift register engine unit 221c can generate a descrambling key using the data input during the horizontal blanking period in any unexpected situation where asynchronous may occur, basically, the descrambling key can also be generated using the scrambling reset information transmitted from the sending end.

[0085] The data comparison unit 221e outputs an enable signal for controlling the high logic level or low logic level of the multiplexer 221b based on the descrambled data and the signal indicating the horizontal blanking period.

[0086] The data comparison unit 221e includes a comparator 221e1 and an AND gate 221e2. The comparator 221e1 receives the descrambled data and outputs "1" if the received data is not "0", and outputs "0" if the received data is "0". The AND gate 221e2 outputs the high logic level enable signal En and the low logic level enable signal En through a logical operation of the signal indicating the horizontal blanking period and the output of the comparator 221e1.

[0087] That is, during the horizontal blanking period and when the descrambled data is not "0", the data comparison unit 221e transmits the scrambling key estimated by the linear feedback shift register estimation unit 221a during the horizontal blanking period to the linear feedback shift register engine unit 221c.

[0088] Conversely, during a period other than the horizontal blanking period and when the descrambled data is "0", the data comparison unit 221e may transmit the descrambling key generated in the previous cycle to the linear feedback shift register engine unit 221c.

[0089] The combining unit 221d can use the descrambling key output by the linear feedback shift register engine unit 221c to descramble the input data and generate and output the descrambled data.

[0090] Figure 8 To show Figure 5 a diagram of scrambling resynchronization.

[0091] Referring to Figure 8 , in the embodiment, when the scrambling synchronization is released due to noise or the like during the horizontal active period of receiving the scrambled data, it can be seen that the scrambling resynchronization is automatically achieved by using the data input during the horizontal blanking period (H-Blank).

[0092] During the horizontal active period when noise is generated, scrambling resynchronization cannot be achieved. However, if the horizontal blanking period (H-Blank) is entered, a scrambling key is generated using two data after the end of the line, and then the scrambling resynchronization is achieved using the scrambling key.

[0093] Figure 9 To show Figure 5 a modified structure of the descrambler.

[0094] Referring to Figure 9 , the modified descrambler 221 may include a linear feedback shift register estimation unit 221a, a multiplexer 221b, a linear feedback shift register engine unit 221c, and a combining unit 221d.

[0095] The data input during the horizontal active period is directly input to the combining unit 221d and is not transmitted to the linear feedback shift register engine unit 221c through the linear feedback shift register estimation unit 221a. The data input during the horizontal blanking period is directly input to the combining unit 221d and is transmitted to the linear feedback shift register engine unit 221c through the linear feedback shift register estimation unit 221a.

[0096] During the horizontal blanking period, the linear feedback shift register estimator 221a estimates a scrambling key having a number of bits that can be processed by the linear feedback shift register engine unit 221c, and the estimated scrambling key can be transmitted to the linear feedback shift register engine unit 221c through the multiplexer 221b.

[0097] The first input terminal of the multiplexer 221b is connected to the output terminal of the linear feedback shift register estimator 221a, and the second input terminal is connected to the output terminal of the linear feedback shift register engine unit 221c. The input terminal is connected to the output terminal of the linear feedback shift register engine unit 221c. Based on the signal indicating the horizontal blanking period, the multiplexer 221b transmits the scrambling key estimated by the linear feedback shift register estimator 221a to the linear feedback shift register engine unit 221c or receives the data output by the linear feedback shift register engine unit 221c from the linear feedback shift register engine unit 221c, that is, the descrambling key is fed back and transmitted.

[0098] For example, if the signal indicating the blanking period is "1", the multiplexer 221b transmits the scrambling key estimated by the linear feedback shift register estimator 221a to the linear feedback shift register engine unit 221c. If the signal indicating the blanking period is "0", the multiplexer 221b receives the data output by the linear feedback shift register engine unit 221c from the linear feedback shift register engine unit 221c, that is, the descrambling key is fed back and transmitted.

[0099] The linear feedback shift register engine unit 221c generates a descrambling key using the scrambling key estimated during the horizontal blanking period and can output the descrambling key output in the previous cycle during the horizontal active period.

[0100] The combining unit 221d can descramble the input data using the descrambling key output from the linear feedback shift register engine unit 221c to generate and output descrambled data.

[0101] In the second embodiment, as an example, a case where the number of data bits input to the descrambler is different from the number of data bits processed by the descrambler is illustrated.

[0102] Figure 10 To show Figure 2 The structural diagram of the descrambler of the second embodiment shown.

[0103] Refer to Figure 10 , the descrambler 221 of the second embodiment may include a multiplexer 221b, a linear feedback shift register engine unit 221c, and a combining unit 221d.

[0104] Data input during the horizontal blanking period is directly input to the combining unit 221d and is not transmitted to the linear feedback shift register engine unit 221c through the multiplexer 221b. Data input during the horizontal blanking period is directly input to the combining unit 221d and is transmitted to the linear feedback shift register engine unit 221c through the multiplexer 221b.

[0105] Data is input to the first input terminal of the multiplexer 221b, and the second input terminal is connected to the output terminal of the linear feedback shift register engine unit 221c. The multiplexer 221b transmits the input data to the linear feedback shift register engine unit 221c through the first input terminal according to the high logic level of the enable signal. On the contrary, the multiplexer 221b receives the descrambling key as feedback from the linear feedback shift register engine unit 221c according to the low logic level of the enable signal and transmits it.

[0106] The combining unit 221d can use the descrambling key output by the linear feedback shift register engine unit 221c to descramble the input data to generate and output descrambled data.

[0107] Figure 11 To show Figure 10 The figure of scrambling resynchronization.

[0108] Referring to Figure 11 , in the embodiment, when the scrambling synchronization is released due to noise or the like during the horizontal active period of receiving scrambled data, it can be seen that the scrambling resynchronization is automatically achieved by using the data input during the horizontal blanking period (H-Blank).

[0109] During the horizontal active period when noise is generated, scrambling resynchronization cannot be achieved. However, if the horizontal blanking period (H-Blank) is entered, a scrambling key is generated using one data after the end of the line, and then the scrambling resynchronization is achieved using the scrambling key.

[0110] Figure 12 The figure is used to compare and illustrate the scrambling resynchronization results of the comparative example and the embodiment.

[0111] Referring to Figure 12 , when driving the horizontal blanking period (H-Blank) between the horizontal active periods (H-Active), in the comparative example, when the scrambling synchronization is released due to noise or the like during the horizontal active period (H-Active), it is necessary to receive the scrambling reset information from the next horizontal active period (H-Active). Therefore, the scrambling resynchronization is achieved by using the scrambling reset information included in the EOL' transmitted after the horizontal active period (H-Active), the horizontal blanking period (H-Blank), and the next horizontal active period (H-Active).

[0112] In contrast, in the embodiment, when the scrambling synchronization is released due to noise or the like during the horizontal active period (H-Active), if entering the horizontal blanking period (H-Blank), the scrambling resynchronization is directly and automatically achieved by using the data input during the horizontal blanking period (H-Blank).

[0113] Therefore, compared with the comparative example, the scrambling resynchronization in the embodiment can be achieved not only further quickly but also without receiving the scrambling reset information from the transmitting end.

Claims

1. A data transmission device, characterized in that, Comprising: A first transmission device that scrambles digital image data using a scrambling key and transmits the scrambled image data; and A second transmission device that descrambles the scrambled image data using a descrambling key to restore the image data, In the case where synchronization with the first transmission device is released, the second transmission device uses predetermined pattern data input during the horizontal blanking period to restore the descrambling key.

2. The data transmission device according to claim 1, characterized in that, The first transmission device transmits the scrambled image data during the horizontal active period, After the horizontal active period, during the horizontal blanking period, pattern data composed of "0" is scrambled using the scrambling key and the scrambled pattern data is transmitted.

3. The data transmission device according to claim 1, wherein The second transmission device includes: A linear feedback shift register estimation unit that estimates the scrambling key using the data input by the first transmission device; A multiplexer that outputs the scrambling key estimated by the linear feedback shift register estimation unit during the horizontal blanking period; A linear feedback shift register engine unit that restores the descrambling key using the scrambling key output by the multiplexer and outputs it; and A combining unit that restores the image data by performing a logical operation on the data input by the first transmission device and the descrambling key output by the linear feedback shift register engine unit.

4. The data transmission device according to claim 3, characterized in that The linear feedback shift register estimation unit estimates the scrambling key using the Nth data and the (N + 1)th data input by the first transmission device, where N is a natural number.

5. The data transmission device according to claim 3, characterized in that The combining unit is an exclusive OR gate that performs an exclusive OR operation on the input data and the descrambling key.

6. The data transmission device according to claim 3, characterized in that The multiplexer receives the descrambling key output by the linear feedback shift register engine unit as feedback during the horizontal active period and outputs the feedback descrambling key to the linear feedback shift register engine unit.

7. The data transmission device according to claim 3, characterized in that, The second transmission device further includes a data comparison unit that selects the output of the multiplexer using the descrambled data output by the combining unit and a signal indicating the horizontal blanking period.

8. The data transmission device according to claim 7, characterized in that, The data comparison unit includes: A comparator that outputs "1" when the descrambled data output by the combining unit is not "0"; and An AND gate that outputs a signal for controlling the output of the multiplexer by performing a logical operation on the output of the comparator and a signal indicating the horizontal blanking period.

9. A display device, characterized in that, Comprising: A display panel having a plurality of pixels provided in an area where a plurality of gate lines intersect a plurality of data lines; A gate driving unit that outputs a gate signal through the gate lines; A data driving unit that outputs a data voltage through the data lines; and A timing controller for controlling the gate driving unit and the data driving unit, The timing controller includes a first transmission device that scrambles digital image data using a scrambling key and transmits the scrambled image data, The data driving unit includes a second transmission device, and the second transmission device uses a descrambling key to descramble the scrambled video data to restore the video data. In the case where synchronization with the first transmission device is released, the second transmission device uses predetermined pattern data input during the horizontal blanking period to restore the descrambling key.

10. The display device according to claim 9, wherein the first transmission device transmits the scrambled video data during the horizontal active period, after the horizontal active period, during the horizontal blanking period, pattern data consisting of "0" is scrambled using the scrambling key and the scrambled pattern data is transmitted.

11. The display device according to claim 9, wherein The second transmission device includes: a multiplexer that outputs the data input during the horizontal blanking period; a linear feedback shift register engine unit that restores the descrambling key using the data output by the multiplexer and outputs the same; and a combining unit that restores the video data by performing a logical operation on the data input by the first transmission device and the descrambling key output by the linear feedback shift register engine unit.

12. The display device according to claim 11, wherein The multiplexer receives the descrambling key output by the linear feedback shift register engine unit as feedback during the horizontal active period, and outputs the feedback descrambling key to the linear feedback shift register engine unit.

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