Thin film transistor, manufacturing method thereof, and display device including the same

Abstract

Disclosed are a thin film transistor, a method of manufacturing the same, and a display device including the same. The thin film transistor includes: a base substrate; an active layer on the base substrate; a gate electrode spaced apart from the active layer and overlapping at least a portion of the active layer; a source electrode connected to the active layer; and a drain electrode spaced apart from the source electrode and connected to the active layer; each of the gate electrode, the source electrode, and the drain electrode includes a first layer, and a second layer on the first layer, each of the source electrode and the drain electrode being connected to the active layer through a first contact portion, the first contact portion contacting each of the second layer of the source electrode and the second layer of the drain electrode, and the second contact portion contacting each of the second layer of the source electrode and the second layer of the drain electrode. The first layer includes a metal oxide (MOx) containing an element M, the second layer includes a low resistance metal, and the element M includes a Group 6B element. Accordingly, an increase in reflectivity of a component in the thin film transistor may be suppressed or prevented.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10 - 2023 - 0197345, filed on December 29, 2023, which is hereby incorporated by reference in its entirety as if fully set forth herein. Technical field

[0003] The present disclosure relates to a thin - film transistor, a method of manufacturing the same, and a display device including the thin - film transistor. Background art

[0004] Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since thin - film transistors can be manufactured on glass substrates or plastic substrates, they are widely used as switching devices for display devices such as liquid - crystal display devices or organic light - emitting devices.

[0005] Recently, research has been continuously conducted to achieve low reflection in the field of transistors. Summary of the invention

[0006] One embodiment of the present invention aims to provide a thin - film transistor in which source and drain electrodes have low - reflection characteristics to suppress or prevent an increase in reflectance.

[0007] One embodiment of the present invention aims to provide a thin - film transistor having low - resistance wiring characteristics while suppressing or preventing an increase in reflectance by adjusting a bilayer structure of source and drain electrodes having low - reflection characteristics.

[0008] Another embodiment of the present invention aims to provide a display device including such a thin - film transistor.

[0009] Another embodiment of the present invention aims to provide a method of manufacturing such a thin - film transistor.

[0010] In addition to the above - mentioned objects of the present disclosure, other objects and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0011] According to aspects of the present disclosure, the above and other objects can be achieved by providing a thin film transistor, which includes: a substrate; an active layer on the substrate; a gate electrode separated from the active layer and overlapping at least a part of the active layer; a source electrode connected to the active layer; and a drain electrode separated from the source electrode and connected to the active layer; each of the gate electrode, the source electrode, and the drain electrode includes a first layer and a second layer on the first layer, each of the source electrode and the drain electrode is connected to the active layer through a first contact portion, the first contact portion contacts each of the second layers of the source electrode and the drain electrode, the first layer includes a metal oxide (MOx) containing an element M, the second layer includes a low-resistance metal, and the element M includes a Group 6B element. In addition, a thin film transistor is also provided, which includes: a gate electrode, a source electrode, and a drain electrode; wherein at least one of the gate electrode, the source electrode, and the drain electrode includes a first layer and a second layer on the first layer, wherein the first layer includes a metal oxide (MOx) containing an element M, wherein the second layer includes a low-resistance metal, and wherein the element M includes a Group 6B element.

[0012] The Group 6B element may include at least one of chromium (Cr), molybdenum (Mo), and tungsten (W), and the low-resistance metal may include at least one of Cu, Ag, Al, Mo, and Ti.

[0013] The first layer may further include a dopant, and the dopant may include at least one of Ta, Ti, and Zn.

[0014] The first layer of the source electrode, the first layer of the drain electrode, and the first layer of the gate electrode may be formed in the same layer.

[0015] The gate electrode, the source electrode, and the drain electrode may be formed in the same layer.

[0016] The active layer may include: a channel region overlapping with the gate electrode; a source region connected to one side of the channel region; and a drain region connected to the other side of the channel region, and the first contact portion may be disposed on the source region and the drain region.

[0017] The first contact portion may include at least one selected from a metal and a transparent conductive oxide (TCO).

[0018] The metal may include a molybdenum-titanium alloy (MoTi).

[0019] Each of the first layer of the source electrode, the first layer of the drain electrode, and the first layer of the gate electrode may have to a thickness of.

[0020] The thin film transistor may further include a light-shielding layer on the substrate, and the source electrode is connected to the light-shielding layer through a second contact portion.

[0021] The light-shielding layer may include a first layer and a second layer on the first layer. The first layer may include a metal oxide (MOx) containing element M, the second layer may include a low-resistance metal, element M may include a Group 6B element, and the low-resistance metal may include at least one of Cu, Ag, Al, Mo, and Ti.

[0022] The second contact portion may include a low-resistance metal, and the low-resistance metal may include at least one of Cu, Ag, Al, Mo, and Ti.

[0023] The second contact portion may include: a first layer in contact with the light-shielding layer; and a second layer on the first layer. The first layer may include a molybdenum-titanium alloy (MoTi), and the second layer may include the low-resistance metal.

[0024] At least a part of the first layer of the second contact portion may contact any one of the first layer of the source electrode and the first layer of the drain electrode, and the first contact portion may contact the first layer of the source electrode and the first layer of the drain electrode.

[0025] Another configuration of the present invention provides a display device including the thin film transistor.

[0026] Another embodiment of the present invention provides a method of manufacturing a thin film transistor, including: forming an active layer on a substrate; forming a first contact portion on the active layer; forming a low-reflection material layer on the active layer; forming a first metal material layer on the low-reflection material layer; and forming a gate electrode, a source electrode, and a drain electrode by etching the low-reflection material layer and the first metal material layer. Each of the gate electrode, the source electrode, and the drain electrode includes a first layer and a second layer on the first layer. Each of the source electrode and the drain electrode is connected to the active layer through a first contact portion, the first contact portion contacts each of the second layer of the source electrode and the second layer of the drain electrode, the first layer includes a metal oxide (MOx) containing element M, the second layer includes a low-resistance metal, and element M includes a Group 6B element.

[0027] The step of forming the first contact on the active layer can be performed by sequentially forming an oxide semiconductor material layer and a second metal material layer and then patterning using a halftone mask.

[0028] After forming a low-reflection material layer on the active layer, the step of forming the first contact on the active layer is performed, and it may further include the step of forming a first photoresist material layer on the low-reflection material layer to etch a part of the first photoresist material layer; the step of forming a second metal material layer on the first photoresist material layer; and the step of removing the first photoresist material layer and the second metal material layer formed on the first photoresist material layer.

[0029] After forming a low-reflection material layer on the active layer, the step of forming the first contact on the active layer is performed, and it may further include: forming a first photoresist material layer on the low-reflection material layer and performing etching using a mask; the step of removing the first photoresist material layer; the step of forming a second metal material layer on the low-reflection material layer; the step of forming a second photoresist material layer on the second metal material layer; and the step of removing the second metal material layer that does not overlap with the second photoresist material layer using a mask.

[0030] One of the first photoresist material layer and the second photoresist material layer may be formed of a positive photoresist pattern, and the other of the first photoresist material layer and the second photoresist material layer may be formed of a negative photoresist pattern. Description of the Drawings

[0031] The above and other objects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the drawings, in which:

[0032] Figure 1 is a cross-sectional view of a thin-film transistor according to an embodiment of the present invention.

[0033] Figure 2 is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention.

[0034] Figure 3 is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention.

[0035] Figure 4 is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention.

[0036] Figure 5 is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention.

[0037] Figure 6 is a diagram showing a mechanism for reflecting external light.

[0038] Figures 7A to 7D is a process diagram showing a method of manufacturing a thin film transistor according to an embodiment of the present invention.

[0039] Figures 8A to 8G is a process diagram showing a method of manufacturing a thin film transistor according to another embodiment of the present invention.

[0040] Figures 9A to 9G is a process diagram showing a method of manufacturing a thin film transistor according to another embodiment of the present invention.

[0041] Figure 10 is a schematic diagram of a display device according to an embodiment of the present invention.

[0042] Figure 11 is Figure 10 a circuit diagram of any one pixel in Detailed Description of the Invention

[0043] The advantages, features, and methods of implementing the present disclosure will be clarified by the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0044] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings for describing the embodiments of the present disclosure are merely examples, and thus the present disclosure is not limited to the details shown. The same reference numerals denote the same elements throughout. In the following description, when it is determined that a detailed description of related known functions or configurations would unnecessarily obscure the focus of the present disclosure, the detailed description will be omitted.

[0045] In cases where "comprising", "having", and "including" are used in this application, additional parts may be added unless "only" is used. Terms in the singular form may include the plural form unless otherwise indicated.

[0046] When interpreting an element, although not explicitly stated, the element should be interpreted as including an error range.

[0047] When describing positional relationships, for example, when the positional relationship is described as "on", "above", "below", "beneath", and "next to", one or more other parts may be provided between the two parts unless "exactly" or "directly" is used.

[0048] Spatial relative terms such as "below", "beneath", "lower", "above", and "upper" may be used herein for ease of description of the relationship of one or more elements shown in the drawings to one or more other elements. It will be understood that these terms are intended to cover different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device shown in the drawings is reversed, the device described as being "below" or "beneath" another device may be disposed "above" the other device. Thus, the exemplary term "below or beneath" may include both the "below or beneath" and "above" orientations. Similarly, the exemplary terms "above" or "on" may include both the "above" and "below or beneath" orientations.

[0049] When describing temporal relationships, for example, when a chronological order is described as "after", "behind", "next", and "before", discontinuous cases may be included, unless "exactly" or "directly" is used.

[0050] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0051] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of the first element, the second element, and the third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0052] As can be fully understood by those skilled in the art, the features of the various embodiments of the present disclosure may be combined or combined with each other partially or wholly, and may be interoperable and driven with each other technically. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0053] When adding reference numerals to the components of the respective drawings describing the embodiments of the present disclosure, the same components that can be shown in other drawings may have the same reference numerals.

[0054] In the embodiments of the present disclosure, for ease of explanation, the source electrode and the drain electrode are distinguished from each other, and the source electrode and the drain electrode may be interchangeable. The source electrode may be the drain electrode, and vice versa. In addition, the source electrode in any one embodiment may be the drain electrode in other embodiments, and the drain electrode in any one embodiment may be the source electrode in other embodiments.

[0055] In some embodiments of the present disclosure, for ease of illustration, the source region is separated from the source electrode, and the drain region is separated from the drain electrode, but the embodiments of the present disclosure are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. In addition, the source region may be the drain electrode, and the drain region may be the source electrode.

[0056] Figure 1 is a cross-sectional view of a thin film transistor 100 according to an embodiment of the present invention. Figure 2 is a cross-sectional view of a thin film transistor 200 according to another embodiment of the present invention. Figure 3 is a cross-sectional view of a thin film transistor 300 according to another embodiment of the present invention. Figure 4 is a cross-sectional view of a thin film transistor 400 according to another embodiment of the present invention. Figure 5 is a cross-sectional view of a thin film transistor 500 according to another embodiment of the present invention.

[0057] Specifically, referring to Figure 1 , a buffer layer 120 disposed on a substrate 110, an active layer 130 disposed on the buffer layer 120, a gate electrode 150 separated from the active layer 130 to at least partially overlap with the active layer 130, a source electrode 160 connected to the active layer 130, and a drain electrode 170 are provided.

[0058] According to an embodiment of the present invention, the thin film transistor 100 may further include a substrate 110. Referring to Figure 1 , the buffer layer 120 is disposed on the substrate 110.

[0059] According to an embodiment of the present invention, the thin film transistor 100 may further include a gate insulating layer 140. Referring to Figure 1 , the gate insulating layer 140 is disposed on the active layer 130. Specifically, the gate insulating layer 140 is disposed between the active layer 130 and the gate electrode 150.

[0060] According to an embodiment of the present invention, other layers of the thin film transistor 100 may be additionally disposed on the gate electrode 150. Specifically, the thin film transistor 100 may further include an interlayer insulating layer. Although not shown in the figure, the gate electrode 150 may be disposed between the gate insulating layer 140 and the interlayer insulating layer.

[0061] Hereinafter, the components of the thin film transistor 100 according to an embodiment of the present invention will be described in more detail.

[0062] Glass or plastic may be used as the substrate 110. As the plastic, a transparent plastic having a flexible property, for example, polyimide, may be used.

[0063] When using polyimide as the base substrate 110, considering the high-temperature deposition process performed on the base substrate 110, heat-resistant polyimide capable of withstanding high temperatures can be used. In this case, in order to form a thin-film transistor, processes such as deposition and etching can be performed in a state where the polyimide substrate is disposed on a carrier substrate made of a highly durable material such as glass.

[0064] Referring to Figure 1 , a buffer layer 120 can be provided on the base substrate 110.

[0065] The buffer layer 120 is formed on the base substrate 110 and can be formed of an inorganic material or an organic material. For example, insulating oxides such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), and aluminum oxide (Al2O3).

[0066] The buffer layer 120 protects the active layer 130 by blocking impurities such as moisture and oxygen introduced from the base substrate 110, flattens the upper portion of the base substrate 110, and can be formed as a single layer or multiple layers.

[0067] Referring to Figure 1 and Figure 2 , an active layer 130 can be provided on the buffer layer 120.

[0068] The active layer 130 can include a channel region 130n, a source region 130a, and a drain region 130b.

[0069] The channel region 130n overlaps with the gate electrode 150. The channel region 130n serves as the channel of the thin-film transistor 100.

[0070] Specifically, the active layer 130 can include a channel region 130n that overlaps with the gate electrode 150, a source region 130a that is not overlapped with the gate electrode 150 and is connected to one side of the channel region 130n, and a drain region 130b that is connected to the other side of the channel region 130n.

[0071] According to an embodiment of the present invention, the source region 130a and the drain region 130b are separated from each other with the channel region 130n sandwiched therebetween.

[0072] According to the configuration of the present invention, the active layer 130 can be formed of a semiconductor material. The active layer 130 can include an oxide semiconductor material.

[0073] The oxide semiconductor material may include at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, and an FIZO (FeInZnO)-based oxide semiconductor material. However, embodiments of the present invention are not limited thereto, and the active layer 130 may be made of other oxide semiconductor materials known in the art.

[0074] The source region 130a and the drain region 130b may be formed by selectively conducting the active layer 130 made of a semiconductor material. According to an embodiment of the present invention, giving conductivity to a specific part of the active layer 130 so that it can be used as a conductor is called selective conduction. Through this selective conduction, the part given conductivity is conductive, while the part not given conductivity is not conductive.

[0075] Although Figure 1 a configuration in which the active layer 130 is formed of a single layer is disclosed in, the configuration of the present invention is not limited thereto. The active layer 130 may have a single-layer structure or a multi-layer structure.

[0076] According to an embodiment of the present invention, the channel region 130n, the source region 130a, and the drain region 130b of the active layer 130 may be integrally formed, and the active layer 130 may have a constant thickness. Specifically, the thickness of the active layer 130 may be substantially the same.

[0077] The gate insulating layer 140 is disposed on the active layer 130. The gate insulating layer 140 protects the channel region 130n. Specifically, the gate insulating layer 140 is disposed between the active layer 130 and the gate electrode 150.

[0078] The gate insulating layer 140 has an insulating property. For example, the gate insulating layer 140 may include at least one of silicon oxide, silicon nitride, and metal-based oxides. The gate insulating layer 140 may have a single-layer structure or a multi-layer structure.

[0079] The gate electrode 150 is disposed on the gate insulating layer 140. The gate electrode 150 overlaps with the channel region 130n of the active layer 130.

[0080] According to an embodiment of the present invention, the gate electrode 150 may include a first layer 150a and a second layer 150b on the first layer 150a.

[0081] Specifically, the first layer 150a of the gate electrode 150 may include a metal oxide (MOx) containing element M, and the second layer 150b may include a low-resistance metal. In this case, element M may include a Group 6B element.

[0082] For example, the Group 6B element may include at least one of chromium (Cr), molybdenum (Mo), and tungsten (W).

[0083] For example, the low-resistance metal may include at least one of Cu, Ag, Al, Mo, and Ti.

[0084] When the first layer 150a of the gate electrode 150 includes a metal oxide (MOx) containing element M and the second layer 150b includes a low-resistance metal, the first layer 150a may reflect a part of the light incident from the outside and transmit or absorb the remaining part of the light. In addition, the remaining light transmitted or absorbed in the first layer 150a may be reflected from the surface of the second layer 150b of the gate electrode 150. Therefore, the light reflected from the first layer 150a and the second layer 150b meets on the surface of the first layer 150a in an opposite phase state, thereby causing destructive interference. Therefore, an increase in reflectance due to external light in the display device can be reduced or prevented.

[0085] According to an embodiment of the present invention, the first layer 150a of the gate electrode 150 may further include a dopant. Specifically, the first layer 150a of the gate electrode 150 may further include a dopant to improve optical characteristics. In this case, the dopant may include at least one of Ta, Ti, and Zn.

[0086] However, the embodiment of the present invention is not limited thereto, and the first layers 160a and 170a of the source electrode 160 and the drain electrode 170 may further include a dopant.

[0087] According to an embodiment of the present invention, the gate insulating layer 140 may be patterned by etching using the gate electrode 150 as a mask. In this process, the active layer 130 may be selectively conductive to form a source region 130a and a drain region 130b. Specifically, according to an embodiment of the present invention, the region of the active layer 130 overlapping with the gate electrode 150 is not conductive, thereby becoming a channel region 130n having semiconductor characteristics, and the regions not overlapping with the gate electrode 150 may be conductive, thereby becoming the source region 130a and the drain region 130b.

[0088] According to an embodiment of the present invention, the thin film transistor 100 may include a source electrode 160 and a drain electrode 170. The positions of the source electrode 160 and the drain electrode 170 may be exchanged with each other. However, the embodiments of the present invention are not limited thereto, and the source region 130a and the drain region 130b may be used as the source electrode and the drain electrode, respectively.

[0089] Referring to Figure 1 , each of the source electrode 160 and the drain electrode 170 may be connected to the active layer 130 through a contact hole. Specifically, the source electrode 160 may be in contact with the source region 130a through the contact hole. The drain electrode 170 may be separated from the source electrode 160 to be in contact with the drain region 130b through the contact hole. More specifically, the source electrode 160 and the drain electrode 170 may be connected to the active layer 130 through the first contact portion 135.

[0090] Hereinafter, the source electrode 160, the drain electrode 170, and the first contact portion 135 according to an embodiment of the present invention will be described in detail.

[0091] Referring to Figure 1 , the source electrode 160 is connected to the active layer 130, and the drain electrode 170 is separated from the source electrode 160 and connected to the active layer 130.

[0092] The source electrode 160 and the drain electrode 170 include a first layer 160a and 170a, and second layers 160b and 170b respectively located on the first layers 160a and 170a.

[0093] In this case, the first layers 150a, 160a, and 170a of the gate electrode 150, the source electrode 160, and the drain electrode 170 may be provided in the same layer. Specifically, referring to Figure 1 , the first layers 150a, 160a, and 170a of the gate electrode 150, the source electrode 160, and the drain electrode 170 are provided on the gate insulating layer 140. More specifically, the first layers 150a, 160a, and 170a of the gate electrode 150, the source electrode 160, and the drain electrode 170 may be formed of the same material through the same process.

[0094] According to an embodiment of the present invention, the gate electrode 150, the source electrode 160, and the drain electrode 170 may be provided in the same layer. Specifically, referring to Figure 1 , the gate electrode 150, the source electrode 160, and the drain electrode 170 are provided on the gate insulating layer 140. More specifically, the gate electrode 150, the source electrode 160, and the drain electrode 170 may be formed of the same material through the same process.

[0095] According to an embodiment of the present invention, the first layers 160a and 170a of the source electrode 160 and the drain electrode 170 may include a metal oxide (MOx) containing an element M, and the second layers 160b and 170b may include a low-resistance metal. In this case, the element M may include a Group 6B element.

[0096] For example, the Group 6B element may include at least one of chromium (Cr), molybdenum (Mo), and tungsten (W).

[0097] For example, the low-resistance metal may include at least one of Cu, Ag, Al, Mo, and Ti.

[0098] When the first layers 160a and 170a of the source electrode 160 and the drain electrode 170 include a metal oxide (MOx) containing an element M and the second layers 160b and 170b include a low-resistance metal, the first layers 160a and 170a may reflect a part of the light incident from the outside and transmit or absorb the remaining part of the light. In addition, the remaining light transmitted or absorbed by the first layers 160a and 170a may be reflected from the surfaces of the second layers 160b and 170b of the source electrode 160 and the drain electrode 170. Therefore, the light reflected from the first layers 160a and 170b meets on the surfaces of the first layers 160a and 170a in opposite phase states, thereby causing destructive interference. Therefore, an increase in reflectance due to external light in the display device can be reduced or prevented.

[0099] In addition, when the second layers 160b and 170b of the source electrode 160 and the drain electrode 170 contain a low-resistance metal material such as a low-resistance metal, the source electrode 160 and the drain electrode 170 can be used as wirings having low-resistance characteristics.

[0100] That is, in the source electrode 160 and the drain electrode 170 according to the present invention, the first layers 160a and 170a include a metal oxide (MOx) containing an element M, thereby reducing the reflectance of the light incident from the outside. At the same time, the second layers 160b and 170b contain a low-resistance metal, thereby reducing the resistance of the source electrode 160 and the drain electrode 170 so that they can be used as wirings.

[0101] According to an embodiment of the present invention, the first contact portions 135 may be in contact with the second layer 160b of the source electrode 160 and the second layer 170b of the drain electrode 170, respectively.

[0102] Specifically, the first contact portions 135 may be disposed on the source region 130a and the drain region 130b of the active layer 130. Figure 1In this case, a structure is shown in which the second layer 160b of the source electrode 160 is connected to the source region 130a through the first contact portion 135, and a structure is shown in which the second layer 170b of the drain electrode 170 is connected to the drain region 130b through the first contact portion 135.

[0103] According to an embodiment of the present invention, the first contact portion may include at least one selected from metals and transparent conductive oxides (TCOs). Specifically, the metal may include a molybdenum-titanium alloy (MoTi), and the transparent conductive oxide (TCO) may include ITO (InSnO), IZO (InZnO), IO (InO), TO (SnO), and ZO (ZnO). However, the embodiments of the present invention are not limited thereto, and the first contact portion 135 may include a conductive oxide.

[0104] The first contact portion 135 may have a reducing property. The active layer 130 may be selectively conductive through the first contact portion 135. According to an embodiment of the present invention, the source region 130a and the drain region 130b are respectively in contact with the first contact portion 135. The regions of the active layer 130 in contact with the first contact portion 135 are conductive, and the source region 130a and the drain region 130b may be respectively formed.

[0105] Specifically, according to an embodiment of the present invention, portions of the active layer 130 in contact with the first contact portion 135 may be respectively reduced to form the source region 130a and the drain region 130b.

[0106] For example, when a part of the active layer 130 in contact with and overlapping the first contact portion 135 is reduced, an oxygen vacuum occurs in the active layer 130, and thus, the active layer 130 may be selectively conductive. Through the selective reduction of the active layer 130, the source region 130a and the drain region 130b may be formed.

[0107] According to an embodiment of the present invention, a separate layer including a metal or a conductive oxide is not provided between the first layers 150a, 160a, and 170a of the gate electrode 150, the source electrode 160, and the drain electrode 170 and the gate insulating layer 140.

[0108] When a separate layer including a metal or a conductive oxide having a high reflectivity is provided between the gate insulating layer 140 and the first layers 150a, 160a, and 170a of the gate electrode 150, the source electrode 160, and the drain electrode 170, the reflectivity with respect to light incident from the outside is excessively increased. As a result, it becomes difficult to suppress an increase in the reflectivity with respect to external light in the display device.

[0109] According to an embodiment of the present invention, the thicknesses of the first layers 150a, 160a, and 170a of the gate electrode 150, the source electrode 160, and the drain electrode 170 may be 200 to In this case, when the first layers 150a, 160a, and 170a of the gate electrode 150, the source electrode 160, and the drain electrode 170 have a thickness of 200 to the first layers 150a, 160a, and 170a can be effectively stacked on the gate insulating layer 140 and, at the same time, have excellent low-reflection characteristics.

[0110] On the other hand, when the first layers 150a, 160a, and 170a of the gate electrode 150, the source electrode 160, and the drain electrode 170 have a thickness less than the first layers 150a, 160a, and 170a cannot be sufficiently stacked, and thus the thin-film transistor 100 may not have excellent low-reflection characteristics.

[0111] In addition, when the first layers 150a, 160a, and 170a of the gate electrode 150, the source electrode 160, and the drain electrode 170 have a thickness greater than the distance between the gate electrode 150 and the active layer 130 becomes too far, resulting in a problem that the influence of the electric field generated in the gate electrode 150 is excessively reduced. In addition, when the first layers 150a, 160a, and 170a have a thickness greater than the thickness of the first layers 150a, 160a, and 170a becomes too thick, causing a step difference between the respective layers and resulting in a problem of seams appearing in the step difference.

[0112] The thin-film transistor 200 according to an embodiment of the present invention may further include a light-shielding layer 111. Figure 2 The structure in which the light-shielding layer 111 is provided on the substrate 110 is shown.

[0113] According to an embodiment of the present invention, the source electrode 160 may be connected to the light-shielding layer 111 through the second contact portion 136. Figure 2 The structure in which the source electrode 160 and the light-shielding layer 111 are connected through the second contact portion 136 is shown.

[0114] According to an embodiment of the present invention, the light-shielding layer 111 may include a first layer 111a and a second layer 111b on the first layer 111a. Specifically, the first layer 111a of the light-shielding layer 111 may include a metal oxide (MOx) containing an element M, and the second layer 111b may include a low-resistance metal. In this case, the element M may include a Group 6B element. For example, the Group 6B element may include at least one of chromium (Cr), molybdenum (Mo), and tungsten (W), and the low-resistance metal may include at least one of Cu, Ag, Al, Mo, and Ti.

[0115] Compared with Figure 1 Figure 2Further including a light-shielding layer 111, even in this case, the first layer 111a of the light-shielding layer 111 can reflect a part of the light incident from the outside, and transmit or absorb the remaining part of the light. In addition, the remaining light transmitted or absorbed in the first layer 111a can be reflected on the surface of the second layer 111b of the light-shielding layer 111. Therefore, the light reflected from the first layer 111a and the second layer 111b meets on the surface of the first layer 111a in opposite phase states, thereby causing destructive interference. Therefore, an increase in reflectance due to external light in the display device can be reduced or prevented.

[0116] According to an embodiment of the present invention, the second contact portion 136 may include a low-resistance metal. Specifically, the second contact portion 136 may be formed of the same material as the materials of the second layers 150b, 160b, and 170b of the gate electrode 150, the source electrode 160, and the drain electrode 170.

[0117] According to an embodiment of the present invention, the second contact portion 136 may include a first layer 136a and a second layer 136b on the first layer 136a. Specifically, referring to Figure 3 , the second contact portion 136 may include a first layer 136a in contact with the light-shielding layer 111 and a second layer 136b in contact with the source electrode 160.

[0118] The second contact portion 136 refers to a region formed inside the hole compared to the source electrode 160. Specifically, the second contact portion 136 refers to a region formed in the thin-film transistor manufacturing process and surrounded by the buffer layer 120, the gate insulating layer 140, and the first layer 160a of the source electrode 160.

[0119] In this case, the first layer 136a of the second contact portion 136 may include a molybdenum-titanium alloy (MoTi), and the second layer 136b may include a low-resistance metal. Specifically, the first layer 136a of the second contact portion 136 may be formed of the same material as the first contact portion 135 by the same process, and the second layer 136b of the second contact portion 136 may be formed of the same material as the second layers 150b, 160b, and 170b of the gate electrode 150, the source electrode 160, and the drain electrode 170 by the same process.

[0120] According to an embodiment of the present invention, the first layer 136a of the second contact portion 136 may be in contact with the first layer 160a of the source electrode 160. In Figure 3 , a structure in which the first layer 136a of the second contact portion 136 is in contact with the first layer 160a of the source electrode 160 is shown. In this case, the first contact portion 135 may be in contact with the first layers 160a and 170a of the source electrode 160 and the drain electrode 170.

[0121] Specifically, the first contact portion 135 contacts the first layers 160a and 170a of the source electrode 160 and the drain electrode 170 in the hole region. In this case, the hole region refers to the region formed by etching the gate insulating layer 140. More specifically, the first contact portion 135 is formed along the side surface of the gate insulating layer 140, and the first contact portion 135 formed along the side surface can contact the first layers 160a and 170a of the source electrode 160 and the drain electrode 170.

[0122] However, the embodiment of the present invention is not limited thereto, and the first layer 136a of the second contact portion 136 can be separated from the first layer 160a of the source electrode 160. For example, in Figure 4 and Figure 5 although there are differences in the separation distance between the first layer 136a of the second contact portion 136 and the first layer 160a of the source electrode 160, a structure in which the first layer 136a of the second contact portion 136 is separated from the first layer 160a of the source electrode 160 is shown. In addition, although not shown in the figure, at least a part of the first layer 136a of the second contact portion 136 can contact any one of the first layer 160a of the source electrode 160 and the first layer 170a of the drain electrode 170, and the first contact portion 135 can contact the first layer 160a of the source electrode 160 and the first layer 170a of the drain electrode 170.

[0123] Figure 6 is a diagram showing a mechanism for reflecting external light.

[0124] Figure 6 shows a mechanism in which external light 1 and external light 2 are reflected from the first layer 160a and the second layer 160b of the source electrode 160.

[0125] Specifically, Figure 6 the external light 1 shows a state in which the light incident from the outside is reflected from the first layer 160a of the source electrode 160, and the intensity of the reflected light is weaker than the intensity of the incident light. Therefore, an increase in reflectivity due to external light in the display device can be reduced or prevented.

[0126] Figure 6 the external light 2 shows a state in which the light incident from the outside passes through the first layer 160a of the source electrode 160 and is reflected from the surface of the second layer 160b provided on the first layer 160a. Even in this case, the intensity of the reflected light is weaker than the intensity of the incident light. Therefore, an increase in reflectivity due to external light in the display device can be reduced or prevented.

[0127] In this case, although not shown in the drawings, the light reflected from the first layer 160a and the second layer 160b has opposite phases to each other, and thus meets on the surface of the first layer 160a to cause destructive interference. Therefore, an increase in reflectance due to external light in the display device can be reduced or prevented, thereby achieving a low reflection characteristic.

[0128] Although Figure 6 only the state in which the external light is reflected only in the source electrode 160 is shown, the external light is reflected not only in the source electrode 160 but also in the first layers 111a, 150a, and 170a and the second layers 111b, 150b, and 170b of the light-shielding layer 111, the gate electrode 150, and the drain electrode 170, thereby reducing or preventing an increase in reflectance to achieve a low reflection characteristic.

[0129] Hereinafter, a method of manufacturing a thin film transistor according to an embodiment of the present invention will be described.

[0130] According to an embodiment of the present invention, a method of manufacturing a thin film transistor may include: forming an active layer 130 on a substrate 110; forming a low-reflection material layer 105 on the active layer 130; forming a first metal material layer 107a on the low-reflection material layer 105; and forming a gate electrode 150, a source electrode 160, and a drain electrode 170 by etching the low-reflection material layer 105 and the first metal material layer 107a.

[0131] Figures 7A to 7D is a process diagram of a method of manufacturing a thin film transistor according to an embodiment of the present invention. Figures 7A to 7D Corresponding to Figure 2 a cross-sectional view.

[0132] Referring to Figure 7A , a light-shielding layer 111, a buffer layer 120, and an active layer 130 are sequentially stacked on a substrate 110, and then a first contact portion 135 is formed on the active layer 130.

[0133] In this case, although not specifically shown in the drawings, after sequentially forming an oxide semiconductor material layer and a second metal material layer 107b, the step of forming the first contact portion 135 on the active layer 130 in Figure 7A may be performed by patterning using a halftone mask.

[0134] Referring to Figure 7B , a gate insulating layer 140a and a low-reflection material layer 105 are sequentially formed on the active layer 130 and the first contact portion 135.

[0135] Referring to Figure 7C , holes are formed by etching a part of the gate insulating layer 140a and the low-reflection material layer 105.

[0136] Referring to Figure 7D , after the first metal material layer 107a is formed on the low-reflection material layer 105, the low-reflection material layer 105 and the first metal material layer 107a are etched to form a gate electrode 150, a source electrode 160, and a drain electrode 170.

[0137] In this case, the formed gate electrode 150, source electrode 160, and drain electrode 170 include first layers 150a, 160a, and 170a and second layers 150b, 160b. The source electrode 160 and the drain electrode 170 are respectively connected to the active layer 130 through first contact portions 135. The first contact portions 135 are in contact with the second layers 160b of the source electrode 160 and the second layers 170b of the drain electrode 170. The first layers 150a, 160a, and 170a respectively include a metal oxide (MOx) containing element M, and the second layers 150b, 160b, and 170b may include a low-resistance metal.

[0138] However, the embodiments of the present invention are not limited thereto, and a gate wiring (not shown) extending from the gate electrode 150 may also form layers corresponding to the first layer 150a and the second layer 150b of the gate electrode 150, and source wirings (not shown) and drain wirings (not shown) extending from the source electrode 160 and the drain electrode 170 may also form layers corresponding to the first layers 160a and 170a and the second layers 160b and 170b of the source electrode 160 and the drain electrode 170. Therefore, an increase in the reflectance with respect to external light in the display device can be suppressed.

[0139] Figures 8A to 8G is a process diagram showing a method of manufacturing a thin film transistor according to another embodiment of the present invention. Figures 8A to 8G Corresponding to Figure 2 the cross-sectional view.

[0140] Referring to Figure 8A , a light-shielding layer 111, a buffer layer 120, and an active layer 130 are sequentially stacked on a substrate 110.

[0141] Referring to Figure 8B , a gate insulating layer 140a and a low-reflection material layer 105 are sequentially formed on the active layer 130.

[0142] Referring to Figure 8C , after a first photoresist material layer 106 is formed on the low-reflection material layer 105, a part of the gate insulating layer 140a and the low-reflection material layer 105 is etched using a mask M.

[0143] Referring to Figure 8D, a second metal material layer 107b is formed on the first photoresist material layer 106. In this case, the second metal material layer 107b is stacked on the entire surface of the thin film transistor.

[0144] Refer to Figure 8E , the first photoresist material layer 106 and the second metal material layer 107b formed on the first photoresist material layer 106 are removed. In this case, the first photoresist material layer 106 and the second metal material layer 107b formed on the first photoresist material layer 106 are removed. In addition, the second contact portion 136 can be formed by the process shown in Figure 8E .

[0145] Refer to Figure 8F , a first metal material layer 107a can be formed on the low-reflection material layer 105. Specifically, the first metal material layer 107a covers the entire surfaces of the low-reflection material layer 105 and the second metal material layer 107b.

[0146] Refer to Figure 8G , the gate electrode 150, the source electrode 160, and the drain electrode 170 are formed by etching the low-reflection material layer 105 and the first metal material layer 107a. The first contact portion 135 is formed by the etching in Figure 8G .

[0147] Figures 9A to 9G is a process diagram showing a method of manufacturing a thin film transistor according to another embodiment of the present invention. Figures 9A to 9G Corresponds to Figure 2 's cross-sectional view.

[0148] Refer to Figure 9A , a light-shielding layer 111, a buffer layer 120, and an active layer 130 are sequentially stacked on the base substrate 110.

[0149] Refer to Figure 9B , a gate insulating layer 140a and a low-reflection material layer 105 are sequentially formed on the active layer 130.

[0150] Refer to Figure 9C , after forming the first photoresist material layer 106 on the low-reflection material layer 105, a part of the gate insulating layer 140a and the low-reflection material layer 105 is etched using the mask M.

[0151] Refer to Figure 9D , the first photoresist material layer 106 is removed, a second metal material layer 107b is formed on the low-reflection material layer 105, and a second photoresist material layer 108 is formed in a region that does not overlap with the mask M used in Figure 9C .

[0152] In this case, the first photoresist material layer 106 and the second photoresist material layer 108 are formed of different types of photoresist patterns. For example, one of the first photoresist material layer 106 and the second photoresist material layer 108 may be formed of a positive (+) type photoresist pattern, and the other may be formed of a negative (-) type photoresist pattern.

[0153] Referring to Figure 9E , the second photoresist material layer 108 and the second metal material layer 107b on which the second photoresist material layer 108 is not provided are removed. In this case, the second photoresist material layer 108 and the second metal material layer 107b on which the second photoresist material layer 108 is not provided are removed. In addition, the second contact portion 136 can be formed by the process shown in Figure 9E .

[0154] Referring to Figure 9F , the first metal material layer 107a can be formed on the low-reflection material layer 105. Specifically, the first metal material layer 107a covers the entire surfaces of the low-reflection material layer 105 and the second metal material layer 107b.

[0155] Referring to Figure 9G , the first metal material layer 107a is formed on the low-reflection material layer 105, and then the low-reflection material layer 105 and the first metal material layer 107a are etched to form the gate electrode 150, the source electrode 160, and the drain electrode 170. The first contact portion 135 is formed by the etching in Figure 9G .

[0156] Figure 10 is a schematic diagram showing a display device 1000 according to still another embodiment of the present disclosure.

[0157] As shown in Figure 10 , a display device 1000 according to still another embodiment of the present disclosure may include: a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0158] The display panel 310 includes gate lines GL and data lines DL, and pixels P are provided in the crossing regions of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be provided on a substrate 110.

[0159] The controller 340 controls the gate driver 320 and the data driver 330.

[0160] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 by using signals supplied from an external system (not shown). In addition, the controller 340 samples the input image data input from the external system, realigns the sampled data, and supplies the realigned digital image data RGB to the data driver 330.

[0161] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, a control signal for controlling the shift register may be included in the gate control signal GCS.

[0162] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0163] The data driver 330 supplies a data voltage to the data lines DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into an analog data voltage and supplies the data voltage to the data lines DL.

[0164] According to an embodiment of the present disclosure, the gate driver 320 may be encapsulated on the display panel 310. In this way, the structure in which the gate driver 320 is directly encapsulated on the display panel 310 will be referred to as an in-panel gate (GIP) structure. Specifically, in the in-panel gate (GIP) structure, the gate driver 320 may be disposed on the base substrate 110.

[0165] The display device 1000 according to an embodiment of the present disclosure may include the above-described thin film transistors 100, 200, 300, 400, and 500. According to an embodiment of the present disclosure, the gate driver 320 may include the above-described thin film transistors 100, 200, 300, 400, and 500.

[0166] The gate driver 320 may include a shift register 350.

[0167] The shift register 350 sequentially provides gate pulses to the gate lines GL in one frame by using a start signal and a gate clock transmitted from the controller 340. In this case, one frame refers to a period during which one image is output through the display panel 310. The gate pulse has a conduction voltage capable of turning on a switching device (thin film transistor) provided in the pixel P.

[0168] In addition, during another period of a frame, the shift register 350 will be able to provide a gate cut-off signal for turning off the switching device to the gate line GL that has not been provided with a gate pulse. Hereinafter, the gate pulse and the gate cut-off signal are collectively referred to as the scan signal SS or Scan.

[0169] The shift register 350 may include the thin film transistors 100, 200, 300, 400, and 500 described above.

[0170] Figure 11 Yes Figure 10 is the circuit diagram of any one pixel P in.

[0171] Figure 11 The circuit diagram of is an equivalent circuit diagram of the pixel P of the display device 1000 including an organic light emitting diode (OLED) as the display element 710.

[0172] Referring to Figure 11 , the pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710. Specifically, the display device 1000 according to an embodiment of the present disclosure may include a pixel driving circuit PDC on the substrate 110.

[0173] Figure 11 The pixel driving circuit PDC of includes a first thin film transistor TR1 as a switching transistor and a second thin film transistor TR2 as a driving transistor. The display device 1000 according to another embodiment of the present disclosure may include at least one of the thin film transistors 100, 200, 300, 400, and 500 described above.

[0174] The first thin film transistor TR1 is connected to the gate line GL and the data line DL and is turned on or off by the scan signal SS supplied through the gate line GL. In this case, the gate line GL and the data line DL may form layers corresponding to the first layer 150a, 160a, 170a and the second layer 150b, 160b, 170b of the gate electrode 150, source electrode 160, and drain electrode 170 according to an embodiment of the present invention. Therefore, an increase in the reflectance with respect to external light in the display device can be suppressed.

[0175] The data line DL provides a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls the application of the data voltage Vdata.

[0176] The driving power supply line PL provides a driving voltage Vdd to the display element 710, and the first thin film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the organic light emitting diode (OLED) as the display element 710.

[0177] When the first thin film transistor TR1 is turned on by a scan signal SS applied from the gate driver 320 through the gate line GL, a data voltage Vdata provided through the data line DL is supplied to the gate electrode of the second thin film transistor TR2 connected to the display element 710. The data voltage Vdata is charged in a storage capacitor C1 formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0178] The amount of current supplied to the organic light emitting diode (OLED) serving as the display element 710 through the second thin film transistor TR2 is controlled according to the data voltage Vdata, whereby the gray level of the light output from the display element 710 can be controlled.

[0179] According to the present disclosure, the following beneficial effects can be obtained.

[0180] In the thin film transistor according to an embodiment of the present invention, since the source electrode and the drain electrode have a double layer structure with low reflection characteristics, an increase in reflectivity can be suppressed or prevented.

[0181] The thin film transistor according to an embodiment of the present invention can suppress or prevent an increase in reflectivity by adjusting the double layer structure of the source electrode and the drain electrode having low reflection characteristics, and can have the characteristics of a low resistance wiring.

[0182] In addition to the above effects, other effects of the present invention can be clearly understood by those of ordinary skill in the art to which the present invention pertains from such technology and description.

[0183] It will be apparent to those skilled in the art that the above present disclosure is not limited by the above embodiments and the drawings, and various substitutions, modifications and changes can be made in the present disclosure without departing from the spirit or scope of the present disclosure. Accordingly, the scope of the present disclosure is defined by the appended claims, and all changes or modifications derived from the meaning, scope and equivalent concepts of the claims fall within the scope of the present disclosure.

Claims

1. A thin film transistor, comprising: A substrate; An active layer on the substrate; A gate electrode separated from the active layer and overlapping at least a part of the active layer; A source electrode connected to the active layer; And A drain electrode separated from the source electrode and connected to the active layer; Wherein each of the gate electrode, the source electrode, and the drain electrode includes a first layer and a second layer on the first layer, Wherein each of the source electrode and the drain electrode is connected to the active layer through a first contact portion, Wherein the first contact portion contacts each of the second layer of the source electrode and the second layer of the drain electrode, Wherein the first layer includes a metal oxide (MOx) containing an element M, Wherein the second layer includes a low-resistance metal, and Wherein the element M includes a Group 6B element.

2. The thin film transistor according to claim 1, wherein the Group 6B element includes at least one of chromium (Cr), molybdenum (Mo), and tungsten (W), and The low-resistance metal includes at least one of Cu, Ag, Al, Mo, and Ti.

3. The thin film transistor according to claim 1, wherein the first layer further includes a dopant, and The dopant includes at least one of Ta, Ti, and Zn.

4. The thin film transistor according to claim 1, wherein the first layer of the source electrode, the first layer of the drain electrode, and the first layer of the gate electrode are formed in the same layer.

5. The thin film transistor according to claim 1, wherein the gate electrode, the source electrode, and the drain electrode are formed in the same layer.

6. The thin film transistor according to claim 1, wherein the active layer includes: A channel region overlapping the gate electrode; A source region connected to one side of the channel region; And A drain region connected to the other side of the channel region, and Wherein the first contact portion is provided on the source region and the drain region.

7. The thin film transistor according to claim 1, wherein the first contact portion includes at least one selected from a metal and a transparent conductive oxide (TCO).

8. The thin film transistor according to claim 7, wherein the metal includes a molybdenum-titanium alloy (MoTi).

9. The thin film transistor according to claim 1, wherein each of the first layer of the source electrode, the first layer of the drain electrode, and the first layer of the gate electrode has to a thickness of.

10. The thin film transistor according to claim 1, further comprising a light-shielding layer on the substrate, and The source electrode is connected to the light-shielding layer through a second contact portion.

11. The thin film transistor according to claim 10, wherein the light-shielding layer includes a first layer and a second layer on the first layer, The first layer includes a metal oxide (MOx) containing an element M, The second layer includes a low-resistance metal, The element M includes a Group 6B element, and The low-resistance metal includes at least one of Cu, Ag, Al, Mo, and Ti.

12. The thin film transistor according to claim 10, wherein the second contact portion includes a low-resistance metal, and The low-resistance metal includes at least one of Cu, Ag, Al, Mo, and Ti.

13. The thin film transistor according to claim 12, wherein the second contact portion includes: a first layer in contact with the light-shielding layer; and a second layer on the first layer; the first layer includes a molybdenum-titanium alloy (MoTi), and the second layer includes the low-resistance metal.

14. The thin film transistor according to claim 13, wherein at least a part of the first layer of the second contact portion contacts any one of the first layer of the source electrode and the first layer of the drain electrode, and the first contact portion contacts the first layer of the source electrode and the first layer of the drain electrode.

15. A thin film transistor, comprising: a gate electrode, a source electrode, and a drain electrode; wherein at least one of the gate electrode, the source electrode, and the drain electrode includes a first layer and a second layer on the first layer, wherein the first layer includes a metal oxide (MOx) containing element M, wherein the second layer includes a low-resistance metal, and wherein the element M includes a Group 6B element.

16. A display device, comprising the thin film transistor according to any one of claims 1 to 15.

17. A method of manufacturing a thin film transistor, comprising: forming an active layer on a substrate; forming a first contact portion on the active layer; forming a low-reflection material layer on the active layer; forming a first metal material layer on the low-reflection material layer; and forming a gate electrode, a source electrode, and a drain electrode by etching the low-reflection material layer and the first metal material layer, wherein each of the gate electrode, the source electrode, and the drain electrode includes a first layer and a second layer on the first layer, wherein each of the source electrode and the drain electrode is connected to the active layer through the first contact portion, wherein the first contact portion contacts each of the second layer of the source electrode and the second layer of the drain electrode, wherein the first layer includes a metal oxide (MOx) containing element M, wherein the second layer includes a low-resistance metal, and wherein the element M includes a Group 6B element.

18. The method of manufacturing a thin film transistor according to claim 17, wherein forming the first contact portion on the active layer is performed by sequentially forming an oxide semiconductor material layer and a second metal material layer, and then patterning using a halftone mask.

19. The method of manufacturing a thin film transistor according to claim 17, wherein after forming the low-reflection material layer on the active layer, forming the first contact portion on the active layer is performed, the method further includes: forming a first photoresist material layer on the low-reflection material layer to etch a part of the first photoresist material layer; forming a second metal material layer on the first photoresist material layer; and removing the first photoresist material layer and the second metal material layer formed on the first photoresist material layer.

20. The method of manufacturing a thin film transistor according to claim 17, wherein after forming the low-reflection material layer on the active layer, forming the first contact portion on the active layer is performed, the method further includes: A first photoresist material layer is formed on the low-reflection material layer and etched using a mask; The first photoresist material layer is removed; A second metal material layer is formed on the low-reflection material layer; A second photoresist material layer is formed on the second metal material layer; And The second metal material layer that does not overlap with the second photoresist material layer is removed using a mask.

21. The method of manufacturing a thin film transistor according to claim 20, wherein one of the first photoresist material layer and the second photoresist material layer is formed of a positive photoresist pattern, and the other of the first photoresist material layer and the second photoresist material layer is formed of a negative photoresist pattern.

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