Thin film transistor substrate, manufacturing method thereof and display device including the same

Abstract

The present disclosure relates to a thin film transistor substrate, a method of manufacturing the same, and a display device including the same. The thin film transistor substrate includes a first thin film transistor and a second thin film transistor on a base substrate, the first thin film transistor including a first active layer on the base substrate, and a first gate electrode spaced apart from the first active layer and overlapping at least a portion of the first active layer, and a second thin film transistor including a second active layer on the base substrate and a second gate electrode spaced apart from the second active layer and overlapping at least a portion of the second active layer, the first active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, and the second active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, and a third oxide semiconductor layer on the second oxide semiconductor layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0001857, filed on January 5, 2024, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical field

[0003] The present disclosure relates to a thin-film transistor substrate, a method of manufacturing the same, and a display device, and relates to a thin-film transistor including an oxide semiconductor layer having a crystalline structure, a method of manufacturing the same, and a display device including such a thin-film transistor. Background art

[0004] Since thin-film transistors can be fabricated on glass or plastic substrates, they are widely used as switching or driving elements in display devices (such as liquid crystal display devices or organic light-emitting devices).

[0005] Based on the material constituting the active layer, thin-film transistors can be classified into amorphous silicon thin-film transistors in which amorphous silicon is used as the active layer, polycrystalline silicon thin-film transistors in which polycrystalline silicon is used as the active layer, and oxide semiconductor thin-film transistors in which an oxide semiconductor is used as the active layer.

[0006] Oxide semiconductor thin-film transistors (oxide semiconductor TFTs) having a large resistance change according to the oxygen content have the advantage of being able to easily obtain desired physical properties. In addition, the manufacturing cost is low because an oxide constituting the active layer can be formed at a relatively low temperature during the manufacturing process of the oxide semiconductor thin-film transistor. Due to the nature of the oxide, since the oxide semiconductor is transparent, it is advantageous for realizing a transparent display. However, oxide semiconductor thin-film transistors have the disadvantage of low mobility.

[0007] In order to improve reliability and mobility by preventing physical and chemical damage or defects that cause deterioration of oxide semiconductor thin-film transistors, there is a method of forming an oxide semiconductor into a crystalline structure.

[0008] Recently, a gate-in-panel (GIP) structure in which a gate driver is embedded in a display panel in the form of thin-film transistors has been applied to display devices. In order to improve the performance of the display device, a large number of thin-film transistors are provided in the gate driver. Summary of the invention

[0009] Embodiments of the present disclosure provide a thin-film transistor substrate in which a multilayer structure of an active layer is selectively applied.

[0010] Another embodiment of the present disclosure provides a thin-film transistor substrate having an active layer, the active layer including an oxide semiconductor layer having a crystalline structure, and the thin-film transistor substrate improves mobility and reliability.

[0011] Another embodiment of the present disclosure provides a method of manufacturing a thin-film transistor substrate that improves mobility and reliability.

[0012] Another embodiment of the present disclosure aims to provide a display device including a thin-film transistor substrate that improves mobility and reliability.

[0013] Another embodiment of the present disclosure aims to provide a thin-film transistor applying a multilayer structure of an active layer.

[0014] In addition to the technical features of the present disclosure described above, those skilled in the art will clearly understand additional technical features and characteristics of the present disclosure from the following description of the present disclosure.

[0015] According to an aspect of the present disclosure, a thin-film transistor substrate includes a first thin-film transistor and a second thin-film transistor on a substrate, wherein the first thin-film transistor includes a first active layer on the substrate and a first gate electrode spaced apart from the first active layer and overlapping at least a part of the first active layer, and the second thin-film transistor includes a second active layer on the substrate and a second gate electrode spaced apart from the second active layer and overlapping at least a part of the second active layer, the first active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, the second active layer includes a first oxide semiconductor layer, a second oxide semiconductor layer on the first oxide semiconductor layer, and a third oxide semiconductor layer on the second oxide semiconductor layer, the first oxide semiconductor layer of the first active layer has an amorphous structure, the second oxide semiconductor layer of the first active layer has a crystalline structure, the first oxide semiconductor layer and the third oxide semiconductor layer of the second active layer have an amorphous structure, and the second oxide semiconductor layer of the second active layer has a crystalline structure.

[0016] The first oxide semiconductor layer of the first active layer may be made of the same material as the first oxide semiconductor layer of the second active layer.

[0017] The second oxide semiconductor layer of the first active layer may be made of the same material as the second oxide semiconductor layer of the second active layer and may have the same crystalline structure.

[0018] The first oxide semiconductor layer of the first active layer, the first oxide semiconductor layer of the second active layer, and the third oxide semiconductor layer of the second active layer include at least one of the following oxide semiconductor materials: IZO (InZnO)-based oxide semiconductor materials, IGZO (InGaZnO)-based oxide semiconductor materials, IGZTO (InGaZnSnO)-based oxide semiconductor materials, GZTO (GaZnSnO)-based oxide semiconductor materials, and GZO (GaZnSnO)-based oxide semiconductor materials. The second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer may include at least one of the following oxide semiconductor materials: IZO (InZnO)-based oxide semiconductor materials, where the concentration of In is 50% or more compared to the total concentration of In and Zn based on the number of atoms; IGO (InGaO)-based oxide semiconductor materials, where the concentration of In is 70% or more compared to the total concentration of In and Ga based on the number of atoms; IGZO (InGaZnO)-based oxide semiconductor materials, where the concentration of In is 50% or more compared to the total concentration of In, Ga, and Zn based on the number of atoms; ITO (InSnO)-based oxide semiconductor materials, where the concentration of In is 80% or more compared to the total concentration of In and Sn based on the number of atoms; IGZTO (InGaZnSnO)-based oxide semiconductor materials, where the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Ga, Zn, and Sn based on the number of atoms; and ITZO (InSnZnO)-based oxide semiconductor materials, where the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Sn, and Zn based on the number of atoms.

[0019] Each of the second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer may further include a dopant doped into the oxide semiconductor material, and the dopant may include at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), and germanium (Ge).

[0020] The dopant included in the second oxide semiconductor layer of the first active layer may have a content of 0.1 to 10 atomic % based on the total number of atoms of the second oxide semiconductor layer of the first active layer, and the dopant included in the second oxide semiconductor layer of the second active layer may have a content of 0.1 to 10 atomic % based on the total number of atoms of the second oxide semiconductor layer of the second active layer.

[0021] The first oxide semiconductor layer of the first active layer and the first oxide semiconductor layer of the second active layer may have a thickness of 1 to 10 nm, the second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer may have a thickness of 10 to 50 nm, and the third oxide semiconductor layer of the second active layer may have a thickness of 1 to 20 nm.

[0022] The second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer may have at least one of a (400) plane, a (222) plane, a (220) plane, a (311) plane, and a (0016) plane.

[0023] The second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer may have at least one of a cubic crystal structure, a rhodochrosite crystal structure, a spinel crystal structure, and a hexagonal crystal structure.

[0024] The second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer may include grains having a particle size of 3 to 500 nm.

[0025] The first active layer includes a third oxide semiconductor layer having a crystalline structure and disposed between the first oxide semiconductor layer and the second oxide semiconductor layer of the first active layer, and a fourth oxide semiconductor layer having a crystalline structure and disposed on the second oxide semiconductor layer of the first active layer, and the second active layer includes a fourth oxide semiconductor layer having a crystalline structure and disposed between the first oxide semiconductor layer and the second oxide semiconductor layer of the second active layer, and a fifth oxide semiconductor layer having a crystalline structure and disposed between the second oxide semiconductor layer and the third oxide semiconductor layer of the second active layer.

[0026] The third oxide semiconductor layer of the first active layer may be made of the same material as the first oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the second active layer may be made of the same material as the first oxide semiconductor layer of the second active layer, and the fifth oxide semiconductor layer of the second active layer may be made of the same material as the third oxide semiconductor layer of the second active layer.

[0027] Each of the third oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the second active layer, and the fifth oxide semiconductor layer of the second active layer may have a thickness of 0.1 to 3 nm.

[0028] The third oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the second active layer, and the fifth oxide semiconductor layer of the second active layer may have a (009) crystal plane and may have a CAAC crystal structure.

[0029] The third oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the second active layer, and the fifth oxide semiconductor layer of the second active layer may include grains having a particle size of 1 to 10 nm.

[0030] The s factor of the second thin film transistor may be greater than the s factor of the first thin film transistor, and the mobility of the first thin film transistor may be greater than the mobility of the second thin film transistor.

[0031] Another embodiment of the present disclosure provides a method of manufacturing a thin film transistor substrate, including: preparing a base substrate placed in a first region and a second region; forming the first active layer on the base substrate placed in the first region, and forming the second active layer on the base substrate placed in the second region; forming a first gate electrode and a second gate electrode to at least partially overlap the first active layer and the second active layer, respectively. Forming the first active layer and the second active layer includes sequentially stacking a first oxide semiconductor material layer, a second oxide semiconductor material layer, and a third oxide semiconductor material layer on the base substrate; patterning the first oxide semiconductor material layer, the second oxide semiconductor material layer, and the third oxide semiconductor material layer to form a first active pattern and a second active pattern including a first oxide semiconductor pattern layer, a second oxide semiconductor pattern layer, and a third oxide semiconductor pattern layer, respectively; heat-treating the first active pattern and the second active pattern; and wet-etching the third oxide semiconductor pattern layer of the first active pattern using the photoresist material layer that overlaps the second active pattern provided in the second region and does not overlap the first active pattern provided in the first region.

[0032] The first oxide semiconductor material layer, the second oxide semiconductor material layer, and the third oxide semiconductor material layer are formed by sputtering deposition, and when forming the second oxide semiconductor material layer, sputtering deposition may be performed at a temperature of 100 to 300 °C, and when forming the first oxide semiconductor material layer and the third oxide semiconductor material layer, sputtering deposition may be performed at a temperature of 15 to less than 100 °C.

[0033] The step of heat-treating the first active pattern and the second active pattern may be performed at a temperature of 350°C to 450°C.

[0034] Another embodiment of the present disclosure provides a display device including a thin-film transistor substrate.

[0035] It may include a gate driver on a substrate, and the gate driver may include a first thin-film transistor.

[0036] It includes a gate driver and a pixel driving circuit on a substrate, and the first thin-film transistor may be included in the gate driver or may be a switching transistor of the pixel driving circuit.

[0037] An embodiment of the present disclosure provides a thin-film transistor including an active layer and a gate electrode spaced apart from and overlapping at least a part of the active layer, wherein the active layer includes a first oxide semiconductor layer, a second oxide semiconductor layer on the first oxide semiconductor layer, and a third oxide semiconductor layer on the second oxide semiconductor layer, the first oxide semiconductor layer and the third oxide semiconductor layer have an amorphous structure, and the second oxide semiconductor layer has a crystalline structure.

[0038] The first oxide semiconductor layer and the third oxide semiconductor layer may include at least one of the following oxide semiconductor materials: IZO (InZnO)-based oxide semiconductor materials, IGZO (InGaZnO)-based oxide semiconductor materials, IGZTO (InGaZnSnO)-based oxide semiconductor materials, GZTO (GaZnSnO)-based oxide semiconductor materials, and GZO (GaZnSnO)-based oxide semiconductor materials. The second oxide semiconductor layer may include at least one of the following oxide semiconductor materials: IZO (InZnO)-based oxide semiconductor materials, in which the concentration of In is 50% or more compared to the total concentration of In and Zn based on the number of atoms; IGO (InGaO)-based oxide semiconductor materials, in which the concentration of In is 70% or more compared to the total concentration of In and Ga based on the number of atoms; IGZO (InGaZnO)-based oxide semiconductor materials, in which the concentration of In is 50% or more compared to the total concentration of In, Ga, and Zn based on the number of atoms; ITO (InSnO)-based oxide semiconductor materials, in which the concentration of In is 80% or more compared to the total concentration of In and Sn based on the number of atoms; IGZTO (InGaZnSnO)-based oxide semiconductor materials, in which the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Ga, Zn, and Sn based on the number of atoms; and ITZO (InSnZnO)-based oxide semiconductor materials, in which the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Sn, and Zn based on the number of atoms.

[0039] The second oxide semiconductor layer may further include a dopant doped into the oxide semiconductor material, and the dopant may include at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), and germanium (Ge).

[0040] The dopant included in the second oxide semiconductor layer may have a content of 0.1 to 10 atomic % based on the total number of atoms of the second oxide semiconductor layer.

[0041] The first oxide semiconductor layer may have a thickness of 1 to 10 nm, the second oxide semiconductor layer may have a thickness of 10 to 50 nm, and the third oxide semiconductor layer may have a thickness of 1 to 20 nm.

[0042] The second oxide semiconductor layer may have at least one of (400) crystal plane, (222) crystal plane, (220) crystal plane, (311) crystal plane, and (0016) crystal plane.

[0043] The second oxide semiconductor layer may have at least one of a cubic crystal structure, a brownmillerite crystal structure, a spinel crystal structure, and a hexagonal crystal structure.

[0044] The second oxide semiconductor layer may include grains having a particle diameter of 3 to 500 nm.

[0045] The active layer may further include a fourth oxide semiconductor layer having a crystalline structure and provided between the first oxide semiconductor layer and the second oxide semiconductor layer, and a fifth oxide semiconductor layer having a crystalline structure and provided between the second oxide semiconductor layer and the third oxide semiconductor layer.

[0046] The fourth oxide semiconductor layer may be made of the same material as the first oxide semiconductor layer, and the fifth oxide semiconductor layer may be made of the same material as the third oxide semiconductor layer.

[0047] Each of the fourth oxide semiconductor layer and the fifth oxide semiconductor layer may have a thickness of 0.1 nm to 3 nm.

[0048] The fourth oxide semiconductor layer and the fifth oxide semiconductor layer may have a (009) crystal plane and may have a CAAC crystal structure.

[0049] The fourth oxide semiconductor layer and the fifth oxide semiconductor layer may include grains having a particle diameter of 1 to 10 nm. Description of the Drawings

[0050] The above and other objects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0051] Figure 1 is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure.

[0052] Figure 2 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0053] Figure 3 is a photograph of an oxide semiconductor layer having a crystalline structure according to another embodiment of the present disclosure.

[0054] Figures 4A to 4H is a diagram showing a manufacturing process of a thin film transistor substrate according to another embodiment of the present disclosure.

[0055] Figure 5 is a partial cross-sectional view of a display device according to another embodiment of the present disclosure.

[0056] Figure 6 It is a cross-sectional view of a thin-film transistor according to an embodiment of the present disclosure.

[0057] Figure 7 It is a cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0058] Figure 8 It is a schematic diagram of a display device according to another embodiment of the present disclosure.

[0059] Figure 9 It is a schematic diagram of a shift register.

[0060] Figure 10 It is provided in Figure 9 A circuit diagram of an embodiment of a stage in the shift register.

[0061] Figure 11 It is Figure 8 A circuit diagram of any one pixel P.

[0062] Figure 12 It is Figure 11 A plan view of the pixel.

[0063] Figure 13 It is along Figure 12 A cross-sectional view taken along line I-I'. Detailed implementation mode

[0064] The advantages and features of the present disclosure and the method for implementing them will be clarified by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0065] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples. Therefore, the present disclosure is not limited to the details shown. Throughout the specification, like reference numerals denote like elements. In the following description, when the detailed description of related known functions or configurations is determined to unnecessarily obscure the focus of the present disclosure, the detailed description will be omitted.

[0066] In cases where "including", "having", and "comprising" described in the present disclosure are used, another part may be added unless "only~" is used. Unless otherwise stated to the contrary, terms in the singular form may include the plural form.

[0067] When interpreting an element, the element is interpreted as including an error margin, although not explicitly described.

[0068] When describing a positional relationship, for example, when the positional relationship is described as "on", "above", "below", and "next to", one or more parts may be disposed between two other parts unless "exactly" or "directly" is used.

[0069] Spatial relative terms such as "below", "beneath", "lower", "above", and "upper" may be used herein to easily describe the relationship of one or more elements shown in the drawings to another or more elements. It should be understood that these terms are intended to cover different orientations of the device in addition to the orientation shown in the drawings. For example, if the device shown in the figure is inverted, the device described as being "below" or "beneath" another device may be disposed "above" another device. Thus, the exemplary term "below or beneath" may include the orientations of "below or beneath" and "above". Similarly, the exemplary terms "above" or "on" may include the orientations of "above" and "below or beneath".

[0070] When describing a temporal relationship, for example, when the time sequence is described as "after", "subsequently", "next", and "before", discontinuous cases may be included unless "exactly" or "directly" is used.

[0071] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0072] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of the first element, the second element, and the third element" may include two or more elements selected from the first element, the second element, and the third element, as well as all combinations of each of the first element, the second element, and the third element. The scope in the description includes its (multiple) boundary points unless otherwise explicitly stated.

[0073] The features of the various embodiments of the present disclosure may be partially or wholly coupled or combined with each other, and may operate differently from each other and be technically driven, as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be executed independently of each other, or may be executed together in a mutually dependent relationship.

[0074] When adding reference numerals to the components of each drawing depicting embodiments of the present disclosure, identical components may have the same symbols that may be shown on other drawings.

[0075] In embodiments of the present disclosure, for ease of description, a source electrode and a drain electrode are mentioned, and the source electrode and the drain electrode may be interchangeable. The source electrode may be the drain electrode, and vice versa. Additionally, the source electrode of any one embodiment may be the drain electrode of another embodiment, and the drain electrode of any one embodiment may be the source electrode of another embodiment.

[0076] In some embodiments of the present disclosure, for ease of description, the source region is separately mentioned from the source electrode, and the drain region is separately mentioned from the drain electrode, but embodiments of the present disclosure are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. Additionally, the source region may be the drain electrode, and the drain region may be the source electrode.

[0077] Figure 1 is a cross-sectional view of a thin film transistor substrate 100 according to an embodiment of the present disclosure.

[0078] The thin film transistor substrate 100 according to an embodiment of the present disclosure includes a first thin film transistor TR1 and a second thin film transistor TR2. Specifically, referring to Figure 1 , the thin film transistor substrate 100 includes a first thin film transistor TR1 and a second thin film transistor TR2 on a base substrate 110.

[0079] The first thin film transistor TR1 includes a first active layer 130 and a first gate electrode 150 that is spaced apart from the first active layer 130 and at least partially overlaps the first active layer 130.

[0080] The second thin film transistor TR2 includes a second active layer 230 and a second gate electrode 250 that is spaced apart from the second active layer 230 and at least partially overlaps the second active layer 230.

[0081] Glass or plastic may be used as the base substrate 110. As the plastic, a transparent plastic having flexible characteristics, such as polyimide, may be used. Referring to Figure 1 , the base substrate 110 on which the first thin film transistor TR1 is disposed and the base substrate 110 on which the second thin film transistor TR2 is disposed may be integrally formed with each other.

[0082] Light-shielding layers 111 and 211 may be disposed on the base substrate 110. The light-shielding layers 111 and 211 block light incident from the base substrate 110 to protect the first active layer 130 and the second active layer 230. When another structure serves as a light-shielding function, the light-shielding layers 111 and 211 may also be omitted.

[0083] According to an embodiment of the present disclosure, the buffer layer 120 may be disposed on the base substrate 110 and the light-shielding layers 111 and 211.

[0084] The buffer layer 120 has insulating properties and protects the first active layer 130 and the second active layer 230. The buffer layer 120 may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), and metal oxides having insulating properties.

[0085] The first active layer 130 and the second active layer 230 may be disposed on the buffer layer 120.

[0086] Each of the first active layer 130 and the second active layer 230 includes an oxide semiconductor material. According to an embodiment of the present disclosure, the first active layer 130 and the second active layer 230 are oxide semiconductor layers made of an oxide semiconductor material. The first active layer 130 and the second active layer 230 made of an oxide semiconductor material include a metal and oxygen (O).

[0087] In addition, each of the first active layer 130 and the second active layer 230 may include at least one layer having a crystalline structure.

[0088] According to an embodiment of the present disclosure, the first active layer 130 includes a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132. The second oxide semiconductor layer 132 may be disposed on the first oxide semiconductor layer 131.

[0089] Furthermore, according to an embodiment of the present disclosure, the second active layer 230 includes a first oxide semiconductor layer 231, a second oxide semiconductor layer 232, and a third oxide semiconductor layer 233. The second oxide semiconductor layer 232 is disposed on the first oxide semiconductor layer 231, and the third oxide semiconductor layer 233 is disposed on the second oxide semiconductor layer 232.

[0090] According to an embodiment of the present disclosure, the first oxide semiconductor layer 131 of the first active layer 130 may have an amorphous structure, and the second oxide semiconductor layer 132 may have a crystalline structure. In addition, the first oxide semiconductor layer 231 and the third oxide semiconductor layer 233 of the second active layer 230 may have an amorphous structure, and the second oxide semiconductor layer 232 may have a crystalline structure. According to an embodiment of the present disclosure, the crystalline structure and the amorphous structure are referred to based on the content of grains included in the oxide semiconductor layer. More specifically, according to an embodiment of the present disclosure, the crystalline structure and the amorphous structure are distinguished from each other based on the ratio of grains having a particle size of 1 nm or more.

[0091] According to an embodiment of the present disclosure, a grain refers to an aggregate of atoms with a regular arrangement. In a grain, the atoms have a regular arrangement. An aggregate of internal atoms with a regular arrangement refers to a grain.

[0092] According to an embodiment of the present disclosure, the arrangement state of atoms can be confirmed by using a cross-sectional image taken by a transmission electron microscope (TEM). A cross-sectional image of an oxide semiconductor layer can be obtained by using a transmission electron microscope (TEM). In the cross-sectional image of the oxide semiconductor layer, a grain has the shape of an aggregate or a two-dimensional aggregate with boundaries.

[0093] A grain has a grain size. In a cross-sectional image taken by a transmission electron microscope (TEM), the length of the longest axis of the grain is referred to as the grain size of the grain.

[0094] According to an embodiment of the present disclosure, in a cross-sectional image of an oxide semiconductor layer taken by a transmission electron microscope (TEM), when the ratio of grains with a grain size of 1 nm or more is 50% or more of the total cross-sectional area, the oxide semiconductor layer is referred to as having a crystalline structure. Additionally, in a cross-sectional image of an oxide semiconductor layer taken by a transmission electron microscope (TEM), when the ratio of grains with a grain size of 1 nm or more is 10% or less of the total cross-sectional area, the oxide semiconductor layer is referred to as having an amorphous structure.

[0095] According to an embodiment of the present disclosure, the first oxide semiconductor layer 131 of the first active layer 130, the first oxide semiconductor layer 231 of the second active layer 230, and the third oxide semiconductor layer 233 have an amorphous structure. Specifically, in a cross-sectional image of the first oxide semiconductor layers 131, 231, and the third oxide semiconductor layer 233 taken by a transmission electron microscope (TEM), the ratio of grains with a grain size of 1 nm or more can be 10% or less of the total cross-sectional area. More specifically, in a cross-sectional image of the first oxide semiconductor layers 131 and 231 and the third oxide semiconductor layer 233 taken by a transmission electron microscope (TEM), the ratio of grains with a grain size of 5 nm to 10 nm can be 10% or less of the total cross-sectional area.

[0096] The first oxide semiconductor layer 131 of the first active layer 130, the first oxide semiconductor layer 231 of the second active layer 230, and the third oxide semiconductor layer 233 may include, for example, at least one of an IZO (InZnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, and a GZO (GaZnO)-based oxide semiconductor material. More specifically, the first oxide semiconductor layer 131 of the first active layer 130, the first oxide semiconductor layer 231 of the second active layer 230, and the third oxide semiconductor layer 233 may include an IGZO (InGaZnO)-based oxide semiconductor material. In some embodiments, the first oxide semiconductor layer 131 of the first active layer 130, the first oxide semiconductor layer 231 of the second active layer 230, and the third oxide semiconductor layer 233 of the second active layer 230 may include an IGZO (InGaZnO)-based oxide semiconductor material.

[0097] According to an embodiment of the present disclosure, the first oxide semiconductor layer 131 of the first active layer 130 and the first oxide semiconductor layer 231 of the second active layer 230 may have a thickness of 1 nm to 10 nm.

[0098] When the thickness of the first oxide semiconductor layers 131 and 231 is less than 1 nm, it is not easy to etch the first oxide semiconductor layers 131 and 231 due to the too thin thickness, so patterning of the first oxide semiconductor layers 131 and 231 may not be performed. As a result, difficulties in forming the first active layer 130 and the second active layer 230 may occur.

[0099] The first oxide semiconductor layers 131 and 231 are used to improve the etchability of the second oxide semiconductor layers 132 and 232. Therefore, the first oxide semiconductor layer 131 can be made thinner. When the thickness of the first oxide semiconductor layers 131 and 231 exceeds 10 nm, the first active layer 130 and the second active layer 230 may become unnecessarily thick, which may be disadvantageous in thin film formation.

[0100] According to an embodiment of the present disclosure, the first oxide semiconductor layer 131 of the first active layer 130 may be formed of the same material as the first oxide semiconductor layer 231 of the second active layer 230. Specifically, the first oxide semiconductor layer 131 and 231 may be formed by the same process. Although the structure in which the first oxide semiconductor layers 131 and 231 are disposed on the same layer is shown in Figure 1 the embodiments of the present disclosure are not limited thereto, and may be disposed on another layer.

[0101] According to embodiments of the present disclosure, the second oxide semiconductor layers 132 and 232 are respectively disposed on the first oxide semiconductor layers 131 and 231. Specifically, the second oxide semiconductor layer 132 of the first active layer 130 is disposed on the first oxide semiconductor layer 131 of the first active layer 130, and the second oxide semiconductor layer 232 of the second active layer 230 is disposed on the first oxide semiconductor layer 231 of the second active layer 230. By adjusting the composition and manufacturing conditions in the manufacturing process of the second oxide semiconductor layers 132 and 232, the second oxide semiconductor layers 132 and 232 can have a crystalline structure. For example, in order to form a crystalline structure, the second oxide semiconductor layers 132 and 232 can be formed by sputter deposition and a heat treatment step performed at a temperature of 350 °C to 450 °C. In this case, the sputter deposition can be performed at a temperature of 100 to 300 °C.

[0102] According to embodiments of the present disclosure, the second oxide semiconductor layers 132 and 232 have a crystalline structure. Specifically, in a cross-sectional image of the second oxide semiconductor layers 132 and 232 taken using a transmission electron microscope (TEM), the ratio of grains having a particle size of 1 nm or more can be 50% or more of the total cross-sectional area. More specifically, in a cross-sectional image of the second oxide semiconductor layers 132 and 232 taken using a transmission electron microscope (TEM), the ratio of grains having a particle size of 5 nm to 10 nm can be 50% or more of the total cross-sectional area.

[0103] According to embodiments of the present disclosure, since the crystalline second oxide semiconductor layers 132 and 232 are formed on the amorphous first oxide semiconductor layers 131 and 231, grains having a relatively small particle size can be formed on the second oxide semiconductor layers 132 and 232. As a result, the second oxide semiconductor layers 132 and 232 can be easily etched while having a crystalline structure.

[0104] By forming the second oxide semiconductor layers 132 and 232 having crystal-forming characteristics on the amorphous first oxide semiconductor layers 131 and 231, a crystalline structure can be formed on the second oxide semiconductor layers 132 and 232 without going through strict crystallization process control, for example, a heat treatment process with strict temperature control. In this case, a large number of grains having a small particle size can be formed on the second oxide semiconductor layers 132 and 232.

[0105] The second oxide semiconductor layers 132 and 232 may include at least one of the following oxide semiconductor materials: IZO (InZnO)-based oxide semiconductor materials, in which the concentration of In is 50% or more compared to the total concentration of In and Zn based on the number of atoms; IGO (InGaO)-based oxide semiconductor materials, in which the concentration of In is 70% or more compared to the total concentration of In and Ga based on the number of atoms; IGZO (InGaZnO)-based oxide semiconductor materials, in which the concentration of In is 50% or more compared to the total concentration of In, Ga, and Zn based on the number of atoms; ITO (InSnO)-based oxide semiconductor materials, in which the concentration of In is 80% or more compared to the total concentration of In and Sn based on the number of atoms; IGZTO (InGaZnSnO)-based oxide semiconductor materials, in which the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Ga, Zn, and Sn based on the number of atoms; and ITZO (InSnZnO)-based oxide semiconductor materials, in which the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Sn, and Zn based on the number of atoms. In some embodiments, the second oxide semiconductor layers 132 and 232 may include IZO (InZnO)-based oxide semiconductor materials, in which the concentration of In is 50% or more compared to the total concentration of In and Zn.

[0106] For example, in the case of IZO (InZnO)-based oxide semiconductor materials, the ratio of In to Zn may be 5:5, 6:4, and 7:3. Additionally, in the case of IGO (InGaO)-based oxide semiconductor materials, the ratio of In to Ga may be 7:3, 8:2, and 9:1.

[0107] According to an embodiment of the present disclosure, the second oxide semiconductor layer 132 of the first active layer 130 and the second oxide semiconductor layer 232 of the second active layer 230 may be formed of the same material. Specifically, the second oxide semiconductor layer 132 of the first active layer 130 and the second oxide semiconductor layer 232 of the second active layer 230 may have the same crystal structure.

[0108] According to an embodiment of the present disclosure, the second oxide semiconductor layers 132 and 232 may be doped with a dopant. For example, the dopant may be doped into the second oxide semiconductor layers 132 and 232 by an ion implantation method. Thus, according to an embodiment of the present disclosure, the second oxide semiconductor layers 132 and 232 may further include a dopant doped into an oxide semiconductor material. The dopant may include at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), and germanium (Ge). Specifically, the second oxide semiconductor layers 132 and 232 may be formed of an IGO (InGaO)-based oxide semiconductor material doped with at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), and germanium (Ge).

[0109] The dopant may be disposed in the grains or at the boundaries between the grains. Even when the dopant is included in an aggregate of atoms, when atoms other than the dopant are regularly arranged in the aggregate of atoms, the aggregate of these atoms is referred to as a grain.

[0110] When the second oxide semiconductor layers 132 and 232 are doped with a dopant, defects in the particles of the second oxide semiconductor layers 132 and 232 can be prevented, so that the second oxide semiconductor layers 132 and 232 can have a stable crystal structure, and grains having a particle size of 3 nm to 500 nm can be easily formed on the second oxide semiconductor layers 132 and 232. When at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), and germanium (Ge) is doped into the second oxide semiconductor layers 132 and 232, grains can be easily formed. Specifically, since the dopant has a high bonding force with oxygen (O) which is a constituent element of the oxide semiconductor material, the second oxide semiconductor layers 132 and 232 can stably have a crystal structure, and grains having a particle size of 3 nm to 500 nm can be easily formed on the second oxide semiconductor layers 132 and 232. As a result, the second oxide semiconductor layers 132 and 232 can have etching characteristics and can have excellent defect resistance.

[0111] According to embodiments of the present disclosure, beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), and germanium (Ge) can be used as crystal stabilizing agents for controlling the crystallization conditions, grain size, or crystallization state of the second oxide semiconductor layers 132 and 232. Additionally, dopants having metallic properties can be used as electrical stabilizing agents for controlling changes in the electrical properties of the second oxide semiconductor layers 132 and 232. Specifically, beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), and germanium (Ge) doped into the oxide semiconductor material can be controlled such that grains can be effectively formed in the second oxide semiconductor layers 132 and 232, and the electrical properties of the second oxide semiconductor layers 132 and 232 can be stably maintained.

[0112] The dopants included in the second oxide semiconductor layers 132 and 232 can have a content of 0.1 to 10 atomic % based on the total number of atoms of the second oxide semiconductor layers 132 and 232. Specifically, the dopants included in the second oxide semiconductor layer 132 of the first active layer can have a content of 0.1 to 10 atomic % based on the total number of atoms of the second oxide semiconductor layer 132, and the dopants included in the second oxide semiconductor layer 232 of the second active layer can have a content of 0.1 to 10 atomic % based on the total number of atoms of the second oxide semiconductor layer 232.

[0113] When the dopants included in each of the second oxide semiconductor layers 132 and 232 have a content of less than 0.1 atomic % based on the total number of atoms in each of the second oxide semiconductor layers 132 and 232, there is a problem that they cannot be used as crystal stabilizing agents for controlling crystallization conditions, grain size, or crystallization state.

[0114] Additionally, if the dopants included in each of the second oxide semiconductor layers 132 and 232 have a content of more than 10 atomic % based on the total number of atoms in each of the second oxide semiconductor layers 132 and 232, the activation energy for crystallization of the second oxide semiconductor layers 132 and 232 may increase, which may require a very high heat treatment temperature, and the dopants included in the second oxide semiconductor layers 132 and 232 may interfere with the lattice arrangement, making it difficult to ensure crystallinity or the problem of amorphization. As a result, the oxide semiconductor may not have the properties of a semiconductor, and the electrical properties may deteriorate.

[0115] According to embodiments of the present disclosure, the second oxide semiconductor layers 132 and 232 may be used as the main channel layers of the active layers 130 and 230. To this end, the second oxide semiconductor layers 132 and 232 may have a thickness of 10 nm to 50 nm. When the thickness of the second oxide semiconductor layers 132 and 232 is less than 10 nm, crystal growth may not be smooth, and the current flowing through the second oxide semiconductor layers 132 and 232 used as the main channel layers may not be smooth. On the other hand, when the thickness of the second oxide semiconductor layers 132 and 232 exceeds 50 nm, the active layers 130 and 230 may become thick, which may not be conducive to forming a thin film.

[0116] According to embodiments of the present disclosure, the second oxide semiconductor layers 132 and 232 may have at least one of a (400) crystal plane, a (222) crystal plane, a (220) crystal plane, a (311) crystal plane, and a (0016) crystal plane.

[0117] According to embodiments of the present disclosure, the second oxide semiconductor layers 132 and 232 may have at least one of a cubic crystal structure, a paratacamite crystal structure, a spinel crystal structure, and a hexagonal crystal structure.

[0118] In the second oxide semiconductor layers 132 and 232 having a crystalline structure, defects in the particles can be prevented, thereby preventing defects or damage during the manufacturing process or driving. As a result, the second oxide semiconductor layers 132 and 232 may have excellent reliability. The first thin film transistor TR1 and the second thin film transistor TR2 including the second oxide semiconductor layers 132 and 232 have excellent reliability characteristics due to reduced defects and may have high mobility characteristics at the same time.

[0119] According to embodiments of the present disclosure, the second thin film transistor TR2 may further include a third oxide semiconductor layer 233.

[0120] The third oxide semiconductor layer 233 is used to protect the second oxide semiconductor layer 232 of the second active layer 230 and may have an amorphous structure.

[0121] The third oxide semiconductor layer 233 of the second active layer 230 may include at least one of the following oxide semiconductor materials: an IZO (InZnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, and a GZO (GaZnSnO)-based oxide semiconductor material. Specifically, the third oxide semiconductor layer 233 may include an IGZO (InGaZnO)-based oxide semiconductor material.

[0122] According to an embodiment of the present disclosure, the third oxide semiconductor layer 233 of the second active layer 230 may have a thickness of 1 nm to 20 nm.

[0123] When the thickness of the third oxide semiconductor layer 233 is less than 1 nm, it is not easy to etch the third oxide semiconductor layer 233 due to its too thin thickness, so patterning of the third oxide semiconductor layer 233 may not be performed. As a result, it may be difficult to form the second active layer 230.

[0124] When the thickness of the third oxide semiconductor layer 233 exceeds 20 nm, the thickness of the second active layer 230 may be unnecessarily thick, which may not be conducive to forming a thin film.

[0125] By adjusting the composition and manufacturing conditions during the manufacturing process of the third oxide semiconductor layer 233, a third oxide semiconductor layer 233 having an amorphous structure can be formed.

[0126] According to an embodiment of the present disclosure, the first thin film transistor TR1 may include a first active layer 130 having a bilayer structure (amorphous - crystalline), and the second thin film transistor TR2 may include a second active layer 230 having a trilayer structure (amorphous - crystalline - amorphous).

[0127] When the first active layer 130 of the first thin film transistor TR1 has a bilayer structure (amorphous - crystalline), the second oxide semiconductor layer 132 having a crystalline structure can be used as a channel layer, and when the second active layer 230 of the second thin film transistor TR2 has a trilayer structure (amorphous - crystalline - amorphous), the second oxide semiconductor layer 232 having a crystalline structure and the third oxide semiconductor layer 233 having an amorphous structure can be used as channel layers.

[0128] In this case, compared with the second thin film transistor TR2 in which only the second oxide semiconductor layer 132 having a crystalline structure is used as a main channel layer, the first thin film transistor TR1 does not have an amorphous structure provided in the main channel layer, so the carrier mobility ("mobility") can be higher.

[0129] On the other hand, in the case where both the second oxide semiconductor layer 232 having a crystalline structure and the third oxide semiconductor layer 233 having an amorphous structure are used as the channel layer of the second thin film transistor TR2, the second oxide semiconductor layer 232 having a crystalline structure can be used as the main channel layer. In this case, the third oxide semiconductor layer 233 having an amorphous structure is disposed between the second oxide semiconductor layer 232 serving as the main channel layer and the gate insulating layer 140, and a relatively small amount of electrons is trapped between the second active layer 230 and the gate insulating layer 140. More specifically, a relatively small amount of electrons can be trapped at the interface between the second active layer 230 and the gate insulating layer 140. As a result, the second thin film transistor TR2 can have higher reliability than the first thin film transistor TR1. More specifically, the s-factor of the second thin film transistor TR2 can be greater than the s-factor of the first thin film transistor TR1.

[0130] In order for a current-driven display device to have excellent gray-scale expression ability, it is advantageous to increase the s-factor of the thin film transistor that drives the pixels of the display device.

[0131] The subthreshold swing (s-factor) represents the reciprocal value of the slope of the curve in the threshold voltage (Vth) interval in the drain-source current IDS characteristic curve (not shown) with respect to the gate voltage VG of the thin film transistor. As the s-factor increases, the rate of change of the drain-source current IDS with respect to the gate voltage VG in the threshold voltage (Vth) interval decreases. Therefore, the gray-scale expression ability of the display device driven by such a thin film transistor can be improved.

[0132] Specifically, the first thin film transistor TR1 can be disposed in the gate driver of the display device that requires excellent current characteristics, and the second thin film transistor TR2 can be disposed in the pixel driving circuit of the display device that requires excellent gray-scale expression ability.

[0133] According to the present disclosure, an advantage is that the first active layer 130 of the first thin film transistor TR1 and the second active layer 230 of the second thin film transistor TR2 can be formed by a single process.

[0134] Figure 2 FIG. 200 is a cross-sectional view of a thin film transistor substrate 200 according to another embodiment of the present disclosure. Hereinafter, the description of the components that have been described will be omitted to avoid repetition.

[0135] According to an embodiment of the present disclosure, the first active layer 130 may further include a third oxide semiconductor layer 133 and a fourth oxide semiconductor layer 134. In addition, the second active layer 230 may further include a fourth oxide semiconductor layer 234 and a fifth oxide semiconductor layer 235.

[0136] The third oxide semiconductor layer 133 of the first active layer 130 is disposed between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 of the first active layer 130, and the fourth oxide semiconductor layer 134 of the first active layer 130 is disposed on the second oxide semiconductor layer 132 of the first active layer 130.

[0137] In this case, the third oxide semiconductor layer 133 and the fourth oxide semiconductor layer 134 of the first active layer 130 have a crystalline structure.

[0138] The fourth oxide semiconductor layer 234 of the second active layer 230 is disposed between the first oxide semiconductor layer 231 and the second oxide semiconductor layer 232 of the second active layer 230, and the fifth oxide semiconductor layer 235 of the second active layer 230 is disposed between the second oxide semiconductor layer 232 and the third oxide semiconductor layer 233 of the second active layer 230.

[0139] In this case, the fourth oxide semiconductor layer 234 and the fifth oxide semiconductor layer 235 of the second active layer 230 have a crystalline structure.

[0140] By adjusting the manufacturing conditions during the manufacturing processes of the third oxide semiconductor layer 133, the fourth oxide semiconductor layers 134 and 234, and the fifth oxide semiconductor layer 235, the third oxide semiconductor layer 133, the fourth oxide semiconductor layers 134 and 234, and the fifth oxide semiconductor layer 235 can have a crystalline structure. For example, in order to form a crystalline structure, a heat treatment step may be included during the formation of the first active layer 130 and the second active layer 230. In this case, the heat treatment may be performed at a temperature of 350 to 450 °C.

[0141] According to an embodiment of the present disclosure, the third oxide semiconductor layer 133, the fourth oxide semiconductor layers 134 and 234, and the fifth oxide semiconductor layer 235 may include at least one of the following oxide semiconductor materials: IZO (InZnO)-based oxide semiconductor materials, IGZO (InGaZnO)-based oxide semiconductor materials, IGZTO (InGaZnSnO)-based oxide semiconductor materials, GZTO (GaZnSnO)-based oxide semiconductor materials, and GZO (GaZnSnO)-based oxide semiconductor materials. For example, the third oxide semiconductor layer 133, the fourth oxide semiconductor layers 134 and 234, and the fifth oxide semiconductor layer 235 may include IGZO (InGaZnO)-based oxide semiconductor materials.

[0142] According to an embodiment of the present disclosure, the third oxide semiconductor layer 133 of the first active layer 130 may be formed of the same material as the first oxide semiconductor layer 131 of the first active layer 130, and the fourth oxide semiconductor layer 234 of the second active layer 230 may be formed of the same material as the first oxide semiconductor layer 231 of the second active layer 230. And the fifth oxide semiconductor layer 235 of the second active layer 230 may be formed of the same material as the third oxide semiconductor layer 233 of the second active layer 230.

[0143] When forming the active layers 130 and 230, the second oxide semiconductor layers 132 and 232 are first crystallized, and the crystallized second oxide semiconductor layers 132 and 232 serve as catalysts for amorphous oxide semiconductor layers stacked on upper and lower portions of the second oxide semiconductor layers 132 and 232, thereby forming the crystallized third oxide semiconductor layer 133, fourth oxide semiconductor layers 134 and 234, and fifth oxide semiconductor layer 235.

[0144] That is, the crystallized second oxide semiconductor layers 132 and 232 are used as catalysts for amorphous oxide semiconductor layers stacked on upper and lower portions of the second oxide semiconductor layers 132 and 232, and the amorphous oxide semiconductor layers stacked on upper and lower portions of the second oxide semiconductor layers 132 and 232 erode in the direction of the second oxide semiconductor layers 132 and 232 to form the crystallized third oxide semiconductor layer 133, fourth oxide semiconductor layers 134 and 234, and fifth oxide semiconductor layer 235.

[0145] Therefore, the third oxide semiconductor layer 133, fourth oxide semiconductor layers 134 and 234, and fifth oxide semiconductor layer 235 are layers crystallized by eroding an amorphous structure with high reliability. That is, even if the third oxide semiconductor layer 133, fourth oxide semiconductor layers 134 and 234, and fifth oxide semiconductor layer 235 have a crystalline structure, the mobility may be slightly lower than that of the second oxide semiconductor layers 132 and 232, and the reliability may be high.

[0146] According to an embodiment of the present disclosure, the amorphous oxide semiconductor layer formed on the fourth oxide semiconductor layer 134 of the first active layer 130 is removed by wet etching. Therefore, the first thin film transistor TR1 includes the first active layer 130 having a four-layer structure (amorphous - crystalline - crystalline - crystalline), and the second thin film transistor TR2 may include the second active layer 230 having a five-layer structure (amorphous - crystalline - crystalline - crystalline - amorphous).

[0147] In this case, when the thickness of the first oxide semiconductor layer 131 of the first active layer 130 exceeds 5 nm, the side surface of the first oxide semiconductor layer 131 having an amorphous structure can be partially etched by forming an amorphous oxide semiconductor layer on the fourth oxide semiconductor layer 134 through wet etching.

[0148] When the first active layer 130 of the first thin film transistor TR1 has a four-layer structure (amorphous - crystalline - crystalline - crystalline), the second oxide semiconductor layer 132, the third oxide semiconductor layer 133, and the fourth oxide semiconductor layer 134 having a crystalline structure can be used as the channel layer. When the second active layer 230 of the second thin film transistor TR2 has a five-layer film structure (amorphous - crystalline - crystalline - crystalline - amorphous), the second oxide semiconductor layer 232, the fourth oxide semiconductor layer 234, the fifth oxide semiconductor layer 235 having a crystalline structure, and the third oxide semiconductor layer 233 having an amorphous structure can be used as the channel layer.

[0149] In this case, compared with the second thin film transistor TR2, the first thin film transistor TR1 in which the second oxide semiconductor layer 132, the third oxide semiconductor layer 133, and the fourth oxide semiconductor layer 134 having a crystalline structure are used as the main channel layer does not have an amorphous structure provided in the main channel layer, and thus the mobility can be high.

[0150] On the other hand, in the case of the second thin film transistor TR2 in which the second oxide semiconductor layer 232, the fourth oxide semiconductor layer 234, and the fifth oxide semiconductor layer 235 having a crystalline structure and the third oxide semiconductor layer 233 having an amorphous structure are all used as the channel layer, the second oxide semiconductor layer 232, the fourth oxide semiconductor layer 234, and the fifth oxide semiconductor layer 235 having a crystalline structure are used as the main channel layer, and the third oxide semiconductor layer 233 having an amorphous structure is provided between the fifth oxide semiconductor layer 235 and the gate insulating layer 140 provided on top of the main channel layer, and a relatively small amount of electrons are trapped between the second active layer 230 and the gate insulating layer 140. As a result, the second thin film transistor TR2 can have higher reliability than the first thin film transistor TR1. More specifically, the s factor of the second thin film transistor TR2 can be greater than the s factor of the first thin film transistor TR1.

[0151] Specifically, the first thin film transistor TR1 can be placed in the gate driver of a display device that requires excellent current characteristics, and the second thin film transistor TR2 can be placed in the pixel driving circuit of a display device that requires excellent gray-scale expression ability.

[0152] According to an embodiment of the present disclosure, since the first active layer 130 includes the fourth oxide semiconductor layer 134 with high reliability on the second oxide semiconductor layer 132 with high mobility in the main channel layer, the first thin film transistor TR1 can ensure high mobility and prevent electron traps to increase reliability.

[0153] In addition, according to an embodiment of the present disclosure, the second active layer 230 includes the fifth oxide semiconductor layer 235 that ensures both reliability and mobility between the second oxide semiconductor layer 232 with high mobility and the third oxide semiconductor layer 233 with high reliability, so that the second thin film transistor TR2 can ensure both mobility and reliability.

[0154] In the cross-sectional images of the third oxide semiconductor layer 133, the fourth oxide semiconductor layer 134 of the first active layer 130, and the fourth oxide semiconductor layer 234 and the fifth oxide semiconductor layer 235 of the second active layer 230 taken by a transmission electron microscope (TEM), the ratio of grains with a particle size of 1 nm or more can be 50% or more of the entire cross-sectional area. More specifically, in the cross-sectional images of the third oxide semiconductor layer 133, the fourth oxide semiconductor layer 134 and 234, and the fifth oxide semiconductor layer 235 taken by a transmission electron microscope (TEM), the ratio of grains with a particle size of 5 nm to 10 nm can be 50% or more of the entire cross-sectional area.

[0155] According to an embodiment of the present disclosure, the third oxide semiconductor layer 133, the fourth oxide semiconductor layer 134 of the first active layer 130, and the fourth oxide semiconductor layer 234 and the fifth oxide semiconductor layer 235 of the second active layer 230 can have a (009) crystal plane.

[0156] Specifically, the third oxide semiconductor layer 133, the fourth oxide semiconductor layer 134 of the first active layer 130, and the fourth oxide semiconductor layer 234 and the fifth oxide semiconductor layer 235 of the second active layer 230 can have a CAAC crystal structure.

[0157] More specifically, the third oxide semiconductor layer 133 and the fourth oxide semiconductor layer 134 of the first active layer 130, and the fourth oxide semiconductor layer 234 and the fifth oxide semiconductor layer 235 of the second active layer 230 can have crystal surfaces and crystal structures different from those of the second oxide semiconductor layers 132 and 232.

[0158] According to embodiments of the present disclosure, the third oxide semiconductor layer 133, the fourth oxide semiconductor layer 134 of the first active layer 130, and the fourth oxide semiconductor layer 234 and the fifth oxide semiconductor layer 235 of the second active layer 230 may include grains having a particle size of 1 nm to 10 nm. Specifically, the third oxide semiconductor layer 133, the fourth oxide semiconductor layer 134 of the first active layer 130, and the fourth oxide semiconductor layer 234 and the fifth oxide semiconductor layer 235 of the second active layer 230 may have smaller grains than the second oxide semiconductor layers 132 and 232.

[0159] Compared with giant crystals, it is possible to easily etch the small grains included in the third oxide semiconductor layer 133 and the fourth oxide semiconductor layer 134 of the first active layer 130, and the fourth oxide semiconductor layer 234 and the fifth oxide semiconductor layer 235 of the second active layer 230.

[0160] The third oxide semiconductor layer 133 and the fourth oxide semiconductor layer 134 of the first active layer 130, and the fourth oxide semiconductor layer 234 and the fifth oxide semiconductor layer 235 of the second active layer 230, which are composed of small grains, have excellent etching characteristics and thus can be easily patterned.

[0161] According to embodiments of the present disclosure, the third oxide semiconductor layer 133, the fourth oxide semiconductor layer 134 of the first active layer 130, and the fourth oxide semiconductor layer 234 and the fifth oxide semiconductor layer 235 of the second active layer 230 may have a thickness of 0.1 to 3 nm.

[0162] On the other hand, when the thickness of the third oxide semiconductor layer 133, the fourth oxide semiconductor layer 134 of the first active layer 130, and the fourth oxide semiconductor layer 234 and the fifth oxide semiconductor layer 235 of the second active layer 230 is less than 0.1 nm, the reliability improvement function of suppressing electron traps may deteriorate.

[0163] When the thickness of the third oxide semiconductor layer 133, the fourth oxide semiconductor layer 134 of the first active layer 130, and the fourth oxide semiconductor layer 234 and the fifth oxide semiconductor layer 235 of the second active layer 230 exceeds 3 nm, the proportion of the film characteristics with a mobility lower than that of the second oxide semiconductor layers 132 and 232 as the main channel layer increases. As a result, there may be a problem of a decrease in the overall mobility of the thin film transistor.

[0164] The gate insulating layer 140 is disposed on the active layers 130 and 230. The gate insulating layer 140 may include at least one of silicon oxide and silicon nitride, and may include a metal oxide or a metal nitride. The gate insulating layer 140 may have a single-layer structure or a multi-layer structure. The gate insulating layer 140 may be disposed to cover the entire upper surface of the buffer layer 120.

[0165] The gate insulating layer 140 may be formed by atomic layer deposition (ALD) method or metal organic chemical vapor deposition (MOCVD). The gate insulating layer 140 may or may not be patterned. Figure 1 The structure in which the gate insulating layer 140 is not patterned is shown.

[0166] The gate electrodes 150 and 250 are disposed on the gate insulating layer 140. The gate electrodes 150 and 250 may include a first gate electrode 150 and a second gate electrode 250. Refer to Figure 1 and Figure 2 , the first thin film transistor TR1 includes the first gate electrode 150, and the second thin film transistor TR2 includes the second gate electrode 250. The gate electrodes 150 and 250 are spaced apart from the active layers 130 and 230 to at least partially overlap the active layers 130 and 230.

[0167] The gate electrodes 150 and 250 may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloy, silver-based metals such as silver (Ag) or silver alloy, copper-based metals such as copper (Cu) or copper alloy, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may have a multi-layer structure including at least two conductive layers with different physical properties.

[0168] Refer to Figure 1 , the first gate electrode 150 and the second gate electrode 250 may be formed on the same layer. Specifically, the first gate electrode 150 and the second gate electrode 250 may be formed of the same material by the same process.

[0169] The interlayer insulating layer 160 is disposed on the gate electrodes 150 and 250. The interlayer insulating layer 160 is disposed on the entire first thin film transistor TR1 and the second thin film transistor TR2. The interlayer insulating layer 160 is an insulating layer made of an insulating material. Specifically, the interlayer insulating layer 160 may be formed of an organic material, an inorganic material, or a laminate of an organic material layer and an inorganic material layer.

[0170] The source electrodes 171 and 271 and the drain electrodes 172 and 272 are disposed on the interlayer insulating layer 160. The source electrodes 171 and 271 and the drain electrodes 172 and 272 are spaced apart from each other and are respectively connected to the active layers 130 and 230. The source electrodes 171 and 271 and the drain electrodes 172 and 272 are respectively connected to the active layers 130 and 230 through contact holes formed in the interlayer insulating layer 160.

[0171] Each of the source electrodes 171 and 271 and the drain electrodes 172 and 272 may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. Each of the source electrodes 171 and 271 and the drain electrodes 172 and 272 may be formed of a single layer formed of a metal or a metal alloy, or may be formed of a multi-layer of two or more layers.

[0172] According to an embodiment of the present disclosure, the active layers 130 and 230 may be selectively conductive by selectively making the active layers 130 and 230 conductive. Applying conductivity to specific portions of the active layers 130 and 230 is referred to as selectively making the active layers 130 and 230 conductive. The selectively conductive portions may have a higher carrier concentration than the non-selectively conductive portions.

[0173] According to an embodiment of the present disclosure, the active layers 130 and 230 may be selectively conductive by using the gate electrodes 150 and 250 as masks. In this case, the regions of the active layers 130 and 230 overlapping with the gate electrodes 150 and 250 are not made conductive and become the channel portions 130n and 230n. The regions of the active layers 130 and 230 not overlapping with the gate electrodes 150 and 250 are made conductive and become the first connection portions 130a and 230a and the second connection portions 130b and 230b. The first connection portions 130a and 230a and the second connection portions 130b and 230b may generally be formed on both sides of the channel portions 130n and 230n.

[0174] According to an embodiment of the present disclosure, the active layers 130 and 230 may be selectively conductive by doping, plasma treatment, or dry etching.

[0175] For example, the active layers 130 and 230 may be selectively conductive by doping with a dopant. For doping in the selective conductive process, for example, at least one dopant selected from boron (B) ions, phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions may be used. In this case, the doped regions may be made conductive.

[0176] One of the first connection portions 130a and 230a and the second connection portions 130b and 230b becomes a source region, and the other of them becomes a drain region. Refer to Figure 1 , the first connection portions 130a and 230a may be source regions connected to the source electrodes 171 and 271. The second connection portions 130b and 230b may be drain regions connected to the drain electrodes 172 and 272. In the embodiments of the present disclosure, the source region and the drain region are mentioned only for convenience of description, and the source region and the drain region may be exchanged.

[0177] Figure 3 is a photograph of an oxide semiconductor layer having a crystalline structure according to another embodiment of the present disclosure.

[0178] Specifically, Figure 3 is a transmission electron microscope (TEM) photograph of the second oxide semiconductor layers 132 and 232 of the first active layer 130 and the second active layer 230 having a crystalline structure, and is a diagram showing the crystal surface 11 and the crystal orientation 12 of the second oxide semiconductor layers 132 and 232.

[0179] Specifically, refer to Figure 3 , it can be seen that the crystals of the second oxide semiconductor layers 132 and 232 including an IGO (InGaO)-based oxide semiconductor material grow uniformly in the (222) direction (diagonal direction). In this case, Figure 3 the crystal orientation 12 of the crystal plane 11 shown corresponds to the (222) direction.

[0180] Figures 4A to 4H is a manufacturing process diagram of a thin film transistor substrate 100 according to another embodiment of the present disclosure. The description of the components described above is omitted.

[0181] Refer to Figure 4A , a light-shielding layer 111 and 211 are formed on the base substrate 110. Specifically, after preparing the base substrate 110 provided in the first region Area1 and the second region Area2, the first light-shielding layer 111 may be formed on the base substrate 110 provided in the first region Area1, and the second light-shielding layer 211 may be formed on the base substrate 110 provided in the second region Area2.

[0182] Refer to Figure 4B , a buffer layer 120 is formed on the light-shielding layers 111 and 211. Specifically, the buffer layer 120 may be integrally formed on the first light-shielding layer 111 provided in the first region Area1 and the second light-shielding layer 211 provided in the second region Area2.

[0183] Refer to Figure 4C, a first oxide semiconductor material layer 135a, a second oxide semiconductor material layer 135b, and a third oxide semiconductor material layer 135c may be sequentially stacked on a substrate 110. In this case, the first oxide semiconductor material layer 135a, the second oxide semiconductor material layer 135b, and the third oxide semiconductor material layer 135c may be formed over the entire first region Area1 and the second region Area2.

[0184] In this case, each of the first oxide semiconductor material layer 135a and the third oxide semiconductor material layer 135c may include at least one of the following oxide semiconductor materials: an IZO (InZnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, and a GZO (GaZnO)-based oxide semiconductor material, and the second oxide semiconductor material layer 135b may include at least one of the following oxide semiconductor materials: an InZnO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, and an ITZO (InSnZnO)-based oxide semiconductor material.

[0185] Specifically, the second oxide semiconductor material layer 135b may include at least one of the following oxide semiconductor materials: an IZO (InZnO)-based oxide semiconductor material in which the concentration of In is 50% or more compared to the total concentration of In and Zn based on the number of atoms; an IGO (InGaO)-based oxide semiconductor material in which the concentration of In is 70% or more compared to the total concentration of In and Ga based on the number of atoms; an IGZO (InGaZnO)-based oxide semiconductor material in which the concentration of In is 50% or more compared to the total concentration of In, Ga, and Zn based on the number of atoms; an ITO (InSnO)-based oxide semiconductor material in which the concentration of In is 80% or more compared to the total concentration of In and Sn based on the number of atoms; an IGZTO (InGaZnSnO)-based oxide semiconductor material in which the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Ga, Zn, and Sn based on the number of atoms; and an ITZO (InSnZnO)-based oxide semiconductor material in which the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Sn, and Zn based on the number of atoms.

[0186] In this case, the first oxide semiconductor material layer 135a, the second oxide semiconductor material layer 135b, and the third oxide semiconductor material layer 135c can be formed by sputter deposition. When forming the first oxide semiconductor material layer 135a and the third oxide semiconductor material layer 135c, sputter deposition can be performed at a temperature of 15°C to less than 100°C. In some embodiments, it can be performed at a temperature of 15°C to 70°C. In some embodiments, it can be performed at a temperature of 15°C to 50°C.

[0187] When forming the second oxide semiconductor material layer 135b, sputter deposition can be performed at a temperature of 100°C to 300°C. When depositing the second oxide semiconductor material layer 135b at a temperature of 100 to 300°C, compared with room temperature deposition, the second oxide semiconductor material layer 135b can increase the film density and have few defects in the film, thereby forming a film that is easy to crystallize. Specifically, during high-temperature film formation, the amorphous state is the same, but the stoichiometry is improved and there are few defects inside the film, so that crystallization can occur better during the heat treatment for crystallization. Even in this case, the second oxide semiconductor material layer 135b has an amorphous structure.

[0188] When forming the second oxide semiconductor material layer 135b under high-temperature sputtering conditions, the second oxide semiconductor material layer 135b can partially form an arrangement. In this case, even if it undergoes a conductivity process after crystallization, the problem of returning to the amorphous structure can be prevented.

[0189] In addition, when forming the second oxide semiconductor material layer 135b by high-temperature sputtering conditions, compared with the case where the high-temperature sputtering step is not performed, the second oxide semiconductor material layer 135b can have a higher film density after the crystallization step. Therefore, the advantage is that even if it undergoes a conductivity process after crystallization, it does not return to the amorphous structure.

[0190] Reference Figure 4D , the first oxide semiconductor material layer 135a, the second oxide semiconductor material layer 135b, and the third oxide semiconductor material layer 135c can be patterned to form a first active pattern 130m and a second active pattern 230m respectively including a first oxide semiconductor pattern layer 131m and 231m, a second oxide semiconductor pattern layer 132m and 232m, and a third oxide semiconductor pattern layer 133m and 233m.

[0191] In this case, the first active pattern 130m is disposed on the buffer layer 120 in the first region Area1, and the second active pattern 230m is disposed on the buffer layer 120 in the second region Area2.

[0192] In addition, referring to Figure 4D , the first active pattern 130m may include a first oxide semiconductor pattern layer 131m, a second oxide semiconductor pattern layer 132m, and a third oxide semiconductor pattern layer 133m stacked in sequence, and the second active pattern 230m may include a first oxide semiconductor pattern layer 231m, a second oxide semiconductor pattern layer 232m, and a third oxide semiconductor pattern layer 233m stacked in sequence.

[0193] Referring to Figure 4E , the first active pattern 130m and the second active pattern 230m may be heat-treated. In this case, the step of heat-treating the first active pattern 130m and the second active pattern 230m may be performed at a temperature of 350 °C to 450 °C.

[0194] Referring to Figure 4E and Figure 4F , the second oxide semiconductor pattern layers 132m and 232m have a crystalline structure through the heat-treatment step, and the first oxide semiconductor pattern layers 131m and 231m and the third oxide semiconductor pattern layers 133m and 233m have an amorphous structure, respectively.

[0195] Furthermore, through the above sputtering deposition step and heat-treatment step, the second oxide semiconductor pattern layers 132m and 232m may be crystallized first, and the crystallized second oxide semiconductor pattern layers 132m and 232m may be used as catalysts for amorphous oxide semiconductor layers stacked on the upper and lower portions of the second oxide semiconductor pattern layers 132m and 232m to form crystalline oxide semiconductor layers. The crystalline oxide semiconductor layers may correspond to the above third oxide semiconductor layer 133, fourth oxide semiconductor layer 134, 234, and fifth oxide semiconductor layer 235.

[0196] That is, the crystallized second oxide semiconductor pattern layers 132m and 232m may be used as catalysts for amorphous oxide semiconductor layers stacked on the upper and lower portions of the second oxide semiconductor pattern layers 132m and 232m, and the amorphous oxide semiconductor layers stacked on the upper and lower portions of the second oxide semiconductor pattern layers 132m and 232m may be etched in the direction of the second oxide semiconductor pattern layers 132m and 232m to form crystalline oxide semiconductor layers.

[0197] Referring to Figure 4F , a photoresist material layer 136 may be formed to overlap with the second active pattern 230m provided in the second region Area2. Specifically, the photoresist material layer 136 does not overlap with the first active pattern 130m provided in the first region Area1.

[0198] Reference Figure 4G Figure 4G , a photoresist material layer 136 may be used as a mask to wet-etch a third oxide semiconductor pattern layer 133m of the first active pattern 130m. The first active layer 130 and the second active layer 230 are formed by this wet-etching.

[0199] The first active layer 130 includes a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132, and the second active layer 230 includes a first oxide semiconductor layer 231, a second oxide semiconductor layer 232, and a third oxide semiconductor layer 233.

[0200] Although not shown in the figure, the first active layer 130 may further include a third oxide semiconductor layer 133 disposed between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 and a fourth oxide semiconductor layer 134 disposed on the second oxide semiconductor layer 132.

[0201] In addition, the second active layer 230 may further include a fourth oxide semiconductor layer 234 disposed between the first oxide semiconductor layer 231 and the second oxide semiconductor layer 232 and a fifth oxide semiconductor layer 235 disposed between the second oxide semiconductor layer 232 and the third oxide semiconductor layer 233.

[0202] Reference Figure 4H Figure 4H , a gate insulating layer 140, gate electrodes 150 and 250, an interlayer insulating layer 160, source electrodes 171 and 271, and drain electrodes 172 and 272 may be sequentially formed on the first active layer 130 and the second active layer 230.

[0203] Figure 5 is a partial cross-sectional view of a display device 900 according to another embodiment of the present disclosure.

[0204] A display device 900 according to another embodiment of the present disclosure may include the above-described thin film transistor substrates 100 and 200 and a display device 710. Although Figure 5 shows the case of using the thin film transistor substrate 100 according to Figure 1 , the embodiments of the present disclosure are not limited thereto. Figure 2 Any one of the thin film transistor substrates 200 shown may be used as the thin film transistor substrate of a display device 900 according to another embodiment of the present disclosure.

[0205] Reference Figure 5 Figure 5 , the display device 710 may include a first electrode 711, an organic light emitting layer 712 on the first electrode 711, and a second electrode 713 on the organic light emitting layer 713. Figure 5The display device 900 is an organic light-emitting display device including an organic light-emitting diode (OLED) as a display device 710.

[0206] Reference Figure 5 , a planarization layer 175 may be disposed on the first thin-film transistor TR1 and the second thin-film transistor TR2, and a first electrode 711 of the display device 710 may be disposed on the planarization layer 175. Here, the planarization layer 175 planarizes the upper portions of the first thin-film transistor TR1 and the second thin-film transistor TR2 and protects the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0207] A bank 750 is disposed on an edge of the first electrode 711. The bank 750 defines a light-emitting region of the display device 710. An organic light-emitting layer 712 is disposed on the first electrode 711, and a second electrode 713 is disposed on the organic light-emitting layer 712 to form an organic light-emitting diode (OLED) in the display device 710.

[0208] In Figure 5 the display device 900, the first thin-film transistor TR1 may be a transistor of a gate driver. In addition, Figure 5 the first thin-film transistor TR1 of

[0209] Figure 5 may be used as a switching transistor of the display panel.

[0210] Figure 6 is a cross-sectional view of a thin-film transistor 10 according to an embodiment of the present disclosure. Figure 7 is a cross-sectional view of a thin-film transistor 20 according to another embodiment of the present disclosure.

[0211] Reference Figure 6 and Figure 7 , the thin-film transistors 10 and 20 include an active layer 30 and a gate electrode 15 spaced apart from the active layer 30 and at least partially overlapping the active layer 30.

[0212] The thin-film transistors 10 and 20 according to an embodiment of the present disclosure further include a substrate 11.

[0213] Glass or plastic may be used as the substrate 11. Transparent plastic having a flexible property (e.g., polyimide) may be used as the plastic. Figure 6 and Figure 7 The substrate 11 shown in Figure 1 and Figure 2 may correspond to the substrate 110 shown in

[0214] The light-shielding layer 12 may be disposed on the base substrate 11. The light-shielding layer 12 blocks the light incident from the base substrate 11 to protect the active layer 30. When another structure is used as the light-shielding portion, the light-shielding layer 12 may be omitted. Figure 6 and Figure 7 The illustrated light-shielding layer 12 may correspond to Figure 1 and Figure 2 the illustrated light-shielding layers 111 and 211.

[0215] According to an embodiment of the present disclosure, the buffer layer 13 may be disposed on the base substrate 11 and the light-shielding layer 12.

[0216] The buffer layer 13 has an insulating property and protects the active layer 30. The buffer layer 13 may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), and a metal oxide having an insulating property. Figure 6 and Figure 7 The illustrated base substrate 11 may correspond to Figure 1 and Figure 2 the illustrated base substrate 110.

[0217] The active layer 30 may be disposed on the buffer layer 13.

[0218] The active layer 30 includes an oxide semiconductor material. According to an embodiment of the present disclosure, the active layer 30 is an oxide semiconductor layer made of an oxide semiconductor material. The active layer 30 made of an oxide semiconductor material includes a metal and oxygen (O).

[0219] In addition, the active layer 30 may include at least one layer having a crystalline structure.

[0220] According to an embodiment of the present disclosure, the active layer 30 includes a first oxide semiconductor layer 31, a second oxide semiconductor layer 32, and a third oxide semiconductor layer 33. The second oxide semiconductor layer 32 is disposed on the first oxide semiconductor layer 31, and the third oxide semiconductor layer 33 is disposed on the second oxide semiconductor layer 32.

[0221] According to an embodiment of the present disclosure, the first oxide semiconductor layer 31 and the third oxide semiconductor layer 33 of the active layer 30 may have an amorphous structure, and the second oxide semiconductor layer 32 may have a crystalline structure. According to an embodiment of the present disclosure, the crystalline structure and the amorphous structure are referred to based on the content of the crystal grains included in the oxide semiconductor layer. More specifically, according to an embodiment of the present disclosure, the crystalline structure and the amorphous structure are referred to based on the ratio of the crystal grains having a particle size of 1 nm or more.

[0222] The content of the crystalline structure and the amorphous structure has been described above and is omitted.

[0223] According to an embodiment of the present disclosure, the first oxide semiconductor layer 31 and the third oxide semiconductor layer 33 have an amorphous structure. Specifically, in the cross-sectional images of the first oxide semiconductor layer 31 and the third oxide semiconductor layer 33 taken by a transmission electron microscope (TEM), the ratio of grains with a particle size of 1 nm or more may be 10% or less of the total cross-sectional area. More specifically, in the cross-sectional images of the first oxide semiconductor layer 31 and the third oxide semiconductor layer 33 taken by a transmission electron microscope (TEM), the ratio of grains with a particle size of 5 nm to 10 nm may be 10% or less of the total cross-sectional area.

[0224] The first oxide semiconductor layer 31 and the third oxide semiconductor layer 33 of the active layer 30 may include at least one of the following oxide semiconductor materials: IZO (InZnO)-based oxide semiconductor materials, IGZO (InGaZnO)-based oxide semiconductor materials, IGZTO (InGaZnSnO)-based oxide semiconductor materials, GZTO (GaZnSnO)-based oxide semiconductor materials, and GZO (GaZnO)-based oxide semiconductor materials. More specifically, the first oxide semiconductor layer 31 and the third oxide semiconductor layer 33 of the active layer 30 may include IGZO (InGaZnO)-based oxide semiconductor materials. In some embodiments, the first oxide semiconductor layer 31 and the third oxide semiconductor layer 33 may include IGZO (InGaZnO)-based oxide semiconductor materials.

[0225] According to an embodiment of the present disclosure, the first oxide semiconductor layer 31 of the active layer 30 may have a thickness of 1 to 10 nm, the second oxide semiconductor layer 32 may have a thickness of 10 to 50 nm, and the third oxide semiconductor layer 33 may have a thickness of 1 to 20 nm.

[0226] According to an embodiment of the present disclosure, by adjusting the composition and manufacturing conditions during the manufacturing process of the second oxide semiconductor layer 32, the second oxide semiconductor layer 32 may have a crystalline structure. For example, in order to form a crystalline structure, the second oxide semiconductor layer 32 may be formed by sputter deposition and heat treatment performed at a temperature of 350°C to 450°C. In this case, sputter deposition may be performed at a temperature of 100°C to 300°C.

[0227] According to an embodiment of the present disclosure, the second oxide semiconductor layer 32 has a crystalline structure. Specifically, in a cross-sectional image of the second oxide semiconductor layer 32 taken using a transmission electron microscope (TEM), the ratio of grains having a particle size of 1 nm or more may be 50% or more of the total cross-sectional area. More specifically, in a cross-sectional image of the second oxide semiconductor layer 32 taken using a transmission electron microscope (TEM), the ratio of grains having a particle size of 5 nm to 10 nm may be 50% or more of the total cross-sectional area.

[0228] The second oxide semiconductor layer 32 may include at least one of the following oxide semiconductor materials: an IZO (InZnO)-based oxide semiconductor material in which the concentration of In is 50% or more compared to the total concentration of In and Zn based on the number of atoms; an IGO (InGaO)-based oxide semiconductor material in which the concentration of In is 70% or more compared to the total concentration of In and Ga based on the number of atoms; an IGZO (InGaZnO)-based oxide semiconductor material in which the concentration of In is 50% or more compared to the total concentration of In, Ga, and Zn based on the number of atoms; an ITO (InSnO)-based oxide semiconductor material in which the concentration of In is 80% or more compared to the total concentration of In and Sn based on the number of atoms; an IGZTO (InGaZnSnO)-based oxide semiconductor material in which the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Ga, Zn, and Sn based on the number of atoms; and an ITZO (InSnZnO)-based oxide semiconductor material in which the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Sn, and Zn based on the number of atoms. In some embodiments, the second oxide semiconductor layer 32 may include an IZO (InZnO)-based oxide semiconductor material in which the concentration of In is 50% or more compared to the total concentration of In and Zn.

[0229] According to an embodiment of the present disclosure, the second oxide semiconductor layer 32 may be doped with a dopant. For example, the dopant may be doped into the second oxide semiconductor layer 32 by an ion implantation method. Accordingly, according to an embodiment of the present disclosure, the second oxide semiconductor layer 32 may further include a dopant doped into the oxide semiconductor material. The dopant may include at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), and germanium (Ge). Specifically, the second oxide semiconductor layer 32 may be formed of an IGO (InGaO)-based oxide semiconductor material doped with at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), and germanium (Ge).

[0230] The dopant included in the second oxide semiconductor layer 32 may have a content of 0.1 to 10 atomic % based on the total number of atoms in the second oxide semiconductor layer 32. Specifically, the dopant included in the second oxide semiconductor layer 32 may have a content of 0.1 to 10 atomic % based on the total number of atoms in the second oxide semiconductor layer 32, and the dopant included in the second oxide semiconductor layer 32 may have a content of 0.1 to 10 atomic % based on the total number of atoms in the second oxide semiconductor layer 32.

[0231] When the dopant is doped into the second oxide semiconductor layer 32, defects in the particles of the second oxide semiconductor layer 32 can be prevented, such that the second oxide semiconductor layer 32 may have a stable crystal structure, and grains having a particle size of 3 nm to 500 nm can be easily formed in the second oxide semiconductor layer 32.

[0232] According to an embodiment of the present disclosure, the second oxide semiconductor layer 32 may have at least one of a (400) crystal plane, a (222) crystal plane, a (220) crystal plane, a (311) crystal plane, and a (0016) crystal plane.

[0233] According to an embodiment of the present disclosure, the second oxide semiconductor layer 32 may have at least one of a cubic crystal structure, a rhombohedral crystal structure, a spinel crystal structure, and a hexagonal crystal structure.

[0234] According to an embodiment of the present disclosure, the thin film transistor 10 may include an active layer 30 having a three-layer structure (amorphous-crystalline-amorphous). When the active layer 30 of the thin film transistor 10 has a three-layer structure (amorphous-crystalline-amorphous), the second oxide semiconductor layer 32 having a crystalline structure and the third oxide semiconductor layer 33 having an amorphous structure may be used as the channel layer.

[0235] In the case of the thin film transistor 10, where both the second oxide semiconductor layer 32 having a crystalline structure and the third oxide semiconductor layer 33 having an amorphous structure are used as the channel layer, the second oxide semiconductor layer 32 having a crystalline structure may be used as the main channel layer. In this case, the third oxide semiconductor layer 33 having an amorphous structure is disposed between the second oxide semiconductor layer 32 serving as the main channel layer and the gate insulating layer 14, and a relatively small amount of electrons are trapped between the active layer 30 and the gate insulating layer 14. More specifically, a relatively small amount of electrons may be trapped at the interface between the active layer 30 and the gate insulating layer 14. As a result, the thin film transistor 10 may have high reliability. More specifically, the thin film transistor 10 may have a high s-factor.

[0236] Figure 6 and Figure 7 The first oxide semiconductor layer 31, the second oxide semiconductor layer 32, and the third oxide semiconductor layer 33 of the active layer 30 shown correspond to Figure 1 and Figure 2 the first oxide semiconductor layer 231, the second oxide semiconductor layer 232, and the third oxide semiconductor layer 233 of the second active layer 230 shown, and repeated description is omitted.

[0237] According to an embodiment of the present disclosure, the active layer 30 of the thin film transistor 20 may further include a fourth oxide semiconductor layer 34 and a fifth oxide semiconductor layer 35.

[0238] The fourth oxide semiconductor layer 34 of the active layer 30 is disposed between the first oxide semiconductor layer 31 and the second oxide semiconductor layer 32 of the active layer 30, and the fifth oxide semiconductor layer 35 of the active layer 30 is disposed between the second oxide semiconductor layer 32 and the third oxide semiconductor layer 33 of the active layer 30.

[0239] In this case, the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 of the active layer 30 have a crystalline structure.

[0240] By adjusting the manufacturing conditions during the manufacturing processes of the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35, the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 can have a crystalline structure. For example, in order to form a crystalline structure, a heat treatment step during the formation of the active layer 30 can be included. In this case, the heat treatment can be performed at a temperature of 350 to 450 °C.

[0241] The fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 can include at least one of the following oxide semiconductor materials: an IZO (InZnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, and a GZO (GaZnSnO)-based oxide semiconductor material.

[0242] According to an embodiment of the present disclosure, the fourth oxide semiconductor layer 34 of the active layer 30 can be made of the same material as the first oxide semiconductor layer 31 of the active layer 30, and the fifth oxide semiconductor layer 35 of the active layer 30 can be made of the same material as the third oxide semiconductor layer 33 of the active layer 30.

[0243] When forming the active layer 30, first, the second oxide semiconductor layer 32 is crystallized, and the crystallized second oxide semiconductor layer 32 serves as a catalyst for amorphous oxide semiconductor layers stacked on the upper and lower portions of the second oxide semiconductor layer 32 to form the crystalline fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35.

[0244] That is, the crystallized second oxide semiconductor layer 32 serves as a catalyst for amorphous oxide semiconductor layers stacked on the upper and lower portions of the second oxide semiconductor layer 32, and the amorphous oxide semiconductor layers stacked on the upper and lower portions of the second oxide semiconductor layer 32 are etched in the direction of the second oxide semiconductor layer 32 to form the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35.

[0245] Therefore, the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 are layers crystallized by etching an amorphous structure with high reliability. That is, even if the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 have a crystalline structure, the mobility can be slightly lower than that of the second oxide semiconductor layer 32, and the reliability can be high.

[0246] When the active layer 30 of the thin film transistor 20 has a five-layer structure (amorphous - crystalline - crystalline - crystalline - amorphous), the second oxide semiconductor layer 32, the fourth oxide semiconductor layer 34, the fifth oxide semiconductor layer 35 having a crystalline structure, and the third oxide semiconductor layer 33 having an amorphous structure can be used as the channel layer.

[0247] In this case, in the thin film transistor 20 in which the second oxide semiconductor layer 32, the fourth oxide semiconductor layer 34, the fifth oxide semiconductor layer 35 having a crystalline structure, and the third oxide semiconductor layer 33 having an amorphous structure all serve as the channel layer, the second oxide semiconductor layer 32, the fourth oxide semiconductor layer 34, and the fifth oxide semiconductor layer 35 having a crystalline structure serve as the main channel layer, and the third oxide semiconductor layer 33 having an amorphous structure is disposed between the fifth oxide semiconductor layer 35 and the gate insulating layer 14 provided at the top of the main channel layer, and a relatively small amount of electrons is trapped between the active layer 30 and the gate insulating layer 14. As a result, the thin film transistor 20 can have high reliability. More specifically, the thin film transistor 20 can have a high s factor.

[0248] According to an embodiment of the present disclosure, the active layer 30 includes the fifth oxide semiconductor layer 35 having both reliability and mobility between the second oxide semiconductor layer 32 having a high mobility and the third oxide semiconductor layer 33 having high reliability, so that the thin film transistor 20 can ensure both mobility and reliability.

[0249] In the cross-sectional images of the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 of the active layer 30, the ratio of grains having a particle size of 1 nm or more can be 50% or more of the total cross-sectional area. More specifically, in the cross-sectional images of the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 taken by a transmission electron microscope TEM, the ratio of grains having a particle size of 5 nm to 10 nm can be 50% or more of the total cross-sectional area.

[0250] According to an embodiment of the present disclosure, the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 of the active layer 30 can have a (009) crystal plane. Specifically, the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 of the active layer 30 can have a CAAC crystal structure.

[0251] More specifically, the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 of the active layer 30 can have a crystal surface and a crystal structure different from those of the crystal surface and the crystal structure of the second oxide semiconductor layer 32.

[0252] According to an embodiment of the present disclosure, the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 of the active layer 30 may include crystal grains having a particle size of 1 nm to 10 nm. Specifically, the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 of the active layer 30 may have smaller crystal grains than those of the second oxide semiconductor layer 32.

[0253] Compared with giant crystals, the small crystal grains included in the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 of the active layer 30 can be easily etched.

[0254] The fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 of the active layer 30 made of small crystal grains have excellent etching characteristics and thus can be easily patterned.

[0255] According to an embodiment of the present disclosure, the fourth oxide semiconductor layer 34 and the fifth oxide semiconductor layer 35 of the active layer 30 may have a thickness of 0.1 to 3 nm.

[0256] Figure 7 The first oxide semiconductor layer 31, the second oxide semiconductor layer 32, the third oxide semiconductor layer 33, the fourth oxide semiconductor layer 34, and the fifth oxide semiconductor layer 35 of the active layer 30 shown correspond to Figure 2 the first oxide semiconductor layer 231, the second oxide semiconductor layer 232, the third oxide semiconductor layer 233, the fourth oxide semiconductor layer 234, and the fifth oxide semiconductor layer 235 of the second active layer 230 shown, and repeated descriptions thereof are omitted.

[0257] The gate insulating layer 14 is disposed on the active layer 30. The gate insulating layer 14 may include at least one of silicon oxide and silicon nitride, and may include a metal oxide or a metal nitride. The gate insulating layer 14 may have a single-layer structure or a multi-layer structure. The gate insulating layer 14 may be disposed to cover the entire upper surface of the buffer layer 13. Figure 6 and Figure 7 The gate insulating layer 14 shown in Figure 1 and Figure 2 corresponds to the gate insulating layer 140 shown in

[0258] The gate electrode 15 is disposed on the gate insulating layer 14. The gate electrode 15 is spaced apart from the active layer 30 and at least partially overlaps with the active layer 30. The gate electrode 15 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 15 may have a multilayer structure including at least two conductive films having different physical properties.

[0259] Figure 6 and Figure 7 The gate electrode 15 shown in Figure 1 and Figure 2 corresponds to the gate electrodes 150 and 250 shown in

[0260] The interlayer insulating layer 16 is disposed on the gate electrode 15. The interlayer insulating layer 16 may be formed of an organic material, an inorganic material, or a stack of an organic material layer and an inorganic material layer.

[0261] Figure 6 and Figure 7 The interlayer insulating layer 16 shown in Figure 1 and Figure 2 corresponds to the interlayer insulating layer 160 shown in

[0262] The source electrode 17 and the drain electrode 18 are disposed on the interlayer insulating layer 16. The source electrode 17 and the drain electrode 18 are spaced apart from each other and are respectively connected to the active layer 30. The source electrode 17 and the drain electrode 18 are connected to the active layer 30 through contact holes formed in the interlayer insulating layer 16.

[0263] Figure 6 and Figure 7 The source electrode 17 and the drain electrode 18 shown in Figure 1 and Figure 2 correspond to the source electrode 271 and the drain electrode 272 shown in

[0264] According to an embodiment of the present disclosure, the active layer 30 may be selectively conductive by using the gate electrode 15 as a mask. In this case, the region of the active layer 30 that overlaps with the gate electrode 15 is not conductive and becomes the channel portion 30n. The regions of the active layer 30 that do not overlap with the gate electrode 15 are conductive and become the first connection portion 30a and the second connection portion 30b. The first connection portion 30a and the second connection portion 30b may generally be formed on both sides of the channel portion 30n.

[0265] Figure 8 is a schematic diagram of a display device 1000 according to another embodiment of the present disclosure.

[0266] As Figure 8 shown, a display device 1000 according to another embodiment of the present disclosure may include a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0267] The display panel 310 includes gate lines GL and data lines DL, and pixels P are disposed in a crossing region of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be disposed on a base substrate 110.

[0268] The controller 340 controls the gate driver 320 and the data driver 330.

[0269] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 by using signals provided from an external system (not shown). In addition, the controller 340 samples input image data input from the external system, realigns the sampled data, and provides the realigned digital image data RGB to the data driver 330.

[0270] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, control signals for controlling a shift register may be included in the gate control signal GCS.

[0271] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0272] The data driver 330 supplies a data voltage to the data lines DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into an analog data voltage and supplies the data voltage to the data lines DL.

[0273] According to an embodiment of the present disclosure, the gate driver 320 may be encapsulated on the display panel 310. In this way, a structure in which the gate driver 320 is directly encapsulated on the display panel 310 is referred to as a gate-in-panel (GIP) structure. Specifically, in the gate-in-panel (GIP) structure, the gate driver 320 may be disposed on the base substrate 110.

[0274] The display device 1000 according to an embodiment of the present disclosure may include the above-described thin-film transistor substrates 100 and 200. According to an embodiment of the present disclosure, the gate driver 320 may include the first thin-film transistor TR1 of the above-described thin-film transistor substrates 100 and 200.

[0275] The gate driver 320 may include a shift register 350.

[0276] The shift register 350 sequentially supplies gate pulses to the gate lines GL within one frame by using a start signal and a gate clock transmitted from the controller 340. In this case, one frame refers to a time period during which an image is output through the display panel 310. The gate pulse has a conduction voltage capable of turning on a switching device (thin-film transistor) provided in the pixel P.

[0277] In addition, the shift register 350 supplies a gate cut-off signal capable of turning off the gate of the switching device to the gate line GL during another period of one frame in which no gate pulse is provided. Hereinafter, the gate pulse and the gate cut-off signal will be collectively referred to as a scan signal SS or Scan.

[0278] The shift register 350 may include the first thin-film transistor TR1 of the above-described thin-film transistor substrates 100 and 200.

[0279] Figure 9 is a schematic diagram showing the shift register 350. Figure 10 is provided in Figure 9 The circuit diagram of the stage 351 in the shift register 350 of

[0280] Refer to Figure 9 , the shift register 350 may include g stages 351 (ST1 to STg).

[0281] The shift register 350 transmits one scan signal SS to the pixels P connected to one gate line GL through one gate line GL. Each stage 351 may be connected to one gate line GL. When g gate lines GL are formed in the display panel 110, the shift register 350 may include g stages 351 (ST1 to STg) and may generate g scan signals SS1 to SSg.

[0282] Generally, each stage 351 outputs a gate pulse GP once during one frame, and the gate pulses GP are sequentially output from each stage 351.

[0283] Figure 10 is a circuit diagram showing the stage 351 of the shift register 350 of the gate driver 320.

[0284] Figure 10One stage 351 of the shift register shown includes an output unit OBc and OBs for providing an output voltage Vout in response to the logic state of a first node Q, and a first node control unit NC1 for controlling the charging and discharging of the first node Q.

[0285] The output units OBc and OBs include a pull-up transistor Tup that provides an output voltage of a clock signal CLKa in response to control of the first node. The output voltage is provided as a scan pulse and a carry signal for controlling the charging and discharging of other stages to corresponding gate lines.

[0286] The first node control unit NC1 includes a first transistor T1 of a set unit for charging the first node Q with a high potential voltage VDD or a front-end output PRE in response to a front-end output PRE from a previous stage; and a second transistor T2 of a reset unit for discharging the first node Q with a low potential voltage VSS as a reset voltage in response to a back-end output NXT from a next stage. When Figure 10 the stage 351 is the first stage ST, a start pulse Vst is provided instead of the front-end output PRE.

[0287] When Figure 10 the stage 351 is the last stage, a reset pulse Vrst is provided instead of the back-end output NXT.

[0288] In a first period, in response to the front-end output PRE or the start pulse Vst, the first node Q is pre-charged through the conducting first transistor T1, and then the first node Q is floated in a charged state by the non-conducting first transistor T1 and second transistor T2 in a second period. In this case, the gate-conducting voltage (gate high voltage) of the clock signal CLKa is provided to the drain electrode of the pull-up transistor Tup, and the voltage of the first node Q is amplified by the capacitor between the gate electrode and the source electrode of the pull-up transistor Tup, such that the pull-up transistor Tup is stably turned on to output the gate-conducting voltage of the clock signal CLKa as the output voltage.

[0289] Subsequently, in a third period, the pull-up transistor Tup that remains conducting by floating the first node Q outputs the gate-cutoff voltage (gate low voltage) of the clock signal CLKa as the output voltage.

[0290] Then, in a fourth period, the first node Q is discharged through the second transistor T2 that conducts in response to the back-end output NXT or the reset pulse Vrst, and the pull-up transistor Tup is turned off, such that the output voltage remains the gate-cutoff voltage.

[0291] Reference Figure 10, since a carry output unit OBc controlled by a first node Q1 is provided, the output units OBc and OBs are divided into a scan output unit OBs and a carry output unit OBc.

[0292] The scan output unit OBc includes a scan pull-up transistor Tup-S that outputs a clock pulse CLKa as a scan pulse SP in response to the control of the first node Q. The carry output unit OBc includes a carry pull-up transistor Tup-C that outputs a clock pulse CLKa as a carry signal CR in response to the control of the first node Q. The carry signal CR output from the carry output unit OBc is provided as a front-end output PRE for a backend stage and is provided as a backend output NXT for a front-end stage. Therefore, the output node of the carry signal CR and the output node of the scan signal SP are separated to reduce the load on the carry signal CR, thereby reducing the delay of the carry signal CR that controls the charging and discharging of the front-end stage and the backend stage.

[0293] Reference Figure 10 , a carry pull-down transistor Tdn-C is additionally provided, where the carry output unit OBc is controlled by a second node QB; a scan pull-down transistor Tdn-S is additionally provided, where the scan output unit OBs is controlled by the second node QB; and a second node control unit NC2 including an inverter INV connected between the first node Q and the second node QB is additionally provided.

[0294] The scan pull-down transistor Tdn-S of the scan output unit OBs provides a first low potential voltage VSS0 as a first gate cutoff voltage of the scan signal SP in response to the control of the second node QB.

[0295] The carry pull-down transistor Tdn-C of the carry output unit OBc provides a second low potential voltage VSS1 as a second gate cutoff voltage of the carry signal CR in response to the control of the second node QB. The carry signal CR output from the carry output unit OBc is provided as a front-end output PRE for a backend stage and is provided as a backend output NXT for a front-end stage. In the first node control unit NC1, a second transistor T2 as a reset portion discharges the first node Q to a third low potential voltage VSS2 as a reset voltage in response to a backend carry signal CRn.

[0296] The inverter INV of the second node control unit NC2 provides a high potential voltage VH or a low potential voltage VL opposite to the voltage of the first node Q to the second node QB in response to the control of the first node Q.

[0297] The high potential voltages VDD and VH may be the same as or different from each other. The low potential voltages VSS0, VSS1, VSS2, and VL may be the same as or different from each other.

[0298] In addition, the first node control unit NC1 further includes a third transistor T3 of a noise eliminator controlled by the second node QB. The second node control unit NC2 includes an inverter INV composed of fourth to seventh transistors T4 to T7, and further includes an eighth transistor T8 controlled by a front-end output PRE. A third low-potential voltage VSS2 serving as a second reset voltage is applied to the third transistor T3 of the noise eliminator, and a fourth low-potential voltage VSS3 serving as a first reset voltage is applied to the second transistor T2 of the reset unit.

[0299] The third transistor T3 of the noise eliminator added to the first node control unit NC1 discharges the first node Q to the third low-potential voltage VSS2 in response to the control of the second node QB. Therefore, when the first node Q is at a low logic level, the third transistor T3 removes the noise induced in the first node Q due to the coupling of the clock CLKa supplied to the pull-up transistors Tup-C and Tup-S. The inverter INV of the second node control unit NC2 includes fourth to seventh transistors T4, T5, T6, and T7 to supply a high-potential voltage VH or a low-potential voltage VL to the second node QB, so as to be opposite to the voltage of the first node Q. The eighth transistor T8 added to the second node control unit NC2 discharges the second node QB to the low-potential voltage VL in response to the front-end output PRE.

[0300] A first capacitor C1 for amplifying the voltage of the gate electrode Q is formed between the gate electrode and the source electrode of the scan pull-up transistor Tup-S of the scan output unit OBs. A second capacitor C2 for amplifying the voltage of the gate electrode Q is formed between the gate electrode and the source electrode of the carry pull-up transistor Tup-C of the carry output unit OBc.

[0301] When the first node Q is in a charged state through the first node control unit NC1, the scan pull-up transistor Tup-S and the carry pull-up transistor Tup-C respectively output the clock signal CLKa as the scan signal SP and the carry signal CR.

[0302] When the second node QB is in a charged state through the second node control unit NC2, the scan pull-down transistor Tdn-S and the carry pull-down transistor Tdn-C respectively output a first low-potential voltage VSS0 and a second low-potential voltage VSS1 as the scan signal SP and the carry signal CR.

[0303] Figure 11 is a circuit diagram showing Figure 8 any one pixel P of

[0304] Figure 11 The circuit diagram of

[0305] Reference Figure 11 , pixel P includes a display device 710 and a pixel driving circuit PDC for driving the display device 710. Specifically, the display device 1000 according to an embodiment of the present disclosure may include a pixel driving circuit PDC on a base substrate 110.

[0306] Figure 11 The pixel driving circuit PDC of includes a switching transistor and a driving transistor.

[0307] According to another embodiment of the present disclosure, the first thin film transistor TR1 of the above thin film transistor substrates 100 and 200 may be used as the switching transistor. However, the embodiments of the present disclosure are not limited thereto, and the second thin film transistor TR2 of the above thin film transistor substrates 100 and 200 may be used as Figure 11 the switching transistor of the pixel driving circuit PDC shown.

[0308] According to another embodiment of the present disclosure, the second thin film transistor TR2 of the above thin film transistor substrates 100 and 200 may be used as Figure 11 the driving transistor of the pixel driving circuit PDC shown.

[0309] Hereinafter, for ease of explanation, the display device 1000 will be described focusing on the embodiment in which the first thin film transistor TR1 of the above thin film transistor substrates 100 and 200 is used as the switching transistor and the second thin film transistor TR2 is used as the driving transistor. The second thin film transistor TR2 is connected to the display device 710.

[0310] The first thin film transistor TR1 as the switching transistor is connected to the gate line GL and the data line DL, and is turned on or off by a scan signal SS provided through the gate line GL.

[0311] The data line DL provides a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls the application of the data voltage Vdata.

[0312] The driving power supply line PL provides a driving voltage Vdd to the display device 710, and the second thin film transistor TR2 as the driving transistor controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving an organic light emitting diode OLED as the display device 710.

[0313] When the second thin-film transistor TR2 is turned on by a scan signal SS applied through a gate line GL from a gate driver 320, a data voltage Vdata provided through a data line DL is supplied to a gate electrode of the second thin-film transistor TR2 connected to a display device 710. The data voltage Vdata is charged in a storage capacitor Cst formed between the gate electrode and the source electrode of the second thin-film transistor TR2.

[0314] According to the data voltage Vdata, the amount of current supplied to an organic light-emitting diode OLED serving as the display device 710 through the second thin-film transistor TR2 is controlled, and accordingly, the gray level of light output from the display device 710 can be controlled.

[0315] Figure 12 is Figure 11 a plan view of a pixel of Figure 13 is a cross-sectional view taken along line I-I' of Figure 12 of.

[0316] Referring to Figure 13 , a light-shielding layer LS1 and LS2 are provided on a base substrate 110. In this case, the light-shielding layer LS1 and LS2 correspond to the light-shielding layers 111 and 211 shown in Figure 1 and Figure 2 .

[0317] The base substrate 110 may be made of glass or plastic. As the base substrate 110, a plastic having flexible characteristics, such as polyimide (PI), may be used.

[0318] Figure 13 The light-shielding layers LS1 and LS2 shown are provided to be spaced apart from each other.

[0319] The light-shielding layers LS1 and LS2 can be used as light-shielding layers. The light-shielding layers protect the first active layer A1 of the first thin-film transistor TR1 and the second active layer A2 of the second thin-film transistor TR2 by blocking light incident from the outside.

[0320] Referring to Figure 13 , a buffer layer 120 may be provided on the light-shielding layers LS1 and LS2. The buffer layer 120 is provided to cover the entire upper surface of the base substrate 110. The buffer layer 120 is formed of an insulating material and protects the active layers A1 and A2 from moisture, oxygen, etc. introduced from the outside.

[0321] The active layer A1 of the first thin-film transistor TR1 and the active layer A2 of the second thin-film transistor TR2 may be provided on the buffer layer 120.

[0322] The active layers A1 and A2 may include, for example, an oxide semiconductor material. The active layers A1 and A2 may be formed of an oxide semiconductor layer made of an oxide semiconductor material.

[0323] Figure 13 The active layers A1 and A2 of Figure 1 and Figure 2 may correspond to the first active layer 130 and the second active layer 230 shown in Figure 13 Exemplarily, the first active layer 130 and the second active layer 230 of Figure 1 are shown, but embodiments of the present disclosure are not limited thereto, and the first active layer 130 and the second active layer 230 of Figure 2 may be shown.

[0324] Figure 13 The active layer A1 of the first thin film transistor TR1 of

[0325] includes a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132, and the active layer A2 of the second thin film transistor TR2 includes a first oxide semiconductor layer 231, a second oxide semiconductor layer 232, and a third oxide semiconductor layer 233.

[0326] A gate insulating layer 140 is disposed on the active layers A1 and A2. The gate insulating layer 140 may cover the entire upper surface of the active layers A1 and A2, or may cover only a part of the active layers A1 and A2.

[0327] A gate electrode G1 of the first thin film transistor TR1 and a gate electrode G2 of the second thin film transistor TR2 are disposed on the gate insulating layer 140.

[0328] The gate electrode G1 of the first thin film transistor TR1 overlaps at least a part of the active layer A1. The gate electrode G2 of the second thin film transistor TR2 overlaps at least a part of the active layer A2.

[0329] Referring to Figure 12 and Figure 13 , a first capacitor electrode C11 of the first capacitor C1 may be disposed on the same layer as the gate electrodes G1 and G2. The gate electrodes G1 and G2 and the first capacitor electrode C11 may be manufactured together using the same material through the same process.

[0330] An interlayer insulating layer 160 is disposed on the gate electrodes G1 and G2 and the first capacitor electrode C11.

[0331] The source electrodes S1 and S2 and the drain electrodes D1 and D2 are disposed on the interlayer insulating layer 160. According to an embodiment of the present disclosure, the source electrodes S1 and S2 and the drain electrodes D1 and D2 are mentioned only for convenience of description, and the source electrodes S1 and S2 and the drain electrodes D1 and D2 may be exchanged.

[0332] In addition, the data lines DL and the driving power lines PL are disposed on the interlayer insulating layer 160. The source electrode S1 of the first thin film transistor TR1 may be integrally formed with the data line DL. The drain electrode D2 of the second thin film transistor TR2 may be integrally formed with the driving power line PL.

[0333] According to an embodiment of the present disclosure, the source electrode S1 and the drain electrode D1 of the first thin film transistor TR1 are spaced apart from each other and are respectively connected to the active layer A1 of the first thin film transistor TR1. The source electrode S2 and the drain electrode D2 of the second thin film transistor TR2 are spaced apart from each other and are respectively connected to the active layer A2 of the second thin film transistor TR2.

[0334] The source electrode S1 of the first thin film transistor TR1 may contact the source region of the active layer A1 through the first contact hole H1.

[0335] The drain electrode D1 of the first thin film transistor TR1 may contact the drain region of the active layer A1 through the second contact hole H2 and may be connected to the first capacitor electrode C11 of the first capacitor C1 through the third contact hole H3.

[0336] The source electrode S2 of the second thin film transistor TR2 may extend onto the interlayer insulating layer 160, and a part thereof may serve as the second capacitor electrode C12 of the first capacitor C1. The first capacitor electrode C11 and the second capacitor electrode C12 overlap to form the first capacitor C1.

[0337] In addition, the source electrode S2 of the second thin film transistor TR2 may contact the source region of the active layer A2 through the fourth contact hole H4.

[0338] The drain electrode D2 of the second thin film transistor TR2 may contact the drain region of the active layer A2 through the fifth contact hole H5.

[0339] The first thin film transistor TR1 includes an active layer A1, a gate electrode G1, a source electrode S1, and a drain electrode D1, and serves as a switching transistor for controlling the data voltage Vdata applied to the pixel driver PDC.

[0340] The second thin film transistor TR2 includes an active layer A2, a gate electrode G2, a source electrode S2, and a drain electrode D2, and serves as a driving transistor for controlling the driving voltage Vdd applied to the display device 710.

[0341] The planarization layer 175 is disposed on the source electrodes S1 and S2, the drain electrodes D1 and D2, the data line DL, and the driving power line PL. The planarization layer 175 planarizes the upper portions of the first thin film transistor TR1 and the second thin film transistor TR2, and protects the first thin film transistor TR1 and the second thin film transistor TR2.

[0342] The first electrode 711 of the display device 710 is disposed on the planarization layer 175. The first electrode 711 of the display device 710 may be connected to the source electrode S2 of the second thin film transistor TR2 through a sixth contact hole H6 formed in the planarization layer 175.

[0343] The bank 750 is disposed at an edge of the first electrode 711. The bank 750 defines a light emitting region of the display device 710.

[0344] The organic light emitting layer 712 is disposed on the first electrode 711, and the second electrode 713 is disposed on the organic light emitting layer 712. Thus, the display device 710 is completed. Figure 13 The illustrated display device 710 is an organic light emitting diode (OLED). Thus, the display device 1000 according to an embodiment of the present disclosure is an organic light emitting display device.

[0345] According to the present disclosure, the following advantageous effects can be obtained.

[0346] The thin film transistor according to an embodiment of the present disclosure can simultaneously ensure excellent mobility and excellent reliability by selectively applying an active layer having a multi-layer structure.

[0347] The display device according to an embodiment of the present disclosure including such a thin film transistor substrate can have excellent display performance and excellent reliability.

[0348] In addition to the above effects, other features and advantages of the present disclosure will be described below or will be clearly understood by those of ordinary skill in the art to which the present disclosure pertains from these descriptions and techniques.

[0349] It is obvious to those skilled in the art that the present disclosure described above is not limited by the above embodiments and the drawings, and various substitutions, modifications, and changes can be made to the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, it is intended that all changes or modifications derived from the meaning, scope, and equivalent concepts of the claims fall within the scope of the present disclosure.

[0350] The above various embodiments may be combined to provide further embodiments. If necessary, aspects of the embodiments may be modified to adopt the concepts of the various embodiments to provide further embodiments.

[0351] In view of the foregoing detailed description, these and other changes may be made to the embodiments. In general, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which these claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims

1. A thin film transistor structure, comprising: A first thin film transistor and a second thin film transistor on a substrate; Wherein, the first thin film transistor comprises: A first active layer disposed on the substrate; and A first gate electrode spaced apart from the first active layer and overlapping at least a portion of the first active layer; The second thin film transistor comprises: A second active layer disposed on the substrate; and A second gate electrode spaced apart from the second active layer and overlapping at least a portion of the second active layer; The first active layer comprises: A first oxide semiconductor layer; and A second oxide semiconductor layer disposed on the first oxide semiconductor layer; The second active layer comprises: A first oxide semiconductor layer; A second oxide semiconductor layer disposed on the first oxide semiconductor layer; A third oxide semiconductor layer disposed on the second oxide semiconductor layer; The first oxide semiconductor layer of the first active layer has an amorphous structure, The second oxide semiconductor layer of the first active layer has a crystalline structure, The first oxide semiconductor layer and the third oxide semiconductor layer of the second active layer have an amorphous structure, and The second oxide semiconductor layer of the second active layer has a crystalline structure.

2. The thin film transistor structure according to claim 1, wherein, The first oxide semiconductor layer of the first active layer is made of the same material as the first oxide semiconductor layer of the second active layer.

3. The thin film transistor structure according to claim 1, wherein, The second oxide semiconductor layer of the first active layer is made of the same material as the second oxide semiconductor layer of the second active layer and has the same crystalline structure.

4. The thin film transistor structure according to claim 1, wherein, The first oxide semiconductor layer of the first active layer, the first oxide semiconductor layer of the second active layer, and the third oxide semiconductor layer of the second active layer each comprise at least one of the following oxide semiconductor materials: IZO (InZnO)-based oxide semiconductor material, IGZO (InGaZnO)-based oxide semiconductor material, IGZTO (InGaZnSnO)-based oxide semiconductor material, GZTO (GaZnSnO)-based oxide semiconductor material, or GZO (GaZnSnO)-based oxide semiconductor material, and The second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer each include at least one of the following oxide semiconductor materials: IZO (InZnO)-based oxide semiconductor materials, wherein the concentration of In is 50% or more compared to the total concentration of In and Zn based on the number of atoms; IGO (InGaO)-based oxide semiconductor materials, wherein the concentration of In is 70% or more compared to the total concentration of In and Ga based on the number of atoms; IGZO (InGaZnO)-based oxide semiconductor materials, wherein the concentration of In is 50% or more compared to the total concentration of In, Ga, and Zn based on the number of atoms; ITO (InSnO)-based oxide semiconductor materials, wherein the concentration of In is 80% or more compared to the total concentration of In and Sn based on the number of atoms; IGZTO (InGaZnSnO)-based oxide semiconductor materials, wherein the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Ga, Zn, and Sn based on the number of atoms; or ITZO (InSnZnO)-based oxide semiconductor materials, wherein the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Sn, and Zn based on the number of atoms.

5. The thin film transistor structure according to claim 4, wherein, each of the second oxide semiconductor layers of the first active layer and the second active layer further includes a dopant in the oxide semiconductor material, and the dopant includes at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), or germanium (Ge).

6. The thin film transistor structure according to claim 5, wherein, the concentration of the dopant included in the second oxide semiconductor layer of the first active layer is in the range of greater than or equal to 0.1 atomic % and less than or equal to 10 atomic % based on the total number of atoms of the second oxide semiconductor layer of the first active layer, and the concentration of the dopant included in the second oxide semiconductor layer of the second active layer is in the range of greater than or equal to 0.1 atomic % and less than or equal to 10 atomic % based on the total number of atoms of the second oxide semiconductor layer of the second active layer.

7. The thin film transistor structure according to claim 1, wherein, the thicknesses of the first oxide semiconductor layers of the first active layer and the second active layer are each in the range of greater than or equal to 1 nm and less than or equal to 10 nm, the thicknesses of the second oxide semiconductor layers of the first active layer and the second active layer are each in the range of greater than or equal to 10 nm and less than or equal to 50 nm, and the thickness of the third oxide semiconductor layer of the second active layer is in the range of greater than or equal to 1 nm and less than or equal to 20 nm.

8. The thin film transistor structure according to claim 1, wherein, The second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer have at least one of a (400) crystal plane, a (222) crystal plane, a (220) crystal plane, a (311) crystal plane, or a (0016) crystal plane.

9. The thin film transistor structure according to claim 1, wherein, The second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer both have at least one of a cubic crystal structure, a brownmillerite crystal structure, a spinel crystal structure, or a hexagonal crystal structure.

10. The thin film transistor structure according to claim 1, wherein The second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer both include grains having a particle size in the range of greater than or equal to 3 nm and less than or equal to 500 nm.

11. The thin-film transistor structure according to claim 1, wherein, The first active layer includes: A third oxide semiconductor layer disposed between the first oxide semiconductor layer and the second oxide semiconductor layer of the first active layer and having a crystalline structure; and A fourth oxide semiconductor layer disposed on the second oxide semiconductor layer of the first active layer and having a crystalline structure; and The second active layer includes: A fourth oxide semiconductor layer disposed between the first oxide semiconductor layer and the second oxide semiconductor layer of the second active layer and having a crystalline structure; and A fifth oxide semiconductor layer disposed between the second oxide semiconductor layer and the third oxide semiconductor layer of the second active layer and having a crystalline structure.

12. The thin-film transistor structure according to claim 11, wherein, The third oxide semiconductor layer of the first active layer is made of the same material as the first oxide semiconductor layer of the first active layer, The fourth oxide semiconductor layer of the second active layer is made of the same material as the first oxide semiconductor layer of the second active layer, and The fifth oxide semiconductor layer of the second active layer is made of the same material as the third oxide semiconductor layer of the second active layer.

13. The thin film transistor structure according to claim 11, wherein, The thickness of each of the third oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the second active layer, and the fifth oxide semiconductor layer of the second active layer is in the range of greater than or equal to 0.1 nm and less than or equal to 3 nm.

14. The thin film transistor structure according to claim 11, wherein, The third oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the second active layer, and the fifth oxide semiconductor layer of the second active layer all have a (009) crystal plane and a CAAC crystal structure.

15. The thin film transistor structure according to claim 11, wherein, The third oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the first active layer, the fourth oxide semiconductor layer of the second active layer, and the fifth oxide semiconductor layer of the second active layer all include grains having a particle size in the range of greater than or equal to 1 nm and less than or equal to 10 nm.

16. The thin film transistor structure according to claim 1, wherein, the s factor of the second thin film transistor is greater than the s factor of the first thin film transistor, and the carrier mobility of the first thin film transistor is greater than the carrier mobility of the second thin film transistor.

17. A method for manufacturing a thin film transistor structure, comprising: preparing a substrate placed in a first region and a second region; forming a first active layer in the first region on the substrate, and forming a second active layer in the second region on the substrate; forming a first gate electrode and a second gate electrode that respectively at least partially overlap with the first active layer and the second active layer; forming the first active layer and the second active layer includes: sequentially stacking a first oxide semiconductor material layer, a second oxide semiconductor material layer, and a third oxide semiconductor material layer on the substrate; patterning the first oxide semiconductor material layer, the second oxide semiconductor material layer, and the third oxide semiconductor material layer to respectively form a first active pattern and a second active pattern each including a first oxide semiconductor pattern layer, a second oxide semiconductor pattern layer, and a third oxide semiconductor pattern layer; heat-treating the first active pattern and the second active pattern; and wet-etching the third oxide semiconductor pattern layer of the first active pattern using a photoresist material layer, wherein the photoresist material layer overlaps with the second active pattern provided in the second region and does not overlap with the first active pattern provided in the first region.

18. The method for manufacturing a thin film transistor structure according to claim 17, wherein, the first oxide semiconductor material layer, the second oxide semiconductor material layer, and the third oxide semiconductor material layer are formed by sputtering deposition, when forming the second oxide semiconductor material layer, the sputtering deposition is performed at a temperature in the range of greater than or equal to 100 °C and less than or equal to 300 °C, and when forming the first oxide semiconductor material layer and the third oxide semiconductor material layer, the sputtering deposition is performed at a temperature in the range of greater than or equal to 15 °C and less than or equal to 100 °C.

19. The manufacturing method of the thin film transistor structure according to claim 17, wherein, The heat treatment of the first active pattern and the second active pattern is performed at a temperature in the range of greater than or equal to 350 °C and less than or equal to 450 °C.

20. A display device, comprising the thin film transistor structure according to any one of claims 1 to 16.

21. The display device according to claim 20, further comprising a gate driver and a pixel driving circuit on the substrate, the first thin film transistor is included in the gate driver or is a switching transistor of the pixel driving circuit, and the second thin film transistor is a driving transistor of the pixel driving circuit.

22. A thin film transistor, comprising: an active layer; and a gate electrode that is spaced apart from the active layer and overlaps at least a part of the active layer; wherein the active layer includes: a first oxide semiconductor layer; A second oxide semiconductor layer disposed on the first oxide semiconductor layer; and A third oxide semiconductor layer disposed on the second oxide semiconductor layer; and the first oxide semiconductor layer and the third oxide semiconductor layer have an amorphous structure, and the second oxide semiconductor layer has a crystalline structure.

23. The thin film transistor according to claim 22, wherein Both the first oxide semiconductor layer and the third oxide semiconductor layer include at least one of the following oxide semiconductor materials: IZO (InZnO)-based oxide semiconductor material, IGZO (InGaZnO)-based oxide semiconductor material, IGZTO (InGaZnSnO)-based oxide semiconductor material, GZTO (GaZnSnO)-based oxide semiconductor material, or GZO (GaZnO)-based oxide semiconductor material, and The second oxide semiconductor layer includes at least one of the following oxide semiconductor materials: IZO (InZnO)-based oxide semiconductor material, wherein the concentration of In is 50% or more compared to the total concentration of In and Zn based on the number of atoms; IGO (InGaO)-based oxide semiconductor material, wherein the concentration of In is 70% or more compared to the total concentration of In and Ga based on the number of atoms; IGZO (InGaZnO)-based oxide semiconductor material, wherein the concentration of In is 50% or more compared to the total concentration of In, Ga, and Zn based on the number of atoms; ITO (InSnO)-based oxide semiconductor material, wherein the concentration of In is 80% or more compared to the total concentration of In and Sn based on the number of atoms; IGZTO (InGaZnSnO)-based oxide semiconductor material, wherein the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Ga, Zn, and Sn based on the number of atoms; and ITZO (InSnZnO)-based oxide semiconductor material, wherein the sum of the concentrations of In and Sn is 45% or more compared to the total concentration of In, Sn, and Zn based on the number of atoms.

24. The thin film transistor according to claim 23, wherein The second oxide semiconductor layer further includes a dopant in the oxide semiconductor material, and The dopant includes at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), or germanium (Ge).

25. The thin film transistor according to claim 24, wherein, The concentration of the dopant included in the second oxide semiconductor layer is in the range of greater than or equal to 0.1 atomic % and less than or equal to 10 atomic % based on the total number of atoms of the second oxide semiconductor layer.

26. The thin film transistor according to claim 22, wherein The thickness of the first oxide semiconductor layer is in the range of greater than or equal to 1 nm and less than or equal to 10 nm, The thickness of the second oxide semiconductor layer is in the range of greater than or equal to 10 nm and less than or equal to 50 nm, and the thickness of the third oxide semiconductor layer is in the range of greater than or equal to 1 nm and less than or equal to 20 nm.

27. The thin film transistor according to claim 22, wherein, The second oxide semiconductor layer has at least one of a (400) plane, a (222) plane, a (220) plane, a (311) plane, or a (0016) plane.

28. The thin film transistor according to claim 22, wherein, The second oxide semiconductor layer has at least one of a cubic crystal structure, a hercynite crystal structure, a spinel crystal structure, or a hexagonal crystal structure.

29. The thin film transistor according to claim 22, wherein, The second oxide semiconductor layer includes grains having a particle size in the range of greater than or equal to 3 nm and less than or equal to 500 nm.

30. The thin film transistor according to claim 22, wherein, The active layer further includes: a fourth oxide semiconductor layer disposed between the first oxide semiconductor layer and the second oxide semiconductor layer and having a crystalline structure; and a fifth oxide semiconductor layer disposed between the second oxide semiconductor layer and the third oxide semiconductor layer and having a crystalline structure.

31. The thin film transistor according to claim 30, wherein, the fourth oxide semiconductor layer is made of the same material as the first oxide semiconductor layer, and the fifth oxide semiconductor layer is made of the same material as the third oxide semiconductor layer.

32. The thin film transistor according to claim 30, wherein, The thickness of each of the fourth oxide semiconductor layer and the fifth oxide semiconductor layer is in the range of greater than or equal to 0.1 nm and less than or equal to 3 nm.

33. The thin film transistor according to claim 30, wherein The fourth oxide semiconductor layer and the fifth oxide semiconductor layer have a (009) plane and a CAAC crystal structure.

34. The thin film transistor according to claim 30, wherein, Both the fourth oxide semiconductor layer and the fifth oxide semiconductor layer include grains having a particle size in the range of greater than or equal to 1 nm and less than or equal to 10 nm.

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