Light emitting element and display device including the same

Abstract

The invention relates to a light-emitting element and a display device. The light-emitting element includes: a first semiconductor layer; an active layer disposed under the first semiconductor layer; a second semiconductor layer disposed under the active layer; and a reflective layer, wherein the reflective layer includes a sub-reflective layer disposed under the second semiconductor layer and a barrier layer disposed under the sub-reflective layer and having a multilayer structure including a niobium-titanium (Nb-Ti) alloy and chromium (Cr).

Description

Technical Field

[0001] Embodiments generally provide a light-emitting element. More specifically, embodiments relate to a light-emitting element and a display device including the light-emitting element. Background Art

[0002] A light-emitting diode (“LED”) is an element that converts an electrical signal into a light form such as infrared rays and visible light through the characteristics of a compound semiconductor. Specifically, a light-emitting diode is a semiconductor element that, when a forward voltage is applied to a P-N junction diode, injects holes and electrons and converts the energy generated by the recombination of the holes and electrons into light energy. Summary of the Invention

[0003] Embodiments provide a light-emitting element having improved luminous efficiency.

[0004] Embodiments provide a display device including the light-emitting element.

[0005] The light-emitting element in the embodiments of the present disclosure includes: a first semiconductor layer; an active layer disposed under the first semiconductor layer; a second semiconductor layer disposed under the active layer; and a reflective layer, wherein the reflective layer includes: a sub-reflective layer disposed under the second semiconductor layer and a barrier layer disposed under the sub-reflective layer and having a multi-layer structure including a niobium-titanium (Nb-Ti) alloy and chromium (Cr).

[0006] In an embodiment, the barrier layer may include a first layer containing a Nb-Ti alloy, a second layer disposed under the first layer and including Cr, and a third layer disposed under the second layer and including a Nb-Ti alloy.

[0007] In an embodiment, each of the first layer and the third layer may include from about 50 atomic percent (at%) to about 60 at% of niobium (Nb) and from about 40 at% to about 50 at% of titanium (Ti).

[0008] In an embodiment, the thickness of each of the first layer and the third layer may range from about 100 nanometers (nm) to about 200 nm.

[0009] In an embodiment, the sub-reflective layer may include aluminum (Al).

[0010] In an embodiment, the thickness of the sub-reflective layer may range from about 200 nm to about 300 nm.

[0011] In an embodiment, the barrier layer may include a first layer containing a Nb-Ti alloy, a second layer disposed under the first layer and including chromium (Cr), and a third layer disposed under the second layer and including nickel (Ni).

[0012] In an embodiment, the first layer may include from about 50 at% to about 60 at% of Nb and from about 40 at% to about 50 at% of Ti.

[0013] In an embodiment, the reflective layer may further include a corrosion prevention layer disposed on the sub-reflective layer and including a metal, and a metal oxide layer disposed on the corrosion prevention layer.

[0014] In an embodiment, the light-emitting element may further include a connection layer disposed under the barrier layer and including an alloy.

[0015] In an embodiment, the corrosion prevention layer may include Cr, the metal oxide layer may include ITO, and the connection layer may include a tin-silver-copper (Sn-Ag-Cu) alloy.

[0016] The display device according to an embodiment of the present disclosure includes: a pixel electrode disposed on a substrate; a light-emitting element disposed on the pixel electrode; and a common electrode disposed on the light-emitting element. Among them, the light-emitting element extends in a direction perpendicular to the main plane extension direction of the substrate, and includes: a first semiconductor layer; an active layer disposed under the first semiconductor layer; a second semiconductor layer disposed under the active layer; and a reflective layer. Among them, the reflective layer includes: a sub-reflective layer disposed under the second semiconductor layer, and a barrier layer disposed under the sub-reflective layer and having a multi-layer structure including an Nb-Ti alloy and Cr.

[0017] In an embodiment, the barrier layer may include a first layer containing an Nb-Ti alloy, a second layer disposed under the first layer and including Cr, and a third layer disposed under the second layer and including an Nb-Ti alloy.

[0018] In an embodiment, each of the first layer and the third layer may include from about 50 at% to about 60 at% of Nb and from about 40 at% to about 50 at% of Ti.

[0019] In an embodiment, the thickness of each of the first layer and the third layer may be in a range from about 100 nm to about 200 nm.

[0020] In an embodiment, the sub-reflective layer may include Al.

[0021] In an embodiment, the thickness of the sub-reflective layer may be in a range from about 200 nm to about 300 nm.

[0022] In an embodiment, the barrier layer may include a first layer containing an Nb-Ti alloy, a second layer disposed under the first layer and including Cr, and a third layer disposed under the second layer and including Ni.

[0023] In an embodiment, the first layer may include from about 50 at% to about 60 at% of Nb and from about 40 at% to about 50 at% of Ti.

[0024] In an embodiment, the reflective layer may further include a corrosion prevention layer disposed on the sub-reflective layer and including a metal, and a metal oxide layer disposed on the corrosion prevention layer.

[0025] The light-emitting element in an embodiment of the present disclosure may include: a plurality of semiconductor layers; an active layer disposed between the plurality of semiconductor layers; and a reflective layer disposed under the active layer. Here, the reflective layer may include a sub-reflective layer containing Al and a barrier layer having a multi-layer structure including an Nb-Ti alloy and Cr. Therefore, when the light-emitting element is transferred onto a substrate by hot pressing at a relatively high temperature, the occurrence of void defects caused by the diffusion of Al in the sub-reflective layer can be suppressed, and an increase in the resistance of the sub-reflective layer can be minimized. In this case, the light-emitting efficiency of the light-emitting element can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Exemplary, non-limiting embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings.

[0027] Figure 1 is a schematic plan view showing a display device according to an embodiment of the present disclosure.

[0028] Figure 2 is along Figure 1 a schematic cross-sectional view of the display device taken along line I-I' of.

[0029] Figure 3 is Figure 2 an enlarged schematic cross-sectional view of region A of.

[0030] Figure 4 is Figure 3 an enlarged schematic cross-sectional view of region B of.

[0031] Figure 5 is Figure 1 an enlarged schematic plan view of a part of the display area of.

[0032] Figure 6 is a schematic diagram showing the surface resistance of the sub-reflective layer according to a comparative example and an embodiment. DETAILED DESCRIPTION

[0033] Hereinafter, a display device in an embodiment of the present disclosure will be explained in detail with reference to the drawings. In the drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0034] Reference will now be made to the accompanying drawings, which show various embodiments, and the disclosure will be described more fully hereinafter. However, the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Throughout the specification, like reference numerals refer to like elements.

[0035] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements.

[0036] It will be understood that although the terms “first,” “second,” “third,” etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a “first element,” “first component,” “first region,” “first layer” or “first section” discussed below may be referred to as a “second element,” “second component,” “second region,” “second layer” or “second section” without departing from the teachings herein.

[0037] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, including “at least one,” unless the context clearly indicates otherwise. “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprises” and / or “comprising,” or “includes” and / or “including” or “contains” and / or “containing” are used in this specification, they specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0038] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another as shown in the drawings. It will be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device in one of the drawings is flipped, an element described as on the "lower" side of other elements will then be oriented on the "upper" side of the other elements. Thus, depending on the specific orientation of the drawings, the exemplary term "lower" can encompass both the "lower" and "upper" orientations. Similarly, if the device in one of the drawings is flipped, an element described as "below" or "beneath" other elements will then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both the "above" and "below" orientations.

[0039] In view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms "about" or "approximate" as used herein include the stated value and mean within an acceptable deviation range of the particular value as determined by a person of ordinary skill in the art. For example, a term such as "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0040] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a common dictionary), should be interpreted as having a meaning consistent with their meaning in the relevant field and the context of this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0041] Figure 1 is a schematic plan view showing a display device DD according to an embodiment of the present disclosure.

[0042] Reference Figure 1 , the display device DD in the embodiments of the present disclosure may include a display area DA and a non-display area NDA. The display area DA may be an area capable of displaying an image by generating light or adjusting the transmittance of light provided from an external light source. The non-display area NDA may be an area that does not display an image. The non-display area NDA may be provided around the display area DA. For example, in an embodiment, the non-display area NDA may surround the entire display area DA.

[0043] The display area DA may include a plurality of pixel areas. The pixel areas may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, in an embodiment, the pixel areas may include a first pixel area PX1, a second pixel area PX2, and a third pixel area PX3.

[0044] Each of the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3 may refer to an area where light emitted from a light-emitting element is emitted to the outside of the display device DD. For example, in an embodiment, the first pixel area PX1 may emit first light, the second pixel area PX2 may emit second light, and the third pixel area PX3 may emit third light. In an embodiment, the first light may be red light, the second light may be green light, and the third light may be blue light. However, the present disclosure is not limited thereto. For example, in an embodiment, the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3 may be combined to emit yellow light, cyan light, and magenta light.

[0045] The first pixel area PX1, the second pixel area PX2, and the third pixel area PX3 may emit light of four or more colors. For example, in an embodiment, the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3 may be combined to emit at least one of yellow light, cyan light, and magenta light in addition to red light, green light, and blue light. In addition, the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3 may be combined to emit more white light.

[0046] Each of the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3 may have a triangular planar shape, a square planar shape, a circular planar shape, an elliptical planar shape, etc. in a plan view. In an embodiment, each of the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3 may have a quadrilateral shape, for example, a rectangular planar shape, in a plan view. However, the embodiments of the present disclosure are not limited, and each of the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3 may have a different planar shape in a plan view.

[0047] The non-display area NDA may include a pad area PDA. The pad area PDA may be provided on a side away from the display area DA. For example, in an embodiment, the pad area PDA may have a shape extending in the first direction DR1.

[0048] Multiple lines can be disposed in the non-display area NDA, and multiple pad electrodes PDE can be disposed in the pad area PDA. The lines can electrically connect the pad electrodes PDE and the pixel area. For example, in an embodiment, the lines can include data signal lines, scan signal lines, light emission control signal lines, power voltage lines, etc.

[0049] The pad electrodes PDE can be spaced apart from each other in the first direction DR1. For example, in an embodiment, each of the pad electrodes PDE can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in any combination with each other.

[0050] In this specification, a plane can be defined by a first direction DR1 and a second direction DR2 that intersects the first direction DR1. For example, in an embodiment, the first direction DR1 can be perpendicular to the second direction DR2. Further, a third direction DR3 can be perpendicular to the plane.

[0051] Figure 2 is a schematic cross-sectional view of the display device DD taken along the line I-I' Figure 1 of.

[0052] Referring to Figure 2 , the display device DD in an embodiment of the present disclosure can include a substrate SUB, a buffer layer BUF, a first transistor TR1, a second transistor TR2, and a third transistor TR3, a first insulating layer IL1, a second insulating layer IL2, and a third insulating layer IL3, a first pixel electrode PE1, a second pixel electrode PE2, and a third pixel electrode PE3, a first light-emitting element LED1, a second light-emitting element LED2, and a third light-emitting element LED3, a planarization layer PL, and a common electrode CME.

[0053] Here, the first transistor TR1 can include a first active pattern ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1, the second transistor TR2 can include a second active pattern ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2, and the third transistor TR3 can include a third active pattern ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.

[0054] The substrate SUB may include a transparent material or an opaque material. The substrate SUB may include a transparent resin substrate or be composed of a transparent resin substrate. In an embodiment, the transparent resin substrate may include a polyimide substrate. In this case, the polyimide substrate may include a first organic layer, a first buffer layer, a second organic layer, etc. In an alternative embodiment, the substrate SUB may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda lime glass substrate, a non-alkali glass substrate, etc. These may be used alone or in any combination with each other.

[0055] The buffer layer BUF may be disposed on the substrate SUB. The buffer layer BUF may prevent metal atoms or impurities from diffusing from the substrate SUB to the first transistor TR1, the second transistor TR2, and the third transistor TR3. In addition, when the surface of the substrate SUB is uneven, the buffer layer BUF may improve the flatness of the surface of the substrate SUB. For example, in an embodiment, the buffer layer BUF may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in any combination with each other.

[0056] The first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 may be disposed on the buffer layer BUF. Each of the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 may include a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon, polycrystalline silicon, etc.), or an organic semiconductor. Each of the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 may include a source region, a drain region, and a channel region disposed between the source region and the drain region. The first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 may be formed by the same process and may include the same materials as each other.

[0057] The metal oxide semiconductor may include a binary compound (AB x ), a ternary compound (AB x C y ), a quaternary compound (AB x C y D z ), etc., containing or composed of indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. For example, in an embodiment, the metal oxide semiconductor may include zinc oxide (ZnO x ), gallium oxide (GaO x ), tin oxide (SnOx ), indium oxide (InO x ), indium gallium oxide ("IGO"), indium zinc oxide ("IZO"), indium tin oxide ("ITO"), indium zinc tin oxide ("IZTO"), indium gallium zinc oxide ("IGZO"), etc. These can be used alone or in any combination with each other.

[0058] The first insulating layer IL1 can be disposed on the buffer layer BUF. The first insulating layer IL1 can sufficiently cover the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3, and can have a substantially flat upper surface without creating steps around the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3. In an alternative embodiment, the first insulating layer IL1 can cover the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3, and can be provided with a thickness measured in a thickness direction (e.g., the third direction DR3) extending perpendicular to the main plane extension direction of the substrate SUB (e.g., the first direction DR1 and the second direction DR2 defining the main plane), and this thickness can be constant along the contour of each of the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 in the main plane extension direction. For example, in an embodiment, the first insulating layer IL1 can include inorganic materials such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon carbide (SiC x ), silicon oxynitride (SiO x N y ), silicon oxycarbide (SiO x C y ), etc. These can be used alone or in any combination with each other.

[0059] The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 can be disposed on the first insulating layer IL1. The first gate electrode GE1 can overlap with the channel region of the first active pattern ACT1, the second gate electrode GE2 can overlap with the channel region of the second active pattern ACT2, and the third gate electrode GE3 can overlap with the channel region of the third active pattern ACT3.

[0060] Each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. In an embodiment, the metal may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), etc. In an embodiment, the conductive metal oxide may include ITO, IZO, etc. In addition, embodiments of the metal nitride include aluminum nitride (AlN x ), tungsten nitride (WN x ), chromium nitride (CrN x ), etc. These may be used alone or in any combination with each other.

[0061] The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may be formed by the same process and may include the same materials as each other.

[0062] The second insulating layer IL2 may be disposed on the first insulating layer IL1. The second insulating layer IL2 may sufficiently cover the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 and may have a substantially flat upper surface without creating steps around the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3. In an alternative embodiment, the second insulating layer IL2 may cover the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 and may be disposed with a uniform thickness along the contour of each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3. For example, in an embodiment, the second insulating layer IL2 may include inorganic materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, etc. These may be used alone or in any combination with each other.

[0063] The first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 may be disposed on the second insulating layer IL2. The first source electrode SE1 may be connected to the source region of the first active pattern ACT1 through a contact hole penetrating the first insulating layer IL1 and the second insulating layer IL2. The second source electrode SE2 may be connected to the source region of the second active pattern ACT2 through a contact hole penetrating the first insulating layer IL1 and the second insulating layer IL2. The third source electrode SE3 may be connected to the source region of the third active pattern ACT3 through a contact hole penetrating the first insulating layer IL1 and the second insulating layer IL2.

[0064] The first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3 may be disposed on the second insulating layer IL2. The first drain electrode DE1 may be connected to the drain region of the first active pattern ACT1 through a contact hole penetrating through the first insulating layer IL1 and the second insulating layer IL2. The second drain electrode DE2 may be connected to the drain region of the second active pattern ACT2 through a contact hole penetrating through the first insulating layer IL1 and the second insulating layer IL2. The third drain electrode DE3 may be connected to the drain region of the third active pattern ACT3 through a contact hole penetrating through the first insulating layer IL1 and the second insulating layer IL2.

[0065] For example, in an embodiment, each of the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in any combination with each other. The first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3 are formed by the same process as the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3, and may include the same materials as those of the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3.

[0066] The third insulating layer IL3 may be disposed on the second insulating layer IL2. The third insulating layer IL3 may sufficiently cover the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3, and the first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3. The third insulating layer IL3 may include an organic material. For example, in an embodiment, the third insulating layer IL3 may include a phenolic resin, a polyacrylate resin, a polyimide resin, a polyamide resin, a silicone resin, an epoxy resin, etc. These may be used alone or in any combination with each other.

[0067] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be disposed on the third insulating layer IL3. In an embodiment, the third insulating layer IL3 may be a via-insulating layer, but the present disclosure is not limited thereto. The first pixel electrode PE1 may overlap with the first pixel region PX1, the second pixel electrode PE2 may overlap with the second pixel region PX2, and the third pixel electrode PE3 may overlap with the third pixel region PX3. The first pixel electrode PE1 may be connected to the first drain electrode DE1 (or the first source electrode SE1) through a contact hole penetrating through the third insulating layer IL3, and the second pixel electrode PE2 may be connected to the second drain electrode DE2 (or the second source electrode SE2) through a contact hole penetrating through the third insulating layer IL3. In addition, the third pixel electrode PE3 may be connected to the third drain electrode DE3 (or the third source electrode SE3) through a contact hole penetrating through the third insulating layer IL3.

[0068] For example, in an embodiment, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in any combination with each other.

[0069] Since the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are used to be respectively coupled to the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3 which will be described later, in order to reduce the contact resistance between each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 and the first light-emitting element LED1, the second light-emitting element LED2, or the third light-emitting element LED3, it is desirable to reduce the sheet resistance of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. In an embodiment, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a bilayer structure including titanium (Ti) / copper (Cu). However, the present disclosure is not limited thereto.

[0070] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be formed by the same process and may include the same materials as each other. For example, in an embodiment, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may operate as an anode or a cathode.

[0071] The first light-emitting element LED1 may be disposed on the first pixel electrode PE1, the second light-emitting element LED2 may be disposed on the second pixel electrode PE2, and the third light-emitting element LED3 may be disposed on the third pixel electrode PE3. The first light-emitting element LED1 may overlap with the first pixel region PX1, the second light-emitting element LED2 may overlap with the second pixel region PX2, and the third light-emitting element LED3 may overlap with the third pixel region PX3. In an embodiment, the first light-emitting element LED1 may be vertically disposed on the first pixel electrode PE1, the second light-emitting element LED2 may be vertically disposed on the second pixel electrode PE2, and the third light-emitting element LED3 may be vertically disposed on the third pixel electrode PE3. That is, the first light-emitting element LED1 may be disposed on the first pixel electrode PE1 and extend in a direction (e.g., the third direction DR3) perpendicular to the extending direction of the main plane of the substrate SUB (e.g., the first direction DR1 and the second direction DR2 defining the main plane), the second light-emitting element LED2 may be disposed on the second pixel electrode PE2 and extend in a direction (e.g., the third direction DR3) perpendicular to the extending direction of the main plane of the substrate SUB (e.g., the first direction DR1 and the second direction DR2 defining the main plane), and the third light-emitting element LED3 may be disposed on the third pixel electrode PE3 and extend in a direction (e.g., the third direction DR3) perpendicular to the extending direction of the main plane of the substrate SUB (e.g., the first direction DR1 and the second direction DR2 defining the main plane). However, the present disclosure is not limited thereto.

[0072] For example, in an embodiment, the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3 may be picked up individually or in plurality by a transfer mechanism on a wafer and transferred onto the substrate SUB, so as to be respectively bonded to the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. In this case, a thermal compression method at a relatively high temperature (e.g., about 250 degrees Celsius (°C) to about 310 °C) may be used to transfer the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3 onto the substrate SUB.

[0073] The first light-emitting element LED1 may generate first light, the second light-emitting element LED2 may generate second light, and the third light-emitting element LED3 may generate third light. For example, in an embodiment, the first light may be red light, the second light may be green light, and the third light may be blue light. However, the present disclosure is not limited thereto.

[0074] In an embodiment, each of the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3 may be a micro light-emitting diode. The stacked structure of each of the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3 will be described later.

[0075] A planarization layer PL may be provided on the third insulating layer IL3. The planarization layer PL may be provided to surround the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3. The planarization layer PL may be a layer for planarizing the steps caused by the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3. For example, in an embodiment, the upper surface of the planarization layer PL may be provided at the same horizontal plane as the upper surface of each of the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3. However, the present disclosure is not limited thereto.

[0076] The planarization layer PL may include an organic material. For example, in an embodiment, the planarization layer PL may include an organic material such as phenolic resin, acrylic resin, polyimide resin, polyamide resin, silicone resin, epoxy resin, etc. These may be used alone or in any combination with each other.

[0077] A common electrode CME may be provided on the planarization layer PL. The common electrode CME may be provided on the entire surface of the display area DA. That is, the common electrode CME may be an electrode commonly provided in the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3. For example, in an embodiment, the common electrode CME may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in any combination with each other. The common electrode CME may act as a cathode or an anode.

[0078] Figure 3 is Figure 2 An enlarged schematic cross-sectional view of region A of Figure 4 is Figure 3 An enlarged schematic cross-sectional view of region B of Figure 3 is Figure 2 An enlarged schematic cross-sectional view of the first light-emitting element LED1 of Figure 4 is Figure 3 An enlarged schematic cross-sectional view of the reflective layer RL of

[0079] Refer to Figure 3, the first light-emitting element LED1 may include a first semiconductor layer SL1, a second semiconductor layer SL2, an active layer MQW, a third semiconductor layer SL3, a reflective layer RL, and a connection layer CL that are sequentially disposed between the common electrode CME and the first pixel electrode PE1 along a direction opposite to the third direction DR3.

[0080] The first semiconductor layer SL1 may be in contact with the common electrode CME. For example, in an embodiment, the first semiconductor layer SL1 may include an undoped semiconductor. The first semiconductor layer SL1 may include the same material as the second semiconductor layer SL2, but may include a material without doping an n-type dopant or a p-type dopant. For example, in an embodiment, the first semiconductor layer SL1 may include undoped InAlGaN, GaN, AlGaN, InGaN, AlN, InN, etc. These may be used alone or in any combination with each other. However, the present disclosure is not limited thereto.

[0081] The second semiconductor layer SL2 may be disposed under the first semiconductor layer SL1. The second semiconductor layer SL2 may include an n-type semiconductor. For example, in an embodiment, the second semiconductor layer SL2 may include AlGaInN, GaN, AlGaN, InGaN, AlN, InN, etc. doped with an n-type dopant. These may be used alone or in any combination with each other. The second semiconductor layer SL2 may be doped with an n-type dopant, and the n-type dopant may include Si, Ge, Sn, Se, etc. For example, in an embodiment, the second semiconductor layer SL2 may include n-GaN doped with n-type Si.

[0082] The active layer MQW may be disposed under the second semiconductor layer SL2. According to the electrical signals applied through the second semiconductor layer SL2 and the third semiconductor layer SL3, the active layer MQW may generate light (e.g., red light, green light, or blue light) through the combination of electron-hole pairs.

[0083] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. In an embodiment, when the active layer MQW includes a material having a multi-quantum well structure, the active layer MQW may have a structure in which a barrier layer and a plurality of well layers are alternately stacked. In this case, for example, the well layer may include InGaN, and the barrier layer may include GaN or AlGaN. However, the present disclosure is not limited thereto.

[0084] In an alternative embodiment, the active layer MQW may have a structure in which semiconductor materials with relatively large bandgap energies and semiconductor materials with relatively small bandgap energies are alternately stacked, and may include different group III-V semiconductor materials based on the wavelength of the emitted light. For example, in an embodiment, when the semiconductor material included in the active layer MQW includes indium (In), the color of the emitted light may vary based on the proportion of indium (In). When the proportion of indium (In) decreases, the wavelength band of the emitted light may shift towards the red wavelength band, and when the proportion of indium (In) increases, the wavelength band of the emitted light may shift towards the blue wavelength band.

[0085] A superlattice layer may be provided between the active layer MQW and the second semiconductor layer SL2. The superlattice layer may be a layer for eliminating stress between the active layer MQW and the second semiconductor layer SL2. For example, in an embodiment, the superlattice layer may include InGaN or GaN. The superlattice layer may be omitted.

[0086] A third semiconductor layer SL3 may be provided under the active layer MQW. The third semiconductor layer SL3 may include a p-type semiconductor. For example, in an embodiment, the third semiconductor layer SL3 may include p-doped AlGaInN, GaN, AlGaN, InGaN, AlN, InN, etc. These may be used alone or in any combination with each other. The third semiconductor layer SL3 may be doped with a p-type dopant, and the p-type dopant may include Mg, Zn, Ca, Ba, etc. For example, in an embodiment, the third semiconductor layer SL3 may include p-GaN doped with p-type Mg.

[0087] An electron blocking layer may be provided between the active layer MQW and the third semiconductor layer SL3. The electron blocking layer may be a layer that inhibits or prevents excessive electrons from flowing into the active layer MQW. For example, in an embodiment, the electron blocking layer may include p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0088] A reflective layer RL may be provided under the third semiconductor layer SL3. The reflective layer RL may be used to reflect the light emitted from the active layer MQW of the first light-emitting element LED1. The reflective layer RL may include a metallic material that is conductive and has a relatively high light reflectivity.

[0089] Further referring to Figure 4 , the reflective layer RL may include a metal oxide layer MOL, an anti-corrosion layer ACL, a sub-reflective layer SRL, and a barrier layer BAR that are sequentially provided between the third semiconductor layer SL3 and the connection layer CL along a direction opposite to the third direction DR3.

[0090] The metal oxide layer MOL may be disposed under the third semiconductor layer SL3. For example, in an embodiment, the metal oxide layer MOL may include ITO. However, the present disclosure is not limited thereto.

[0091] The anti-corrosion layer ACL may be disposed under the metal oxide layer MOL. The anti-corrosion layer ACL may prevent corrosion of the metal oxide layer MOL and the sub-reflection layer SRL. For example, in an embodiment, the anti-corrosion layer ACL may include chromium (Cr). However, the present disclosure is not limited thereto.

[0092] The sub-reflection layer SRL may be disposed under the anti-corrosion layer ACL. The sub-reflection layer SRL may include a metallic material that is conductive and has a relatively high light reflectivity. For example, in an embodiment, the sub-reflection layer SRL may include aluminum (Al). However, the present disclosure is not limited thereto.

[0093] The thickness TH1 of the sub-reflection layer SRL may be in the range from about 200 nanometers (nm) to about 300 nm. When the thickness TH1 of the sub-reflection layer SRL is less than 200 nm, when the first light-emitting element LED1 is transferred to a substrate (e.g., Figure 2 substrate SUB) by hot pressing at a relatively high temperature (e.g., about 250 °C to about 310 °C), the increase in the resistance of the sub-reflection layer SRL may be relatively large.

[0094] The barrier layer BAR may be disposed under the sub-reflection layer SRL. The barrier layer BAR may block or prevent the diffusion of the material of the sub-reflection layer SRL. In an embodiment, the barrier layer BAR may have a multi-layer structure including a niobium (Nb)-titanium (Ti) alloy and chromium (Cr). Since the barrier layer BAR includes the Nb-Ti alloy, when the first light-emitting element LED1 is transferred to a substrate (e.g., Figure 2 substrate SUB) by hot pressing at a relatively high temperature (e.g., about 250 °C to about 310 °C), the occurrence of void defects caused by the diffusion of Al in the sub-reflection layer SRL can be suppressed.

[0095] In an embodiment, the barrier layer BAR may include a first layer L1 containing the Nb-Ti alloy, a second layer L2 disposed under the first layer L1 and including Cr, and a third layer L3 disposed under the second layer L2 and including the Nb-Ti alloy.

[0096] In another embodiment, the barrier layer BAR may include a first layer L1 containing an Nb-Ti alloy, a second layer L2 disposed under the first layer L1 and including chromium (Cr), and a third layer L3 disposed under the second layer L2 and including Ni. In another embodiment, the barrier layer BAR may include a first layer L1 containing Ni, a second layer L2 disposed under the first layer L1 and including Cr, and a third layer L3 disposed under the second layer L2 and including an Nb-Ti alloy.

[0097] The thicknesses TH2 and TH3 of each of the first layer L1 and the third layer L3 may be different from the thickness TH1 of the sub-reflection layer SRL. In an embodiment, the thickness TH2 of the first layer L1 may be in the range from about 100 nm to about 200 nm, and the thickness TH3 of the third layer L3 may be in the range from about 100 nm to about 200 nm. When the thicknesses TH2 and TH3 of the first layer L1 and the third layer L3 are less than 100 nm, Al diffusion in the sub-reflection layer SRL may not be suppressed during the hot pressing process at a relatively high temperature.

[0098] In an embodiment, each of the first layer L1 and the third layer L3 may include about 50 atomic percent (at%) to about 60 at% of Nb and about 40 at% to about 50 at% of Ti. When Nb and Ti in each of the first layer L1 and the third layer L3 are outside the above ranges, Al diffusion in the sub-reflection layer SRL may not be suppressed during the hot pressing process at a relatively high temperature.

[0099] The connection layer CL may be disposed under the reflection layer RL. Specifically, the connection layer CL may be disposed under the barrier layer BAR included in the reflection layer RL. The first light-emitting element LED1 and the first pixel electrode PE1 may be bonded through the connection layer CL. The connection layer CL may be used to transmit a light-emitting signal from the first pixel electrode PE1 to the first light-emitting element LED1. The connection layer CL may be an ohmic connection electrode. In an alternative embodiment, the connection layer CL may be a Schottky connection electrode.

[0100] The connection layer CL may be disposed at the bottom of the first light-emitting element LED1 and may be disposed farther from the active layer MQW than the reflection layer RL. For example, in an embodiment, the connection layer CL may include Au, Cu, Sn, Ag, Al, Ti, etc. These may be used alone or in any combination with each other. In an embodiment, the connection layer CL may include a tin-silver-copper (Sn-Ag-Cu) alloy. However, the present disclosure is not limited thereto.

[0101] Figure 5 is Figure 1 An enlarged schematic plan view of a part of the display area DA.

[0102] Reference Figure 5 The first light-emitting element LED1 can be disposed on the first pixel electrode PE1 provided in the first pixel region PX1, the second light-emitting element LED2 can be disposed on the second pixel electrode PE2 provided in the second pixel region PX2, and the third light-emitting element LED3 can be disposed on the third pixel electrode PE3 provided in the third pixel region PX3.

[0103] For example, in an embodiment, a plurality of first light-emitting elements LED1 can be arranged on one first pixel electrode PE1, and a plurality of first light-emitting elements LED1 can be arranged in a matrix form along a first direction DR1 and a second direction DR2 on one first pixel electrode PE1.

[0104] For example, in an embodiment, a plurality of second light-emitting elements LED2 can be arranged on one second pixel electrode PE2, and a plurality of second light-emitting elements LED2 can be arranged in a matrix form along a first direction DR1 and a second direction DR2 on one second pixel electrode PE2.

[0105] For example, in an embodiment, a plurality of third light-emitting elements LED3 can be arranged on one third pixel electrode PE3, and a plurality of third light-emitting elements LED3 can be arranged in a matrix form along a first direction DR1 and a second direction DR2 on one third pixel electrode PE3.

[0106] Return to reference Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 and Figure 5 The light-emitting elements (e.g., the first light-emitting element LED1, the second light-emitting element LED2, or the third light-emitting element LED3) in the embodiments of the present disclosure may include a plurality of semiconductor layers (e.g., the first semiconductor layer SL1, the second semiconductor layer SL2, and the third semiconductor layer SL3), an active layer MQW disposed between the plurality of semiconductor layers (e.g., the first semiconductor layer SL1, the second semiconductor layer SL2, and the third semiconductor layer SL3), and a reflective layer RL disposed under the active layer MQW. Here, the reflective layer RL may include a sub-reflective layer SRL containing Al and a barrier layer BAR having a multi-layer structure including Nb-Ti alloy and Cr. Therefore, when the light-emitting element is transferred to the substrate SUB by thermocompression at a relatively high temperature, the occurrence of vacancy defects caused by the diffusion of Al in the sub-reflective layer SRL can be suppressed, and an increase in the resistance of the sub-reflective layer SRL can be minimized. In this case, the luminous efficiency of the light-emitting element can be improved.

[0107] Hereinafter, the effects of the present disclosure according to the comparative examples and embodiments will be described.

[0108] Figure 6 It is a diagram showing the surface resistance of the sub-reflection layer SRL according to the comparative example and the embodiment.

[0109] According to the comparative example and the embodiment, a first metal layer is formed of Al on a glass substrate, and a second metal layer is formed of an Nb-Ti alloy on the first metal layer. Here, the second metal layer includes about 60 at% of Nb and about 40 at% of Ti.

[0110] In Comparative Example 1, the first metal layer is formed to have a thickness of about 1500 angstroms (Å), and the second metal layer is formed to have a thickness of about 1000 Å.

[0111] In Embodiment 1, the first metal layer is formed to have a thickness of about 2000 Å, and the second metal layer is formed to have a thickness of about 1000 Å.

[0112] In Embodiment 2, the first metal layer is formed to have a thickness of about 2500 Å, and the second metal layer is formed to have a thickness of about 1000 Å.

[0113] In Embodiment 3, the first metal layer is formed to have a thickness of about 3000 Å, and the second metal layer is formed to have a thickness of about 1000 Å.

[0114] According to the comparative example and the embodiment, heat treatment at about 450 °C for about one hour is performed on the first metal layer and the second metal layer formed on the glass substrate.

[0115] As a result, it can be confirmed that a diffusion layer is formed at the interface between the first metal layer and the second metal layer. The thickness of the diffusion layer according to the comparative example and the embodiment is shown in Table 1 below.

[0116]

[0117] Furthermore, it can be confirmed that the increase in the surface resistance Rs (expressed in ohms per square (Ω / □)) of the first metal layer after heat treatment according to Comparative Example 1 is greater than the increase in the surface resistance Rs of the first metal layer after heat treatment according to Embodiment 1, Embodiment 2, and Embodiment 3.

[0118] Through this, the light-emitting element in the embodiments of the present disclosure includes a sub-reflection layer SRL containing Al and a barrier layer BAR containing an Nb-Ti alloy, and the thickness of the sub-reflection layer SRL ranges from about 200 nm to about 300 nm. In this case, it can be confirmed that after heat treatment at a relatively high temperature (i.e., 450 °C), an increase in the resistance of the sub-reflection layer SRL can be minimized. In addition, it can be confirmed that after heat treatment at a relatively high temperature, voids due to Al diffusion in the sub-reflection layer SRL are not formed.

[0119] The present disclosure can be applied to various display devices. In an embodiment, the present disclosure can be applied to various display devices such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for exhibitions or information transmission, medical display devices, and the like.

[0120] The above is an illustrative description of the embodiments and is not to be construed as limiting thereof. Although some embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Accordingly, it is to be understood that the above is an illustrative description of various embodiments and is not to be construed as limiting the illustrative embodiments of the disclosure, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A light-emitting element, comprising: A first semiconductor layer; An active layer disposed under the first semiconductor layer; A second semiconductor layer disposed under the active layer; And A reflective layer, comprising: A sub-reflective layer disposed under the second semiconductor layer; And A barrier layer disposed under the sub-reflective layer and having a multi-layer structure including a niobium-titanium alloy and chromium.

2. The light-emitting element according to claim 1, wherein The barrier layer comprises: A first layer including a niobium-titanium alloy; A second layer disposed under the first layer and including chromium; and A third layer disposed under the second layer and including a niobium-titanium alloy.

3. The light-emitting element according to claim 2, wherein, Each of the first layer and the third layer includes 50 at% to 60 at% niobium and 40 at% to 50 at% titanium.

4. The light-emitting element according to claim 2, wherein, The thickness of each of the first layer and the third layer ranges from 100 nanometers to 200 nanometers.

5. The light-emitting element according to claim 1, wherein, The sub-reflective layer includes aluminum.

6. The light-emitting element according to claim 5, wherein, The thickness of the sub-reflective layer ranges from 200 nanometers to 300 nanometers.

7. The light-emitting element according to claim 1, wherein, The barrier layer comprises: A first layer including a niobium-titanium alloy; A second layer disposed under the first layer and including chromium; and A third layer disposed under the second layer and including nickel.

8. The light-emitting element according to claim 7, wherein, The first layer includes 50 at% to 60 at% niobium and 40 at% to 50 at% titanium.

9. The light-emitting element according to claim 1, wherein, The reflective layer further comprises: An anti-corrosion layer disposed on the sub-reflective layer and including a metal; and A metal oxide layer disposed on the anti-corrosion layer.

10. The light-emitting element according to claim 9, further comprising: A connection layer disposed under the barrier layer and including an alloy.

11. The light-emitting element according to claim 10, wherein, The anti-corrosion layer includes chromium, the metal oxide layer includes indium tin oxide, and the connection layer includes a tin-silver-copper alloy.

12. A display device, comprising: A pixel electrode disposed on a substrate; A light-emitting element disposed on the pixel electrode and extending in a direction perpendicular to the main plane extension direction of the substrate, the light-emitting element comprising: A first semiconductor layer; An active layer disposed under the first semiconductor layer; A second semiconductor layer disposed under the active layer; and A reflective layer, comprising: A sub-reflective layer disposed under the second semiconductor layer; and A barrier layer disposed under the sub-reflective layer and having a multi-layer structure including a niobium-titanium alloy and chromium; and A common electrode disposed on the light-emitting element.

13. The display device according to claim 12, wherein, The barrier layer comprises: A first layer including a niobium-titanium alloy; A second layer disposed under the first layer and including chromium; and A third layer disposed under the second layer and including a niobium-titanium alloy.

14. The display device according to claim 13, wherein, Each of the first layer and the third layer includes 50 at% to 60 at% niobium and 40 at% to 50 at% titanium.

15. The display device according to claim 13, wherein, The thickness of each of the first layer and the third layer ranges from 100 nanometers to 200 nanometers.

16. The display device according to claim 12, wherein, The sub-reflective layer includes aluminum.

17. The display device according to claim 16, wherein, The thickness of the sub-reflective layer ranges from 200 nanometers to 300 nanometers.

18. The display device according to claim 12, wherein, The barrier layer comprises: A first layer including a niobium-titanium alloy; A second layer disposed under the first layer and including chromium; and A third layer disposed under the second layer and including nickel.

19. The display device according to claim 18, wherein, The first layer includes 50 at% to 60 at% niobium and 40 at% to 50 at% titanium.

20. The display device according to claim 12, wherein, The reflective layer further includes: a corrosion prevention layer disposed on the sub-reflective layer and including a metal; and a metal oxide layer disposed on the corrosion prevention layer.

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