Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a substrate, a first transistor including a first semiconductor layer on the substrate and a first gate electrode on the first semiconductor layer, a second transistor including a second semiconductor layer on the first gate electrode and a second gate electrode on the second semiconductor layer, an insulating structure between the first gate electrode and the second gate electrode, and a first transfer pattern electrically connected to the first gate electrode through a contact hole passing through the insulating structure at the same layer as a layer of the second gate electrode, and including a first layer and a second layer on the first layer. The first layer includes a first portion in the contact hole and a second portion outside the contact hole. The thickness of the second portion of the first layer is in the range of about # imgabs 0 # to # imgabs 1 #.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0197605, filed with the Korean Intellectual Property Office on December 29, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] Aspects of one or more embodiments of the present disclosure relate to a display device and a method of manufacturing a display device. Background art

[0004] As the display field for visually displaying various electrical signal information has rapidly developed, various display devices having excellent characteristics such as thinness, reduced weight, and low power consumption have been introduced. Among display devices, organic light - emitting display devices have received particular attention as next - generation display devices because organic light - emitting display devices can have a wide viewing angle, excellent contrast, and fast response speed.

[0005] A display device includes thin - film transistors (TFTs), capacitors, and the like as driving circuits. A TFT may include an active layer including a channel region, a source region, and a drain region, and a gate electrode electrically insulated from the active layer through a gate insulating layer. Generally, the active layer of a TFT may include amorphous silicon or polycrystalline silicon.

[0006] The above - disclosed information in this background art section is for enhancing the understanding of the background of the present disclosure, and thus it may include information that does not constitute prior art. Summary of the invention

[0007] One or more embodiments of the present disclosure may relate to a display device having improved display quality and a method of manufacturing a display device. However, aspects and features of the present disclosure are not limited to or restricted by this.

[0008] Additional aspects and features will be partially described in the following description, and will be partially apparent from the description, or may be learned by practicing one or more of the embodiments presented of the present disclosure.

[0009] According to one or more embodiments of the present disclosure, a display device includes: a substrate, a first transistor, a second transistor, an insulating structure, and a first transmission pattern. The first transistor includes a first semiconductor layer on the substrate and a first gate electrode on the first semiconductor layer and at least partially overlapping the first semiconductor layer. The second transistor includes a second semiconductor layer on the first gate electrode and a second gate electrode on the second semiconductor layer and at least partially overlapping the second semiconductor layer. The insulating structure is between the first gate electrode and the second gate electrode. The first transmission pattern is at the same layer as the layer of the second gate electrode. The first transmission pattern is electrically connected to the first gate electrode through a contact hole passing through the insulating structure and includes a first layer and a second layer on the first layer. The first layer of the first transmission pattern includes a first portion in the contact hole and a second portion outside the contact hole. The thickness of the second portion of the first layer is in the range of about to .

[0010] In an embodiment, the thickness of the first portion of the first layer may be in the range of about to about .

[0011] In an embodiment, the taper angle of the insulating structure may be in the range of about 40° to about 75°.

[0012] In an embodiment, the thickness of the second layer may be greater than each of the thickness of the first portion of the first layer and the thickness of the second portion of the first layer.

[0013] In an embodiment, the first layer may include titanium (Ti).

[0014] In an embodiment, the display device may further include a second transmission pattern on the first transmission pattern and electrically connecting the first transmission pattern and the second semiconductor layer to each other.

[0015] In an embodiment, the display device may further include a capacitor electrode between the first gate electrode and the first transmission pattern and having an opening overlapping a portion of the first transmission pattern. The contact hole may overlap the opening in the capacitor electrode.

[0016] In an embodiment, the insulating structure may include a first insulating layer between the first gate electrode and the capacitor electrode, a second insulating layer between the capacitor electrode and the second semiconductor layer, and a third insulating layer between the second semiconductor layer and the first transmission pattern.

[0017] In an embodiment, the substrate may include a display area and a peripheral area outside the display area. The display device may further include a data transmission line bypassing a partial area in the display area and configured to receive a data signal.

[0018] In an embodiment, the data transmission line may include a first connection line that is disposed on the second gate electrode and extends in a first direction, and a second connection line that is disposed on the first connection line and extends in a second direction intersecting the first direction. The first connection line and the second connection line may be electrically connected to each other through a connection contact hole.

[0019] In an embodiment, the first connection line and the second connection line may be configured to receive the same data signal as each other.

[0020] In an embodiment, the display device may further include a first input line, a second input line, and a third input line, a first data line, a third data line, and a second data line. The first input line, the second input line, and the third input line are sequentially positioned in the peripheral region in a direction from the edge of the peripheral region toward the center of the peripheral region. The first data line is connected to the first input line. The third data line is on one side of the first data line and is connected to the third input line. The second data line is on the other side of the first data line and is electrically connected to the second input line through the first connection line and the second connection line.

[0021] In an embodiment, the first connection line may be electrically insulated from the first data line and may overlap the first data line in at least a part of the region.

[0022] In an embodiment, the first data line, the second data line, and the third data line may be positioned at the same layer as the layer of the second connection line.

[0023] In an embodiment, the first semiconductor layer may include a silicon semiconductor material.

[0024] In an embodiment, the second semiconductor layer may include an oxide semiconductor material.

[0025] According to one or more embodiments of the present disclosure, a display device includes a substrate, a first transistor, a second transistor, an insulating structure, and a first transmission pattern. The first transistor includes a first semiconductor layer on the substrate and a first gate electrode on the first semiconductor layer and at least partially overlapping the first semiconductor layer. The second transistor includes a second semiconductor layer on the first gate electrode and a second gate electrode on the second semiconductor layer and at least partially overlapping the second semiconductor layer. The insulating structure is between the first gate electrode and the second gate electrode. The first transmission pattern is at the same layer as the layer of the second gate electrode and is electrically connected to the first gate electrode through a contact hole passing through the insulating structure. The taper angle of the insulating structure may be in a range of about 40° to about 75°.

[0026] In an embodiment, the display device may further include a second transmission pattern that is disposed on the first transmission pattern and electrically connects the first transmission pattern and the second semiconductor layer to each other.

[0027] In an embodiment, the display device may further include a capacitor electrode that is between the first gate electrode and the first transmission pattern and has an opening overlapping a part of the first transmission pattern. The contact hole may overlap the opening in the capacitor electrode.

[0028] In an embodiment, the insulating structure may include a first insulating layer between the first gate electrode and the capacitor electrode, a second insulating layer between the capacitor electrode and the second semiconductor layer, and a third insulating layer between the second semiconductor layer and the second gate electrode.

[0029] In an embodiment, the first transmission pattern may include a first layer and a second layer on the first layer. The first layer may include a first portion in the contact hole and a second portion outside the contact hole. The thickness of the first portion of the first layer may be in the range of about to about .

[0030] In an embodiment, the thickness of the second layer may be greater than each of the thickness of the first portion of the first layer and the thickness of the second portion of the first layer.

[0031] In an embodiment, the first layer may contain titanium (Ti).

[0032] In an embodiment, the substrate may include a display area and a peripheral area outside the display area. The display device may further include a data transmission line that bypasses a partial area in the display area and is configured to receive a data signal.

[0033] According to one or more embodiments of the present disclosure, a method of manufacturing a display device includes: forming a first transistor including a first semiconductor layer disposed on a substrate and a first gate electrode disposed on the first semiconductor layer and overlapping at least a part of the first semiconductor layer; forming a first insulating layer on the first gate electrode; forming a capacitor electrode on the first insulating layer; forming a second insulating layer on the capacitor electrode; forming a second semiconductor layer on the second insulating layer; forming a third insulating layer on the second semiconductor layer; forming a contact hole overlapping the first gate electrode by removing a part of each of the first insulating layer, the second insulating layer, and the third insulating layer and then performing a first heat treatment; and forming a first transmission pattern on the third insulating layer that is electrically connected to the first gate electrode through the contact hole.

[0034] In an embodiment, when forming the contact hole, a part of each of the first insulating layer, the second insulating layer, and the third insulating layer may be removed such that an insulating structure including the first insulating layer, the second insulating layer, and the third insulating layer and having a taper angle in the range of about 40° to about 75° may be formed.

[0035] In an embodiment, the first transmission pattern may include a first layer and a second layer on the first layer. The first layer may include a first portion in the contact hole and a second portion outside the contact hole, and the thickness of the first portion of the first layer may be in the range of about to about .

[0036] In an embodiment, the thickness of the second portion of the first layer may be in the range of about to about .

[0037] In an embodiment, the method may further include performing a second heat treatment after forming the first transmission pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative non - limiting embodiments with reference to the accompanying drawings, in which:

[0039] Figure 1 is a plan view schematically showing a part of a display device according to an embodiment;

[0040] Figure 2 is a side view schematically showing Figure 1 the display device;

[0041] Figure 3 is a plan view schematically showing a display panel according to an embodiment;

[0042] Figure 4 and Figure 5 is a plan view schematically showing Figure 3 an enlarged view of region A;

[0043] Figure 6 is an equivalent circuit diagram of a pixel included in a display device according to an embodiment;

[0044] Figure 7 is a plan view schematically showing the structure of a pixel circuit according to an embodiment;

[0045] Figures 8 to 16 is a plan view showing layers of elements included in Figure 7 the pixel circuit;

[0046] Figure 17 is a cross - sectional view schematically showing a part of the structure of a pixel circuit according to an embodiment;

[0047] Figure 18 is a plan view schematically showing Figure 7 an enlarged view of some layers in region B;

[0048] Figure 19is a cross-sectional view schematically showing a cross-section taken along line I-I' of Figure 18 ; and

[0049] Figures 20 to 24 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0050] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numerals always denote like elements. However, the present disclosure may be implemented in various different forms and should not be construed as limited to the embodiments shown herein. Instead, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise noted, like reference numerals represent like elements throughout the drawings and the written description, and thus their redundant description may not be repeated.

[0051] When a particular embodiment can be implemented differently, the specific process order may be different from the described order. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or may be performed in an order opposite to the described order.

[0052] Furthermore, as will be understood by those of ordinary skill in the art, given the entire content of the present disclosure, unless otherwise stated or implied, each appropriate feature of the various embodiments of the present disclosure may be partially or fully combined or combined with each other, and may be interlocked and operated in various appropriate ways technically, and each embodiment may be implemented independently of each other or in combination with each other in any appropriate way.

[0053] In the drawings, for clarity, the relative dimensions, thicknesses, and ratios of elements, layers, and regions may be enlarged and / or simplified. Spatial relative terms, such as "beneath", "below", "under", "underneath", "above", "on", etc., may be used herein for convenience of explanation to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. It should be understood that, in addition to the orientation depicted in the figures, spatial relative terms are intended to also cover different orientations of the device during use or operation. For example, if the device in the figures is flipped, an element described as "beneath" or "below" or "underneath" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "underneath" can cover both orientations of above and below. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive words used herein should be interpreted accordingly.

[0054] In the figures, the x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular or substantially perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0055] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, the first element, component, region, layer, or part described below can be referred to as the second element, component, region, layer, or part without departing from the spirit and scope of the present disclosure.

[0056] It should be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, directly connected to, or coupled to the other element or layer, or there can be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it can be directly electrically connected to the other layer, region, or element, or can be indirectly electrically connected with one or more intervening layers, regions, or elements therebetween. In addition, it should also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0057] The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the disclosure. Unless the context clearly indicates otherwise, the singular forms "a" and "an" as used herein are also intended to include the plural forms. It should also be understood that the terms "comprises," "comprising," "includes," "including," "has," "have," and "having" when used in this specification specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" means A, B, or A and B. Expressions such as "at least one of..." when following a list of elements modify the entire list of elements rather than individual elements in the list. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variants thereof.

[0058] As used herein, the terms "substantially," "about," and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values recognized by those of ordinary skill in the art. In addition, the use of "may" when describing embodiments of the disclosure refers to "one or more embodiments of the disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0059] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0060] Figure 1 is a plan view schematically showing a part of a display device 1 according to an embodiment, and Figure 2 is schematically shown Figure 1 is a side view of the display device 1. InFigure 2 In this case, the display device 1 according to the present embodiment is partially bent. However, for convenience of illustration, Figure 1 the unbent display device 1 is shown.

[0061] Referring to Figure 1 and Figure 2 , the display device 1 may include a display panel 10. The display device 1 may be any suitable display device including the display panel 10. For example, the display device 1 may include various suitable products such as a smart phone, a tablet computer, a notebook computer, a television, or a billboard.

[0062] The display panel 10 may include a display area DA and a peripheral area PA outside the display area DA. The display area DA is the part where an image is displayed, and a plurality of pixels may be arranged in the display area DA. The display area DA may have various suitable shapes such as a circle, an ellipse, a polygon, or a specific shape. In Figure 1 , the display area DA has a rectangular shape including rounded edges.

[0063] The peripheral area PA may be arranged outside the display area DA. The peripheral area PA may include a first peripheral area PA1 arranged to surround at least a part of the display area DA (e.g., around the periphery of at least a part of the display area DA) and a second peripheral area PA2 extending to one side (e.g., in the -y direction) of the display area DA. The width of the second peripheral area PA2 in one direction (e.g., the x-axis direction) may be less than the width of the display area DA. Thus, bending of at least a part of the second peripheral area PA2 can be facilitated.

[0064] In addition, since the display panel 10 includes a substrate 100 (e.g., see Figure 3 ), it can be understood that the substrate 100 includes the display area DA and the peripheral area PA. Hereinafter, for convenience of illustration, the substrate 100 is described in more detail as including the display area DA and the peripheral area PA.

[0065] The display panel 10 may include a main region MR, a bending region BR outside the main region MR, and a sub-region SR spaced apart from the main region MR across the bending region BR. In other words, the main region MR may be arranged on one side of the bending region BR, and the sub-region SR may be arranged on the other side (e.g., the opposite side) of the bending region BR. Since as Figure 2As shown, the display panel 10 is bent in the bending region BR. Thus, when viewed from the z-axis direction (e.g., in a plan view), at least a part of the sub-region SR may overlap with the main region MR. However, the present disclosure is not limited to a bendable display device, and one or more embodiments may be applied to a non-bendable display device. As described in more detail below, the sub-region SR may be a video display region. By allowing the display panel 10 to be bent in the bending region BR, when the display device 1 is viewed from the front (e.g., in the -z direction), the non-display region may be invisible, or even if the non-display region is visible, the visible area may be minimized or reduced.

[0066] The data pad unit (e.g., data pad region) 20 may be disposed in the sub-region SR of the display panel 10. The data pad unit 20 may include an integrated circuit (e.g., a driving chip) to drive the display panel 10. The integrated circuit may be a data driving integrated circuit to generate data signals, but the present disclosure is not limited thereto.

[0067] The data pad unit 20 may be mounted in the sub-region SR of the display panel 10. Although the data pad unit 20 is mounted on the same surface as the display surface of the display region DA, when the data pad unit 20 is bent in the bending region BR, as described above, the data pad unit 20 may be positioned on the back surface of the main region MR. The data pad unit 20 may include a plurality of pads.

[0068] The printed circuit board 30 or the like may be attached to an end of the sub-region SR of the display panel 10. The printed circuit board 30 or the like may be electrically connected to the data pad unit 20 or the like through pads.

[0069] Hereinafter, an organic light emitting display device will be described in more detail as a representative example of the display device 1 according to an embodiment, but the present disclosure is not limited thereto. In another embodiment, the display device 1 of one or more embodiments may be an inorganic light emitting display (e.g., an inorganic electroluminescent display device) or a quantum dot light emitting display. For example, the emission layer of the display element provided in the display device 1 may include an organic material, an inorganic material, quantum dots, both an organic material and quantum dots, or both an inorganic material and quantum dots.

[0070] Figure 3 is a plan view schematically showing a display panel 10 according to an embodiment.

[0071] Referring to Figure 3 the display panel 10 may include a substrate 100. Various elements included in the display panel 10 may be disposed on the substrate 100.

[0072] The substrate 100 may include glass, metal, or a polymer resin. When, as described above, the display panel 10 is bent in the bending region BR (e.g., seeFigure 2 ) When bent, the substrate 100 may have a flexible or bendable property. In this case, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 may have a multilayer structure including two layers each containing at least one of the above polymer resins and a barrier layer containing an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or the like), and various appropriate modifications may be made.

[0073] A plurality of pixels P may be arranged in the display area DA. Each of the pixels P represents a sub-pixel and may be implemented by a display element such as an organic light-emitting diode OLED (e.g., see Figure 6 ). The pixels P may emit, for example, red light, green light, blue light, or white light.

[0074] The pixels P may be electrically connected to an external circuit arranged in the peripheral area PA. The first scan driving circuit 11, the second scan driving circuit 12, the emission control driving circuit 13, the terminal 14, the first power supply line 15, and the second power supply line 16 may be arranged in the peripheral area PA.

[0075] The first scan driving circuit 11 may provide a scan signal to the pixels P through the scan line SL. The second scan driving circuit 12 may be arranged parallel to the first scan driving circuit 11 across the display area DA. Some of the pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 11, and other pixels of the pixels P may be connected to the second scan driving circuit 12. In another embodiment, the second scan driving circuit 12 may be omitted as needed or desired.

[0076] The emission control driving circuit 13 may be arranged on one side of the first scan driving circuit 11 and may provide an emission control signal to the pixels P through the emission control line EL. In Figure 3 it, the emission control driving circuit 13 is shown as being arranged on one side of the display area DA. However, the emission control driving circuit 13 may be arranged on the opposite side of the display area DA.

[0077] The terminal 14 may be arranged in the second peripheral area PA2 of the substrate 100. The terminal 14 may be exposed without being covered by an insulating layer and may be electrically connected to the printed circuit board 30. The terminal 34 of the printed circuit board 30 may be electrically connected to the terminal 14 of the display panel 10.

[0078] The printed circuit board 30 can send signals or power of a control unit (e.g., a controller) to the display panel 10. Control signals generated by the control unit can be sent to the driving circuits 11, 12, and 13 respectively through the printed circuit board 30. Additionally, the control unit can supply a first power voltage ELVDD and a second power voltage ELVSS (e.g., see Figure 6 ) to the first power supply line 15 and the second power supply line 16 respectively. The first power voltage (e.g., driving voltage) ELVDD can be supplied to each pixel P through a driving voltage line PL connected to the first power supply line 15, and the second power voltage (e.g., common voltage) ELVSS can be supplied to the opposite electrode of the pixel P connected to the second power supply line 16. The first power supply line 15 can be provided to extend in one direction (e.g., the x direction) from the lower side of the second peripheral region PA2. The second power supply line 16 can have an annular shape including an open side and can partially surround the display area DA (e.g., around the periphery of the display area DA).

[0079] Moreover, the control unit can generate data signals, and the generated data signals can be sent to the input line IL through the data pad unit 20 and then sent to the pixel P through a data line DL connected to the input line IL.

[0080] Figure 4 and Figure 5 schematically shows an enlarged plan view of region A Figure 3 shown.

[0081] Referring to Figure 4 , various signals can be sent to the display area DA (e.g., see Figure 3 ). For example, data signals or similar signals for adjusting the brightness of each pixel can be sent to the display area DA, and thus, as shown in Figure 4 , data lines DL1 to DL6 that are parallel or substantially parallel to each other can be positioned on the substrate in the display area DA. In addition to the data lines DL1 to DL6, various lines (such as power lines or scan lines) can be positioned inside or outside the display area DA.

[0082] In the peripheral region PA (e.g., see Figure 3 ), or in other words, the second peripheral region PA2, first input lines IL1 to sixth input lines IL6 that are connected to the data pad unit 20 (e.g., see Figure 3 ) and receive data signals can be arranged. The first data lines DL1 to sixth data lines DL6 can be respectively connected to the first input lines IL1 to sixth input lines IL6 to send data signals to corresponding pixels.

[0083] In Figure 4 and Figure 5In order to facilitate illustration, six input lines and six data lines are shown. However, the number of input lines and the number of data lines may be more than or substantially more than six.

[0084] The first input line IL1 to the sixth input line IL6 may be sequentially arranged in a direction from the edge of the second peripheral region PA2 to the center of the second peripheral region PA2. In an embodiment, the first input line IL1, the third input line IL3, and the fifth input line IL5 are odd-numbered and may be respectively connected to the first data line DL1, the third data line DL3, and the fifth data line DL5 that are arranged adjacent to each other continuously. The first input line IL1, the third input line IL3, and the fifth input line IL5 may be integrally formed with the first data line DL1, the third data line DL3, and the fifth data line DL5 respectively, or as Figure 4 shown in, may be connected to the first contact hole CNT1. The first data line DL1, the third data line DL3, and the fifth data line DL5 may respectively receive data signals from the first input line IL1, the third input line IL3, and the fifth input line IL5.

[0085] The second input line IL2, the fourth input line IL4, and the sixth input line IL6 may be respectively connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6 that are arranged adjacent to each other continuously through the first data transmission line DTL1 to the third data transmission line DTL3. In other words, the second data line DL2, the fourth data line DL4, and the sixth data line DL6 may respectively receive data signals from the second input line IL2, the fourth input line IL4, and the sixth input line IL6 via the first data transmission line DTL1 to the third data transmission line DTL3.

[0086] The first data transmission line DTL1 to the third data transmission line DTL3 may be arranged to pass through the display area DA by bypassing the portion of the display area DA adjacent to the peripheral area PA. The second input line IL2 may be electrically connected to the second data line DL2 through the first data transmission line DTL1. The fourth input line IL4 may be electrically connected to the fourth data line DL4 through the second data transmission line DTL2. The sixth input line IL6 may be electrically connected to the sixth data line DL6 through the third data transmission line DTL3.

[0087] One end of each of the first data transmission line DTL1 to the third data transmission line DTL3 may be connected to one of the second input line IL2, the fourth input line IL4, and the sixth input line IL6 through the second contact hole CNT2, and the other end of each of the first data transmission line DTL1 to the third data transmission line DTL3 may be connected to one of the second data line DL2, the fourth data line DL4, and the sixth data line DL6 through the third contact hole CNT3. In Figure 4 and Figure 5In [the figure], the second contact hole CNT2 and the third contact hole CNT3 are shown to be positioned in the peripheral area PA. However, the present disclosure is not limited thereto. In another embodiment, the second contact hole CNT2 and / or the third contact hole CNT3 may be positioned in the display area DA. Thus, the second input line IL2 may transmit a data signal to the second data line DL2, the fourth input line IL4 may transmit a data signal to the fourth data line DL4, and the sixth input line IL6 may transmit a data signal to the sixth data line DL6.

[0088] Referring to Figure 5 , a connection relationship outside the display area DA (e.g., see Figure 3 ) in which the first data transmission line DTL1 to the third data transmission line DTL3 are arranged is shown. Figure 5 It can be understood as a specific illustration of the above Figure 4 .

[0089] Referring to Figure 5 , the second input line IL2, the fourth input line IL4, and the sixth input line IL6 may be electrically connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6 through the first data transmission line DTL1 to the third data transmission line DTL3, respectively.

[0090] In an embodiment, each of the first data transmission line DTL1 to the third data transmission line DTL3 includes a first connection line DH1 to DH3, a second connection line DV1 to DV3, and a third connection line DV1' to DV3'. The first connection lines DH1 to DH3 may extend in a first direction (e.g., the x direction) intersecting with the second direction (e.g., the y direction). The second connection lines DV1 to DV3 and the third connection lines DV1' to DV3' may extend in the second direction (e.g., the y direction) parallel or substantially parallel to the data lines.

[0091] The second input line IL2, the fourth input line IL4, and the sixth input line IL6 may be connected to the second connection lines DV1 to DV3 through the second contact hole CNT2, respectively. The third connection lines DV1' to DV3' may be connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6 through the third contact hole CNT3, respectively. The first connection lines DH1 to DH3 may be connected to the second connection lines DV1 to DV3 and the third connection lines DV1' to DV3' through a first connection contact hole DH-CNT1 and a second connection contact hole DH-CNT2 respectively positioned at one end and the other end (e.g., opposite ends) of each of the first connection lines DH1 to DH3.

[0092] In an embodiment, the first connection lines DH1 to DH3, the second connection lines DV1 to DV3, and the third connection lines DV1' to DV3' may be disposed at the same layer as each other (e.g., middle or upper), or at least some of the first connection lines DH1 to DH3, the second connection lines DV1 to DV3, and the third connection lines DV1' to DV3' may be disposed at a layer different from the layer where other connection lines are disposed (e.g., middle or upper). For example, the second connection lines DV1 to DV3 and the third connection lines DV1' to DV3' may be disposed at the same layer as each other (e.g., middle or upper), and the first connection lines DH1 to DH3 may be disposed at a layer different from the layer of the second connection lines DV1 to DV3 and the third connection lines DV1' to DV3' (e.g., middle or upper). As used herein, when lines are said to be disposed at the same layer as each other (e.g., middle or upper), the lines may be formed synchronously or substantially simultaneously by the same mask process and may include the same material as each other. As described above, when the second connection lines DV1 to DV3 and the third connection lines DV1' to DV3' are disposed at the same layer as each other (middle or upper), the second connection lines DV1 to DV3 and the third connection lines DV1' to DV3' may be disposed at the same layer as the layer where the data lines DL (e.g., see Figure 3 ) are disposed (e.g., middle or upper).

[0093] The first connection lines DH1 to DH3 may overlap some of the first data lines DL1 to the sixth data lines DL6. The first connection lines DH1 to DH3 may be disposed to pass under the first data lines DL1 to the sixth data lines DL6. For example, as Figure 5 shown, the 2-1 connection line DH1 may partially overlap the first data line DL1 and may not be electrically connected to the first data line DL1, the 2-2 connection line DH2 may partially overlap the first data line DL1, the second data line DL2, and the third data line DL3 and may not be electrically connected to the first data line DL1, the second data line DL2, and the third data line DL3, and the 2-3 connection line DH3 may partially overlap the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, and the fifth data line DL5 and may not be electrically connected to the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, and the fifth data line DL5.

[0094] In some embodiments, dummy lines may also be disposed at the same layer as the layer in which the first connection lines DH1 to DH3, the second connection lines DV1 to DV3, and the third connection lines DV1' to DV3' are disposed. The dummy lines may be continuously formed with each of the first connection lines DH1 to DH3, the second connection lines DV1 to DV3, and the third connection lines DV1' to DV3', and may be provided to be electrically disconnected in some regions to constitute the first data transmission lines DTL1 to the third data transmission lines DTL3. The disconnected portions may be positioned around the above-described first connection contact holes DH-CNT1 and the second connection contact holes DH-CNT2. The dummy lines may exist in the form of floating electrodes isolated from other electrodes and / or lines, and a signal or a constant voltage may be applied to prevent or substantially prevent static electricity.

[0095] Figure 6 is an equivalent circuit diagram of a pixel P included in a display device according to an embodiment.

[0096] Referring to Figure 6 , the pixel P may include a pixel circuit PC and an organic light-emitting diode OLED.

[0097] For example, as Figure 6 shown, the pixel circuit PC may include a plurality of thin-film transistors T1 to T7 and a storage capacitor Cst. The plurality of thin-film transistors T1 to T7 and the storage capacitor Cst may be connected to signal lines SL1, SL2, SLp, SLn, EL, and DL, a first initialization voltage line VL1, a second initialization voltage line VL2 (e.g., an anode initialization voltage line), and a driving voltage line PL. In an embodiment, at least one of the above-described lines (such as taking the driving voltage line PL as an example) may be shared by adjacent pixels P.

[0098] The plurality of thin-film transistors T1 to T7 may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensating thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7. The driving thin-film transistor T1, the switching thin-film transistor T2, the compensating thin-film transistor T3, the first initialization thin-film transistor T4, the operation control thin-film transistor T5, the emission control thin-film transistor T6, and the second initialization thin-film transistor T7 may be respectively referred to as the first transistor to the seventh transistor.

[0099] The organic light-emitting diode OLED may include a first electrode (e.g., an anode electrode or a pixel electrode) and a second electrode (e.g., a cathode electrode or a counter electrode). The first electrode of the organic light-emitting diode OLED is connected to the driving thin-film transistor T1 via the emission control thin-film transistor T6 to receive a driving current I OLED. The second electrode may receive a second power supply voltage ELVSS. The organic light-emitting diode OLED may generate light having a brightness corresponding to the driving current I OLED corresponding brightness.

[0100] Some of the plurality of thin film transistors T1 to T7 may be provided as n-channel metal oxide semiconductor field effect transistors (MOSFETs; NMOSs), and others may be provided as p-channel MOSFETs (PMOSs). For example, the compensation thin film transistor T3 and the first initialization thin film transistor T4 among the plurality of thin film transistors T1 to T7 may be provided as NMOSs, and others may be provided as PMOSs.

[0101] In another embodiment, the compensation thin film transistor T3, the first initialization thin film transistor T4, and the second initialization thin film transistor T7 among the plurality of thin film transistors T1 to T7 may be provided as NMOSs, and others may be provided as PMOSs. In some embodiments, only one of the plurality of thin film transistors T1 to T7 may be provided as an NMOS, and others may be provided as PMOSs. In some embodiments, all of the plurality of thin film transistors T1 to T7 may be provided as NMOSs.

[0102] The signal lines may include a first scan line SL1 for transmitting a first scan signal Sn, a second scan line SL2 for transmitting a second scan signal Sn', a previous scan line SLp for transmitting the previous scan signal Sn-1 to the first initialization thin film transistor T4, an emission control line EL for transmitting an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, a next scan line SLn for transmitting the next scan signal Sn+1 to the second initialization thin film transistor T7, and a data line DL that intersects the first scan line SL1 and is for transmitting a data signal Dm.

[0103] The driving voltage line PL may transmit a driving voltage ELVDD to the driving thin film transistor T1, and the first initialization voltage line VL1 may transmit a first initialization voltage Vint1 for initializing the driving thin film transistor T1. The second initialization voltage line VL2 may transmit a second initialization voltage Vint2 for initializing the pixel electrode.

[0104] The driving gate electrode of the driving thin film transistor T1 may be connected to the storage capacitor Cst, the driving source region of the driving thin film transistor T1 may be connected to the driving voltage line PL via the operation control thin film transistor T5, and the driving drain region of the driving thin film transistor T1 may be electrically connected to the pixel electrode of the organic light-emitting diode OLED via the emission control thin film transistor T6. In response to the switching operation of the switching thin film transistor T2, the driving thin film transistor T1 may receive the data signal Dm and supply the driving current I OLED to the organic light-emitting diode OLED.

[0105] The switching gate electrode of the switching thin-film transistor T2 can be connected to the first scan line SL1 configured to send the first scan signal Sn, the switching source region of the switching thin-film transistor T2 can be connected to the data line DL, and the switching drain region of the switching thin-film transistor T2 can be connected to the driving voltage line PL via the operation control thin-film transistor T5 and connected to the driving source region of the driving thin-film transistor T1. The switching thin-film transistor T2 can be turned on in response to the first scan signal Sn received via the first scan line SL1, and can perform a switching operation for transmitting the data signal Dm received via the data line DL to the driving source region of the driving thin-film transistor T1.

[0106] The compensation gate electrode of the compensation thin-film transistor T3 can be connected to the second scan line SL2. The compensation drain region of the compensation thin-film transistor T3 can be connected to the pixel electrode of the organic light-emitting diode OLED via the emission control thin-film transistor T6 and connected to the driving drain region (or node N3) of the driving thin-film transistor T1. The compensation source region of the compensation thin-film transistor T3 can be connected to the first electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving thin-film transistor T1. Additionally, the compensation source region can be connected to the first initialization drain region of the first initialization thin-film transistor T4.

[0107] The compensation thin-film transistor T3 can be turned on in response to the second scan signal Sn' received via the second scan line SL2, and can electrically connect the driving gate electrode of the driving thin-film transistor T1 to the driving drain region so as to connect the driving thin-film transistor T1 in a diode manner.

[0108] The first initialization gate electrode of the first initialization thin-film transistor T4 can be connected to the previous scan line SLp. The first initialization source region of the first initialization thin-film transistor T4 can be connected to the second initialization source region of the second initialization thin-film transistor T7 and the first initialization voltage line VL1. The first initialization drain region of the first initialization thin-film transistor T4 can be connected to the first electrode CE1 of the storage capacitor Cst, the compensation source region of the compensation thin-film transistor T3, and the driving gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 can be turned on in response to the previous scan signal Sn-1 received via the previous scan line SLp, and can perform an initialization operation for transmitting the first initialization voltage Vint1 to the driving gate electrode of the driving thin-film transistor T1 and initializing the voltage of the driving gate electrode of the driving thin-film transistor T1.

[0109] The operation control gate electrode of the operation control thin film transistor T5 can be connected to the emission control line EL, the operation control source region of the operation control thin film transistor T5 can be connected to the driving voltage line PL, and the operation control drain region of the operation control thin film transistor T5 can be connected to the driving source region (or node N1) of the driving thin film transistor T1 and the switching drain region of the switching thin film transistor T2.

[0110] The emission control gate electrode of the emission control thin film transistor T6 can be connected to the emission control line EL, the emission control source region of the emission control thin film transistor T6 can be connected to the driving drain region of the driving thin film transistor T1 and the compensation drain region of the compensation thin film transistor T3, and the emission control drain region of the emission control thin film transistor T6 can be electrically connected to the second initialization drain region of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0111] The operation control thin film transistor T5 and the emission control thin film transistor T6 can be turned on synchronously or substantially simultaneously with each other in response to the emission control signal En received via the emission control line EL, so that the driving voltage ELVDD is sent to the organic light emitting diode OLED to make the driving current I OLED flow to the organic light emitting diode OLED.

[0112] The second initialization gate electrode of the second initialization thin film transistor T7 can be connected to the next scan line SLn, the second initialization drain region of the second initialization thin film transistor T7 can be connected to the emission control drain region of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and the second initialization source region of the second initialization thin film transistor T7 can be connected to the second initialization voltage line VL2 to receive the second initialization voltage Vint2. The second initialization thin film transistor T7 can be turned on in response to the next scan signal Sn+1 received via the next scan line SLn, and can initialize the pixel electrode of the organic light emitting diode OLED.

[0113] As Figure 6 shown, the second initialization thin film transistor T7 can be connected to the next scan line SLn. In another embodiment, the second initialization thin film transistor T7 can be connected to the emission control line EL and be driven in response to the emission control signal En. However, the positions of the source region and the drain region can be variously modified according to the type of the transistor (e.g., p-type or n-type).

[0114] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 of the storage capacitor Cst may be connected to the driving gate electrode of the driving thin film transistor T1, and the second electrode CE2 of the storage capacitor Cst may be connected to the driving voltage line PL. The storage capacitor Cst may store charges corresponding to the voltage difference between the voltage of the driving gate electrode of the driving thin film transistor T1 and the driving voltage ELVDD.

[0115] The detailed operations of each of the pixels P according to the embodiments will be described below.

[0116] During the initialization period, when the previous scan signal Sn-1 is supplied through the previous scan line SLp, the first initialization thin film transistor T4 may be turned on in response to the previous scan signal Sn-1, and the driving thin film transistor T1 may be initialized by the first initialization voltage Vint1 supplied from the first initialization voltage line VL1.

[0117] During the data programming period, when the first scan signal Sn and the second scan signal Sn' are supplied through the first scan line SL1 and the second scan line SL2, respectively, the switching thin film transistor T2 and the compensation thin film transistor T3 may be turned on in response to the first scan signal Sn and the second scan signal Sn', respectively. In this case, the driving thin film transistor T1 may be connected in a diode manner through the turned-on compensation thin film transistor T3 and forward-biased.

[0118] Then, a compensation voltage (Dm + Vth, where Vth is negative) obtained by subtracting the threshold voltage (Vth) of the driving thin film transistor T1 from the data signal Dm supplied from the data line DL may be applied to the driving gate electrode.

[0119] The driving voltage ELVDD and the compensation voltage (Dm + Vth) may be applied to the two terminals of the storage capacitor Cst, and the storage capacitor Cst stores charges corresponding to the voltage difference between the terminals.

[0120] During the emission period, the operation control thin film transistor T5 and the emission control thin film transistor T6 may be turned on according to the emission control signal En supplied from the emission control line EL. A driving current I may be generated according to the voltage difference between the voltage of the driving gate electrode of the driving thin film transistor T1 and the driving voltage ELVDD OLED , and the driving current IOLED may be supplied to the organic light emitting diode OLED through the emission control thin film transistor T6.

[0121] In the present embodiment, at least one of the plurality of thin film transistors T1 to T7 may include a semiconductor layer containing an oxide, and the other thin film transistors may include a semiconductor layer containing silicon.

[0122] For example, the driving thin film transistor T1 that directly affects the brightness of the display device may include a semiconductor layer containing polysilicon with high reliability so that a display device with high resolution can be realized.

[0123] Since the oxide semiconductor has a high carrier mobility and a low leakage current, even when the display device is driven for a long time, the voltage drop may not be significant. In other words, even during low-frequency driving, the color change of the image due to the voltage drop may not be significant, and thus the display device can be driven at a low frequency.

[0124] As described above, since the oxide semiconductor has a low leakage current, at least one of the compensation thin film transistor T3, the first initialization thin film transistor T4, and the second initialization thin film transistor T7 connected to the driving gate electrode of the driving thin film transistor T1 can be adopted as a thin film transistor containing an oxide semiconductor to reduce power consumption while preventing or substantially preventing the leakage current that may flow to the driving gate electrode.

[0125] Figure 7 is a plan view schematically showing the structure of a pixel circuit according to an embodiment. Figures 8 to 16 is shown included in Figure 7 the layer of elements in the pixel circuit of Figure 17 is a cross-sectional view schematically showing a part of the structure of a pixel circuit according to an embodiment.

[0126] Figure 8 shows the first semiconductor layer 1100.

[0127] With Figure 7 and Figure 17 together with reference to Figure 8 , the display device 1 (for example, see Figure 1 ) may include a first pixel P1 and a second pixel P2 adjacent to each other. In an embodiment, as Figure 7 and Figure 8 shown, the first pixel P1 and the second pixel P2 may have a structure in which the first pixel P1 and the second pixel P2 are symmetric or substantially symmetric with respect to an imaginary line. In another embodiment, the first pixel P1 and the second pixel P2 may have a structure in which the same or substantially the same pixel structure is continuously repeated, rather than a symmetric structure. The first pixel P1 may include a first pixel circuit PC1, and the second pixel P2 may include a second pixel circuit PC2.

[0128] Hereinafter, for convenience, the elements will be described in more detail based on the first pixel circuit PC1. However, the elements may also be provided symmetrically or substantially symmetrically in the second pixel circuit PC2.

[0129] The substrate 100 may include glass, quartz, plastic, or the like. In an embodiment, the substrate 100 may include plastic, and thus, the display device 1 may have a flexible property. In this case, the substrate 100 may have a structure in which at least one organic film layer and at least one barrier layer are stacked alternately with each other. For example, the organic film layer may be formed by using an organic material such as polyimide, and the barrier layer may be formed by using an inorganic material.

[0130] The buffer layer 101 (for example, see Figure 17 ) may be disposed on the substrate 100. The buffer layer 101 may prevent or substantially prevent metal atoms or impurities from diffusing from the substrate 100 into the first semiconductor layer 1100. In addition, the buffer layer 101 may adjust the rate of heat supply during the crystallization process for forming the first semiconductor layer 1100 so that the first semiconductor layer 1100 can be formed uniformly or substantially uniformly.

[0131] The first semiconductor layer 1100 may be disposed on the buffer layer 101. A part of the first semiconductor layer 1100 may be included in the first pixel circuit PC1, and another part of the first semiconductor layer 1100 may be included in the second pixel circuit PC2. The portion of the first semiconductor layer 1100 corresponding to the first pixel circuit PC1 and the portion of the first semiconductor layer 1100 corresponding to the second pixel circuit PC2 may be symmetric or substantially symmetric with respect to a hypothetical line.

[0132] In an embodiment, the first semiconductor layer 1100 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, or the like. For example, the first semiconductor layer 1100 may include low-temperature polycrystalline silicon (LTPS).

[0133] In an embodiment, ions may be implanted into the first semiconductor layer 1100. For example, when the driving thin-film transistor T1, the switching thin-film transistor T2, the operation control thin-film transistor T5, the emission control thin-film transistor T6, and the second initialization thin-film transistor T7 are PMOS transistors, ions such as boron may be implanted into the first semiconductor layer 1100.

[0134] The first gate insulating layer 110 (for example, see Figure 17 ) may cover the first semiconductor layer 1100 and may be disposed on the buffer layer 101. The first gate insulating layer 110 may be disposed between the first semiconductor layer 1100 and the first conductive layer 1200 described in more detail below. The first gate insulating layer 110 may contain an insulating material. For example, the first gate insulating layer 110 may contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

[0135] Figure 9 The first conductive layer 1200 is shown. Figure 10Shows the arrangement of the driving thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7, and also shows together Figure 8 the first semiconductor layer 1100 of Figure 9 and the first conductive layer 1200 of

[0136] Together with Figure 7 and Figure 17 with reference to together Figure 9 and Figure 10 , the first conductive layer 1200 may be disposed on the first gate insulating layer 110. The first conductive layer 1200 may be disposed on the first semiconductor layer 1100. The first conductive layer 1200 may include a first gate line 1210, a first gate electrode 1220, and a second gate line 1230.

[0137] The first gate line 1210 may extend in a first direction (e.g., the x direction). The first gate line 1210 may correspond to the first scan line SL1 (e.g., see Figure 6 ). The first gate line 1210 and the first semiconductor layer 1100 may form the switching thin film transistor T2. In other words, the switching thin film transistor T2 may include the first semiconductor layer 1100 and the first gate line 1210 that at least partially overlaps with the first semiconductor layer 1100. For example, the first scan signal Sn (e.g., see Figure 6 ) may be provided to the first gate line 1210. Additionally, the first gate line 1210 and the first semiconductor layer 1100 may form the second initialization thin film transistor T7. In other words, the second initialization thin film transistor T7 may include the first semiconductor layer 1100 and the first gate line 1210 that at least partially overlaps with the first semiconductor layer 1100. For example, the next scan signal Sn+1 (e.g., see Figure 6 ) may be provided to the first gate line 1210. The first scan signal Sn (e.g., see Figure 6 ) and the next scan signal Sn+1 may have the same or substantially the same waveform as each other but have a time difference.

[0138] The first gate electrode 1220 may be disposed in an island shape. The first gate electrode 1220 and the first semiconductor layer 1100 may form the driving thin film transistor T1. In other words, the driving thin film transistor T1 may include the first semiconductor layer 1100 and the first gate electrode 1220 that at least partially overlaps with the first semiconductor layer 1100.

[0139] The second gate line 1230 may extend in the first direction (e.g., the x direction). The second gate line 1230 may correspond to the emission control line EL (e.g., see Figure 6)。The second gate line 1230 and the first semiconductor layer 1100 may form an operation control thin film transistor T5 and an emission control thin film transistor T6. In other words, each of the operation control thin film transistor T5 and the emission control thin film transistor T6 may include the first semiconductor layer 1100 and the second gate line 1230 that at least partially overlaps with the first semiconductor layer 1100. For example, an emission control signal En (for example, see Figure 6 ) may be provided to the second gate line 1230.

[0140] The first conductive layer 1200 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the first conductive layer 1200 may include a silver (Ag)-containing alloy, molybdenum (Mo), a Mo-containing alloy, aluminum (Al), an Al-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), and / or the like.

[0141] The second gate insulating layer 120 (for example, see Figure 17 ) may cover the first conductive layer 1200 and may be disposed on the first gate insulating layer 110. The second gate insulating layer 120 may be disposed on the first gate line 1210, the first gate electrode 1220, and the second gate line 1230. The second gate insulating layer 120 may be disposed between the first conductive layer 1200 and the second conductive layer 1300 described in more detail below. Similar to the first gate insulating layer 110, the second gate insulating layer 120 may include an insulating material.

[0142] Figure 11 The second conductive layer 1300 is shown.

[0143] With Figure 7 and Figure 17 referred to together Figure 11 , the second conductive layer 1300 may be disposed on the second gate insulating layer 120 (for example, see Figure 17 ). The second conductive layer 1300 may be disposed on the first conductive layer 1200. The second conductive layer 1300 may include a third gate line 1310, a fourth gate line 1320, a capacitor electrode 1330 (for example, Figure 6 's second electrode CE2) and a first initialization voltage line 1340 (for example, Figure 6 's first initialization voltage line VL1). In other words, the third gate line 1310, the fourth gate line 1320, the capacitor electrode 1330, and the first initialization voltage line 1340 may be disposed at the same layer (for example, middle or upper) with respect to each other.

[0144] The third gate line 1310 may extend in a first direction (e.g., the x direction). The third gate line 1310 may correspond to the previous scan line SLp (e.g., see Figure 6 ). In a plan view, the third gate line 1310 may be spaced apart from the first gate line 1210. The previous scan signal Sn-1 (e.g., see Figure 6 ) may be provided to the third gate line 1310.

[0145] The fourth gate line 1320 may correspond to the second scan line SL2 (e.g., see Figure 6 ). In a plan view, the fourth gate line 1320 may be spaced apart from the first gate line 1210 and the third gate line 1310. The second scan signal Sn' (e.g., see Figure 6 ) may be provided to the fourth gate line 1320.

[0146] The capacitor electrode 1330 may overlap with the first gate electrode 1220. The capacitor electrode 1330 may overlap with at least a part of the first transmission pattern 1530 (e.g., see Figure 13 ) described in more detail below. The capacitor electrode 1330 may be disposed between the first gate electrode 1220 and the first transmission pattern 1530 (e.g., see Figure 13 ). The capacitor electrode 1330 may have an opening 1330OP passing through the capacitor electrode 1330. The opening 1330OP defined in the capacitor electrode 1330 may expose a part of the first gate electrode 1220. A part of the capacitor electrode 1330 may be included in the first pixel circuit PC1, and another part of the capacitor electrode 1330 may be included in the second pixel circuit PC2. The part of the capacitor electrode 1330 corresponding to the first pixel circuit PC1 and the part of the capacitor electrode 1330 corresponding to the second pixel circuit PC2 may be symmetric or substantially symmetric with respect to an imaginary line.

[0147] The capacitor electrode 1330 and the first gate electrode 1220 may constitute a storage capacitor Cst. In other words, the storage capacitor Cst may include the first gate electrode 1220 and the capacitor electrode 1330. The first gate electrode 1220 may be the gate electrode of the driving thin film transistor T1 and may be the first electrode CE1 of the storage capacitor Cst. The capacitor electrode 1330 may be the second electrode CE2 of the storage capacitor Cst. The driving voltage ELVDD (e.g., see Figure 6 ) may be provided to the capacitor electrode 1330.

[0148] The first initialization voltage line 1340 may extend in a first direction (e.g., the x direction). In a plan view, the first initialization voltage line 1340 may be spaced apart from the third gate line 1310. The first initialization voltage Vint1 (e.g., see Figure 6) may be provided through the first initialization voltage line 1340. The first initialization voltage line 1340 may at least partially overlap with the second semiconductor layer 1400 described in more detail below, and may transmit the first initialization voltage Vint1 to the second semiconductor layer 1400. The first initialization voltage line 1340 may be electrically connected to the second semiconductor layer 1400 through contact holes 1630CNT1 and 1630CNT2 defined in the third transmission pattern 1630 described in more detail below with reference to Figure 15 The first initialization voltage line 1340 may be the Figure 6 first initialization voltage line VL1.

[0149] The second conductive layer 1300 may include, for example, metal, alloy, conductive metal oxide, transparent conductive material, or the like.

[0150] The first interlayer insulating layer 130 (e.g., see Figure 17 ) may cover the second conductive layer 1300 and may be disposed on the second gate insulating layer 120. The first interlayer insulating layer 130 may be disposed on the third gate line 1310, the fourth gate line 1320, the capacitor electrode 1330, and the first initialization voltage line 1340. The first interlayer insulating layer 130 may be disposed between the second conductive layer 1300 and the second semiconductor layer 1400 described in more detail below. For example, the first interlayer insulating layer 130 may be disposed between the capacitor electrode 1330 and the second semiconductor layer 1400. The first interlayer insulating layer 130 may include an insulating material. For example, the first interlayer insulating layer 130 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

[0151] Figure 12 The second semiconductor layer 1400 is shown.

[0152] In conjunction with Figure 7 and Figure 17 with reference to Figure 12 , the second semiconductor layer 1400 may be disposed on the first interlayer insulating layer 130. The second semiconductor layer 1400 may be disposed on the second conductive layer 1300. In this embodiment, the second semiconductor layer 1400 may include an oxide semiconductor. The second semiconductor layer 1400 may be disposed in a layer different from the layer where the first semiconductor layer 1100 is disposed (e.g., middle or upper). The second semiconductor layer 1400 may not overlap with the first semiconductor layer 1100.

[0153] The third gate insulating layer 140 (e.g., see Figure 17)It can cover the second semiconductor layer 1400 and can be disposed on the first interlayer insulating layer 130. The third gate insulating layer 140 can be disposed between the second semiconductor layer 1400 and the third conductive layer 1500 which will be described in more detail below. The third gate insulating layer 140 can include an insulating material. For example, the third gate insulating layer 140 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

[0154] In an embodiment, as Figure 17 shown, the third gate insulating layer 140 can cover the entire or substantially the entire second semiconductor layer 1400. In another embodiment, the third gate insulating layer 140 can be a pattern covering a part of the second semiconductor layer 1400 and can expose the remaining part. For example, the third gate insulating layer 140 can include a pattern that is the same as or substantially the same as the pattern of the third conductive layer 1500.

[0155] Figure 13 The third conductive layer 1500 is shown. Figure 14 The arrangement of the compensation thin film transistor T3 and the first initialization thin film transistor T4 is shown, and together with Figure 12 the second semiconductor layer 1400 and Figure 13 the third conductive layer 1500 are shown together.

[0156] With Figure 7 and Figure 17 referring together to Figure 13 and Figure 14 , the third conductive layer 1500 can be disposed on the third gate insulating layer 140. The third conductive layer 1500 can be disposed on the second semiconductor layer 1400. The third conductive layer 1500 can include a second gate electrode 1510, a fifth gate line 1520, and a first transmission pattern 1530. In other words, the second gate electrode 1510, the fifth gate line 1520, and the first transmission pattern 1530 can be disposed at the same layer (e.g., middle or upper) with respect to each other.

[0157] The second gate electrode 1510 (e.g., gate pattern) can overlap with the third gate line 1310 and the second semiconductor layer 1400. In this embodiment, the second gate electrode 1510 can be electrically connected to the third gate line 1310. For example, the second gate electrode 1510 can contact the third gate line 1310 through a contact hole 1510CNT. The second gate electrode 1510 can include a contact portion in the contact hole 1510CNT, and the contact portion of the second gate electrode 1510 can contact the third gate line 1310. The contact hole 1510CNT overlapping with the second gate electrode 1510 can penetrate through the insulating layers (e.g., the first interlayer insulating layer 130 and the third gate insulating layer 140) disposed between the third gate line 1310 and the second gate electrode 1510.

[0158] The previous scan signal Sn-1 (for example, see Figure 6 ) may be provided to the second gate electrode 1510. The third gate line 1310, the second semiconductor layer 1400, and the second gate electrode 1510 may form a first initialization thin film transistor T4. The first initialization thin film transistor T4 may include the second semiconductor layer 1400 and the second gate electrode 1510 overlapping at least a part of the second semiconductor layer 1400. The first initialization thin film transistor T4 may include the second semiconductor layer 1400, the second gate electrode 1510, and the third gate line 1310 overlapping at least partially with the second semiconductor layer 1400. For example, the third gate line 1310 may correspond to the back gate electrode of the first initialization thin film transistor T4, and the second gate electrode 1510 may correspond to the gate electrode of the first initialization thin film transistor T4.

[0159] The fifth gate line 1520 may extend in a first direction (for example, the x direction). The fifth gate line 1520 may overlap with the fourth gate line 1320 and the second semiconductor layer 1400. In some embodiments, the fifth gate line 1520 may be electrically connected to the fourth gate line 1320. For example, the fifth gate line 1520 may contact the fourth gate line 1320 through a contact hole 1520CNT. The fifth gate line 1520 may include a contact portion in the contact hole 1520CNT, and the contact portion of the fifth gate line 1520 may contact the fourth gate line 1320. The contact hole 1520CNT overlapping with the fifth gate line 1520 may pass through an insulating layer (for example, the first interlayer insulating layer 130 and the third gate insulating layer 140) disposed between the fourth gate line 1320 and the fifth gate line 1520.

[0160] The second scan signal Sn' (for example, see Figure 6 ) may be provided to the fifth gate line 1520. The fourth gate line 1320, the second semiconductor layer 1400, and the fifth gate line 1520 may form a compensation thin film transistor T3. The compensation thin film transistor T3 may include the second semiconductor layer 1400 and the fifth gate line 1520 overlapping at least a part of the second semiconductor layer 1400. The portion of the fifth gate line 1520 overlapping with the second semiconductor layer 1400 may be the gate electrode of the compensation thin film transistor T3. The compensation thin film transistor T3 may include the second semiconductor layer 1400, the fifth gate line 1520, and the fourth gate line 1320 overlapping at least partially with the second semiconductor layer 1400. For example, the fourth gate line 1320 may correspond to the back gate electrode of the compensation thin film transistor T3, and the fifth gate line 1520 may correspond to the gate electrode of the compensation thin film transistor T3.

[0161] The first transmission pattern 1530 may be electrically connected to the first gate electrode 1220 through the contact hole 1530CNT. For example, the first transmission pattern 1530 may be in contact with the first gate electrode 1220 through the contact hole 1530CNT. The first transmission pattern 1530 may include a contact portion in the contact hole 1530CNT, and the contact portion of the first transmission pattern 1530 may be in contact with the first gate electrode 1220. The contact hole 1530CNT overlapping the first transmission pattern 1530 may pass through an insulating layer (e.g., the second gate insulating layer 120, the first interlayer insulating layer 130, and the third gate insulating layer 140) disposed between the first gate electrode 1220 and the first transmission pattern 1530).

[0162] Hereinafter, a plurality of insulating layers including the second gate insulating layer 120, the first interlayer insulating layer 130, and the third gate insulating layer 140 may be referred to as an insulating structure IS (e.g., see Figure 17 ). In other words, the insulating structure IS through which the contact hole 1530CNT defined in the first transmission pattern 1530 passes may include the second gate insulating layer 120, the first interlayer insulating layer 130, and the third gate insulating layer 140. The second gate insulating layer 120, the first interlayer insulating layer 130, and the third gate insulating layer 140 may be referred to as the first insulating layer, the second insulating layer, and the third insulating layer of the insulating structure IS, respectively. The insulating structure IS may be disposed between the first conductive layer 1200 and the third conductive layer 1500. For example, as Figure 17 shown, the insulating structure IS may be disposed between the first gate electrode 1220 and the fifth gate line 1520. For example, the insulating structure IS may be disposed between the first gate electrode 1220 and the second gate electrode 1510).

[0163] The contact hole 1530CNT overlapping the first transmission pattern 1530 may overlap an opening 1330OP defined in the capacitor electrode 1330. The first transmission pattern 1530 may be in contact with the first gate electrode 1220 exposed through the opening 1330OP defined in the capacitor electrode 1330).

[0164] The first transmission pattern 1530 may be electrically connected to a second transmission pattern 1620 described in more detail below (e.g., see Figure 15 ). As the second transmission pattern 1620 (e.g., see Figure 15 ) connects the first transmission pattern 1530 and the second semiconductor layer 1400 to each other, the second semiconductor layer 1400 and the first gate electrode 1220 may be electrically connected to each other. As a third transmission pattern 1630 (e.g., see Figure 15 ) described in more detail below connects the second semiconductor layer 1400 and the first initialization voltage line 1340 to each other, the first transmission pattern 1530 may transmit the first initialization voltage Vint1 to the first gate electrode 1220).

[0165] The second interlayer insulating layer 150 (for example, see Figure 17 ) may cover the third conductive layer 1500 and may be disposed on the third gate insulating layer 140. The second interlayer insulating layer 150 may be disposed between the third conductive layer 1500 and the fourth conductive layer 1600 described in more detail below. The second interlayer insulating layer 150 may include an insulating material. For example, the second interlayer insulating layer 150 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

[0166] Figure 15 The fourth conductive layer 1600 is shown.

[0167] With Figure 7 and Figure 17 referring together to Figure 15 , the fourth conductive layer 1600 may be disposed on the second interlayer insulating layer 150. The fourth conductive layer 1600 may be disposed on the third conductive layer 1500. For example, the first connection line 1610 may be disposed on the second gate electrode 1510. The fourth conductive layer 1600 may include the first connection line 1610, the second transmission pattern 1620, the third transmission pattern 1630, the fourth transmission pattern 1640, the second initialization voltage line 1650, the fifth transmission pattern 1660, the sixth transmission pattern 1670, and the seventh transmission pattern 1680. In other words, the first connection line 1610, the second transmission pattern 1620, the third transmission pattern 1630, the fourth transmission pattern 1640, the second initialization voltage line 1650, the fifth transmission pattern 1660, the sixth transmission pattern 1670, and the seventh transmission pattern 1680 may be disposed at the same layer (for example, middle or upper) with respect to each other.

[0168] The first connection line 1610 may extend in a first direction (for example, the x direction). A data signal Dm (for example, see Figure 6 ) may be provided to the first connection line 1610.

[0169] The second transmission pattern 1620 may be disposed on the first transmission pattern 1530 and may overlap a part of the first transmission pattern 1530. The second transmission pattern 1620 may electrically connect the second semiconductor layer 1400 and the first transmission pattern 1530 to each other. The second transmission pattern 1620 may be electrically connected to the second semiconductor layer 1400 and the first transmission pattern 1530. For example, the second transmission pattern 1620 may contact the second semiconductor layer 1400 and the first transmission pattern 1530 through contact holes 1620CNT1 and 1620CNT2 positioned on one side and the other side of the second transmission pattern 1620, respectively. The second transmission pattern 1620 may include contact portions disposed in the contact holes 1620CNT1 and 1620CNT2 positioned on one side and the other side of the second transmission pattern 1620, respectively. The contact portion on one side of the second transmission pattern 1620 may contact the second semiconductor layer 1400, and the contact portion on the other side of the second transmission pattern 1620 may contact the first transmission pattern 1530. The contact hole 1620CNT1 overlapping the second semiconductor layer 1400 on one side of the second transmission pattern 1620 may penetrate through an insulating layer (e.g., the third gate insulating layer 140 and the second interlayer insulating layer 150) disposed between the second semiconductor layer 1400 and the second transmission pattern 1620. The contact hole 1620CNT2 overlapping the first transmission pattern 1530 on the other side of the second transmission pattern 1620 may penetrate through an insulating layer (e.g., the second interlayer insulating layer 150) disposed between the first transmission pattern 1530 and the second transmission pattern 1620.

[0170] The third transmission pattern 1630 may be electrically connected to the second semiconductor layer 1400 and the first initialization voltage line 1340. For example, the third transmission pattern 1630 may contact the second semiconductor layer 1400 and the first initialization voltage line 1340 through contact holes 1630CNT1 and 1630CNT2 positioned on one side and the other side of the third transmission pattern 1630, respectively. The third transmission pattern 1630 may include contact portions disposed in the contact holes 1630CNT1 and 1630CNT2 positioned on one side and the other side of the third transmission pattern 1630, respectively. The contact portion on one side of the third transmission pattern 1630 may contact the second semiconductor layer 1400, and the contact portion on the other side of the third transmission pattern 1630 may contact the first initialization voltage line 1340. Accordingly, the third transmission pattern 1630 may apply the first initialization voltage Vint1 (e.g., see Figure 6)It is transmitted to the first initialization thin film transistor T4. The contact hole 1630CNT1 overlapping with the second semiconductor layer 1400 on one side of the third transmission pattern 1630 can pass through the insulating layers (e.g., the third gate insulating layer 140 and the second interlayer insulating layer 150) disposed between the second semiconductor layer 1400 and the third transmission pattern 1630. The contact hole 1630CNT2 overlapping with the first initialization voltage line 1340 on the other side of the third transmission pattern 1630 can pass through the insulating layers (e.g., the first interlayer insulating layer 130, the third gate insulating layer 140, and the second interlayer insulating layer 150) disposed between the first initialization voltage line 1340 and the third transmission pattern 1630).

[0171] The fourth transmission pattern 1640 can be electrically connected to the first semiconductor layer 1100. For example, the fourth transmission pattern 1640 can be in contact with the first semiconductor layer 1100 through the contact hole 1640CNT. The fourth transmission pattern 1640 can include a contact portion in the contact hole 1640CNT, and the contact portion of the fourth transmission pattern 1640 can be in contact with the first semiconductor layer 1100. The fourth transmission pattern 1640 can be electrically connected to the data line 1710 described in more detail below (e.g., see Figure 16 ). Accordingly, the data signal Dm provided to the data line 1710 can be transmitted to the first semiconductor layer 1100 through the fourth transmission pattern 1640. The contact hole 1640CNT overlapping with the fourth transmission pattern 1640 can pass through the insulating layers (e.g., the first gate insulating layer 110, the second gate insulating layer 120, the first interlayer insulating layer 130, the third gate insulating layer 140, and the second interlayer insulating layer 150) disposed between the first semiconductor layer 1100 and the fourth transmission pattern 1640).

[0172] The second initialization voltage line 1650 (e.g., Figure 6 the second initialization voltage line VL2) can extend in the first direction (e.g., the x direction). The second initialization voltage Vint2 (e.g., see Figure 6 ) can be provided to the second initialization voltage line 1650. The second initialization voltage line 1650 can be in contact with the first semiconductor layer 1100 through the contact hole 1650CNT, and can transmit the second initialization voltage Vint2 to the first semiconductor layer 1100. The second initialization voltage line 1650 can include a contact portion in the contact hole 1650CNT, and the contact portion of the second initialization voltage line 1650 can be in contact with the first semiconductor layer 1100. The contact hole 1650CNT overlapping with the second initialization voltage line 1650 can pass through the insulating layers (e.g., the first gate insulating layer 110, the second gate insulating layer 120, the first interlayer insulating layer 130, the third gate insulating layer 140, and the second interlayer insulating layer 150) disposed between the second initialization voltage line 1650 and the first semiconductor layer 1100).

[0173] The fifth transmission pattern 1660 may be electrically connected to the second semiconductor layer 1400 and the first semiconductor layer 1100. For example, the fifth transmission pattern 1660 may be in contact with the second semiconductor layer 1400 and the first semiconductor layer 1100 through contact holes 1660CNT1 and 1660CNT2 positioned on one side and the other side of the fifth transmission pattern 1660, respectively. The fifth transmission pattern 1660 may include contact portions disposed in the contact holes 1660CNT1 and 1660CNT2 positioned on one side and the other side of the fifth transmission pattern 1660, respectively. The contact portion on one side of the fifth transmission pattern 1660 may be in contact with the second semiconductor layer 1400, and the contact portion on the other side of the fifth transmission pattern 1660 may be in contact with the first semiconductor layer 1100. Accordingly, the fifth transmission pattern 1660 may electrically connect the second semiconductor layer 1400 and the first semiconductor layer 1100 to each other. The contact hole 1660CNT1 overlapping with the second semiconductor layer 1400 on one side of the fifth transmission pattern 1660 may pass through an insulating layer (e.g., the third gate insulating layer 140 and the second interlayer insulating layer 150) disposed between the second semiconductor layer 1400 and the fifth transmission pattern 1660. The contact hole 1660CNT2 overlapping with the first semiconductor layer 1100 on the other side of the fifth transmission pattern 1660 may pass through an insulating layer (e.g., the first gate insulating layer 110, the second gate insulating layer 120, the first interlayer insulating layer 130, the third gate insulating layer 140, and the second interlayer insulating layer 150) disposed between the first semiconductor layer 1100 and the fifth transmission pattern 1660.

[0174] The sixth transmission pattern 1670 may extend in a first direction (e.g., the x direction). The sixth transmission pattern 1670 may be electrically connected to the first semiconductor layer 1100 and the capacitor electrode 1330. For example, the sixth transmission pattern 1670 may be in contact with the first semiconductor layer 1100 and the capacitor electrode 1330 through contact holes 1670CNT1 and 1670CNT2 positioned on one side and the other side of the sixth transmission pattern 1670, respectively. The sixth transmission pattern 1670 may include contact portions disposed in the contact holes 1670CNT1 and 1670CNT2 positioned on one side and the other side of the sixth transmission pattern 1670, respectively. The contact portion on one side of the sixth transmission pattern 1670 may be in contact with the first semiconductor layer 1100, and the contact portion on the other side of the sixth transmission pattern 1670 may be in contact with the capacitor electrode 1330. The driving voltage ELVDD (e.g., see Figure 6 ) may be supplied through a voltage line 1730 described in more detail below (e.g., see Figure 16)Provided to the sixth transmission pattern 1670. Since the sixth transmission pattern 1670 can be in contact with the first semiconductor layer 1100 through the contact hole 1670CNT1, the driving voltage ELVDD can be transmitted to the first semiconductor layer 1100. The contact hole 1670CNT1 overlapping with the first semiconductor layer 1100 on one side of the sixth transmission pattern 1670 can pass through the insulating layers (e.g., the first gate insulating layer 110, the second gate insulating layer 120, the first interlayer insulating layer 130, the third gate insulating layer 140, and the second interlayer insulating layer 150) disposed between the first semiconductor layer 1100 and the sixth transmission pattern 1670. The contact hole 1670CNT2 overlapping with the capacitor electrode 1330 on the other side of the sixth transmission pattern 1670 can pass through the insulating layers (e.g., the first interlayer insulating layer 130, the third gate insulating layer 140, and the second interlayer insulating layer 150) disposed between the capacitor electrode 1330 and the sixth transmission pattern 1670.

[0175] The seventh transmission pattern 1680 can be electrically connected to the first semiconductor layer 1100. For example, the seventh transmission pattern 1680 can be in contact with the first semiconductor layer 1100 through the contact hole 1680CNT. The seventh transmission pattern 1680 can include a contact portion in the contact hole 1680CNT, and the contact portion of the seventh transmission pattern 1680 can be in contact with the first semiconductor layer 1100. The seventh transmission pattern 1680 can transmit the driving current or the second initialization voltage Vint2 (e.g., see Figure 6 ) from the first semiconductor layer 1100 to the organic light emitting diode OLED.

[0176] The first planarization insulating layer 160 (e.g., see Figure 17 ) can cover the fourth conductive layer 1600 and can be disposed on the second interlayer insulating layer 150. The first planarization insulating layer 160 can be disposed between the fourth conductive layer 1600 and the fifth conductive layer 1700 (e.g., see Figure 16 ) described in more detail below. The first planarization insulating layer 160 can contain an organic insulating material. For example, the first planarization insulating layer 160 can contain photoresist, polyacrylic acid-based resin, polyimide-based resin, acrylic acid-based resin, or the like.

[0177] With Figure 7 And Figure 17 Refer to together Figure 16, the fifth conductive layer 1700 may be disposed on the first planarization insulating layer 160. The fifth conductive layer 1700 may be disposed on the fourth conductive layer 1600. The fifth conductive layer 1700 may include data lines 1710, second connection lines 1720, voltage lines 1730, and eighth transmission patterns 1740. In other words, the data lines 1710, second connection lines 1720, voltage lines 1730, and eighth transmission patterns 1740 may be disposed at the same layer as each other (e.g., middle or upper).

[0178] The data lines 1710 may extend in the second direction (e.g., the y direction). The data lines 1710 may correspond to Figure 6 the data lines DL. The data lines 1710 may be connected to the fourth transmission patterns 1640 through contact holes 1710CNT. The data signal Dm (e.g., see Figure 6 ) may be transmitted to the first semiconductor layer 1100 through the data lines 1710 and the fourth transmission patterns 1640.

[0179] The second connection lines 1720 may extend in the second direction (e.g., the y direction). The second connection lines 1720 may be disposed on the first connection lines 1610. In an embodiment, the second connection lines 1720 may be in contact with the first connection lines 1610. The second connection lines 1720 may be electrically connected to the first connection lines 1610.

[0180] In an embodiment, the first connection lines 1610 may correspond to the first connection lines DH1 to DH3 (e.g., see Figure 5 ), the data lines 1710 may correspond to the first data lines DL1 to the sixth data lines DL6 (e.g., see Figure 5 ), and the second connection lines 1720 may correspond to the second connection lines DV1 to DV3 or the third connection lines DV1' to DV3' described above with reference to Figure 5 .

[0181] For example, the data lines 1710 and the second connection lines 1720 may receive different data voltages from each other. For example, a first data voltage may be transmitted to the first semiconductor layer 1100 through the data lines 1710, and a second data voltage different from the first data voltage may be transmitted to the first connection lines 1610 through the second connection lines 1720. The same data signal may be applied to the first connection lines 1610 and the second connection lines 1720.

[0182] The voltage lines 1730 may extend in the second direction (e.g., the y direction). The voltage lines 1730 may correspond to Figure 6 the driving voltage lines PL. The voltage lines 1730 may provide a driving voltage ELVDD (e.g., see Figure 6 ). The voltage lines 1730 may be connected to the sixth transmission patterns 1670 through contact holes 1730CNT, and may transmit the driving voltage ELVDD (e.g., seeFigure 6 ) is supplied to the capacitor electrode 1330 and the operation control thin film transistor T5.

[0183] In an embodiment, the voltage line 1730 may be provided in each of the first pixel circuit PC1 and the second pixel circuit PC2. In another embodiment, the voltage line 1730 may be shared by the first pixel circuit PC1 and the second pixel circuit PC2 adjacent to each other.

[0184] The eighth transmission pattern 1740 may be in contact with the seventh transmission pattern 1680 through the contact hole 1740CNT1 on one side thereof. The eighth transmission pattern 1740 may transmit the driving current I OLED or the second initialization voltage Vint2 (for example, see Figure 6 ) to the organic light emitting diode OLED.

[0185] In addition, the eighth transmission pattern 1740 may be in contact with the pixel electrode 210 (for example, see Figure 17 ) through the contact hole 1740CNT2 on the other side. The emission control thin film transistor T6 may be electrically connected to the pixel electrode 210 through the eighth transmission pattern 1740.

[0186] The second planarization layer 170 may cover the fifth conductive layer 1700 and may be disposed on the first planarization insulating layer 160. The second planarization layer 170 may include an organic insulating material. For example, the first planarization insulating layer 160 and the second planarization layer 170 may include a general polymer (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a parylene polymer, a vinyl alcohol-based polymer, and / or any suitable blend thereof.

[0187] Referring to Figure 17 , the organic light emitting diode OLED may be disposed on the second planarization layer 170. The organic light emitting diode OLED may include a pixel electrode 210, an intermediate layer 220 including an organic emission layer, and a counter electrode 230.

[0188] The pixel electrode 210 may be a (semi-) transmissive electrode or a reflective electrode. In an embodiment, the pixel electrode 210 may include a reflective layer containing Ag, magnesium (Mg), Al, Pt, palladium (Pd), gold (Au), Ni, neodymium (Nd), iridium (Ir), Cr, or the like, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the pixel electrode 210 may be provided as ITO / Ag / ITO.

[0189] The pixel defining layer 180 may be disposed on the second planarization layer 170. The pixel defining layer 180 may prevent or substantially prevent arcing or the like at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the counter electrode 230 on the pixel electrode 210.

[0190] The pixel defining layer 180 may include one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, BCB, and phenolic resin, and may be formed by spin coating or a similar method.

[0191] The intermediate layer 220 of the organic light emitting diode OLED may be disposed in the opening 180OP formed by the pixel defining layer 180. The emission region EA of the organic light emitting diode OLED may be defined by the opening 180OP defined in the pixel defining layer 180.

[0192] The intermediate layer 220 may include an organic emission layer. The organic emission layer may include an organic material containing a fluorescent or phosphorescent material that emits red light, green light, blue light, or white light. The organic emission layer may be a low molecular weight organic material or a polymeric organic material. Below and above the organic emission layer, functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and / or an electron injection layer (EIL) may also be selectively disposed.

[0193] The organic emission layer may be arranged to correspond to each pixel electrode 210 provided for each pixel P (e.g., see Figure 3 ). In addition to the organic emission layer, the intermediate layer 220 may include a layer that is integral across a plurality of pixel electrodes 210, and various appropriate modifications may be made.

[0194] The counter electrode 230 may be a transmissive electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or semi-transparent electrode and may include a metal thin film with a low work function containing lithium (Li), calcium (Ca), lithium fluoride (LiF), Al, Ag, Mg, their suitable compounds, and / or materials having a multilayer structure such as LiF / Ca or LiF / Al. Additionally, a transparent conductive oxide (TCO) film containing ITO, IZO, ZnO, or In2O3 may be disposed on the metal thin film. The counter electrode 230 may be integrally formed across the entire or substantially the entire surface of the display area DA (e.g., see Figure 3 ) and may be disposed throughout the intermediate layer 220 and the pixel defining layer 180.

[0195] Figure 18 is a schematic enlarged plan view showing some layers in region B of Figure 7 . Figure 19 is a schematic cross-sectional view taken along line I-I' of Figure 18 .

[0196] Referring to Figure 18 and Figure 19 , the first semiconductor layer 1100, the first gate electrode 1220, the capacitor electrode 1330, and the first transmission pattern 1530 are shown. A portion of the first gate electrode 1220 may overlap with the first semiconductor layer 1100 and may constitute the driving thin film transistor T1. The first semiconductor layer 1100 may include a channel region C overlapping with the first gate electrode 1220 and a source region S and a drain region D disposed on opposite sides of the channel region C, respectively. The first gate electrode 1220 and the capacitor electrode 1330 may constitute a storage capacitor Cst (e.g., see Figure 6 ).

[0197] The first gate electrode 1220 may be disposed on the first gate insulating layer 110. The insulating structure IS may be disposed on the first gate electrode 1220. The insulating structure IS may be disposed between the first gate electrode 1220 and the first transmission pattern 1530. The insulating structure IS may include a second gate insulating layer 120, a first interlayer insulating layer 130, and a third gate insulating layer 140. The second gate insulating layer 120 may be disposed on the first gate electrode 1220. The second gate insulating layer 120 may be disposed between the first gate electrode 1220 and the capacitor electrode 1330. The first interlayer insulating layer 130 may be disposed on the capacitor electrode 1330. The first interlayer insulating layer 130 may be disposed between the capacitor electrode 1330 and the third gate insulating layer 140. The first interlayer insulating layer 130 may be disposed between the capacitor electrode 1330 and the first transmission pattern 1530. The third gate insulating layer 140 may be disposed between the first transmission pattern 1530 and the first interlayer insulating layer 130.

[0198] Hereinafter, the inclination of the inner wall of the insulating structure IS formed by the contact hole 1530CNT passing through (e.g., penetrating) the insulating structure IS may be referred to as the taper angle θ1. In other words, the taper angle θ1 of the insulating structure IS may be the angle between the upper surface of the first gate electrode 1220 and the inner wall of the insulating structure IS in the region where the upper surface of the first gate electrode 1220 and the first transmission pattern 1530 overlap each other. The first transmission pattern 1530 may be disposed on the inner wall of the insulating structure IS.

[0199] The taper angle θ1 of the insulating structure IS may be in the range of about 40° to about 75°. Since the taper angle θ1 of the insulating structure IS can be formed to be about 75° or less, the thickness TH1 of the first portion 1531a of the first layer 1531 of the first transmission pattern 1530, which will be described in more detail below, can be formed to be relatively large. When the taper angle θ1 of the insulating structure IS is less than about 40°, the size of the first transmission pattern 1530 may become too large, making it more difficult to achieve high resolution.

[0200] At least a part of the first transmission pattern 1530 may overlap with the driving thin film transistor T1. The first transmission pattern 1530 may be electrically connected to the first gate electrode 1220 through the contact hole 1530CNT passing through (e.g., penetrating) the insulating structure IS. The contact portion of the first transmission pattern 1530 may overlap with the opening 1330OP defined in the capacitor electrode 1330. The first transmission pattern 1530 may be electrically connected to the first gate electrode 1220 exposed through the opening 1330OP defined in the capacitor electrode 1330.

[0201] The first transmission pattern 1530 may include a first layer 1531 and a second layer 1532 on the first layer 1531. The first layer 1531 and the second layer 1532 of the first transmission pattern 1530 may be referred to as a lower conductive layer and an upper conductive layer, respectively. Similar to the structure of the first transmission pattern 1530, the conductive layer (e.g., the second gate electrode 1510 and the fifth gate line 1520 (e.g., see Figure 13 )) disposed on the layer on which the first transmission pattern 1530 is disposed may have a double-layer structure including a lower conductive layer and an upper conductive layer.

[0202] The first layer 1531 of the first transmission pattern 1530 may contain a conductive material that adsorbs hydrogen (H). The first layer 1531 of the first transmission pattern 1530 may contain, for example, Ti.

[0203] The first layer 1531 of the first transmission pattern 1530 may include a first portion 1531a disposed in the contact hole 1530CNT and a second portion 1531b disposed outside the contact hole 1530CNT. The thickness TH2 of the second portion 1531b of the first layer 1531 may be equal to or greater than the thickness TH1 of the first portion 1531a of the first layer 1531.

[0204] For example, the thickness TH1 of the first portion 1531a of the first layer 1531 may be in the range of about to about For example, the thickness TH1 of the first portion 1531a of the first layer 1531 may be in the range of about to about When the thickness TH1 of the first portion 1531a of the first layer 1531 is less than about as described in more detail below with reference to Table 1, during the heat treatment process operation, the distribution of hydrogen adsorbed by the first layer 1531 of the first transfer pattern 1530 may be non-uniform, which may cause spot defects. In an embodiment, the thickness TH1 of the first portion 1531a of the first layer 1531 of the first transfer pattern 1530 may be formed to be about or greater, and thus the spot defects may be reduced.

[0205] In an embodiment, since the taper angle θ1 of the insulating structure IS may be formed in the range of about 40° to about 75°, the thickness TH1 of the first portion 1531a of the first layer 1531 may be more easily formed to be about or greater.

[0206] For example, the thickness TH2 of the second portion 1531b of the first layer 1531 may be in the range of about to about For example, the thickness TH2 of the second portion 1531b of the first layer 1531 may be in the range of about to about When the thickness TH2 of the second portion 1531b of the first layer 1531 is less than the thickness TH1 of the first portion 1531a of the first layer 1531 may be formed to be less than In an embodiment, the thickness TH2 of the second portion 1531b of the first layer 1531 may be formed to be about or greater to reduce spot defects and improve the display quality of the display device. When the thickness TH1 of the first portion 1531a and the thickness TH2 of the second portion 1531b of the first layer 1531 exceed it may be more difficult to achieve a thin display device.

[0207] Table 1 below shows the spot defect rates of comparative examples and some embodiments in which the thickness of the first layer 1531 of the first transfer pattern 1530 of the present disclosure varies.

[0208] Table 1

[0209]

[0210] As shown in Table 1, the maximum thickness and the stipple defect rate of the first part 1531a formed when the thickness of the second part 1531b of the first layer 1531 of the first transfer pattern 1530 is formed as , and in the comparative example, Example 1, Example 2, and Example 3 are shown. The stipple defect rate is measured by the brightness difference around the stipples.

[0211] Referring to Table 1, in the comparative example, when the thickness of the second part 1531b of the first layer 1531 of the first transfer pattern 1530 is formed to be less than of , the maximum thickness of the first part 1531a of the first layer 1531 is and the stipple defect rate of the first part 1531a of the first layer 1531 is 25%. In Example 1, when the thickness of the second part 1531b of the first layer 1531 of the first transfer pattern 1530 is formed as , the maximum thickness of the first part 1531a of the first layer 1531 is and the stipple defect rate of the first part 1531a is 3%. Accordingly, when the thickness of the second part 1531b of the first layer 1531 of the first transfer pattern 1530 is or greater, the thickness of the first part 1531a of the first layer 1531 can be formed to be about or greater, and the defect rate can be significantly reduced compared to when the thickness of the second part 1531b is less than .

[0212] In addition, according to Example 2, when the thickness of the second part 1531b of the first layer 1531 of the first transfer pattern 1530 is formed as , the maximum thickness of the first part 1531a of the first layer 1531 is and the stipple defect rate of the first part 1531a is 0.6%. According to Example 3, when the thickness of the second part 1531b of the first layer 1531 of the first transfer pattern 1530 is formed as , the maximum thickness of the first part 1531a of the first layer 1531 is and the stipple defect rate of the first part 1531a is 0.6%. As described above, when the thickness of the second part 1531b of the first layer 1531 of the first transfer pattern 1530 is or greater, the maximum thickness of the first part 1531a of the first layer 1531 can increase in proportion to the thickness of the second part 1531b, and the stipple defect rate can saturate to about 0.6%.

[0213] Referring toFigure 18 and Figure 19 For Figure 19 , the second layer 1532 of the first transmission pattern 1530 may include a conductive material having a high conductivity. The second layer 1532 of the first transmission pattern 1530 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. The second layer 1532 of the first transmission pattern 1530 may include, for example, Mo, a Mo-containing alloy, Al, an Al-containing alloy, AlN, Ag, an Ag-containing alloy, W, WN, Cu, or the like.

[0214] The thickness TH3 of the second layer 1532 of the first transmission pattern 1530 may be greater than the thickness of the first layer 1531 of the first transmission pattern 1530. In other words, the thickness TH3 of the second layer 1532 of the first transmission pattern 1530 may be greater than the thickness of each of the first portion 1531a and the second portion 1531b of the first layer 1531. In an embodiment, the thickness TH3 of the portion of the second layer 1532 of the first transmission pattern 1530 located in the contact hole 1530CNT may be the same as or substantially the same as the thickness TH3 of the portion located outside the contact hole 1530CNT. However, the present disclosure is not limited thereto. In another embodiment, the thickness TH3 of the portion of the second layer 1532 of the first transmission pattern 1530 located outside the contact hole 1530CNT may be greater than the thickness TH3 of the portion located in the contact hole 1530CNT.

[0215] The second interlayer insulating layer 150 may be disposed on the first transmission pattern 1530.

[0216] Figures 20 to 24 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment. Figures 20 to 24 In correspondence with Figure 19 the cross-sectional view, a method of manufacturing a display device is shown.

[0217] Referring to Figure 20 , a driving thin film transistor T1 may be formed on the substrate 100. A first semiconductor layer 1100 may be formed on the substrate 100. A first gate insulating layer 110 may be formed on the first semiconductor layer 1100. At least a portion of the first gate electrode 1220 may be formed to overlap with the first semiconductor layer 1100.

[0218] In an embodiment, the first semiconductor layer 1100 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, or the like. For example, the first semiconductor layer 1100 may include LTPS.

[0219] The first gate insulating layer 110 may include an insulating material. For example, the first gate insulating layer 110 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

[0220] The first gate electrode 1220 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the first gate electrode 1220 may include Ag, an Ag-containing alloy, Mo, an Mo-containing alloy, Al, an Al-containing alloy, AlN, W, WN, Cu, Ni, Cr, CrN, Ti, Ta, Pt, Sc, ITO, IZO, or the like.

[0221] Next, a second gate insulating layer 120 may be formed on the first gate electrode 1220. The second gate insulating layer 120 may be formed on the first gate insulating layer 110 to cover the first gate electrode 1220. The second gate insulating layer 120 may include an insulating material. For example, the second gate insulating layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

[0222] A capacitor electrode 1330 may be formed on the second gate insulating layer 120. At least a portion of the capacitor electrode 1330 may be formed to overlap with the first gate electrode 1220. The first gate electrode 1220 and the capacitor electrode 1330 may form a storage capacitor. The capacitor electrode 1330 may be formed with an opening 1330OP that exposes a portion of the first gate electrode 1220. The capacitor electrode 1330 may include, for example, a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like.

[0223] Next, a first interlayer insulating layer 130 may be formed on the capacitor electrode 1330. The first interlayer insulating layer 130 may be formed on the second gate insulating layer 120 to cover the capacitor electrode 1330. The first interlayer insulating layer 130 may be disposed in the opening 1330OP defined in the capacitor electrode 1330. For example, the first interlayer insulating layer 130 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

[0224] Referring together Figure 20 and Figure 17 , a second semiconductor layer 1400 may be formed on the first interlayer insulating layer 130. The second semiconductor layer 1400 may be formed not to overlap with the first semiconductor layer 1100. The second semiconductor layer 1400 may include, for example, an oxide semiconductor.

[0225] Next, a third gate insulating layer 140 may be formed on the second semiconductor layer 1400. The third gate insulating layer 140 may be formed on the first interlayer insulating layer 130 to cover the second semiconductor layer 1400. For example, the third gate insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

[0226] Hereinafter, a plurality of insulating layers including a second gate insulating layer 120, a first interlayer insulating layer 130, and a third gate insulating layer 140 may be referred to as an insulating structure IS. The second gate insulating layer 120, the first interlayer insulating layer 130, and the third gate insulating layer 140 may be referred to as a first insulating layer, a second insulating layer, and a third insulating layer of the insulating structure IS, respectively.

[0227] Referring to Figure 21 , a contact hole 1530CNT passing through (e.g., penetrating) the insulating structure IS may be formed. The contact hole 1530CNT of the insulating structure IS may be formed to overlap with the first gate electrode 1220. The contact hole 1530CNT of the insulating structure IS may be formed by removing a portion of each of the second gate insulating layer 120, the first interlayer insulating layer 130, and the third gate insulating layer 140 positioned in a region overlapping with the first gate electrode 1220. The contact hole 1530CNT passing through the insulating structure IS may be formed by an etching process (e.g., a dry etching process).

[0228] The inclination of the inner wall of the insulating structure IS formed by removing the second gate insulating layer 120, the first interlayer insulating layer 130, and the third gate insulating layer 140 may be referred to as a taper angle θ1. The insulating structure IS may be formed to have a taper angle θ1 in the range of about 40° to about 75°. When the taper angle θ1 of the insulating structure IS is about 75° or less, the thickness of the first layer 1531 of the first transfer pattern 1530 formed in a subsequent process (e.g., referring to Figure 23 ) may be formed to be large.

[0229] After forming the contact hole 1530CNT passing through the insulating structure IS, a first heat treatment process ANL1 may be performed. In an embodiment, the first heat treatment process ANL1 may be performed in a temperature range of 370°C to about 380°C for about 10 minutes to about 30 minutes. By performing the first heat treatment process ANL1, hydrogen contained in the plurality of insulating layers and the first semiconductor layer 1100 formed on the substrate 100 may be moved. The hydrogen moved by the first heat treatment process ANL1 may be adsorbed by the first layer 1531 of the first transfer pattern 1530 formed according to a subsequent process (e.g., referring to Figure 23 ).

[0230] Referring to Figure 22 , a preliminary first transfer pattern 1530p may be formed on the insulating structure IS. The preliminary first transfer pattern 1530p may be formed on the third gate insulating layer 140. The preliminary first transfer pattern 1530p may be formed to be in contact with the first gate electrode 1220 through the contact hole 1530CNT.

[0231] The preliminary first transmission pattern 1530p may be formed to include a first preliminary layer 1531p and a second preliminary layer 1532p on the first preliminary layer 1531p. In other words, the first preliminary layer 1531p may be formed on the insulating structure IS, and the second preliminary layer 1532p may be formed on the first preliminary layer 1531p.

[0232] The first preliminary layer 1531p may include a conductive material that adsorbs H. The first preliminary layer 1531p may include, for example, Ti.

[0233] The first preliminary layer 1531p may include a first portion 1531pa disposed in the contact hole 1530CNT and a second portion 1531pb disposed outside the contact hole 1530CNT. For example, the thickness TH2 of the second portion 1531pb of the first preliminary layer 1531p may be formed in the range of about to about . When the thickness TH2 of the second portion 1531pb of the first preliminary layer 1531p is formed in the range of about to about , the thickness TH1 of the first portion 1531pa of the first preliminary layer 1531p may be formed in the range of about to about . Since the taper angle θ1 of the insulating structure IS may be formed to be about 75° or less, the thickness TH1 of the first portion 1531pa of the first preliminary layer 1531p may be more easily formed to be about or greater.

[0234] The second preliminary layer 1532p may include a conductive material having high conductivity. The second preliminary layer 1532p may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. The second preliminary layer 1532p may include, for example, Mo, an Mo-containing alloy, Al, an Al-containing alloy, AlN, Ag, an Ag-containing alloy, W, WN, Cu, or the like.

[0235] Referring to Figure 23 , the first transmission pattern 1530 may be formed by etching Figure 22 the preliminary first transmission pattern 1530p. When the first transmission pattern 1530 is formed by etching the preliminary first transmission pattern 1530p, the second gate electrode 1510 and the fifth gate line 1520 described above with reference to Figure 13 may be formed synchronously or substantially simultaneously. In other words, the second gate electrode 1510 and the fifth gate line 1520 may be formed by etching the preliminary first transmission pattern 1530p. The process of forming the first transmission pattern 1530 by etching the preliminary first transmission pattern 1530p may be, for example, a dry etching process.

[0236] The first transmission pattern 1530 may be electrically connected to the first gate electrode 1220 through the contact hole 1530CNT. The contact portion of the first transmission pattern 1530 may overlap with the opening 1330OP defined in the capacitor electrode 1330. The first transmission pattern 1530 may be electrically connected to the first gate electrode 1220 exposed through the opening 1330OP defined in the capacitor electrode 1330.

[0237] The first transmission pattern 1530 may include a first layer 1531 and a second layer 1532 on the first layer 1531.

[0238] The first layer 1531 of the first transmission pattern 1530 may contain a conductive material that adsorbs H. The first layer 1531 of the first transmission pattern 1530 may contain, for example, Ti.

[0239] The first layer 1531 of the first transmission pattern 1530 may include a first portion 1531a disposed in the contact hole 1530CNT and a second portion 1531b disposed outside the contact hole 1530CNT. For example, the thickness TH2 of the second portion 1531b of the first layer 1531 of the first transmission pattern 1530 may be formed in the range of about to about . When the thickness TH2 of the second portion 1531b of the first layer 1531 of the first transmission pattern 1530 is in the range of about to about , the thickness TH1 of the first portion 1531a of the first layer 1531 of the first transmission pattern 1530 may be in the range of about to about .

[0240] The second layer 1532 of the first transmission pattern 1530 may contain a conductive material having high conductivity. The second layer 1532 of the first transmission pattern 1530 may contain a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. The second layer 1532 of the first transmission pattern 1530 may contain, for example, Mo, an Mo-containing alloy, Al, an Al-containing alloy, AlN, Ag, an Ag-containing alloy, W, WN, Cu, or the like.

[0241] Referring to Figure 24 , a second interlayer insulating layer 150 may be formed on the first transmission pattern 1530. The second interlayer insulating layer 150 may be formed on the third gate insulating layer 140 to cover the first transmission pattern 1530. The second interlayer insulating layer 150 may contain an insulating material. For example, the second interlayer insulating layer 150 may contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

[0242] After forming the second interlayer insulating layer 150, a second heat treatment process ANL2 may be performed. In an embodiment, the second heat treatment process ANL2 may be performed for about 10 minutes to about 30 minutes within a temperature range of 370 °C to about 380 °C. In other words, after forming the first transfer pattern 1530, the second heat treatment process ANL2 may be performed. For example, after forming the second interlayer insulating layer 150 and contact holes passing through a part of the second interlayer insulating layer 150, the second heat treatment process ANL2 may be performed.

[0243] When the second heat treatment process ANL2 is performed, H moved by the first heat treatment process ANL1 can be more easily adsorbed to the first layer 1531 of the first transfer pattern 1530. Accordingly, the adsorption distribution of H can be improved, spot defects can be reduced, and the display quality of the display device can be enhanced.

[0244] According to one or more embodiments of the present disclosure, a display device having improved display quality can be realized by improving the hydrogen adsorption distribution of a transfer pattern connected to a gate electrode of a first thin film transistor. However, aspects and features of the present disclosure are not limited thereto.

[0245] The foregoing is an illustration of some embodiments of the present disclosure and is not to be construed as a limitation thereof. Although some embodiments have been described, those skilled in the art will readily understand that various modifications can be made to the embodiments without departing from the spirit and scope of the present disclosure. It should be understood that, unless otherwise described, the description of features or aspects within each embodiment is generally considered to be available for other similar features or aspects in other embodiments. Thus, as will be apparent to those of ordinary skill in the art, unless otherwise specifically indicated, features, characteristics, and / or elements described in connection with a particular embodiment can be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, it should be understood that the above is an illustration of various exemplary embodiments and is not to be construed as limited to the specific embodiments disclosed herein, and modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, comprising: a substrate; a first transistor, the first transistor comprising: a first semiconductor layer on the substrate; and a first gate electrode on the first semiconductor layer and at least partially overlapping the first semiconductor layer; a second transistor, the second transistor comprising: a second semiconductor layer on the first gate electrode; and a second gate electrode on the second semiconductor layer and at least partially overlapping the second semiconductor layer; an insulating structure between the first gate electrode and the second gate electrode; and a first transmission pattern at the same layer as the layer of the second gate electrode, the first transmission pattern being electrically connected to the first gate electrode through a contact hole passing through the insulating structure and comprising a first layer and a second layer on the first layer, wherein the first layer of the first transmission pattern comprises a first portion in the contact hole and a second portion outside the contact hole, and Among them, the thickness of the second part of the first layer is within to .

2. The display device according to claim 1, wherein, The thickness of the first part of the first layer is within to .

3. The display device according to claim 1, wherein, the taper angle of the insulating structure is in the range of 40° to 75°.

4. The display device according to claim 1, wherein, The thickness of the second layer is greater than each of the thickness of the first portion of the first layer and the thickness of the second portion of the first layer.

5. The display device according to claim 1, wherein, The first layer contains titanium.

6. The display device according to claim 1, further comprising: a second transmission pattern on the first transmission pattern and electrically connecting the first transmission pattern and the second semiconductor layer to each other.

7. The display device according to claim 1, further comprising: a capacitor electrode between the first gate electrode and the first transmission pattern and having an opening overlapping a portion of the first transmission pattern, wherein the contact hole overlaps the opening in the capacitor electrode.

8. The display device according to claim 7, wherein, The insulating structure comprises: a first insulating layer between the first gate electrode and the capacitor electrode; a second insulating layer between the capacitor electrode and the second semiconductor layer; and a third insulating layer between the second semiconductor layer and the first transmission pattern.

9. The display device according to claim 1, wherein, The substrate comprises a display area and a peripheral area outside the display area, and wherein the display device further comprises: a data transmission line bypassing a partial area in the display area and configured to receive a data signal.

10. The display device according to claim 9, wherein, The data transmission line comprises: a first connection line on the second gate electrode and extending in a first direction; and a second connection line on the first connection line and extending in a second direction intersecting the first direction, and wherein the first connection line and the second connection line are electrically connected to each other through a connection contact hole.

11. The display device according to claim 10, wherein, The first connection line and the second connection line are configured to receive the same data signal as each other.

12. The display device according to claim 10, further comprising: A first input line, a second input line, and a third input line, wherein the first input line, the second input line, and the third input line are sequentially positioned in the peripheral region in a direction from an edge of the peripheral region toward a center of the peripheral region; A first data line connected to the first input line; A third data line located on one side of the first data line and connected to the third input line; And A second data line located on the other side of the first data line and electrically connected to the second input line through the first connection line and the second connection line.

13. The display device according to claim 12, wherein, The first connection line is electrically insulated from the first data line and overlaps with the first data line in at least a part of the region.

14. The display device according to claim 12, wherein, The first data line, the second data line, and the third data line are positioned at the same layer as a layer of the second connection line.

15. The display device according to claim 1, wherein, The first semiconductor layer includes a silicon semiconductor material.

16. The display device according to claim 1, wherein, The second semiconductor layer includes an oxide semiconductor material.

17. A display device, comprising: A substrate; A first transistor, the first transistor comprising: A first semiconductor layer on the substrate; and A first gate electrode on the first semiconductor layer and at least partially overlapping with the first semiconductor layer; A second transistor, the second transistor comprising: A second semiconductor layer on the first gate electrode; and A second gate electrode on the second semiconductor layer and at least partially overlapping with the second semiconductor layer; An insulating structure located between the first gate electrode and the second gate electrode; and A first transmission pattern at the same layer as a layer of the second gate electrode and electrically connected to the first gate electrode through a contact hole passing through the insulating structure, wherein a taper angle of the insulating structure is in a range of 40° to 75°.

18. The display device according to claim 17, further comprising: A second transmission pattern on the first transmission pattern and electrically connecting the first transmission pattern and the second semiconductor layer to each other.

19. The display device according to claim 17, further comprising: A capacitor electrode between the first gate electrode and the first transmission pattern and having an opening overlapping with a part of the first transmission pattern, wherein the contact hole overlaps with the opening in the capacitor electrode.

20. The display device according to claim 19, wherein, The insulating structure includes: A first insulating layer located between the first gate electrode and the capacitor electrode; A second insulating layer located between the capacitor electrode and the second semiconductor layer; and A third insulating layer located between the second semiconductor layer and the second gate electrode.

21. The display device according to claim 17, wherein The first transmission pattern includes a first layer and a second layer on the first layer, wherein the first layer includes a first part in the contact hole and a second part outside the contact hole, and Among them, the thickness of the first part of the first layer is within to range.

22. The display device according to claim 21, wherein, The thickness of the second layer is greater than each of the thickness of the first part of the first layer and the thickness of the second part of the first layer.

23. The display device according to claim 21, wherein, The first layer contains titanium.

24. The display device according to claim 17, wherein, The substrate includes a display area and a peripheral area located outside the display area, and wherein, the display device further includes: Data transmission lines that bypass a partial area in the display area and are configured to receive data signals.

25. A method of manufacturing a display device, the method comprising: Forming a first transistor, the first transistor including: A first semiconductor layer disposed on a substrate; and A first gate electrode disposed on the first semiconductor layer to overlap at least a part of the first semiconductor layer; Forming a first insulating layer on the first gate electrode; Forming a capacitor electrode on the first insulating layer; Forming a second insulating layer on the capacitor electrode; Forming a second semiconductor layer on the second insulating layer; Forming a third insulating layer on the second semiconductor layer; Forming contact holes overlapping with the first gate electrode by removing a part of each of the first insulating layer, the second insulating layer, and the third insulating layer and then performing a first heat treatment; and Forming a first transmission pattern on the third insulating layer that is electrically connected to the first gate electrode through the contact holes.

26. The method according to claim 25, wherein, When forming the contact holes, removing the part of each of the first insulating layer, the second insulating layer, and the third insulating layer such that an insulating structure including the first insulating layer, the second insulating layer, and the third insulating layer and having a taper angle in the range of 40° to 75° is formed.

27. The method according to claim 25, wherein: The first transmission pattern includes a first layer and a second layer located on the first layer, The first layer includes a first part located in the contact holes and a second part located outside the contact holes; And The thickness of the first part of the first layer is within to .

28. The method according to claim 27, wherein, The thickness of the second part of the first layer is within to .

29. The method according to claim 25, further comprising: Performing a second heat treatment after forming the first transmission pattern.

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