Display device and head mounted display device including the same

Abstract

A display device and a head-mounted display device including the same are provided. The display device includes: a first single crystal semiconductor substrate on which a first transistor is located; a second single crystal semiconductor substrate on the first single crystal semiconductor substrate, the second single crystal semiconductor substrate having a display region; a plurality of sub-pixels including a light emitting element in the display area of the second single crystal semiconductor substrate; and a heat dissipation member located around the first single crystal semiconductor substrate and below the second single crystal semiconductor substrate, in which the second single crystal semiconductor substrate includes a plurality of first vias having first conductive vias electrically connected to the plurality of data lines and a plurality of second vias having second conductive vias electrically connected to the gate driver, the plurality of data lines are connected to the plurality of sub-pixels, the gate driver is electrically connected to the plurality of sub-pixels, and the heat dissipation member overlaps each of the plurality of first through holes and the plurality of second through holes.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2024 - 0002153, filed on January 5, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device and a head - mounted display device including the display device. Background art

[0004] A head - mounted display (HMD) device is an image display device that is worn on a user's head in the form of glasses or a helmet and forms a focused image at a distance close to the user's eyes in front of the user's eyes. The head - mounted display device can implement virtual reality (VR) or augmented reality (AR).

[0005] The head - mounted display device uses a plurality of lenses to magnify and display an image displayed by a small display device. Therefore, the display device applied to the head - mounted display device needs to provide a high - resolution image (e.g., an image having a resolution of more than 3000 pixels per inch (PPI)). For this purpose, an organic light - emitting diode on silicon (OLEDoS), which is a small organic light - emitting display device having a high resolution, has been used as the display device applied to the head - mounted display device. OLEDoS is a device that displays an image by disposing an organic light - emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal - oxide - semiconductor (CMOS) is provided. Summary of the invention

[0006] Aspects and features of embodiments of the present disclosure provide a display device including a plurality of different single - crystal semiconductor substrates and a head - mounted display device including the display device.

[0007] Aspects and features of embodiments of the present disclosure also provide a display device capable of reducing or minimizing the layout area of vias connecting two different single - crystal semiconductor substrates to each other and effectively dissipating heat generated at a connection portion between the two different single - crystal semiconductor substrates, and a head - mounted display device including the display device.

[0008] However, aspects and features of embodiments of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to one or more embodiments of the present disclosure, a display device includes: a first single-crystalline semiconductor substrate on which a plurality of first transistors are located; a second single-crystalline semiconductor substrate located on the first single-crystalline semiconductor substrate, the second single-crystalline semiconductor substrate having a display area; a plurality of sub-pixels including light-emitting elements located in the display area of the second single-crystalline semiconductor substrate; and a heat dissipation member located around the first single-crystalline semiconductor substrate and below the second single-crystalline semiconductor substrate, wherein the second single-crystalline semiconductor substrate includes a plurality of first vias having first conductive vias electrically connected to a plurality of data lines and a plurality of second vias having second conductive vias electrically connected to a gate driver, the plurality of data lines are connected to the plurality of sub-pixels, the gate driver is electrically connected to the plurality of sub-pixels, the heat dissipation member overlaps each of the plurality of first vias and the plurality of second vias and includes a first heat dissipation layer in contact with each of the lower surface and the side surface of the first single-crystalline semiconductor substrate and a first heat dissipation substrate located on the lower surface of the first heat dissipation layer, and wherein the area of the first single-crystalline semiconductor substrate in a plan view is smaller than the area of the second single-crystalline semiconductor substrate in a plan view.

[0010] In one or more embodiments, the first heat dissipation layer covers the lower surface and the side surface of the first single-crystalline semiconductor substrate and overlaps a portion of the lower surface of the second single-crystalline semiconductor substrate that does not overlap with the first single-crystalline semiconductor substrate, and the heat dissipation member further includes a second heat dissipation substrate overlapping a portion of the second single-crystalline semiconductor substrate where the first single-crystalline semiconductor substrate is not located.

[0011] In one or more embodiments, the first heat dissipation layer overlaps the display area in the thickness direction of the display device.

[0012] In one or more embodiments, the display device further includes a circuit board located on the second single-crystalline semiconductor substrate and overlapping the plurality of first vias, and the heat dissipation member further includes a third heat dissipation layer located on the circuit board and a third heat dissipation substrate located on the third heat dissipation layer.

[0013] In one or more embodiments, the third heat dissipation layer is located on a portion of the second single-crystalline semiconductor substrate where the plurality of first vias are located, and the third heat dissipation substrate does not overlap with the second single-crystalline semiconductor substrate.

[0014] In one or more embodiments, the second single-crystalline semiconductor substrate further includes a plurality of third vias overlapping pads, and the plurality of first vias overlap the circuit board in the thickness direction of the display device.

[0015] In one or more embodiments, the outer side surfaces of each of the first heat dissipation layer, the first heat dissipation substrate, and the second heat dissipation substrate are aligned with the side surface of the second single-crystalline semiconductor substrate.

[0016] In one or more embodiments, the outer surface of each of the first heat dissipation layer, the first heat dissipation substrate, and the second heat dissipation substrate protrudes outward more than the side surface of the second single-crystalline semiconductor substrate.

[0017] In one or more embodiments, the heat dissipation member further includes a thermal barrier layer located between the first single-crystalline semiconductor substrate and the second single-crystalline semiconductor substrate, and the thermal barrier layer includes a plurality of through holes in which connection lines passing through the thermal barrier layer and electrically connected to the first conductive via and the second conductive via are located.

[0018] In one or more embodiments, the first heat dissipation layer overlaps the first single-crystalline semiconductor substrate, and at least a part of the second single-crystalline semiconductor substrate does not overlap with the first heat dissipation layer.

[0019] In one or more embodiments, the first heat dissipation layer covers the lower surface and the side surface of the first single-crystalline semiconductor substrate, and the heat dissipation member further includes a second heat dissipation layer overlapping a part of the lower surface of the second single-crystalline semiconductor substrate that does not overlap with the first single-crystalline semiconductor substrate and a second heat dissipation substrate located on the lower surface of the second heat dissipation layer.

[0020] In one or more embodiments, the display device further includes a circuit board located on the second single-crystalline semiconductor substrate and overlapping the plurality of first through holes, and the heat dissipation member further includes a third heat dissipation layer located on the circuit board and a third heat dissipation substrate located on the third heat dissipation layer.

[0021] In one or more embodiments, the number of the plurality of first through holes is the same as the number of pixel columns of the plurality of sub-pixels arranged in the display area.

[0022] In one or more embodiments, a plurality of data lines extend in a first direction on the second single-crystalline semiconductor substrate and are electrically connected to at least some of the plurality of first transistors, the display device further includes a plurality of scan lines extending in a second direction intersecting the first direction on the second single-crystalline semiconductor substrate and electrically connected to the gate driver, and the number of the plurality of first through holes is the same as the number of the plurality of data lines.

[0023] In one or more embodiments, the width of the first single-crystalline semiconductor substrate measured in one direction is greater than the width of the display area measured in the one direction.

[0024] In one or more embodiments, a head-mounted display device includes: a frame; a plurality of display devices located in the frame; and lenses respectively located on the plurality of display devices, wherein each display device includes: a first single-crystalline semiconductor substrate on which a plurality of first transistors are located; a second single-crystalline semiconductor substrate located on the first single-crystalline semiconductor substrate, the second single-crystalline semiconductor substrate having a display area; a plurality of sub-pixels including light-emitting elements located in the display area of the second single-crystalline semiconductor substrate; and a heat dissipation member located around the first single-crystalline semiconductor substrate and below the second single-crystalline semiconductor substrate, the second single-crystalline semiconductor substrate including a plurality of first vias having first conductive vias electrically connected to a plurality of data lines and a plurality of second vias having second conductive vias electrically connected to a gate driver, the plurality of data lines being connected to the plurality of sub-pixels, the gate driver being electrically connected to the plurality of sub-pixels, the heat dissipation member overlapping each of the plurality of first vias and the plurality of second vias and including a first heat dissipation layer in contact with each of the lower surface and the side surface of the first single-crystalline semiconductor substrate and a first heat dissipation substrate located on the lower surface of the first heat dissipation layer, and the area of the first single-crystalline semiconductor substrate in a plan view being smaller than the area of the second single-crystalline semiconductor substrate in a plan view.

[0025] In one or more embodiments, the first heat dissipation layer covers the lower surface and the side surface of the first single-crystalline semiconductor substrate and overlaps a portion of the lower surface of the second single-crystalline semiconductor substrate that does not overlap with the first single-crystalline semiconductor substrate, and the heat dissipation member further includes a second heat dissipation substrate overlapping a portion of the second single-crystalline semiconductor substrate where the first single-crystalline semiconductor substrate is not located.

[0026] In one or more embodiments, the heat dissipation member further includes a thermal barrier layer located between the first single-crystalline semiconductor substrate and the second single-crystalline semiconductor substrate, and the thermal barrier layer includes a plurality of through-holes through which connection lines respectively electrically connected to the first conductive via and the second conductive via are located.

[0027] In one or more embodiments, the first heat dissipation layer overlaps the first single-crystalline semiconductor substrate, and at least a portion of the second single-crystalline semiconductor substrate does not overlap with the first heat dissipation layer.

[0028] In one or more embodiments, the first heat dissipation layer covers the lower surface and the side surface of the first single-crystalline semiconductor substrate, and the heat dissipation member further includes a second heat dissipation layer overlapping a portion of the lower surface of the second single-crystalline semiconductor substrate that does not overlap with the first single-crystalline semiconductor substrate and a second heat dissipation substrate located on the lower surface of the second heat dissipation layer.

[0029] A display device according to one or more embodiments may include two different single-crystalline semiconductor substrates, and in the manufacturing process of the single-crystalline semiconductor substrate disposed below, a large number of driving units may be manufactured per unit wafer substrate, so that the yield of the driving units can be improved.

[0030] In addition, in a display device according to one or more embodiments, circuit units may be separately disposed on two different single-crystalline semiconductor substrates, and the number of vias connecting the circuit units separately disposed on the two different single-crystalline semiconductor substrates to each other may be minimized. The display device may slow down the high integration on the single-crystalline semiconductor substrate having a small area. In addition, the display device may effectively manage heat generation by further including a heat dissipation member that dissipates heat generated from a part disposed in the via.

[0031] However, aspects according to embodiments of the present disclosure are not limited to the above, and various other aspects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects of the present disclosure will become more apparent by referring to embodiments of the present disclosure in detail with reference to the drawings, in which:

[0033] Figure 1 is an exploded perspective view of a display device according to one or more embodiments;

[0034] Figure 2 shows Figure 1 an example of a driving unit shown in;

[0035] Figure 3 shows Figure 1 an example of a display unit shown in;

[0036] Figure 4 shows the arrangement of multiple lines in the display unit disposed in Figure 3 ;

[0037] Figure 5 is a block diagram of a display device according to one or more embodiments;

[0038] Figure 6 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments;

[0039] Figure 7 is a schematic diagram showing the rear surface of a display device according to one or more embodiments;

[0040] Figure 8 is a schematic cross-sectional view of a display device according to one or more embodiments;

[0041] Figure 9is a schematic cross-sectional view of a driving unit according to one or more embodiments;

[0042] Figure 10 is a plan view showing a pixel defining film, a first electrode, and an emission region of a plurality of sub-pixels disposed in a display region of a display unit according to one or more embodiments;

[0043] Figure 11 is a plan view showing a pixel defining film, a first electrode, and an emission region of a plurality of sub-pixels disposed in a display region of a display unit according to one or more embodiments;

[0044] Figure 12 and Figure 13 is a cross-sectional view showing a part of a display region and a non-display region of a display unit according to one or more embodiments;

[0045] Figure 14 is a schematic cross-sectional view of a display device according to one or more embodiments;

[0046] Figures 15 to 18 is a schematic cross-sectional view of a display device according to one or more embodiments;

[0047] Figure 19 is a perspective view showing a head-mounted display device according to one or more embodiments;

[0048] Figure 20 is showing Figure 19 an exploded perspective view of a head-mounted display device; and

[0049] Figure 21 is a perspective view showing a head-mounted display device according to one or more embodiments. Detailed Description of Embodiments

[0050] Aspects and features of embodiments of the present disclosure and methods for implementing them can be more easily understood by referring to the detailed description of the embodiments and the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, not relevant to the description of the embodiments, or not necessary for those of ordinary skill in the art to fully understand aspects of the present disclosure may be omitted. Unless otherwise indicated, the same reference numerals, characters, or combinations thereof represent the same elements throughout the drawings and the written description, and thus their repeated description may be omitted.

[0051] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as limited to the embodiments shown herein. When describing one or more embodiments, the use of "may", "might", "may not" or "might not" corresponds to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents and alternatives within the concept and technology scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be partially or wholly combined with each other, and various linkages and drives are possible technically. Each embodiment may be implemented independently of each other, or may be implemented jointly together.

[0052] In the drawings, for clarity and / or descriptive purposes, the relative sizes of elements, layers, and regions may be exaggerated. Additionally, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements.

[0053] In this document, various embodiments are described with reference to cross-sectional illustrations that are schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Additionally, the specific structural or functional descriptions disclosed herein are provided only for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes of the illustrated elements, layers, or regions, but should include, for example, deviations in shape caused by manufacturing.

[0054] For example, an implantation region shown as rectangular may generally have rounded or arcuate features and / or a gradient of implantation concentration at its edges rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs.

[0055] For ease of explanation, spatially relative terms such as "below", "beneath", "lower", "underside", "under", "above", "upper", and "upside" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below", "beneath", or "under" another element or feature will then be oriented "above" the other element or feature. Thus, the example terms "below" and "beneath" can encompass both an upper and a lower orientation. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being disposed "on" a second part, this means that the first part is disposed on the upper side or the lower side of the second part, and is not limited to the upper side of the second part based on the direction of gravity.

[0056] In addition, the phrase "in a plan view" means when viewing the object part from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting the object part from the side. The term "overlap" or "overlapped" means that a first object may be above, below, or beside a second object, and vice versa. Additionally, the term "overlap" may include stacking, facing or facing each other, extending over, covering or partially covering, or any other suitable term that would be recognized and understood by one of ordinary skill in the art. The expression "not overlapping" may include meanings such as "spaced apart from", "disposed beside", or "offset from", as well as any other suitable equivalents that would be recognized and understood by one of ordinary skill in the art. The term "face" may mean that a first object may be directly or indirectly opposite a second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite each other, although the first object and the second object still face each other.

[0057] It will be understood that when an element, layer, region or component is referred to as being "formed on", "on", "connected to" or "(operatively or communicatively) coupled to" another element, layer, region or component, the element, layer, region or component can be directly formed on, directly on, directly connected to or coupled to the other element, layer, region or component, or can be indirectly formed on, indirectly on, indirectly connected to or coupled to the other element, layer, region or component, such that there can be one or more intervening elements, layers, regions or components. Additionally, this can generally mean direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, the layer, region or component can be directly electrically connected or coupled to the other layer, region or component, or there can be one or more intervening layers, regions or components. One or more intervening components can include switches, resistors and / or capacitors, etc. When describing embodiments, an expression of connection means electrical connection unless explicitly described as a direct connection, and "direct connection / direct coupling" or "directly on" means that a component is directly connected or coupled to another component or on another component without an intermediate component.

[0058] Further, in this specification, when a part of a layer, film, region or plate, etc. is formed on another part, the forming direction is not limited to the upward direction, but includes forming the part on a side surface or in a downward direction. Conversely, when a part of a layer, film, region or plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is yet another part further between the part and the other part. At the same time, other expressions describing the relationship between components such as "between" and "immediately between" or "adjacent to" and "directly adjacent to" can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0059] For the purposes of the present disclosure, when located after a list of elements, expressions such as "at least one of", "any one of", or "one or more of" modify the entire list of elements and not a single element of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ), or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, when located before or after a list of elements, expressions such as "at least one of", "a plurality of", "one of", and other prepositional phrases modify the entire list of elements and not a single element of the list.

[0060] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms do not correspond to a particular order, position, or superiority, and are only used to distinguish one element, member, component, region, area, layer, part, and / or portion from another element, member, component, region, area, layer, part, and / or portion. Thus, a first element, component, region, layer, or part described below may be referred to as a second element, component, region, layer, or part without departing from the spirit and / or scope of the present disclosure. Describing an element as a "first" element does not require or imply the existence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish different classes or groups of elements. For the sake of brevity, the terms "first", "second", etc. may respectively denote "first class (or first group)", "second class (or second group)", etc.

[0061] In an example, the first direction, the second direction, and / or the third direction are not limited to directions corresponding to the three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the first direction, the second direction, and the third direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0062] The terms used in this disclosure are for the purpose of describing embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a", "an" are intended to include the plural forms as well, and the plural forms are also intended to include the singular forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises", "comprising", "includes" and "having" specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0063] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. Taking into account the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein includes the stated value and means within an acceptable deviation of that particular value as determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value. Additionally, when describing embodiments of the disclosure, the use of "may" refers to "one or more embodiments of the disclosure".

[0064] In some embodiments, well-known structures and devices associated with one or more functional blocks (e.g., block diagrams), units, and / or modules may be described and illustrated in the figures to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wire connections, and other electronic circuits. This may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by a microprocessor or other similar hardware may be programmed and controlled using software to perform the various functions discussed herein, and optionally may be driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) performing functions different from those of the dedicated hardware. Additionally, in some embodiments, a block, unit, and / or module may be physically separated into two or more interacting discrete blocks, units, and / or modules without departing from the spirit and / or scope of the disclosure. Additionally, in one or more embodiments, a block, unit, and / or module may be physically combined into more complex blocks, units, and / or modules without departing from the spirit and / or scope of the disclosure.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or this disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0066] Those of ordinary skill in the art should understand that, given the overall disclosure, each suitable feature of each of the various embodiments of this disclosure may be partially or wholly combined or integrated with each other and may be technically combined and operated in various suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable manner, unless otherwise stated or implied.

[0067] Figure 1 is an exploded perspective view of a display device according to one or more embodiments.

[0068] Reference Figure 1 , the display device 10 according to one or more embodiments is a device for displaying moving images and / or still images. The display device 10 according to one or more embodiments may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and / or ultra-mobile PCs (UMPCs). For example, the display device 10 may be used as a display unit of a television, a laptop computer, a monitor, a billboard, and / or an Internet of Things (IoT) device. Alternatively, the display device 10 may be applied to smart watches, watch phones, and / or head-mounted display (HMD) devices for implementing virtual reality and augmented reality.

[0069] The display device 10 according to one or more embodiments may include a driving unit 100, a display unit 200, and a circuit board 300. The display device 10 may further include a heat dissipation member HTP disposed around the driving unit 100.

[0070] In a plan view, the driving unit 100 may have a shape similar to a quadrilateral shape. For example, in a plan view, the driving unit 100 may have a shape similar to a rectangular shape having one side in a first direction DR1 and another side in a second direction DR2 intersecting the first direction DR1. In the driving unit 100, one side in the first direction DR1 and another side in the second direction DR2 may have different lengths. In the driving unit 100, corners where one side in the first direction DR1 and another side in the second direction DR2 intersect may be rounded with a suitable curvature (e.g., a predetermined curvature) or may be right angles. The shape of the driving unit 100 in a plan view is not limited to a quadrilateral shape and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0071] The display unit 200 may be disposed on the driving unit 100. In the display device 10, the driving unit 100 and the display unit 200 may be coupled to each other. Different from the driving unit 100, the display unit 200 may have a shape similar to a square shape. For example, in a plan view, the display unit 200 may have a shape similar to a square shape in which one side in a first direction DR1 and another side in a second direction DR2 intersecting the first direction DR1 have the same length. The shape of the display unit 200 in a plan view is not limited to a square shape and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The shape of the display device 10 in a plan view may follow the shape of the display unit 200 in a plan view, but is not limited thereto.

[0072] According to one or more embodiments, in the display device 10, the area of the display unit 200 in a plan view may be larger than the area of the driving unit 100 in a plan view. The display device 10 may include the driving unit 100 and the display unit 200 including different substrates, and the driving unit 100 and the display unit 200 may have different areas. Elements formed in the driving unit 100 and elements formed in the display unit 200 may be different from each other, and these elements may be separately formed on different substrates. The display device 10 may be manufactured by forming a plurality of elements different from each other in terms of their sizes, line widths, manufacturing processes, etc. on different substrates and then coupling these plurality of elements to each other, and the performance and / or yield of the product, etc. may be improved.

[0073] A circuit board 300 may be electrically connected to a plurality of pads in a pad region of the display unit 200 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. In Figure 1The circuit board 300 is shown as unbent in [description], but the circuit board 300 can be bent. In this case, one end of the circuit board 300 can be disposed on the lower surface of the driving unit 100. The other end of the circuit board 300 can be connected to a plurality of pads in the pad region of the display unit 200 using a conductive adhesive member. In another embodiment, the circuit board 300 can be attached to the lower surface of the driving unit 100.

[0074] The heat dissipation member HTM can be around the driving unit 100 (e.g., can surround the driving unit 100), and can be disposed on the lower surface of the display unit 200. The heat dissipation member HTM can effectively dissipate the heat generated from the driving unit 100 and the display unit 200. The heat dissipation member HTM can include a layer made of graphite and / or a metal such as silver (Ag), copper (Cu), and / or aluminum (Al) having high thermal conductivity. The heat dissipation member HTM will be described in more detail below.

[0075] Figure 2 is a diagram showing Figure 1 a plan view of an example of the driving unit shown in [description]. Figure 3 is a diagram showing Figure 1 a plan view of an example of the display unit shown in [description]. Figure 4 is a diagram showing the arrangement of Figure 3 multiple lines in the display unit provided in [description].

[0076] Referring to Figures 2 to 4 , the driving unit 100 of the display device 10 can include the driving circuit elements of the display device 10. The driving unit 100 can include a first single-crystalline semiconductor substrate 110 and a driving circuit unit 400 and a data driver 700 formed on the first single-crystalline semiconductor substrate 110.

[0077] The first single-crystalline semiconductor substrate 110 can be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. A plurality of first transistors can be formed on the first single-crystalline semiconductor substrate 110. The plurality of first transistors can be electrically connected to each other to form the driving circuit unit 400 and the data driver 700. The first transistors can be formed by a semiconductor process. For example, the plurality of first transistors can be formed as complementary metal oxide semiconductor (CMOS) transistors.

[0078] In Figure 2 it has been shown that the driving circuit unit 400 is disposed on the upper side of the driving unit 100, and the data driver 700 and the first pad region PDA1 are disposed on the lower side of the driving unit 100. However, the present disclosure is not limited thereto. The positions of the driving circuit unit 400 and the data driver 700 in the driving unit 100 can be differently changed depending on the design structure of the plurality of circuit elements formed on the first single-crystalline semiconductor substrate 110.

[0079] The first pad region PDA1 may include a plurality of first pads PD1 arranged along a first direction DR1. The plurality of first pads PD1 may be electrically connected to a plurality of second pads PD2 of the display unit 200 and may be electrically connected to the circuit board 300 through the plurality of second pads PD2. The first pad PD1 may transmit an electrical signal applied from the circuit board 300 to the driving circuit unit 400, the gate drivers 610 and 620, and the data driver 700.

[0080] The display unit 200 may include a second single crystal semiconductor substrate 210, a plurality of pixels PX formed on the second single crystal semiconductor substrate 210, and gate drivers 610 and 620. The display unit 200 may include a display area DAA in which the plurality of pixels PX are disposed and a non-display area NA disposed around the display area DAA. The gate drivers 610 and 620 and the second pad region PDA2 may be disposed in the non-display area NA.

[0081] The second single crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, and / or a silicon germanium substrate. A plurality of second transistors may be formed on the second single crystal semiconductor substrate 210. The plurality of second transistors may be electrically connected to each other to form the gate drivers 610 and 620 and a pixel circuit unit for emitting light from the plurality of pixels PX. The second transistors may be formed by a semiconductor process. For example, the plurality of second transistors may be formed as CMOS transistors.

[0082] A plurality of pixels PX including light emitting elements may be disposed in the display area DAA. Each of the plurality of pixels PX may include three sub-pixels such as a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The three sub-pixels SP1, SP2, and SP3 may constitute one pixel PX for displaying a color. However, the present disclosure is not limited thereto, and one pixel PX may include four or more sub-pixels. The plurality of sub-pixels SP1, SP2, and SP3 may be arranged in a matrix form along the first direction DR1 and the second direction DR2. For example, the plurality of sub-pixels SP1, SP2, and SP3 may be arranged along the rows and columns of the matrix along the first direction DR1 and the second direction DR2. Each of the plurality of sub-pixels SP1, SP2, and SP3 may be electrically connected to a pixel circuit (e.g., Figure 6 the pixel circuit in) including a plurality of second transistors formed on the second single crystal semiconductor substrate 210. Each of the sub-pixels SP1, SP2, and SP3 may include a light emitting element, and the light emitting element may emit light according to an electrical signal applied from the pixel circuit disposed in the display area DAA.

[0083] Some of the sub-pixels SP1, SP2, and SP3 disposed in the display area DAA of the display unit 200 may overlap with the driving unit 100 in the thickness direction (e.g., the third direction DR3), and others of the sub-pixels SP1, SP2, and SP3 may not overlap with the driving unit 100. The driving unit 100 may have an area smaller than the area of the display unit 200 and may be disposed adjacent to one side of the display unit 200. Accordingly, only some of the plurality of sub-pixels SP1, SP2, and SP3 may overlap with the driving unit 100 in the thickness direction (e.g., the third direction DR3).

[0084] In the display area DAA, a plurality of scan lines GL extending in the first direction DR1 and arranged along the second direction DR2 and a plurality of data lines DL extending in the second direction DR2 and arranged along the first direction DR1 may be provided. The plurality of scan lines GL may include different types of scan lines such as first to third scan lines GWL, GCL, and GBL (see Figure 5 ) and emission control lines EL1 and EL2 (see Figure 5 ). The plurality of scan lines GL and the data lines DL may be connected to each of the plurality of sub-pixels SP1, SP2, and SP3 in the display area DAA. The plurality of scan lines GL may be electrically connected to the gate drivers 610 and 620 of the display unit 200, and the plurality of data lines DL may be electrically connected to the data driver 700 of the driving unit 100. The data line DL may be electrically connected to the data driver 700 of the driving unit 100 through the first through-hole TSV1.

[0085] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be electrically connected to the scan line GL and the data line DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 may receive the data voltage of the data line DL according to the scan signal of the scan line GL and may allow the light-emitting element to emit light according to the data voltage.

[0086] The non-display area NA may be provided around the display area DAA (e.g., surrounding the display area DAA). The non-display area NA may be an area where no pixel PX is provided, and accordingly, light is not emitted. The gate drivers 610 and 620, the second pad area PDA2, and the plurality of through-holes TSV1, TSV2, and TSV3 may be provided in the non-display area NA.

[0087] The gate drivers 610 and 620 may include a scan driver 610 and an emission driver 620. The scan driver 610 may include a plurality of scan transistors formed on the second single-crystalline semiconductor substrate 210, and the emission driver 620 may include a plurality of light-emitting transistors formed on the second single-crystalline semiconductor substrate 210. The plurality of scan transistors and the plurality of light-emitting transistors may be formed by a semiconductor process. For example, the plurality of scan transistors and the plurality of light-emitting transistors may be formed as CMOS transistors.

[0088] The scan driver 610 may be disposed on the left side, which is one side of the display area DAA in the first direction DR1, of the display area DAA, and the emission driver 620 may be disposed on the right side, which is the other side of the display area DAA in the first direction DR1, of the display area DAA. A plurality of scan lines GL may each be electrically connected to one of the scan driver 610 and the emission driver 620. As an example, the first to third scan lines GWL, GCL, and GBL (e.g., see Figure 5 ) of the scan lines GL may be connected to the scan driver 610, and the emission control lines EL1 and EL2 (e.g., see Figure 5 ) may be connected to the emission driver 620.

[0089] The second pad region PDA2 may be disposed on the lower side, which is one side of the display area DAA in the second direction DR2, of the display area DAA. A plurality of second pads PD2 arranged along the first direction DR1 may be disposed in the second pad region PDA2. The plurality of second pads PD2 may be electrically connected to the plurality of first pads PD1 of the driving unit 100, and the circuit board 300 may be attached to the plurality of second pads PD2. The second pad PD2 is electrically connected to the circuit board 300 and may transmit an electrical signal applied from the circuit board 300 to the driving unit 100.

[0090] The display device 10 may include a plurality of through-silicon vias TSV1, TSV2, and TSV3 that form paths through which elements formed in the driving unit 100 and the display unit 200 are electrically connected to each other. The plurality of through-silicon vias TSV1, TSV2, and TSV3 may be formed to pass through the second single-crystalline semiconductor substrate 210 of the display unit 200. The driving circuit unit 400 and the data driver 700 provided in the driving unit 100 may be electrically connected to the display unit 200 and the circuit board 300 through connection lines provided in the through-silicon vias TSV1, TSV2, and TSV3.

[0091] The plurality of through-silicon vias TSV1, TSV2, and TSV3 may include a plurality of first through-silicon vias TSV1, a plurality of second through-silicon vias TSV2, and a plurality of third through-silicon vias TSV3 provided in the non-display area NA.

[0092] The first through - via TSV1 can be disposed on one side of the display area DAA, in the non - display area NA. For example, the first through - via TSV1 can be disposed on the lower side of the display area DAA. In one or more embodiments, the first through - via TSV1 can be disposed in the second pad area PDA2 and can be arranged not to overlap with the second pad PD2. The first through - via TSV1 can be arranged to correspond to a plurality of data lines DL disposed in the display area DAA respectively. The number of the first through - via TSV1 can be the same as the number of the data lines DL and the number of pixel columns of the plurality of sub - pixels SP1, SP2, and SP3 disposed in the display area DAA. Each of the plurality of data lines DL can correspond to the first through - via TSV1 and can be electrically connected to the connection line disposed in the first through - via TSV1. Each of the sub - pixels SP1, SP2, and SP3 can receive the data voltage applied from the data line DL connected to the driving unit 100 through the first through - via TSV1.

[0093] The second through - via TSV2 can be disposed in the gate drivers 610 and 620 in the non - display area NA. Some of the plurality of second through - via TSV2 can be disposed in the scan driver 610, and the others of the plurality of second through - via TSV2 can be disposed in the emission driver 620. The connection lines connecting the gate drivers 610 and 620 to the driving unit 100 can be disposed in the second through - via TSV2, and the signals for driving the gate drivers 610 and 620 can be applied from the driving unit 100 to the second through - via TSV2. For example, the gate drivers 610 and 620 can be connected to the connection lines of the driving circuit unit 400 connected to the driving unit 100 through the second through - via TSV2 and can receive the timing signals applied to the gate drivers 610 and 620.

[0094] In the non - display area NA, the third through - via TSV3 can be disposed to overlap with the second pad PD2 respectively. The third through - via TSV3 can be disposed to correspond to the second pad PD2 respectively, and the number of the third through - via TSV3 can be the same as the number of the second pad PD2. The second pad PD2 can be electrically connected to the first pad PD1 of the driving unit 100 through the connection line disposed in the third through - via TSV3.

[0095] Figure 5 is a block diagram showing a display device according to one or more embodiments.

[0096] Reference Figure 5 , the driving circuit unit 400 can include a timing controller. Additionally, the driving circuit unit 400 can further include various circuits such as a gamma circuit and a logic circuit involved in driving the display device 10. The driving circuit unit 400 can include driving circuit transistors formed on the first single - crystal semiconductor substrate 110.

[0097] The driving circuit unit 400 can receive digital video data DATA and a timing signal from the outside. The timing controller can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display unit 200 according to the timing signal. The timing controller can output the scan timing control signal SCS to the scan driver 610 among the gate drivers 610 and 620, and can output the emission timing control signal ECS to the emission driver 620 among the gate drivers 610 and 620. The timing controller can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0098] The power supply unit 501 can generate a plurality of panel driving voltages according to an external power supply voltage. For example, the power supply unit 501 can generate a first driving voltage VSS, a second driving voltage VDD, a reference voltage VREF, and an initialization voltage VINT, and can supply the first driving voltage VSS, the second driving voltage VDD, the reference voltage VREF, and the initialization voltage VINT to a plurality of pixels PX.

[0099] The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the driving circuit unit 400 can be supplied to a plurality of pixels PX. The first driving voltage VSS, the second driving voltage VDD, the reference voltage VREF, and the initialization voltage VINT of the power supply unit 501 can also be supplied to a plurality of pixels PX.

[0100] The gate drivers 610 and 620 can include a scan driver 610 and an emission driver 620. The scan driver 610 can include a plurality of scan transistors formed on the second single-crystalline semiconductor substrate 210, and the emission driver 620 can include a plurality of light-emitting transistors formed on the second single-crystalline semiconductor substrate 210. The plurality of scan transistors and the plurality of light-emitting transistors can be formed by a semiconductor process. For example, the plurality of scan transistors and the plurality of light-emitting transistors can be formed as CMOS transistors.

[0101] The scan driver 610 may include a first scan signal output unit 611, a second scan signal output unit 612, and a third scan signal output unit 613. Each of the first scan signal output unit 611, the second scan signal output unit 612, and the third scan signal output unit 613 may receive a scan timing control signal SCS from the driving circuit unit 400. The first scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the driving circuit unit 400, and may sequentially output the write scan signal to the first scan line GWL. The second scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS, and may sequentially output the control scan signal to the second scan line GCL. The third scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and may sequentially output the bias scan signal to the third scan line GBL.

[0102] The emission driver 620 may include a first emission signal output unit 621 and a second emission signal output unit 622. Each of the first emission signal output unit 621 and the second emission signal output unit 622 may receive an emission timing control signal ECS from the driving circuit unit 400. The emission driver 620 may generate an emission control signal according to the emission timing control signal ECS, and may sequentially output the emission control signal to the first emission control line EL1 and the second emission control line EL2.

[0103] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the driving circuit unit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 may be selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0104] A plurality of pixels PX, a plurality of data lines DL, a plurality of scan lines GWL, GCL, and GBL, and a plurality of emission control lines EL1 and EL2 may be provided in a display area DAA of the display unit 200. The plurality of scan lines GWL, GCL, and GBL may include a first scan line GWL, a second scan line GCL, and a third scan line GBL. The plurality of scan lines GWL, GCL, and GBL and the plurality of emission control lines EL1 and EL2 may extend in a first direction DR1 and may be arranged to be spaced apart from each other in a second direction DR2 (e.g., spaced apart from each other). The plurality of data lines DL may extend in the second direction DR2 and may be arranged to be spaced apart from each other in the first direction DR1 (e.g., spaced apart from each other).

[0105] Figure 6 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments.

[0106] Reference Figure 6 , the first sub-pixel SP1 may be connected to the first scan line GWL, the second scan line GCL, the third scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. In addition, the first sub-pixel SP1 may be connected to a first driving voltage line VSL to which a first driving voltage VSS corresponding to a low potential voltage is applied, a second driving voltage line VDL to which a second driving voltage VDD corresponding to a high potential voltage is applied, and a third driving voltage line VIL to which an initialization voltage VINT is applied. That is, the first driving voltage line VSL may be a low potential voltage line, the second driving voltage line VDL may be a high potential voltage line, and the third driving voltage line VIL may be an initialization voltage line. In this case, the first driving voltage VSS may be a voltage lower than the initialization voltage VINT. The second driving voltage VDD may be a voltage higher than the initialization voltage VINT.

[0107] The first sub-pixel SP1 includes a plurality of transistors T1 to T6, a light-emitting element LE, a first capacitor C1, and a second capacitor C2.

[0108] The light-emitting element LE emits light according to the drive current Ids flowing through the channel of the first transistor T1. The amount of light emitted from the light-emitting element LE may be proportional to the drive current Ids. The light-emitting element LE may be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE may be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be an organic light-emitting diode (OLED) including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but is not limited thereto. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor layer disposed between the first electrode and the second electrode, and in this case, the light-emitting element LE may be a micro light-emitting diode.

[0109] The first transistor T1 may be a drive transistor that controls the source-drain current Ids (also referred to as "drive current" herein) flowing between the source electrode and the drain electrode according to the voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0110] The second transistor T2 may be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the first scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. For this reason, the data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the first scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0111] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by the control scan signal of the second scan line GCL to connect the first node N1 to the second node N2. For this reason, the gate electrode and the drain electrode of the first transistor T1 are connected to each other, and thus, the first transistor T1 may operate like a diode (for example, the first transistor T1 may be diode-connected). The third transistor T3 includes a gate electrode connected to the second scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0112] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. For this reason, the drive current Ids of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0113] The fifth transistor T5 may be provided between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal of the third scan line GBL to connect the third node N3 to the third drive voltage line VIL. For this reason, the initialization voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the third scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0114] The sixth transistor T6 may be provided between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. For this reason, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0115] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0116] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second drive voltage line VDL.

[0117] The first node N1 is a contact point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a contact point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a contact point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0118] Each of the first transistor T1 to the sixth transistor T6 may be a metal-oxide semiconductor field-effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, but is not limited thereto. Each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET. Alternatively, some of the first transistor T1 to the sixth transistor T6 may be P-type MOSFETs, and the others of the first transistor T1 to the sixth transistor T6 may be N-type MOSFETs.

[0119] In Figure 6 it has been shown that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to Figure 6 the equivalent circuit diagram shown in Figure 6 For example, the number of transistors and capacitors of the first sub-pixel SP1 is not limited to

[0120] Figure 7 is a schematic diagram showing the rear surface of a display device according to one or more embodiments. Figure 8 is a schematic cross-sectional view of a display device according to one or more embodiments. Figure 8 shows a schematic arrangement of transmission lines RM1, RM2, and RM3 that electrically connect the display unit 200 and the driving unit 100 to each other, and Figure 7 shows the arrangement of the first through-hole TSV1 and the second through-hole TSV2 when viewed from the rear surface of the display device 10.

[0121] Combined with Figure 4 Refer to Figure 7 and Figure 8, according to one or more embodiments, the display device 10 may include a driving unit 100 including a first single-crystalline semiconductor substrate 110 and a driving circuit layer 120 disposed on the first single-crystalline semiconductor substrate 110, and a display unit 200 including a second single-crystalline semiconductor substrate 210 and a pixel circuit unit 220 and a display element layer 230 disposed on the second single-crystalline semiconductor substrate 210. The display device 10 may include two different single-crystalline semiconductor substrates 110 and 210 that overlap each other in a third direction DR3 that is the thickness direction of the display device 10.

[0122] The driving unit 100 may include circuit elements required for the light-emitting elements included in the display element layer 230 of the display unit 200 to emit light. As described above, the driving circuit layer 120 of the driving unit 100 may include a driving circuit unit 400 and / or a data driver 700, etc., and circuit elements such as transistors and capacitors that constitute the driving circuit unit 400 and / or the data driver 700, etc. may be formed as CMOS on the first single-crystalline semiconductor substrate 110.

[0123] The display unit 200 may include a plurality of light-emitting elements that emit light in order to display an image of the display device 10. The light-emitting elements may be electrically connected to the circuit elements formed in the driving unit 100 and may emit light. In addition, the display unit 200 may include a pixel circuit unit 220 in which a plurality of lines, gate drivers 610 and 620, and circuit elements constituting a pixel circuit electrically connected to each sub-pixel SP1, SP2, and SP3 are provided. The pixel circuit unit 220 may include circuit elements such as Figure 6 the first transistor T1 to the sixth transistor T6 that constitute the pixel circuit, scanning transistors and light-emitting transistors that constitute the gate drivers 610 and 620, and a plurality of scanning lines GL and a plurality of data lines DL. In addition, the pixel circuit unit 220 may include a plurality of terminals DTD and GTD connected to through vias TSV1, TSV2, and TSV3 provided in a non-display area NA of the display unit 200 (see Figure 12 ).

[0124] According to one or more embodiments, in the display device 10, the area of the driving unit 100 or the first single-crystalline semiconductor substrate 110 in a plan view may be smaller than the area of the display unit 200 or the second single-crystalline semiconductor substrate 210 in a plan view. The plurality of transistors formed in the driving unit 100 may be formed by a fine semiconductor process to have a very small size or line width. The driving unit 100 has the advantages that a large number of circuit elements can be provided with high integration and the power consumption can be reduced due to the miniaturization of the elements.

[0125] In addition, the driving unit 100 only includes circuit elements formed as CMOS on the first single-crystalline semiconductor substrate 110 and does not include light-emitting elements. Therefore, for the driving unit 100, it may be sufficient to ensure only a space sufficient to set elements formed by a fine semiconductor process. It may be sufficient that the first single-crystalline semiconductor substrate 110 has an area smaller than that of the second single-crystalline semiconductor substrate 210, and a large number of driving units 100 can be manufactured on one wafer substrate on which a process for forming the driving circuit layer 120 is performed, so that the yield of the driving unit 100 can be improved. In particular, the driving unit 100 undergoes a high-cost fine semiconductor process. Therefore, due to the improvement in the yield of the driving unit 100, an effect of cost reduction can be achieved. In addition, in the display unit 200, a large number of light-emitting elements can be formed on the second single-crystalline semiconductor substrate 210 having a relatively large area, so that a high-resolution display device 10 can be realized.

[0126] The display device 10 may include a connection line layer 500 provided between the second single-crystalline semiconductor substrate 210 of the display unit 200 and the driving circuit layer 120 of the driving unit 100. The connection line layer 500 may be provided on the lower surface of the second single-crystalline semiconductor substrate 210. The connection line layer 500 may include a plurality of transmission lines RM1, RM2, and RM3, and the transmission lines RM1, RM2, and RM3 may connect the pixel circuit unit 220 and a circuit board 300 provided on the display unit 200 to the driving unit 100. The driving circuit layer 120 of the driving unit 100 may be electrically connected to the display unit 200 and the circuit board 300 through the transmission lines RM1, RM2, and RM3 of the connection line layer 500 to transmit an electric signal for light emission.

[0127] The first transmission line RM1 may be connected to a data line DL provided in the display unit 200 and a data driver 700 provided in the driving unit 100. The first transmission line RM1 may be provided in a first through-silicon via TSV1 formed in the second single-crystalline semiconductor substrate 210 and may include a data transmission line GDL of the connection line layer 500. A plurality of first through-silicon vias TSV1 may be provided in the non-display area NA of the display unit 200 and may not overlap with the driving unit 100 in the thickness direction (e.g., the third direction DR3).

[0128] A plurality of first vias TSV1 may be disposed in a second pad region PDA2 in a non-display region NA of the display unit 200, and may not overlap with the driving unit 100 in the thickness direction (e.g., the third direction DR3), but may overlap with the circuit board 300 in the thickness direction (e.g., the third direction DR3). The first transmission line RM1 may be partially disposed in the first via TSV1, and the data transmission line GDL may be disposed in the connection line layer 500 and may connect the data driver 700 and the first via TSV1 that does not overlap with the driving unit 100 to each other. The driving unit 100 disposed on the lower surface of the display unit 200 may partially overlap with the non-display region NA of the display unit 200. The driving unit 100 may not overlap with the vias TSV1, TSV2, and TSV3 disposed in the non-display region NA.

[0129] According to one or more embodiments, the number of the first vias TSV1 may be the same as the number of pixel columns of the plurality of sub-pixels SP1, SP2, and SP3 disposed in the display area DAA. For example, the plurality of sub-pixels SP1, SP2, and SP3 may be arranged in the display area DAA along a first direction DR1 and a second direction DR2, and when the number of pixel columns arranged along the first direction DR1 is 4000, the number of the first vias TSV1 may also be 4000, which is the same as the number of pixel columns arranged along the first direction DR1. The first vias TSV1 may correspond to the pixel columns of the sub-pixels SP1, SP2, and SP3 arranged along the first direction DR1 in a one-to-one manner, and may also correspond to the plurality of data lines DL and the first transmission line RM1 arranged along the first direction DR1 in a one-to-one manner. One data line DL arranged in parallel with a pixel column may be connected to the data driver 700 through the first transmission line RM1 disposed in one first via TSV1. The number of the first transmission lines RM1 and the number of the first vias TSV1 may be the same as the number of pixel columns and the number of data lines DL.

[0130] A plurality of data lines DL can extend in a second direction DR2 and can be respectively connected to first vias TSV1 that are parallel to each other without being bent even in a non-display area NA. In the display device 10, the intervals between the data lines DL can be kept constant in both the display area DAA and the non-display area NA of the display unit 200, and a fan-out structure in which the data lines DL are bent and narrowed in the non-display area NA can be omitted. Similar to the intervals between the data lines DL, the intervals between the first vias TSV1 that are spaced apart from each other (e.g., spaced apart from each other) and the intervals between the data transfer lines GDL that are spaced apart from each other (e.g., spaced apart from each other) can also be kept constant. The driving unit 100 of the display device 10 can have a sufficient width such that the data lines DL and the data transfer lines GDL that are spaced apart from each other at equal intervals (e.g., spaced apart from each other) are arranged to extend parallel to each other. For example, the width of the driving unit 100 of the display device 10 measured in a first direction DR1 can be greater than the width of the display area DAA measured in the first direction DR1. In the display device 10, the data lines DL can be connected to the driving unit 100 through the first vias TSV1 and can be arranged parallel to each other without a fan-out structure, and interference between adjacent other lines can be reduced or minimized.

[0131] A second transfer line RM2 can be connected to the gate drivers 610 and 620 provided in the display unit 200 and the drive circuit unit 400 provided in the driving unit 100. The second transfer line RM2 can be disposed in second vias TSV2 formed in the second single-crystalline semiconductor substrate 210 and can include a control transfer line TCL of the connection line layer 500. A plurality of second vias TSV2 can be provided in the non-display area NA of the display unit 200 and can not overlap with the driving unit 100 and the circuit board 300 in a thickness direction (e.g., a third direction DR3). In one or more embodiments, a plurality of second vias TSV2 can be arranged to respectively overlap with the scan driver 610 and the emission driver 620.

[0132] The second transfer line RM2 can be partially disposed in the second vias TSV2, and the control transfer line TCL can be disposed in the connection line layer 500 and can connect the driving unit 100 and the second vias TSV2 that do not overlap with the driving unit 100 to each other.

[0133] The gate drivers 610 and 620 can be electrically connected to the driving circuit unit 400 of the driving unit 100 and can receive timing control signals. Different from the first through-hole TSV1 and the first transmission line RM1, the second through-hole TSV2 and the second transmission line RM2 may not be arranged to correspond to the scanning lines GL in a one-to-one manner. In one or more embodiments, the number of the second through-hole TSV2 and the second transmission line RM2 may be less than the number of the first through-hole TSV1 and the first transmission line RM1, respectively.

[0134] The third transmission line RM3 can be connected to the second pad PD2 provided in the display unit 200 and the first pad PD1 provided in the driving unit 100. The third transmission line RM3 can be disposed in the third through-hole TSV3 formed in the second single-crystalline semiconductor substrate 210. The third through-hole TSV3 can be arranged to overlap with the circuit board 300 and the second pad PD2 in the second pad region PDA2, and the third transmission line RM3 can be partially disposed in the connection line layer 500 and can be arranged to overlap with the driving unit 100. The third transmission line RM3 can be a line for transmitting a signal applied from the circuit board 300 to the driving unit 100.

[0135] The transmission lines RM1, RM2, and RM3 can respectively include connection lines RML1, RML2, and RML3 provided in the connection line layer 500 (see Figure 12 and 13 ) and conductive vias RVA1, RVA2, and RVA3 provided in the through-holes TSV1, TSV2, and TSV3 of the second single-crystalline semiconductor substrate 210 (see Figure 12 and Figure 13 ). The transmission lines RM1, RM2, and RM3 are lines for electrically connecting the layers above and below the second single-crystalline semiconductor substrate 210 to each other, and the arrangement and design of the through-holes TSV1, TSV2, and TSV3 formed in the second single-crystalline semiconductor substrate 210 can be changed depending on the arrangement of the layers electrically connected to the transmission lines RM1, RM2, and RM3.

[0136] The heat dissipation member HTM can include a heat dissipation layer 810 (hereinafter, also referred to as the first heat dissipation layer) provided on the lower surfaces of the driving unit 100 and the display unit 200 and a plurality of heat dissipation substrates 910 and 920 provided below the heat dissipation layer 810.

[0137] The heat dissipation layer 810 may be disposed around the driving unit 100. The heat dissipation layer 810 may be around the driving unit 100 (e.g., may surround the driving unit 100), and may be disposed on the lower surface of the display unit 200. For example, the heat dissipation layer 810 may contact each of the lower surface and the side surface of the driving unit 100 and may be around each of the lower surface and the side surface of the driving unit 100 (e.g., may surround each of the lower surface and the side surface of the driving unit 100), and may extend around the driving unit 100 to cover the entire portion of the lower surface of the display unit 200 that does not overlap with the driving unit 100. The heat dissipation layer 810 may be in direct contact with the first single-crystalline semiconductor substrate 110 of the driving unit 100, and may be in direct contact with the connection line layer 500 disposed below the second single-crystalline semiconductor substrate 210. In addition, the heat dissipation layer 810 may overlap each of the driving circuit layer 120 of the driving unit 100, the pixel circuit unit 220 of the display unit 200, and the display element layer 230.

[0138] The heat dissipation layer 810 may include a material having a high thermal conductivity so as to effectively transfer the heat generated from the driving unit 100, the display unit 200, and the circuit board 300 to the heat dissipation substrates 910 and 920. The heat dissipation layer 810 may include a material having a higher thermal conductivity than the thermal conductivities of the single-crystalline semiconductor substrates 110 and 210 with which the heat dissipation layer 810 is in direct contact, and the heat generated from the driving unit 100 and the display unit 200 may be transferred to the heat dissipation layer 810 instead of the single-crystalline semiconductor substrates 110 and 210. For example, the heat dissipation layer 810 may include a metal material having a high thermal conductivity such as tungsten (W), aluminum (Al), and / or copper (Cu) and / or inorganic particles having a high thermal conductivity such as graphene and / or graphite.

[0139] The heat dissipation substrates 910 and 920 may be disposed below the heat dissipation layer 810. The heat dissipation substrates 910 and 920 may overlap the driving unit 100 and the display unit 200, and may dissipate the heat transferred to the heat dissipation layer 810 to the outside. As an example, the heat dissipation substrates 910 and 920 may include a first heat dissipation substrate 910 disposed to overlap the driving unit 100 and a second heat dissipation substrate 920 that does not overlap with the driving unit 100 and is spaced apart (e.g., separated) from the first heat dissipation substrate 910.

[0140] The first heat dissipation substrate 910 may be arranged to cover the driving unit 100 and the periphery of the driving unit 100. The first heat dissipation substrate 910 may be arranged to be biased towards one side in the second direction DR2 with respect to the center of the display unit 200, and may completely overlap with the part of the driving unit 100 and the circuit board 300. A part of the first heat dissipation substrate 910 may overlap with the driving unit 100, and other parts of the first heat dissipation substrate 910 may overlap with the display unit 200 exposed around the driving unit 100 and the circuit board 300 disposed above the display unit 200. Additionally, the first heat dissipation substrate 910 may be around the side surface of the driving unit 100 (e.g., may surround the side surface of the driving unit 100).

[0141] The second heat dissipation substrate 920 may be separated from (e.g., spaced apart from) the first heat dissipation substrate 910, and may not overlap with the driving unit 100. The second heat dissipation substrate 920 may be arranged to be biased towards the other side in the second direction DR2 with respect to the center of the display unit 200, and may overlap with the part of the display unit 200 that does not overlap with the driving unit 100 and the circuit board 300. However, the present disclosure is not limited thereto, and the heat dissipation substrates 910 and 920 may not be divided into the first heat dissipation substrate 910 and the second heat dissipation substrate 920, and may be integrally formed with each other.

[0142] In one or more embodiments, the corresponding side surfaces of the first heat dissipation substrate 910 and the second heat dissipation substrate 920 may be aligned with the side surface of the display unit 200. The first heat dissipation substrate 910 and the second heat dissipation substrate 920 may fill the step between the driving unit 100 and the display unit 200. However, the present disclosure is not limited thereto.

[0143] The heat dissipation substrates 910 and 920 may include materials with high thermal conductivity to effectively dissipate the heat generated from the driving unit 100, the display unit 200, and the circuit board 300. For example, the heat dissipation substrates 910 and 920 may be made of metal materials with high thermal conductivity such as tungsten (W), aluminum (Al), and / or copper (Cu).

[0144] The display device 10 may include different single-crystalline semiconductor substrates 110 and 210 included in the driving unit 100 and the display unit 200, respectively, and may include a plurality of transmission lines RM1, RM2, and RM3 that connect the different single-crystalline semiconductor substrates 110 and 210 to each other. The transmission lines RM1, RM2, and RM3 may be respectively disposed in through holes TSV1, TSV2, and TSV3 formed in the second single-crystalline semiconductor substrate 210, and may transmit electrical signals for driving the display device 10. The transmission lines RM1, RM2, and RM3 are centrally disposed in a partial area of the display device 10, and accordingly, when the display device 10 is driven, a large amount of heat may be generated in the driving unit 100, the display unit 200, and the circuit board 300 around the through holes TSV1, TSV2, and TSV3. The display device 10 according to one or more embodiments may effectively dissipate heat by including a heat dissipation layer 810 and heat dissipation substrates 910 and 920 as heat dissipation members HTM disposed around the driving unit 100.

[0145] Hereinafter, the structure of the driving circuit layer 120 of the driving unit 100 and the display element layer 230 of the display unit 200 will be described in detail with reference to other drawings.

[0146] Figure 9 is a schematic cross-sectional view of a driving unit according to one or more embodiments.

[0147] Reference Figure 9 , the driving unit 100 may include a first single-crystalline semiconductor substrate 110 and a driving circuit layer 120 disposed on the first single-crystalline semiconductor substrate 110. Figure 9 The cross-sectional structure of a data driver 700 of a circuit unit disposed in the driving unit 100 is schematically shown.

[0148] The first single-crystalline semiconductor substrate 110 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The first single-crystalline semiconductor substrate 110 may be a substrate doped with a first type of impurity. A plurality of well regions WA may be provided in the upper surface of the first single-crystalline semiconductor substrate 110. The plurality of well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the above-mentioned first type of impurity. For example, when the first type of impurity is a P-type impurity, the second type of impurity may be an N-type impurity. Alternatively, when the first type of impurity is an N-type impurity, the second type of impurity may be a P-type impurity.

[0149] Each of the plurality of well regions WA includes a source region SA corresponding to the source electrode of the first transistor PTR1, a drain region DA corresponding to the drain electrode of the first transistor PTR1, and a channel region CH disposed between the source region SA and the drain region DA.

[0150] The bottom insulating film BINS can be disposed between the gate electrode GE and the well region WA. The side surface insulating film SINS can be disposed on the side surface of the gate electrode GE. The side surface insulating film SINS can be disposed on the bottom insulating film BINS.

[0151] Each of the source region SA and the drain region DA can be a region doped with a first type of impurity. The gate electrode GE of the first transistor PTR1 can overlap with the well region WA in the third direction DR3. The channel region CH can overlap with the gate electrode GE in the third direction DR3. The source region SA can be disposed on one side of the gate electrode GE, and the drain region DA can be disposed on the other side of the gate electrode GE.

[0152] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 can be a region having an impurity concentration lower than that of the source region SA due to the bottom insulating film BINS. The second low-concentration impurity region LDD2 can be a region having an impurity concentration lower than that of the drain region DA due to the bottom insulating film BINS. The distance between the source region SA and the drain region DA can be increased by the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH of each of the first transistors PTR1 can be increased, and thus, the punch-through and hot carrier phenomena caused by the short channel can be prevented.

[0153] The first single-crystal semiconductor substrate 110 can include a plurality of first transistors PTR1 that constitute a plurality of circuit elements of the driving unit 100. The first transistors PTR1 included in the first single-crystal semiconductor substrate 110 can constitute the driving circuit unit 400 or the data driver 700.

[0154] When forming the driving circuit layer 120 on the silicon wafer substrate, a process of reducing the thickness of the first single-crystal semiconductor substrate 110 can be performed. The first single-crystal semiconductor substrate 110 can have a thickness smaller than the thickness of the wafer substrate on which the semiconductor process for forming the driving circuit layer 120 is performed. In some embodiments, the first single-crystal semiconductor substrate 110 can have a thickness of 100 μm or less (for example, a thickness in the range of 80 μm to 100 μm).

[0155] The driving circuit layer 120 may include a first semiconductor insulating film SINS1, a second semiconductor insulating film SINS2, a plurality of contact electrodes CTE, a first interlayer insulating film INS1, a second interlayer insulating film INS2, a plurality of conductive layers ML1 to ML8, and a plurality of vias VA1 to VA8. The driving circuit layer 120 may include lines electrically connected to a plurality of first transistors PTR1 included in the first single crystal semiconductor substrate 110.

[0156] The first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2 may be disposed on the first single crystal semiconductor substrate 110. The first semiconductor insulating film SINS1 may be an insulating film disposed on the first single crystal semiconductor substrate 110, and the second semiconductor insulating film SINS2 may be an insulating film disposed on the gate electrode GE of the first transistor PTR1 and the first semiconductor insulating film SINS1. The first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2 may each be formed as a silicon carbonitride (SiC x N y )-based inorganic film and / or a silicon oxide (SiO x )-based inorganic film, but is not limited thereto. In Figure 9 , the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2 are each shown to be formed as a single layer having a suitable thickness (e.g., a predetermined thickness), but the present disclosure is not limited thereto. The first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2 may also have a structure in which a plurality of layers are stacked.

[0157] The plurality of contact electrodes CTE may be disposed on the first single crystal semiconductor substrate 110. Each of the plurality of contact electrodes CTE may be connected through a hole passing through the semiconductor insulating films SINS1 and SINS2 to one of the gate electrode GE, the source region SA, and the drain region DA of each of the first transistors PTR1 included in the first single crystal semiconductor substrate 110. Each of the plurality of contact electrodes CTE may be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or their alloys or compounds. The upper surfaces of the plurality of contact electrodes CTE may be exposed without being covered by the semiconductor insulating films SINS1 and SINS2.

[0158] The first interlayer insulating film INS1 may be disposed on the plurality of contact electrodes CTE and the semiconductor insulating films SINS1 and SINS2. The second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1. The first interlayer insulating film INS1 and the second interlayer insulating film INS2 may each be formed as a silicon carbonitride (SiC x N y) type inorganic film and / or silicon oxide (SiO x ) type inorganic film, but not limited thereto. In Figure 9 it has been shown that the first interlayer insulating film INS1 and the second interlayer insulating film INS2 are each formed as a single layer, but the present disclosure is not limited thereto. The first interlayer insulating film INS1 and the second interlayer insulating film INS2 may each have a structure in which a plurality of layers are stacked, and may be provided between the first conductive layer ML1 to the eighth conductive layer ML8 to be described later.

[0159] The first conductive layer ML1 to the eighth conductive layer ML8 and the first via VA1 to the eighth via VA8 may be electrically connected to a plurality of contact electrodes CTE, and may form a driving circuit unit 400 or a data driver 700 of the driving unit 100. A plurality of first transistors PTR1 included in the first single crystal semiconductor substrate 110 may be electrically connected to each other through the first conductive layer ML1 to the eighth conductive layer ML8 and the first via VA1 to the eighth via VA8, and may form a driving circuit unit 400 and a data driver 700 of the driving unit 100.

[0160] The first conductive layer ML1 may be connected to the contact electrode CTE through the first via VA1. The first conductive layer ML1 may be provided on the contact electrode CTE, and the first via VA1 may be provided between the first conductive layer ML1 and the contact electrode CTE and in contact with each of the first conductive layer ML1 and the contact electrode CTE. The second conductive layer ML2 may be connected to the first conductive layer ML1 through the second via VA2. The second conductive layer ML2 may be provided on the first conductive layer ML1, and the second via VA2 may be provided between the first conductive layer ML1 and the second conductive layer ML2 and in contact with each of the first conductive layer ML1 and the second conductive layer ML2.

[0161] The third conductive layer ML3 can be connected to the second conductive layer ML2 through the third via VA3. The fourth conductive layer ML4 can be connected to the third conductive layer ML3 through the fourth via VA4, the fifth conductive layer ML5 can be connected to the fourth conductive layer ML4 through the fifth via VA5, and the sixth conductive layer ML6 can be connected to the fifth conductive layer ML5 through the sixth via VA6. The third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be sequentially disposed on the second conductive layer ML2, and the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be disposed between the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The third via VA3 to the sixth via VA6 can be in contact with different conductive layers disposed above and below the third via VA3 to the sixth via VA6, respectively. The seventh via VA7 can be disposed on the sixth conductive layer ML6. The seventh via VA7 can be in contact with the seventh conductive layer ML7 and the sixth conductive layer ML6 disposed above and below the seventh via VA7, respectively.

[0162] The first conductive layer ML1 to the sixth conductive layer ML6 and the first via VA1 to the seventh via VA7 can be disposed in the first interlayer insulating film INS1. The first conductive layer ML1 to the sixth conductive layer ML6 and the first via VA1 to the seventh via VA7 can form a first driving circuit layer disposed in the first interlayer insulating film INS1 of the driving circuit layer 120.

[0163] The seventh conductive layer ML7 can be connected to the sixth conductive layer ML6 through the seventh via VA7. The seventh conductive layer ML7 can be disposed on the first interlayer insulating film INS1 and the sixth conductive layer ML6, and the seventh via VA7 can be disposed between the sixth conductive layer ML6 and the seventh conductive layer ML7 and in contact with each of the sixth conductive layer ML6 and the seventh conductive layer ML7. The eighth conductive layer ML8 can be connected to the seventh conductive layer ML7 through the eighth via VA8. The eighth conductive layer ML8 can be disposed on the seventh conductive layer ML7, and the eighth via VA8 can be disposed between the seventh conductive layer ML7 and the eighth conductive layer ML8 and in contact with each of the seventh conductive layer ML7 and the eighth conductive layer ML8. The upper surface of the eighth conductive layer ML8 can be exposed without being covered by the second interlayer insulating film INS2 and can be electrically connected to the transmission lines RM1, RM2, and RM3 disposed in the above-mentioned connection line layer 500.

[0164] The seventh conductive layer ML7, the eighth via VA8, and the eighth conductive layer ML8 can be disposed in the second interlayer insulating film INS2. The seventh conductive layer ML7, the eighth via VA8, and the eighth conductive layer ML8 can form a second driving circuit layer disposed in the second interlayer insulating film INS2 of the driving circuit layer 120.

[0165] In Figure 9 it has been shown that the first conductive layer ML1 to the eighth conductive layer ML8 and the first via hole VA1 to the eighth via hole VA8 are sequentially stacked, but the arrangement and connection of the first conductive layer ML1 to the eighth conductive layer ML8 and the first via hole VA1 to the eighth via hole VA8 can be variably changed depending on the circuit of the driving circuit unit 400 of the driving unit 100 and the data driver 700. Figure 9 The connection structure shown in is merely an example, and the connection of the driving circuit layer 120 provided in the driving unit 100 of the display device 10 is not limited thereto. In addition, the driving circuit layer 120 may not necessarily include the first conductive layer ML1 to the eighth conductive layer ML8 and the first via hole VA1 to the eighth via hole VA8, and some of the first conductive layer ML1 to the eighth conductive layer ML8 and some of the first via hole VA1 to the eighth via hole VA8 may be omitted, or a larger number of conductive layers and via holes may be provided.

[0166] The first conductive layer ML1 to the eighth conductive layer ML8 and the first via hole VA1 to the eighth via hole VA8 may be made of substantially the same material. For example, each of the first conductive layer ML1 to the eighth conductive layer ML8 and each of the first via hole VA1 to the eighth via hole VA8 may be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or their alloys or compounds.

[0167] The thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of each of the first via hole VA1, the second via hole VA2, the third via hole VA3, the thickness of the fourth via hole VA4, the thickness of the fifth via hole VA5, and the thickness of the sixth via hole VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be substantially the same as each other. For example, the thickness of the first conductive layer ML1 may be approximately The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be approximately And each of the thicknesses of the first vias VA1, the second vias VA2, the third vias VA3, the fourth vias VA4, the fifth vias VA5, and the sixth vias VA6 may be substantially

[0168] Each of the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than each of the thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. Each of the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than each of the thicknesses of the seventh vias VA7 and the eighth vias VA8. Each of the thicknesses of the seventh vias VA7 and the eighth vias VA8 may be greater than each of the thicknesses of the first vias VA1, the second vias VA2, the third vias VA3, the fourth vias VA4, the fifth vias VA5, and the sixth vias VA6. The thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be substantially the same as each other. For example, each of the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately Each of the thicknesses of the seventh vias VA7 and the eighth vias VA8 may be approximately

[0169] Figure 10 is a plan view showing a pixel defining film disposed in a display area of a display unit and first electrodes and emission regions of a plurality of sub-pixels according to one or more embodiments.

[0170] Reference Figure 10 , each of the plurality of pixels PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first to third sub-pixels SP1, SP2, and SP3 may include emission regions EA1, EA2, and EA3, respectively. For example, the first sub-pixel SP1 may include a first emission region EA1, the second sub-pixel SP2 may include a second emission region EA2, and the third sub-pixel SP3 may include a third emission region EA3.

[0171] In a plan view, each of a first emission region EA1, a second emission region EA2, and a third emission region EA3 may have a quadrilateral shape such as a rectangular shape, a square shape, or a rhombus shape. For example, in a plan view, the third emission region EA3 may have a rectangular shape including a short side extending in a first direction DR1 and a long side extending in a second direction DR2. Additionally, in a plan view, each of the second emission region EA2 and the first emission region EA1 may have a rectangular shape including a long side extending in the first direction DR1 and a short side extending in the second direction DR2.

[0172] Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be a region defined by a pixel defining layer PDL. For example, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be a region defined by a first pixel defining layer PDL1.

[0173] A length of the third emission region EA3 in the first direction DR1 may be less than a length of the first emission region EA1 in the first direction DR1 and may be less than a length of the second emission region EA2 in the first direction DR1. The length of the first emission region EA1 in the first direction DR1 and the length of the second emission region EA2 in the first direction DR1 may be substantially the same as each other.

[0174] In each of a plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the second direction DR2. Additionally, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the first direction DR1. An area of the first emission region EA1, an area of the second emission region EA2, and an area of the third emission region EA3 may be different from each other.

[0175] In Figure 10 it has been shown that each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 has a quadrilateral shape in a plan view, but the present disclosure is not limited thereto. For example, in a plan view, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have other polygonal shapes, a circular shape, or an elliptical shape in addition to the quadrilateral shape.

[0176] The first emission region EA1 can emit first light, the second emission region EA2 can emit second light, and the third emission region EA3 can emit third light. Here, the first light can be light in the red wavelength band, the second light can be light in the green wavelength band, and the third light can be light in the blue wavelength band. For example, the blue wavelength band can indicate that the main peak wavelength of the light is included in the wavelength band of approximately 370 nm to approximately 460 nm, the green wavelength band can indicate that the main peak wavelength of the light is included in the wavelength band of approximately 480 nm to approximately 560 nm, and the red wavelength band can indicate that the main peak wavelength of the light is included in the wavelength band of approximately 600 nm to approximately 750 nm.

[0177] In a plan view, the first electrode AND of the light-emitting element (see Figure 12 ) can have a rectangular shape. Among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the shape of the first electrode AND of the light-emitting element in the plan view can be different. For example, in the plan view, each of the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the second sub-pixel SP2 can have a rectangular shape including a long side extending in the first direction DR1 and a short side extending in the second direction DR2. In the plan view, the first electrode AND of the third sub-pixel SP3 can have a rectangular shape including a short side extending in the first direction DR1 and a long side extending in the second direction DR2. The length of the first electrode AND of the third sub-pixel SP3 in the first direction DR1 can be less than the length of the first electrode AND of each of the first sub-pixel SP1 and the second sub-pixel SP2 in the first direction DR1. The length of the first electrode AND of the first sub-pixel SP1 in the second direction DR2 can be greater than the length of the first electrode AND of the second sub-pixel SP2 in the second direction DR2.

[0178] The first electrode AND of the light-emitting element can be connected to the reflective electrode layer RL (see Figure 12 ) through an electrode via VAP (see Figure 12 ). The electrode via VAP can overlap with the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 in the third direction DR3.

[0179] At least one trench TRC can be for disconnecting the light-emitting stack IL (see Figure 12The structure of at least one charge generation layer. At least one trench TRC may be provided between the first emission region EA1 and the second emission region EA2, between the first emission region EA1 and the third emission region EA3, and between the second emission region EA2 and the third emission region EA3. More specifically, at least one trench TRC may be provided between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the second sub-pixel SP2, between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the third sub-pixel SP3, and between the first electrode AND of the second sub-pixel SP2 and the first electrode AND of the third sub-pixel SP3.

[0180] Figure 11 is a plan view showing a pixel defining film provided in a display area of a display unit and first electrodes and emission regions of a plurality of sub-pixels according to one or more embodiments.

[0181] Reference Figure 11 , except for the shapes of the first emission region EA1, the second emission region EA2, and the third emission region EA3 in the plan view, the current embodiment is substantially the same as the Figure 10 embodiment, and thus, descriptions that are repetitive of the description of the Figure 10 embodiment are omitted.

[0182] In the plan view, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be arranged in a hexagonal structure having a hexagonal shape. In this case, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1, but the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the first diagonal direction DD1 and the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 is a direction between the first direction DR1 and the second direction DR2 and may refer to a direction inclined 45° with respect to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 may be a direction orthogonal to the first diagonal direction DD1.

[0183] In Figure 10 and Figure 11 , it has been shown that each of the plurality of pixels PX includes three emission regions EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may also include four emission regions.

[0184] In addition, the arrangement of the emission regions of the plurality of pixels PX is not limited to Figure 10 and Figure 11The arrangement shown. For example, the emission regions of the plurality of pixels PX may be in a bar structure in which the emission regions are arranged along the first direction DR1, in a diamond arrangement in which the emission regions have a diamond arrangement, or in a hexagonal structure in which the emission regions arranged have a hexagonal shape in a plan view. structure, or in a hexagonal structure in which the emission regions arranged have a hexagonal shape in a plan view. is a registered trademark of Samsung Display Co., Ltd. of Korea.

[0185] Figure 12 and Figure 13 are cross-sectional views showing a part of the display region and the non-display region of a display unit according to one or more embodiments. Figure 12 and Figure 13 show a schematic cross-sectional structure of the display region DAA, the non-display region NA, and the pad region PDA.

[0186] Referring Figure 12 and Figure 13 , the display unit 200 may include a semiconductor backplane SBP, a light-emitting element backplane EBP, a light-emitting element layer EML, a packaging layer TFE, an adhesive layer ADL, a color filter layer CFL, a lens LNS, a filling layer FIL, and a cover layer DCL. In one or more embodiments, the display unit 200 may further include a polarizer disposed on the cover layer DCL. The connection line layer 500 may be disposed between the second single-crystalline semiconductor substrate 210 of the semiconductor backplane SBP and the first single-crystalline semiconductor substrate 110. Alternatively, the connection line layer 500 may be disposed between the light-emitting element layer EML and the first single-crystalline semiconductor substrate 110.

[0187] The semiconductor backplane SBP may include a second single-crystalline semiconductor substrate 210 including a plurality of second transistors PTR2, a plurality of semiconductor insulating films disposed on the plurality of second transistors PTR2, and a plurality of contact electrodes CTE respectively electrically connected to the plurality of second transistors PTR2. The plurality of second transistors PTR2 may be the first transistor T1 to the sixth transistor T6 constituting Figure 6 the pixel circuit or the scanning transistors and light-emitting transistors of the gate drivers 610 and 620.

[0188] The second single-crystalline semiconductor substrate 210 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The second single-crystalline semiconductor substrate 210 may be a substrate doped with a first type of impurity. A plurality of well regions WA may be provided in the upper surface of the second single-crystalline semiconductor substrate 210. The plurality of well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the above-mentioned first type of impurity. For example, when the first type of impurity is a P-type impurity, the second type of impurity may be an N-type impurity. Alternatively, when the first type of impurity is an N-type impurity, the second type of impurity may be a P-type impurity.

[0189] Similar to the first single-crystalline semiconductor substrate 110, the second single-crystalline semiconductor substrate 210 may include a plurality of second transistors PTR2. The structure of the second transistor PTR2 may be the same as the structure of the first transistor PTR1, and thus, its detailed description is omitted.

[0190] In the display device 10, the first transistor PTR1 included in the first single-crystalline semiconductor substrate 110 of the driving unit 100 and the second transistor PTR2 included in the second single-crystalline semiconductor substrate 210 of the display unit 200 may be formed on different wafer substrates. According to one or more embodiments, in the display device 10, the sizes and / or line widths, etc. of the first transistor PTR1 included in the first single-crystalline semiconductor substrate 110 and the second transistor PTR2 included in the second single-crystalline semiconductor substrate 210 may be different from each other.

[0191] For example, in the display device 10, the minimum line width of the first transistor PTR1 included in the first single-crystalline semiconductor substrate 110 may be smaller than the minimum line width of the second transistor PTR2 included in the second single-crystalline semiconductor substrate 210. The semiconductor process performed on the first wafer substrate to form the first transistor PTR1 may be a process with a higher resolution than the semiconductor process performed on the second wafer substrate to form the second transistor PTR2, and the sizes of elements such as transistors manufactured according to the semiconductor process performed on the first wafer substrate may be smaller than the sizes of elements such as transistors manufactured according to the semiconductor process performed on the second wafer substrate. In other words, the semiconductor process performed on the first wafer substrate may be a finer process than the semiconductor process performed on the second wafer substrate.

[0192] As described above, in a plan view, the first single-crystalline semiconductor substrate 110 of the driving unit 100 may have an area smaller than that of the second single-crystalline semiconductor substrate 210 of the display unit 200, and components having small sizes may be provided on the first single-crystalline semiconductor substrate 110 with high integration, so that power consumption can be reduced and the yield of the driving unit 100 can be improved. On the other hand, in a plan view, the second single-crystalline semiconductor substrate 210 of the display unit 200 has an area larger than that of the first single-crystalline semiconductor substrate 110, and a process with a relatively large line width can be performed on the second single-crystalline semiconductor substrate 210. When the second transistor PTR2 is included in the second single-crystalline semiconductor substrate 210, the second transistor PTR2 can be formed with a larger area compared to when the second transistor PTR2 is included in the first single-crystalline semiconductor substrate 110, and the second transistor PTR2 constituting the pixel circuit does not require high integration. Accordingly, the semiconductor process performed on the first wafer substrate can be performed as a high-cost process with a small line width, and the semiconductor process performed on the second wafer substrate can be performed as a low-cost process with a relatively large line width.

[0193] In one or more embodiments, the lengths of the channel regions CH of the plurality of transistors PTR1 and PTR2 may be different from each other, and the minimum line width or length of the channel region CH of the first transistor PTR1 may be smaller than the minimum line width or length of the channel region CH of the second transistor PTR2. The minimum line width or length of the channel region CH of the first transistor PTR1 may be 100 nm or less, or may be in the range of 2 nm to 80 nm. The minimum line width or length of the channel region CH of the second transistor PTR2 may be 100 nm or more, or may be in the range of 100 nm to 5 μm.

[0194] The second single crystal semiconductor substrate 210 may include a plurality of through vias TSV1, TSV2, and TSV3 that are spaced apart from each other (e.g., spaced apart from each other). The through vias TSV1, TSV2, and TSV3 may penetrate from the upper surface of the second single crystal semiconductor substrate 210 to the lower surface of the second single crystal semiconductor substrate 210, and may also pass through a plurality of semiconductor insulating films SINS3 and SINS4 and interlayer insulating films INS3, INS4, INS5, and INS6 provided on the second single crystal semiconductor substrate 210. Conductive vias RVA1, RVA2, and RVA3 of transmission lines RM1, RM2, and RM3 may be provided in the through vias TSV1, TSV2, and TSV3. The through vias TSV1, TSV2, and TSV3 may form connection channels of the transmission lines RM1, RM2, and RM3 that electrically connect the driving unit 100 to the pixel circuit unit 220 and the second pad PD2 of the display unit 200. In one or more embodiments, the through vias TSV1, TSV2, and TSV3 of the second single crystal semiconductor substrate 210 may be formed by a through-silicon via (TSV) process of forming holes through the wafer substrate. By forming the through vias TSV1, TSV2, and TSV3 in the second single crystal semiconductor substrate 210, the display element layer 230 and the driving unit 100 may be electrically connected to each other through the transmission lines RM1, RM2, and RM3 without separate wiring.

[0195] The process of reducing the thickness of the second single crystal semiconductor substrate 210 may be performed after bonding the driving unit 100 to the silicon wafer substrate. The second single crystal semiconductor substrate 210 may have a thickness smaller than the thickness of the wafer substrate on which the process for forming the conductive layer is performed. In one or more embodiments, the second single crystal semiconductor substrate 210 may have a thickness of 100 μm or less (e.g., a thickness in the range of 80 μm to 100 μm).

[0196] The pixel circuit unit 220 may be provided on the second single crystal semiconductor substrate 210. The pixel circuit unit 220 may include a part of the semiconductor backplane SBP and the light-emitting element backplane EBP.

[0197] The third semiconductor insulating film SINS3 may be provided on the second single crystal semiconductor substrate 210 and the second transistor PTR2. The third semiconductor insulating film SINS3 may be formed as a silicon carbonitride (SiC x N y )-based inorganic film and / or a silicon oxide (SiO x )-based inorganic film, but is not limited thereto.

[0198] The fourth semiconductor insulating film SINS4 may be provided on the third semiconductor insulating film SINS3. The fourth semiconductor insulating film SINS4 may be formed as a silicon oxide (SiO x )-based inorganic film, but is not limited thereto.

[0199] Each of the plurality of contact electrodes CTE can be connected to one of the gate electrodes GE, source regions SA, and drain regions DA of each of the second transistors PTR2 through holes passing through the third semiconductor insulating film SINS3 and the fourth semiconductor insulating film SINS4. Each of the plurality of contact electrodes CTE can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or their alloys or compounds.

[0200] The light-emitting element backplane EBP can include third to seventh interlayer insulating films INS3, INS4, INS5, INS6, and INS7 and a plurality of transfer conductive layers RMT. The transfer conductive layers RMT can include lines electrically connected to the plurality of second transistors PTR2 included in the second single-crystalline semiconductor substrate 210, a plurality of scan lines GL and data lines DL provided in the display unit 200, and a plurality of terminals DTD and GDT. In one or more embodiments, the light-emitting element backplane EBP can further include an eighth insulating layer INS8 and a reflective electrode layer RL.

[0201] The third interlayer insulating film INS3 can be provided on the plurality of contact electrodes CTE and the semiconductor insulating films SINS3 and SINS4. The fourth interlayer insulating film INS4 can be provided on the third interlayer insulating film INS3. The fifth interlayer insulating film INS5, the sixth interlayer insulating film INS6, and the seventh interlayer insulating film INS7 can be sequentially provided on the fourth interlayer insulating film INS4. The plurality of transfer conductive layers RMT can be provided between the third interlayer insulating film INS3 and the seventh interlayer insulating film INS7. The third interlayer insulating film INS3 to the seventh interlayer insulating film INS7 can each be formed as a silicon carbonitride (SiC x N y )-based inorganic film and / or a silicon oxide (SiO x )-based inorganic film, but is not limited thereto. In Figure 12 and Figure 13 it has been shown that each of the third interlayer insulating film INS3 to the seventh interlayer insulating film INS7 is formed as a single layer, but the present disclosure is not limited thereto. The third interlayer insulating film INS3 to the seventh interlayer insulating film INS7 can each have a structure in which a plurality of layers are stacked, and can be provided between the conductive layers included in the transfer conductive layer RMT.

[0202] The transmission conductive layer RMT may have a structure similar to that of the plurality of conductive layers ML1 to ML8 and the plurality of vias VA1 to VA8 of the driving circuit layer 120. The transmission conductive layer RMT may be configured to form a line or terminals DTD and GTD provided in the display unit 200 by including one or more conductive layers and vias provided between the one or more conductive layers. For example, the transmission conductive layer RMT provided in the display area DAA of the pixel circuit unit 220 may be electrically connected to the second transistor PTR2. Figure 12 and Figure 13 the transmission conductive layer RMT shown in may be connected to a plurality of second transistors PTR2 to form Figure 6 the pixel circuit. The transmission conductive layer RMT may be used as a connection line connecting the second transistor PTR2 and other circuit elements to each other. Additionally, in one or more embodiments, some of the transmission conductive layers RMT provided in the display area DAA of the pixel circuit unit 220 may be scan lines GL or data lines DL, or may be used as connection lines constituting the gate drivers 610 and 620.

[0203] The pixel circuit unit 220 may include a plurality of terminals DTD and GTD provided in the non-display area NA. The plurality of terminals DTD and GTD may include data terminals DTD electrically connected to the data lines DL and gate terminals GTD electrically connected to the gate drivers 610 and 620. The data terminals DTD may be electrically connected to the data lines DL and the first transmission line RM1, and the gate terminals GTD may be electrically connected to the gate drivers 610 and 620 and the second transmission line RM2.

[0204] The connection line layer 500 may be provided on the lower surface of the second single-crystalline semiconductor substrate 210. The connection line layer 500 may include an interlayer insulating film RINS and a plurality of connection lines RML1, RML2, and RML3.

[0205] The interlayer insulating film RINS may be provided on the lower surface of the second single-crystalline semiconductor substrate 210. The interlayer insulating film RINS may be formed as a silicon carbonitride (SiC x N y )-type inorganic film and / or a silicon oxide (SiO x )-type inorganic film, but is not limited thereto. In Figure 12 and Figure 13 it has been shown that the interlayer insulating film RINS is formed as a single layer, but the present disclosure is not limited thereto, and the interlayer insulating film RINS may also have a structure in which a plurality of layers are stacked and the plurality of layers may be provided between the connection lines RML1, RML2, and RML3.

[0206] The connection lines RML1, RML2, and RML3 can form transmission lines RM1, RM2, and RM3 together with a plurality of conductive vias RVA1, RVA2, and RVA3. The connection lines RML1, RML2, and RML3 can include one or more conductive layers and one or more vias connecting the one or more conductive layers to each other. The description of the connection and structure of the connection lines RML1, RML2, and RML3 can be the same as the description of the above-mentioned plurality of conductive layers ML1 to ML8 and vias VA1 to VA8. The connection lines RML1, RML2, and RML3 can be electrically connected to the pixel circuit unit 220 and / or the second pad PD2 through the conductive vias RVA1, RVA2, and RVA3 provided in the through holes TSV1, TSV2, and TSV3 of the second single crystal semiconductor substrate 210, and can be electrically connected to the drive circuit layer 120 of the drive unit 100.

[0207] According to one or more embodiments, the display unit 200 of the display device 10 can include a first through hole TSV1, a second through hole TSV2, and a third through hole TSV3 passing through the second single crystal semiconductor substrate 210. The first to third through holes TSV1, TSV2, and TSV3 can each be provided in the non-display area NA. As described above, the first through hole TSV1 and the third through hole TSV3 can be provided in the pad area PDA of the display unit 200 (for example, see Figure 4 ), and the second through hole TSV2 can be provided to overlap with the gate drivers 610 and 620 in the non-display area NA (for example, see Figure 4 ).

[0208] The first transmission line RM1 connecting the data terminal DTD connected to the data line DL and the drive circuit layer 120 of the drive unit 100 to each other can be provided in the first through hole TSV1. The first through hole TSV1 can pass through the second single crystal semiconductor substrate 210, the semiconductor insulating films SINS3 and SINS4, and the interlayer insulating films INS3, INS4, INS5, and INS6, and can penetrate from the lower surface of the data terminal DTD to the lower surface of the second single crystal semiconductor substrate 210. The first conductive via RVA1 can be provided to extend from the lower surface of the data terminal DTD to the lower surface of the second single crystal semiconductor substrate 210, and can be connected to each of the data terminal DTD and the first connection line RML1. The first connection line RML1 can be the data transmission line GDL described above with reference to Figure 7 the description.

[0209] The second transmission line RM2 that connects the gate terminals GTD connected to the gate drivers 610 and 620 and the drive circuit layer 120 of the drive unit 100 to each other may be disposed in the second through-hole TSV2. The second through-hole TSV2 may penetrate the second single-crystalline semiconductor substrate 210, the semiconductor insulating films SINS3 and SINS4, and the interlayer insulating films INS3, INS4, INS5, and INS6, and may penetrate from the lower surface of the gate terminal GTD to the lower surface of the second single-crystalline semiconductor substrate 210. The second conductive via RVA2 may be disposed to extend from the lower surface of the gate terminal GTD to the lower surface of the second single-crystalline semiconductor substrate 210, and may be connected to each of the gate terminal GTD and the second connection line RML2. The second connection line RML2 may be the control transmission line TCL described above with reference to Figure 7 the control transmission line TCL described above.

[0210] Figure 12 The through-holes and conductive vias shown in Figure 12 the non-display area NA may be the first through-hole TSV1 or the second through-hole TSV2 and the first conductive via RVA1 or the second conductive via RVA2, respectively. The terminals shown in

[0211] the non-display area NA may be the data terminal DTD or the gate terminal GTD. The first transmission line RM1 and the second transmission line RM2, and the first through-hole TSV1 and the second through-hole TSV2 differ from each other only in terms of their positions, numbers, and / or connection relationships where they are disposed, and may be substantially the same in terms of their cross-sectional structures.

[0212] In the display device 10, the circuit units formed in the driving unit 100 can be formed by a high-cost fine semiconductor process, and thus, the circuit units formed in the driving unit 100 can be formed with a high degree of integration on the first single-crystalline semiconductor substrate 110 having a small area. The manufacturing process of the driving unit 100 can have a high yield per unit wafer substrate, and the circuit elements (e.g., the first transistor PTR1) can have small sizes, so that the power consumption can also be reduced. In addition, by providing pixel circuits, some circuit elements, and lines for the light emission of the light-emitting elements in the display unit 200, it is possible to prevent the degree of integration of the first single-crystalline semiconductor substrate 110 from becoming too high. In addition, by optimizing the number of the vias TSV1, TSV2, and TSV3 provided with the transmission lines RM1, RM2, and RM3 connecting the display unit 200 and the driving unit 100 to each other, it is possible to reduce or minimize the space of the vias TSV1, TSV2, and TSV3 having a suitable diameter (e.g., a predetermined diameter) and a suitable interval (e.g., spaced apart) from each other.

[0213] The reflective electrode layer RL can be provided on the seventh interlayer insulating film INS7. The reflective electrode layer RL can include one or more reflective electrodes RL1, RL2, RL3, and RL4. For example, as Figure 12 shown, the reflective electrode layer RL can include the first to fourth reflective electrodes RL1, RL2, RL3, and RL4.

[0214] Each of the first reflective electrodes RL1 can be provided on the seventh interlayer insulating film INS7 and can be connected to a via passing through the seventh interlayer insulating film INS7. Each of the first reflective electrodes RL1 can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or their alloys or compounds. For example, each of the first reflective electrodes RL1 can be made of titanium nitride (TiN).

[0215] Each of the second reflective electrodes RL2 can be provided on the first reflective electrodes RL1. Each of the second reflective electrodes RL2 can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or their alloys or compounds. For example, each of the second reflective electrodes RL2 can be made of aluminum (Al).

[0216] Each of the third reflective electrodes RL3 can be disposed on the second reflective electrode RL2. Each of the third reflective electrodes RL3 can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or their alloys or compounds. For example, each of the third reflective electrodes RL3 can be made of titanium nitride (TiN).

[0217] Each of the fourth reflective electrodes RL4 can be disposed on the third reflective electrode RL3. Each of the fourth reflective electrodes RL4 can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or their alloys or compounds. For example, each of the fourth reflective electrodes RL4 can be made of titanium (Ti).

[0218] The second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element, and in one or more embodiments, the thickness of the second reflective electrode RL2 can be greater than the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, in one or more embodiments, the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately And the thickness of the second reflective electrode RL2 can be approximately

[0219] The eighth interlayer insulating film INS8 can be disposed on the seventh interlayer insulating film INS7. The eighth interlayer insulating film INS8 can be disposed between the reflective electrode layers RL adjacent to each other. In the first sub-pixel SP1, the eighth interlayer insulating film INS8 can be disposed on the reflective electrode layer RL. The eighth interlayer insulating film INS8 can be formed as an inorganic film such as silicon oxide (SiO x ) but is not limited thereto.

[0220] The ninth interlayer insulating film INS9 can be disposed on the eighth interlayer insulating film INS8 and the reflective electrode layer RL. The ninth interlayer insulating film INS9 can be formed as an inorganic film such as silicon oxide (SiO x ) but is not limited thereto.

[0221] In at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, considering the resonance distance of the light emitted from the light-emitting element, the eighth interlayer insulating film INS8 and / or the ninth interlayer insulating film INS9 may not be disposed under the first electrode AND.

[0222] For example, the first electrode AND of the third sub-pixel SP3 can be directly disposed on the fourth reflective electrode RL4 and may not overlap with the eighth interlayer insulating film INS8 and the ninth interlayer insulating film INS9. The first electrode AND of the second sub-pixel SP2 can be disposed on the ninth interlayer insulating film INS9, and the ninth interlayer insulating film INS9 can be directly disposed on the fourth reflective electrode RL4. That is, the first electrode AND of the second sub-pixel SP2 may not overlap with the eighth interlayer insulating film INS8. The first electrode AND of the first sub-pixel SP1 can be disposed on the ninth interlayer insulating film INS9 and may overlap with the eighth interlayer insulating film INS8.

[0223] In one or more embodiments, among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the distance between the first electrode AND and the reflective electrode layer RL may be different. In order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the main peak wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence and absence of the eighth interlayer insulating film INS8 and the ninth interlayer insulating film INS9 may be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, in Figure 12 the distance between the first electrode AND in the first sub-pixel SP1 and the reflective electrode layer RL may be greater than the distance between the first electrode AND in the second sub-pixel SP2 and the reflective electrode layer RL and the distance between the first electrode AND in the third sub-pixel SP3 and the reflective electrode layer RL, and the distance between the first electrode AND in the second sub-pixel SP2 and the reflective electrode layer RL may be greater than the distance between the first electrode AND in the third sub-pixel SP3 and the reflective electrode layer RL. However, the present disclosure is not limited thereto. The distance between the first electrode AND and the reflective electrode layer RL in each of the sub-pixels SP1, SP2, and SP3 can be differently modified and designed.

[0224] In addition, Figure 12 and Figure 13 show the setting of the eighth interlayer insulating film INS8 and the ninth interlayer insulating film INS9, but a tenth interlayer insulating film may be further disposed under the first electrode AND of each of the sub-pixels SP1 and SP2. In this case, the ninth interlayer insulating film INS9 and the tenth interlayer insulating film may be disposed under the first electrode AND of the second sub-pixel SP2, and the eighth interlayer insulating film INS8, the ninth interlayer insulating film INS9, and the tenth interlayer insulating film may be disposed under the first electrode AND of the first sub-pixel SP1.

[0225] Each of the electrode vias VAP can pass through the eighth interlayer insulating film INS8 and / or the ninth interlayer insulating film INS9 in the first sub-pixel SP1 and the second sub-pixel SP2 to connect to the exposed fourth reflective electrode RL4. Each of the electrode vias VAP can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or their alloys or compounds. The thickness of the electrode via VAP in the second sub-pixel SP2 can be less than the thickness of the electrode via VAP in the first sub-pixel SP1.

[0226] The display element layer 230 can be disposed on the light-emitting element backplane EBP. The display element layer 230 can include a light-emitting element layer EML, a packaging layer TFE, an adhesive layer ADL, an optical layer OPL, and a cover layer DCL. The display element layer 230 can include light-emitting elements electrically connected to the pixel circuit unit 220 and the driving unit 100 to emit light.

[0227] The light-emitting element layer EML can be disposed on the reflective electrode layer RL and the ninth interlayer insulating film INS9. The light-emitting element layer EML can include a pixel defining film PDL, a plurality of trenches TRC, and light-emitting elements each including a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0228] The first electrode AND of each of the light-emitting elements can be disposed on the ninth interlayer insulating film INS9 or the reflective electrode layer RL and can be connected to the electrode via VAP. The first electrode AND of each of the light-emitting elements can be connected to the second transistor PTR2 through the electrode via VAP, the first reflective electrode RL1 to the fourth reflective electrode RL4, the transmission conductive layer RMT, and the contact electrode CTE. The first electrode AND of each of the light-emitting elements can be made of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or their alloys or compounds. For example, the first electrode AND of each of the light-emitting elements can be made of titanium nitride (TiN).

[0229] The pixel defining film PDL can be disposed on a partial area of the first electrode AND of each of the light-emitting elements. The pixel defining film PDL can cover the edge of the first electrode AND of each of the light-emitting elements. The pixel defining film PDL is used to separate the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3.

[0230] The first emission area EA1 can be defined as an area where a first electrode AND, a light-emitting stack IL, and a second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 can be defined as an area where a first electrode AND, a light-emitting stack IL, and a second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 can be defined as an area where a first electrode AND, a light-emitting stack IL, and a second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0231] The pixel defining layer PDL can include first to third pixel defining layers PDL1, PDL2, and PDL3. The first pixel defining layer PDL1 can be disposed on the edge of the first electrode AND of each of the light-emitting elements, the second pixel defining layer PDL2 can be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 can be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 can be formed as an inorganic film such as silicon oxide (SiO x ) but is not limited thereto. Each of the thicknesses of the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 can be approximately

[0232] When the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 are formed as one pixel defining layer, the height of the one pixel defining layer increases, such that the first inorganic encapsulation layer TFE1 may be disconnected due to the step coverage. The step coverage refers to the ratio of the degree to which a thin film is coated on an inclined portion to the degree to which the thin film is coated on a flat portion. The lower the step coverage, the higher the possibility that the thin film will be disconnected at the inclined portion.

[0233] To prevent the first inorganic encapsulation layer TFE1 from being disconnected due to the step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 can have a cross-sectional structure with steps (which have a stepped shape). For example, the width of the first pixel defining layer PDL1 can be greater than the width of the second pixel defining layer PDL2 and the width of the third pixel defining layer PDL3, and the width of the second pixel defining layer PDL2 can be greater than the width of the third pixel defining layer PDL3. The width of the first pixel defining layer PDL1 refers to the length of the first pixel defining layer PDL1 in the horizontal direction defined by a first direction DR1 and a second direction DR2.

[0234] Each of the plurality of trenches TRC can pass through the first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3. In each of the plurality of trenches TRC, a portion of the eighth interlayer insulating film INS8 can be trenched, and the ninth interlayer insulating film INS9 can be penetrated.

[0235] At least one trench TRC can be disposed between sub-pixels SP1, SP2, and SP3 adjacent to each other. In Figure 12 and Figure 13 two trenches TRC are shown disposed between sub-pixels SP1, SP2, and SP3 adjacent to each other, but the present disclosure is not limited thereto.

[0236] The light-emitting stack IL can include a plurality of intermediate layers. In Figure 12 and Figure 13 the light-emitting stack IL is shown having a three-tandem structure including a first intermediate layer IL1, a second intermediate layer IL2, and a third intermediate layer IL3, but the present disclosure is not limited thereto. For example, the light-emitting stack IL can have a double-tandem structure including two intermediate layers.

[0237] In the three-tandem structure, the light-emitting stack IL can have a tandem structure including a plurality of intermediate layers IL1, IL2, and IL3 that emit different lights. For example, the light-emitting stack IL can include a first intermediate layer IL1 that emits a first light, a second intermediate layer IL2 that emits a third light, and a third intermediate layer IL3 that emits a second light. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 can be sequentially stacked.

[0238] The first intermediate layer IL1 can have a structure in which a first hole transport layer, a first organic light-emitting layer that emits a first light, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 can have a structure in which a second hole transport layer, a second organic light-emitting layer that emits a third light, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 can have a structure in which a third hole transport layer, a third organic light-emitting layer that emits a second light, and a third electron transport layer are sequentially stacked.

[0239] A first charge generation layer for supplying holes to the second intermediate layer IL2 and electrons to the first intermediate layer IL1 can be disposed between the first intermediate layer IL1 and the second intermediate layer IL2. The first charge generation layer can include an N-type charge generation layer that supplies electrons to the first intermediate layer IL1 and a P-type charge generation layer that supplies holes to the second intermediate layer IL2. The N-type charge generation layer can include a dopant of a metal material.

[0240] A second charge generation layer for supplying holes to the third intermediate layer IL3 and electrons to the second intermediate layer IL2 may be disposed between the second intermediate layer IL2 and the third intermediate layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second intermediate layer IL2 and a P-type charge generation layer for supplying holes to the third intermediate layer IL3.

[0241] The first intermediate layer IL1 may be disposed on the first electrode AND and the pixel defining film PDL, and may be disposed on the bottom surface of each of the trenches TRC. Due to the trenches TRC, the first intermediate layer IL1 may be disconnected between the adjacent sub-pixels SP1, SP2, and SP3. The second intermediate layer IL2 may be disposed on the first intermediate layer IL1. Due to the trenches TRC, the second intermediate layer IL2 may be disconnected between the adjacent sub-pixels SP1, SP2, and SP3. A cavity or an empty space ESS may be disposed between the first intermediate layer IL1 and the second intermediate layer IL2. The third intermediate layer IL3 may be disposed on the second intermediate layer IL2. The third intermediate layer IL3 may not be disconnected by the trenches TRC, and may be disposed to cover the second intermediate layer IL2 in each of the trenches TRC. That is, in the three-tandem structure, each of the plurality of trenches TRC may be a structure for disconnecting the first intermediate layer IL1 and the second intermediate layer IL2, the first charge generation layer, and the second charge generation layer of the light-emitting element layer EML between the adjacent sub-pixels SP1, SP2, and SP3. Additionally, in the two-tandem structure, each of the plurality of trenches TRC may be a structure for disconnecting the lower intermediate layer and the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer.

[0242] To stably disconnect the first intermediate layer IL1 and the second intermediate layer IL2 of the light-emitting element layer EML between the adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trenches TRC may be greater than the height of the pixel defining film PDL. The height of each of the plurality of trenches TRC refers to the length of each of the plurality of trenches TRC in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. To disconnect the first intermediate layer IL1 and the second intermediate layer IL2 of the light-emitting element layer EML between the adjacent sub-pixels SP1, SP2, and SP3, there may be other structures instead of the trenches TRC. For example, instead of the trenches TRC, a partition wall having an inverted conical shape may be disposed on the pixel defining film PDL.

[0243] The number of intermediate layers emitting different lights is not limited to Figure 12 and Figure 13The number shown in. For example, the light-emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other of the two intermediate layers may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and holes to the other intermediate layer may be disposed between the two intermediate layers.

[0244] In addition, in Figure 12 and Figure 13 it has been shown that the first to third intermediate layers IL1, IL2, and IL3 are all disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3, but the present disclosure is not limited thereto. For example, the first intermediate layer IL1 may be disposed in the first emission region EA1 and may not be disposed in the second emission region EA2 and the third emission region EA3. In addition, the second intermediate layer IL2 may be disposed in the second emission region EA2 and may not be disposed in the first emission region EA1 and the third emission region EA3. In addition, the third intermediate layer IL3 may be disposed in the third emission region EA3 and may not be disposed in the first emission region EA1 and the second emission region EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the color filter layer CFL may be omitted.

[0245] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be made of a transparent conductive oxide (TCO) capable of transmitting light therethrough, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and / or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and / or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is made of a semi-transmissive conductive material, the light-emitting efficiency of each of the first to third sub-pixels SP1, SP2, and SP3 may be improved by a microcavity.

[0246] The encapsulation layer TFE may be disposed on the light-emitting element layer EML. The encapsulation layer TFE may include at least one inorganic encapsulation layer TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. In addition, the encapsulation layer TFE may include at least one organic film to protect the light-emitting element layer EML from foreign substances such as dust. For example, the encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0247] The first inorganic encapsulation layer TFE1 can be disposed on the second electrode CAT, the organic encapsulation layer TFE2 can be disposed on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 can be disposed on the organic encapsulation layer TFE2. The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 can be formed as a composite film in which a plurality of inorganic films including a silicon nitride (SiN x ) layer, a silicon oxynitride (SiO x N y ) layer, a silicon oxide (SiO x ) layer, a titanium oxide (TiO x ) layer, and an aluminum oxide (AlO x ) layer are alternately stacked. The organic encapsulation layer TFE2 can be made of a monomer. Alternatively, the organic encapsulation layer TFE2 can be an organic film made of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin, etc.

[0248] The adhesive layer ADL can be disposed on the encapsulation layer TFE. The adhesive layer ADL can be a layer for adhering the encapsulation layer TFE and the layer disposed on the encapsulation layer TFE to each other. The adhesive layer ADL can be a double-sided adhesive member. Additionally, the adhesive layer ADL can be a transparent adhesive member made of, for example, a transparent adhesive or a transparent adhesive resin.

[0249] The optical layer OPL can include a color filter layer CFL, a filling layer FIL, and a plurality of lenses LNS. The color filter layer CFL can include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 can be disposed on the adhesive layer ADL.

[0250] The first color filter CF1 can overlap with the first emission region EA1. The first color filter CF1 can transmit the first light (i.e., light in the red wavelength band) therethrough. The red wavelength band can be a band from approximately 600 nm to approximately 750 nm. The first color filter CF1 can transmit the first light among the light emitted from the first emission region EA1 therethrough.

[0251] The second color filter CF2 can overlap with the second emission region EA2. The second color filter CF2 can transmit the second light (i.e., light in the green wavelength band) therethrough. The green wavelength band can be a band from approximately 480 nm to approximately 560 nm. The second color filter CF2 can transmit the second light among the light emitted from the second emission region EA2 therethrough.

[0252] The third color filter CF3 may overlap with the third emission region EA3. The third color filter CF3 may transmit the third light (i.e., light in the blue wavelength band) therethrough. The blue wavelength band may be a band from approximately 370 nm to approximately 460 nm. The third color filter CF3 may transmit the third light among the light emitted from the third emission region EA3 therethrough.

[0253] Each of the plurality of lenses LNS may be disposed on a corresponding one of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the proportion of light guided to the front surface of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape that bulges in the upward direction (e.g., the third direction DR3).

[0254] The filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL may have a suitable refractive index (e.g., a predetermined refractive index) such that light propagates in the third direction DR3 at the interface between the plurality of lenses LNS and the filling layer FIL. Additionally, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film made of, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0255] The cover layer DCL may be disposed on the filling layer FIL. The cover layer DCL may be a glass substrate or a polymer resin. When the cover layer DCL is a glass substrate, the cover layer DCL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to adhere the cover layer DCL. When the cover layer DCL is a glass substrate, the cover layer DCL may serve as a package substrate. When the cover layer DCL is a polymer resin such as a resin, the cover layer DCL may be directly applied to the filling layer FIL. In one or more embodiments, the display unit 200 may further include a polarizing plate disposed on the cover layer DCL. The polarizing plate may be disposed on one surface of the cover layer DCL. The polarizing plate may be a structure for preventing or reducing visibility degradation due to external light reflection. The polarizing plate may include a linear polarizer and a phase retardation film. For example, the phase retardation film may be a λ / 4 plate (e.g., a quarter-wave plate), but is not limited thereto. However, when the visibility due to external light reflection is sufficiently improved by the first to third color filters CF1, CF2, and CF3, the polarizing plate may be omitted.

[0256] Hereinafter, various embodiments of the display device 10 will be described with reference to other drawings.

[0257] Figure 14 is a schematic cross-sectional view of a display device according to one or more embodiments.

[0258] ReferenceFigure 14 In the display device 10 according to one or more embodiments, the heat dissipation member HTM may protrude more than the outer surface of the display unit 200. In the display device 10, the side surfaces of the heat dissipation layer 810 of the heat dissipation member HTM and the heat dissipation substrates 910 and 920 may not be aligned with the side surface of the display unit 200. In the display device 10, in a plan view, the area of the region surrounded by the side surface of the heat dissipation member HTM may be larger than the area of the display unit 200.

[0259] For example, the area of the heat dissipation layer 810 in a plan view may be larger than the area of the display unit 200 in a plan view, and the portion provided on the lower surface of the display unit 200 may protrude more than the side surface of the display unit 200. The heat dissipation layer 810 may protrude parallel to each side surface of the display unit 200 in the first direction DR1 and / or the second direction DR2. The first heat dissipation substrate 910 and the second heat dissipation substrate 920 may each be provided on the lower surface of the heat dissipation layer 810, and the side surface of each of the first heat dissipation substrate 910 and the second heat dissipation substrate 920 may be aligned with the side surface of the heat dissipation layer 810. The first heat dissipation substrate 910 and the second heat dissipation substrate 920 may also each protrude more than the side surface of the display unit 200.

[0260] In the display device 10 according to one or more embodiments, the heat dissipation layer 810 of the heat dissipation member HTM may be provided to have an area larger than the areas of the display unit 200 and the driving unit 100, and may dissipate the heat generated by the driving unit 100 and the display unit 200 while diffusing the heat over a wider area. The display device 10 may manage heat generation more effectively by forming the heat dissipation member HTM to have a large area.

[0261] Figures 15 to 18 is a schematic cross-sectional view of a display device according to one or more embodiments.

[0262] Reference Figure 15, in a display device 10 according to one or more embodiments, the heat dissipation member HTM may further include a thermal barrier layer 820 disposed between the display unit 200 and the driving unit 100. The thermal barrier layer 820 may be disposed to overlap with the driving unit 100, and may overlap with a plurality of vias TSV1, TSV2, and TSV3 in which transmission lines RM1, RM2, and RM3 are disposed. In the display device 10, a large amount of heat may be generated in a portion of the driving unit 100 connected to the display unit 200, and the thermal barrier layer 820 may prevent or reduce the heat generated from the driving unit 100 from being transferred to the display unit 200. In one or more embodiments, the thermal barrier layer 820 may include a material having a thermal conductivity lower than that of the single crystal semiconductor substrates 110 and 210, and may prevent the heat generated from the driving unit 100 from diffusing to the display unit 200.

[0263] In one or more embodiments, the thermal barrier layer 820 may be disposed between the driving unit 100 and the display unit 200, may overlap with the transmission lines RM1, RM2, and RM3, and may include a plurality of vias in which connection lines electrically connected to the transmission lines RM1, RM2, and RM3 are disposed. Similar to the vias formed in the second single crystal semiconductor substrate 210, the thermal barrier layer 820 may include vias in which connection lines may be disposed, and the connection lines connected to the transmission lines RM1, RM2, and RM3 may pass through the thermal barrier layer 820 and may be connected to the driving unit 100. In one or more embodiments, at least a portion of the second single crystal semiconductor substrate 210 does not overlap with the heat dissipation layer 810.

[0264] Since the heat dissipation member HTM includes the thermal barrier layer 820, the heat dissipation layer 810 and the heat dissipation substrate 910 may be disposed to overlap with the driving unit 100. The heat dissipation layer 810 and the heat dissipation substrate 910 may be disposed to be biased toward the above-mentioned side in the second direction DR2 with respect to the center of the display unit 200, and may be disposed to cover the driving unit 100. Different from Figure 8 the embodiment of, the heat dissipation layer 810 may be disposed to overlap with the thermal barrier layer 820 around the driving unit 100, and may not be disposed below a portion of the display unit 200 that does not overlap with the thermal barrier layer 820. The heat dissipation substrate 910 may also be disposed on the heat dissipation layer 810, and may not be disposed below a portion of the display unit 200 that does not overlap with the thermal barrier layer 820. The heat dissipation layer 810 and the heat dissipation substrate 910 are disposed to be larger than Figure 8The heat dissipation layer 810, heat dissipation substrates 910 and 920 of the embodiments are small, and correspondingly, the heat dissipation layer 810 and the heat dissipation substrates 910 may protrude from the side surface which is the other side surface of the display unit 200 in the second direction DR2. The portions of the heat dissipation layer 810 and the heat dissipation substrates 910 that protrude from the display unit 200 may overlap with the circuit board 300 in the third direction DR3.

[0265] Reference Figure 16 , in the display device 10 according to one or more embodiments, in addition to the heat blocking layer 820, the heat dissipation member HTM may include heat dissipation layers 810 and 830 and heat dissipation substrates 910 and 920 disposed on the display unit 200. The display device 10 according to the current embodiment is different from the display device 10 according to Figure 15 the embodiments in that the heat dissipation member HTM of the display device 10 further includes a second heat dissipation layer 830 and a second heat dissipation substrate 920 disposed below the portion of the display unit 200 that does not overlap with the heat blocking layer 820.

[0266] The second heat dissipation layer 830 may include substantially the same material as that of the first heat dissipation layer 810, and may be disposed on the lower surface of the display unit 200. The second heat dissipation layer 830 may be disposed below the portion of the display unit 200 that does not overlap with the heat blocking layer 820, and may be formed to protrude from the side surface of the display unit 200. The second heat dissipation layer 830 may be disposed to be spaced apart (e.g., separated) from the heat blocking layer 820, and may not overlap with the driving unit 100. Similar to the first heat dissipation substrate 910, the second heat dissipation substrate 920 may be disposed on the lower surface of the second heat dissipation layer 830. The display device 10 may dissipate heat more effectively by including more heat dissipation layers 810 and 830 and heat dissipation substrates 910 and 920.

[0267] Reference Figure 17 , in the display device 10 according to one or more embodiments, the heat dissipation member HTM may further include a third heat dissipation layer 840 and a third heat dissipation substrate 930 disposed on the circuit board 300. The display device 10 according to the current embodiment is different from the display device 10 according to Figure 14 the embodiments in that the heat dissipation member HTM of the display device 10 further includes a third heat dissipation layer 840 and a third heat dissipation substrate 930.

[0268] The display device 10 may further include a third heat dissipation layer 840 disposed in the non-display area NA of the circuit board 300 and the display unit 200. The third heat dissipation layer 840 may overlap with the circuit board 300 and the vias TSV1, TSV2, and TSV3 formed in the display unit 200. The third heat dissipation layer 840 may dissipate heat generated from the circuit board 300 and the transmission lines RM1, RM2, and RM3 disposed in the display unit 200.

[0269] A third heat dissipation substrate 930 may be disposed on the third heat dissipation layer 840 on the circuit board 300. In one or more embodiments, the third heat dissipation substrate 930 may not overlap with the display unit 200 and the driving unit 100, and may only overlap with the circuit board 300. However, in one or more other embodiments, the third heat dissipation substrate 930 may at least partially overlap with the display unit 200. The third heat dissipation substrate 930 may protrude beyond the side surface of the circuit board 300 and may effectively dissipate the heat transferred through the third heat dissipation layer 840.

[0270] Reference Figure 18 , the display device 10 according to one or more embodiments is different from the Figure 17 display device 10 in that the heat dissipation member HTM of the display device 10 further includes a thermal barrier layer 820 disposed between the display unit 200 and the driving unit 100. The current embodiment may be considered as an embodiment in which the Figure 16 configuration of the display device 10 and the Figure 17 configuration of the display device 10 are combined with each other. The display device 10 according to the current embodiment has a structure substantially the same as the structure of the above-described embodiment, and thus, its detailed description is omitted.

[0271] Figure 19 is a perspective view showing a head-mounted display device according to one or more embodiments. Figure 20 is showing Figure 19 the exploded perspective view of the head-mounted display device.

[0272] Reference Figure 19 and 20 , the head-mounted display device 1000 according to one or more embodiments includes a first display device 11, a second display device 12, a display device housing part 1100, a housing part cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600, and a connector.

[0273] The first display device 11 provides an image to the left eye of the user, and the second display device 12 provides an image to the right eye of the user. Each of the first display device 11 and the second display device 12 is substantially the same as the display device 10 described with reference to Figure 1 and thus the description of the first display device 11 and the second display device 12 is omitted.

[0274] The first optical member 1510 may be disposed between the first display device 11 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 12 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0275] The intermediate frame 1400 may be disposed between the first display device 11 and the control circuit board 1600, and may be disposed between the second display device 12 and the control circuit board 1600. The intermediate frame 1400 is for supporting and fixing the first display device 11, the second display device 12, and the control circuit board 1600.

[0276] The control circuit board 1600 may be disposed between the intermediate frame 1400 and the display device housing portion 1100. The control circuit board 1600 may be connected to the first display device 11 and the second display device 12 through connectors. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA, and may transmit the digital video data DATA to the first display device 11 and the second display device 12 through connectors.

[0277] The control circuit board 1600 may transmit the digital video data DATA corresponding to the left-eye image optimized for the left eye of the user to the first display device 11, and may transmit the digital video data DATA corresponding to the right-eye image optimized for the right eye of the user to the second display device 12. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 11 and the second display device 12.

[0278] The display device housing portion 1100 is for housing the first display device 11, the second display device 12, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connectors. The housing portion cover 1200 is provided to cover an open surface of the display device housing portion 1100. The housing portion cover 1200 may include a first eyepiece 1210 on which the left eye of the user is placed and a second eyepiece 1220 on which the right eye of the user is placed. In Figure 19 and Figure 20The first eyepiece 1210 and the second eyepiece 1220 are shown as being separately provided in the [original text context], but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one eyepiece.

[0279] The first eyepiece 1210 may be aligned with the first display device 11 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 12 and the second optical member 1520. Accordingly, the user can view the image magnified into a virtual image by the first optical member 1510 of the first display device 11 through the first eyepiece 1210, and can view the image magnified into a virtual image by the second optical member 1520 of the second display device 12 through the second eyepiece 1220.

[0280] The head-mounted band 1300 is used to fix the display device housing part 1100 to the user's head, so that the first eyepiece 1210 and the second eyepiece 1220 of the housing part cover 1200 can be held in a state where they are respectively located on the user's left eye and right eye. When the display device housing part 1100 is implemented to have a light weight and a small size, the head-mounted display device 1000 may include spectacle temple arms instead of the head-mounted band 1300.

[0281] In addition, the head-mounted display device 1000 may further include a battery for power supply, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a Universal Serial Bus (USB) terminal, a DisplayPort, or a High-Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wireless Fidelity (WiFi) module, and / or a Bluetooth module.

[0282] Figure 21 is a perspective view showing a head-mounted display device according to one or more embodiments.

[0283] Reference Figure 21 , the head-mounted display device 1000_1 according to one or more embodiments may be a spectacle-type display device in which the display device housing part 1200_1 is implemented to have a light weight and a small size. The head-mounted display device 1000_1 according to one or more embodiments may include a display device 13, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, spectacle temple arms 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device housing part 1200_1.

[0284] The display device housing part 1200_1 can accommodate the display device 13, the optical member 1060, and the optical path conversion member 1070. An image displayed on the display device 13 can be magnified by the optical member 1060, converted in terms of the optical path by the optical path conversion member 1070, and provided to the user's right eye through the right-eye lens 1020. For this reason, the user can view an augmented reality image in which a virtual image displayed on the display device 13 seen through his / her right eye and a real image seen through the right-eye lens 1020 are combined with each other.

[0285] It has been shown in Figure 21 that the display device housing part 1200_1 is provided at the right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device housing part 1200_1 can be provided at the left end of the support frame 1030, and in this case, an image of the display device 13 can be provided to the user's left eye. Alternatively, the display device housing part 1200_1 can be provided at both the left end and the right end of the support frame 1030, and in this case, the user can view an image displayed on the display device 13 through his / her left eye and right eye.

[0286] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the aspects of the present disclosure. Therefore, the embodiments of the present disclosure are used only in a general and descriptive sense and are not for the purpose of limitation.

Claims

1. A display device, comprising: A first single-crystalline semiconductor substrate, on which a plurality of first transistors are located; A second single-crystalline semiconductor substrate, located on the first single-crystalline semiconductor substrate, the second single-crystalline semiconductor substrate having a display area; A plurality of sub-pixels, including light-emitting elements, located in the display area of the second single-crystalline semiconductor substrate; And A heat dissipation member, located around the first single-crystalline semiconductor substrate and below the second single-crystalline semiconductor substrate, Wherein, the second single-crystalline semiconductor substrate includes a plurality of first through-holes having first conductive vias electrically connected to a plurality of data lines and a plurality of second through-holes having second conductive vias electrically connected to a gate driver, the plurality of data lines are connected to the plurality of sub-pixels, and the gate driver is electrically connected to the plurality of sub-pixels, Wherein, the heat dissipation member overlaps with each of the plurality of first through-holes and the plurality of second through-holes and includes a first heat dissipation layer in contact with each of the lower surface and the side surface of the first single-crystalline semiconductor substrate and a first heat dissipation substrate located on the lower surface of the first heat dissipation layer, and Wherein, the area of the first single-crystalline semiconductor substrate in a plan view is smaller than the area of the second single-crystalline semiconductor substrate in the plan view.

2. The display device according to claim 1, wherein, The first heat dissipation layer covers the lower surface and the side surface of the first single-crystalline semiconductor substrate and overlaps with a portion of the lower surface of the second single-crystalline semiconductor substrate that does not overlap with the first single-crystalline semiconductor substrate, and Wherein, the heat dissipation member further includes a second heat dissipation substrate overlapping with a portion of the second single-crystalline semiconductor substrate where the first single-crystalline semiconductor substrate is not located.

3. The display device according to claim 2, wherein, The first heat dissipation layer overlaps with the display area in the thickness direction of the display device.

4. The display device according to claim 2, further comprising: A circuit board, located on the second single-crystalline semiconductor substrate and overlapping with the plurality of first through-holes, Wherein, the heat dissipation member further includes a third heat dissipation layer located on the circuit board and a third heat dissipation substrate located on the third heat dissipation layer.

5. The display device according to claim 4, wherein, The third heat dissipation layer is located on a portion of the second single-crystalline semiconductor substrate where the plurality of first through-holes are located, and Wherein, the third heat dissipation substrate does not overlap with the second single-crystalline semiconductor substrate.

6. The display device according to claim 4, wherein, The second single-crystalline semiconductor substrate further includes a plurality of third through-holes overlapping with pads, and Wherein, the plurality of first through-holes overlap with the circuit board in the thickness direction of the display device.

7. The display device according to claim 2, wherein, The outer side surfaces of each of the first heat dissipation layer, the first heat dissipation substrate, and the second heat dissipation substrate are aligned with the side surface of the second single-crystalline semiconductor substrate.

8. The display device according to claim 2, wherein, The outer side surfaces of each of the first heat dissipation layer, the first heat dissipation substrate, and the second heat dissipation substrate protrude outward from the side surface of the second single-crystalline semiconductor substrate.

9. The display device according to claim 1, wherein, The heat dissipation member further includes: A thermal barrier layer, located between the first single-crystalline semiconductor substrate and the second single-crystalline semiconductor substrate, Wherein, the thermal barrier layer includes a plurality of through holes, and connection lines passing through the thermal barrier layer and electrically connected to the first conductive via and the second conductive via are located in the plurality of through holes.

10. The display device according to claim 9, wherein, The first heat dissipation layer overlaps with the first single-crystalline semiconductor substrate, and wherein, at least a part of the second single-crystalline semiconductor substrate does not overlap with the first heat dissipation layer.

11. The display device according to claim 9, wherein, The first heat dissipation layer covers the lower surface and the side surface of the first single-crystalline semiconductor substrate, and wherein, the heat dissipation member further includes a second heat dissipation layer overlapping with a part of the lower surface of the second single-crystalline semiconductor substrate that does not overlap with the first single-crystalline semiconductor substrate, and a second heat dissipation substrate located on the lower surface of the second heat dissipation layer.

12. The display device according to claim 11, further comprising: A circuit board located on the second single-crystalline semiconductor substrate and overlapping with the plurality of first through holes, wherein, the heat dissipation member further includes a third heat dissipation layer located on the circuit board and a third heat dissipation substrate located on the third heat dissipation layer.

13. The display device according to any one of claims 1 to 12, wherein, The number of the plurality of first through holes is the same as the number of pixel columns of the plurality of sub-pixels arranged in the display area.

14. The display device according to claim 13, wherein, The plurality of data lines extend in a first direction on the second single-crystalline semiconductor substrate and are electrically connected to at least some of the plurality of first transistors, wherein, the display device further includes a plurality of scan lines extending in a second direction intersecting with the first direction on the second single-crystalline semiconductor substrate and electrically connected to the gate driver, and wherein, the number of the plurality of first through holes is the same as the number of the plurality of data lines.

15. The display device according to claim 1, wherein, The width of the first single-crystalline semiconductor substrate measured in one direction is greater than the width of the display area measured in the one direction.

16. A head-mounted display device, comprising: A frame; A plurality of display devices located in the frame; And Lenses respectively located on the plurality of display devices, wherein, the display device includes: A first single-crystalline semiconductor substrate, on which a plurality of first transistors are located; A second single-crystalline semiconductor substrate located on the first single-crystalline semiconductor substrate, the second single-crystalline semiconductor substrate having a display area; A plurality of sub-pixels including light-emitting elements located in the display area of the second single-crystalline semiconductor substrate; and A heat dissipation member located around the first single-crystalline semiconductor substrate and below the second single-crystalline semiconductor substrate, The second single-crystalline semiconductor substrate includes a plurality of first through holes having first conductive vias electrically connected to a plurality of data lines and a plurality of second through holes having second conductive vias electrically connected to a gate driver, the plurality of data lines are connected to the plurality of sub-pixels, and the gate driver is electrically connected to the plurality of sub-pixels, The heat dissipation member overlaps with each of the plurality of first through holes and the plurality of second through holes and includes a first heat dissipation layer in contact with each of the lower surface and the side surface of the first single-crystalline semiconductor substrate and a first heat dissipation substrate located on the lower surface of the first heat dissipation layer, and The area of the first single-crystalline semiconductor substrate in the plan view is smaller than the area of the second single-crystalline semiconductor substrate in the plan view.

17. The head-mounted display device according to claim 16, wherein, The first heat dissipation layer covers the lower surface and the side surface of the first single-crystalline semiconductor substrate and overlaps with a part of the lower surface of the second single-crystalline semiconductor substrate that does not overlap with the first single-crystalline semiconductor substrate, and wherein, the heat dissipation member further includes a second heat dissipation substrate that overlaps with a part of the second single-crystalline semiconductor substrate where the first single-crystalline semiconductor substrate is not located.

18. The head-mounted display device according to claim 16, wherein, The heat dissipation member further includes: a thermal barrier layer located between the first single-crystalline semiconductor substrate and the second single-crystalline semiconductor substrate, wherein, the thermal barrier layer includes a plurality of through holes, and connection lines passing through the thermal barrier layer and electrically connected to the first conductive via and the second conductive via respectively are located in the plurality of through holes.

19. The head-mounted display device according to claim 18, wherein, The first heat dissipation layer overlaps with the first single-crystalline semiconductor substrate, and wherein, at least a part of the second single-crystalline semiconductor substrate does not overlap with the first heat dissipation layer.

20. The head-mounted display device according to claim 18, wherein, The first heat dissipation layer covers the lower surface and the side surface of the first single-crystalline semiconductor substrate, and wherein, the heat dissipation member further includes a second heat dissipation layer that overlaps with a part of the lower surface of the second single-crystalline semiconductor substrate that does not overlap with the first single-crystalline semiconductor substrate and a second heat dissipation substrate located on the lower surface of the second heat dissipation layer.

Images