Display panel mother board, preparation method of display panel and display device

Abstract

The invention provides a display panel mother board, a preparation method of a display panel and a display device. The display panel mother board comprises a substrate, at least one test terminal and at least one test line. The substrate is divided into a panel area and a first cuttable area located on the periphery of the panel area, the panel area comprises a second cuttable area and a plurality of sub-board areas, the sub-board areas are separated by the second cuttable area, at least one test terminal is located on the substrate and located in the first cuttable area on the periphery of the panel area, and the surface, away from the substrate, of the test terminal is exposed. At least one test line is located on the substrate, the test line extends from the second cuttable area to the first cuttable area, one end of the test line is connected with the corresponding sub-board area, and the other end of the test line extends to the first cuttable area to be connected with the test terminal. In the display panel mother board, the optical parameters of the light-emitting device can be monitored in the evaporation process by utilizing the test terminal exposed on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display panel mother board, a method for manufacturing a display panel, and a display device. Background Art

[0002] An organic light-emitting diode (OLED) is an organic thin-film electroluminescent device. Due to its advantages such as simple manufacturing process, low cost, low power consumption, high brightness, wide viewing angle, high contrast, and flexible display capabilities, it has received great attention and is widely used in electronic display products. By setting an isolation structure in the display panel, the PPI (pixel density) of the display panel can be increased. For the composition, preparation, etc. of the isolation structure (which can also be called a partition structure or isolation structure), reference can also be made to the relevant descriptions in patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 099419, PCT / CN2024 / 099072, CN117979755A, CN117998900A, CN117062489A, CN117580403A, CN116583155A, CN116669477A, CN117396039A, CN116669480A, CN116600606A, CN117500332A, which will not be elaborated here.

[0003] However, during the processing of current display products, it is impossible to monitor the optical parameters of the product during the evaporation process. Summary of the Invention

[0004] In a first aspect of the present disclosure, a display panel mother board, a method for manufacturing a display panel, and a display device are provided. The display panel mother board includes a substrate, at least one test terminal, and at least one test line. The substrate is divided into a panel area and a first scribe area located outside the panel area. The panel area includes a second scribe area and a plurality of sub-panel areas, and each sub-panel area is separated by the second scribe area. At least one test terminal is located on the substrate and in the first scribe area outside the panel area, and the surface of the test terminal away from the substrate is exposed so that the test terminal can be connected to an external test signal. At least one test line is located on the substrate, and the test line extends from the second scribe area to the first scribe area. One end of the test line is connected to the corresponding sub-panel area, and the other end of the test line extends to the first scribe area to be connected to the test terminal.

[0005] In the above solution, by connecting the test terminals exposed on the substrate to an external test signal, it is possible to monitor the optical parameters of the display panel mother board during the evaporation process.

[0006] In a specific implementation manner of the first aspect of the present disclosure, there are multiple test terminals, multiple test lines, the sub-board area is divided into a display area and a bonding area located on at least one side of the display area, and the display panel mother board further includes multiple isolation structures and multiple light-emitting devices. The multiple isolation structures are located on the substrate and at least partially located in the display area. The isolation structures enclose to form multiple isolation openings in the display area, at least part of the light-emitting devices are located in the isolation openings, and the film layer of the light-emitting devices at least covers the panel area of the display panel mother board.

[0007] In the above solution, based on the isolation structures, the light-emitting devices can be formed by full-surface evaporation without the aid of a mask plate, thereby reducing the size between the light-emitting devices and achieving a higher pixel density.

[0008] In a specific implementation manner of the first aspect of the present disclosure, the multiple light-emitting devices at least include a first light-emitting device and a second light-emitting device that emit light of different colors. The second light-emitting device is limited in part of the isolation openings, and the first light-emitting device and the second light-emitting device are limited in the remaining part of the isolation openings, and the second light-emitting device is located on the side of the first light-emitting device away from the substrate. Among them, the film layer of the light-emitting device that at least covers the panel area is the same as the film layer corresponding to the second light-emitting device.

[0009] In a specific implementation manner of the first aspect of the present disclosure, the display panel mother board further includes an initial first encapsulation layer, and the initial first encapsulation layer is located on the side of the isolation structure away from the substrate. Among them, the initial first encapsulation layer includes multiple encapsulation units and an encapsulation material film layer. The orthographic projection of the encapsulation unit on the substrate covers the orthographic projection of the light-emitting device of one color of emitted light on the substrate, and the encapsulation material film layer covers the side of the encapsulation unit away from the substrate, and the orthographic projection of the encapsulation material film layer on the substrate at least covers the panel area.

[0010] In a specific implementation manner of the first aspect of the present disclosure, the test terminals and the light-emitting devices are located on opposite sides of the substrate, and the orthographic projection of the film layer corresponding to the light-emitting device on the substrate is located outside the orthographic projection of the test terminal on the substrate; and the orthographic projection of the encapsulation material film layer on the substrate is located outside the orthographic projection of the part of the test line in the first scribe area on the substrate, and the orthographic projection of the encapsulation material film layer on the substrate is located outside the orthographic projection of the test terminal on the substrate.

[0011] In a specific embodiment of the first aspect of the present disclosure, the test terminal and the light-emitting device are located on opposite sides of the substrate, and the orthographic projection of the film layer corresponding to the light-emitting device on the substrate completely covers the orthographic projection of the test terminal on the substrate; and the orthographic projection of the encapsulation material film layer on the substrate covers the orthographic projections of the test terminal and the test line on the substrate.

[0012] In a specific embodiment of the first aspect of the present disclosure, the test line includes at least two conductive layers.

[0013] In a specific embodiment of the first aspect of the present disclosure, the display panel mother board further includes a thin-film transistor, a first planarization layer, a first signal line, a second signal line, and a second planarization layer stacked in sequence on the substrate, and the second planarization layer is located on the side of the light-emitting device close to the substrate. The test line includes a first sub-test line located on the substrate and a second sub-test line located on the side of the first sub-test line away from the substrate. The first sub-test line is on the same layer and made of the same material as the first signal line, and the second sub-test line is on the same layer and made of the same material as the second signal line; and / or, the test terminal and the light-emitting device are located on the same side of the substrate, the orthographic projection of the second planarization layer on the substrate is outside the orthographic projection of the test terminal on the substrate, and the test terminal includes a first-layer sub-test terminal and a second-layer sub-test terminal. The first-layer sub-test terminal is on the same layer and made of the same material as the first signal line, and the second-layer sub-test terminal is on the same layer and made of the same material as the second signal line.

[0014] In a specific embodiment of the first aspect of the present disclosure, the isolation structure includes a support portion and a crown portion. The support portion is located between the crown portion and the substrate, and the orthographic projection of the surface of the support portion away from the substrate on the substrate is within the orthographic projection of the crown portion on the substrate.

[0015] In a specific embodiment of the first aspect of the present disclosure, the isolation structure further includes a bottom portion, and the bottom portion is located between the support portion and the substrate. The orthographic projection of the support portion on the substrate is within the orthographic projection of the bottom portion on the substrate.

[0016] The second aspect of the present disclosure provides a method for manufacturing a display panel, and the manufacturing method includes: providing a substrate, which is divided into a panel area and a first scribe area located outside the panel area. The panel area includes a second scribe area and a plurality of sub-panel areas, and each sub-panel area is separated by the second scribe area; forming at least one test terminal in the first scribe area of the substrate, and the surface of the test terminal away from the substrate is exposed to connect the test terminal to an external test signal; forming at least one test line on the substrate, and the test line extends from the second scribe area to the first scribe area. One end of the test line is connected to the corresponding display panel, and the other end of the test line extends to the first scribe area and is connected to the test terminal; cutting off the first scribe area and the second scribe area of the display panel mother board to obtain a plurality of display panels.

[0017] In the above solution, during the process of fabricating the display panel by the fabrication method of the display panel, the optical parameters of the light-emitting devices after full-surface evaporation are monitored by using the test terminals exposed on the substrate, which can timely detect problems and improve product quality. In addition, the test terminals are arranged in the first scribe area and are cut off later, without affecting the structure of the display panel.

[0018] In a specific embodiment of the second aspect of the present disclosure, the sub-board area is divided into a display area and a bonding area located on at least one side of the display area. The fabrication method further includes: before cutting the display panel mother board, forming a plurality of isolation structures on the evaporation side of the substrate, at least part of the isolation structures being located in the display area, and the isolation structures enclosing a plurality of isolation openings formed in the display area; forming a plurality of light-emitting devices, at least part of the light-emitting devices being located in the isolation openings. Forming a plurality of light-emitting devices includes: forming a plurality of spaced-apart first electrodes in the display area, at least part of the first electrodes being located within the isolation openings; fabricating a light-emitting functional layer and a second electrode located in the isolation openings based on the isolation structures, and a light-emitting device being constituted by the first electrode, the light-emitting functional layer, and the second electrode stacked on top of each other in each isolation opening.

[0019] In the above solution, the isolation structures are used to partition the light-emitting devices after full-surface evaporation, which can avoid separately fabricating each light-emitting device using a mask plate and does not require considering the alignment accuracy problem during evaporation. Therefore, the gap between the light-emitting devices can be designed to be a smaller size, which is beneficial to improving the pixel density of the fabricated display panel.

[0020] In a specific embodiment of the second aspect of the present disclosure, fabricating a light-emitting functional layer and a second electrode located in the isolation openings based on the isolation structures includes: depositing a light-emitting material thin film and a first conductive material thin film, the light-emitting material thin film and the first conductive material thin film covering the isolation structures and the isolation openings, wherein the parts of the light-emitting material thin film and the first conductive material thin film located in the isolation openings respectively form the light-emitting functional layer and the second electrode; depositing a packaging material film layer to cover the light-emitting devices; testing the formed light-emitting devices based on at least one test terminal exposed on the substrate; forming a first photoresist layer on the packaging material film layer and performing a patterning process on the first photoresist layer to form a first photoresist pattern, the first photoresist pattern covering part of the isolation openings; etching the packaging material film layer, the light-emitting material thin film, and the first conductive material thin film based on the first photoresist pattern, wherein the remaining part of the packaging material film layer forms a packaging unit, and the light-emitting functional layer and the second electrode not covered by the packaging unit are etched; repeating the above process to form light-emitting devices and packaging units in the isolation openings where no light-emitting devices are formed, and all the packaging units constitute a first packaging layer.

[0021] In a specific embodiment of the second aspect of the present disclosure, when forming at least one test terminal in the first scribe area of the substrate, at least one test terminal is formed on the evaporation side of the substrate, and the test terminal and the light-emitting device are on the same side of the substrate. During the deposition of the light-emitting material thin film and the first conductive material thin film, the first scribe area is shielded so that the orthographic projections of the light-emitting material thin film and the first conductive material thin film on the substrate are outside the first scribe area to expose the test terminal. During the deposition of the encapsulation material film layer to cover the light-emitting device, the first scribe area is shielded so that the orthographic projection of the encapsulation material film layer on the substrate is outside the first scribe area to expose the test terminal.

[0022] In a specific embodiment of the second aspect of the present disclosure, the manufacturing method further includes: before forming a plurality of light-emitting devices, sequentially forming a thin-film transistor and a first planarization layer on the evaporation side of the substrate. The thin-film transistor is at least located in the display area, and the first planarization layer at least covers the panel area. Depositing a second conductive material thin film layer on the substrate with the first planarization layer formed thereon. Forming a second photoresist layer on the second conductive material thin film layer, and performing a patterning process on the second photoresist layer to form a second photoresist pattern that covers a part of the display area. Etching the second conductive material thin film layer based on the second photoresist pattern, wherein the remaining part of the second conductive material thin film layer in the display area is formed into a first signal line. Depositing a third conductive material thin film layer on the substrate with the second conductive material thin film layer formed thereon. Forming a third photoresist layer on the third conductive material thin film layer, and performing a patterning process on the third photoresist layer to form a third photoresist pattern that covers a part of the display area. Etching the third conductive material thin film layer based on the third photoresist pattern, wherein the remaining part of the third conductive material thin film layer in the display area is formed into a second signal line.

[0023] In a specific embodiment of the second aspect of the present disclosure, when forming the second photoresist layer on the second conductive material thin film layer, the second photoresist pattern also covers a part of the second scribe area and a part of the first scribe area. When etching the second conductive material thin film layer based on the second photoresist pattern, the remaining part of the second conductive material thin film layer in the second scribe area and the first scribe area is formed into a first sub-test line. When forming the third photoresist layer on the third conductive material thin film layer, the third photoresist pattern also covers a part of the second scribe area and a part of the first scribe area. When etching the third conductive material thin film layer based on the third photoresist pattern, the remaining part of the third conductive material thin film layer in the second scribe area and the first scribe area is formed into a second sub-test line, and the first sub-test line and the second sub-test line constitute a test line; and / or, the remaining part of the second conductive material thin film layer in the first scribe area is also formed into a first layer of sub-test terminals, and the remaining part of the third conductive material thin film layer in the first scribe area is also formed into a second layer of sub-test terminals, and the first layer of sub-test terminals and the second layer of sub-test terminals constitute a test terminal.

[0024] In a specific embodiment of the second aspect of the present disclosure, when forming at least one test terminal in the first scribe region of the substrate, at least one test terminal is formed on the non-evaporation side of the substrate, and the test terminal and the light-emitting device are located on different sides of the substrate. When depositing the light-emitting material thin film and the first conductive material thin film, the orthographic projections of the light-emitting material thin film and the first conductive material thin film on the substrate cover the panel region and the first scribe region of the substrate; when depositing the encapsulation material film layer to cover the light-emitting device, the orthographic projection of the encapsulation material film layer on the substrate covers the panel region and the first scribe region of the substrate.

[0025] In a specific embodiment of the second aspect of the present disclosure, the manufacturing method further includes: before forming a plurality of light-emitting devices, sequentially forming a thin-film transistor and a first planarization layer on the evaporation side of the substrate, the thin-film transistor is at least located in the display region, and the first planarization layer covers the panel region and the first scribe region; forming a via hole on the substrate, and the via hole exposes a partial surface of the test terminal close to the substrate; depositing a second conductive material thin film layer on the substrate with the first planarization layer formed thereon, and the second conductive material thin film layer fills the via hole; forming a second photoresist layer on the second conductive material thin film layer, and performing a patterning process on the second photoresist layer to form a second photoresist pattern, and the second photoresist pattern covers a part of the display region; etching the second conductive material thin film layer based on the second photoresist pattern, wherein the remaining part of the second conductive material thin film layer in the display region is formed into a first signal line; depositing a third conductive material thin film layer on the substrate with the second conductive material thin film layer formed thereon; forming a third photoresist layer on the third conductive material thin film layer, and performing a patterning process on the third photoresist layer to form a third photoresist pattern, and the third photoresist pattern covers a part of the display region; etching the third conductive material thin film layer based on the third photoresist pattern, wherein the remaining part of the third conductive material thin film layer in the display region is formed into a second signal line.

[0026] In a specific embodiment of the second aspect of the present disclosure, when forming the second photoresist layer on the second conductive material thin film layer, the second photoresist pattern also covers a part of the second scribe region and a part of the first scribe region, and the orthographic projection of the second photoresist pattern on the substrate partially overlaps with the orthographic projection of the test terminal on the substrate; etching the second conductive material thin film layer based on the second photoresist pattern, and the remaining part of the second conductive material thin film layer in the second scribe region and the first scribe region is formed into a first sub-test line; when forming the third photoresist layer on the third conductive material thin film layer, the third photoresist pattern also covers a part of the second scribe region and a part of the first scribe region, and the orthographic projection of the third photoresist pattern on the substrate partially overlaps with the orthographic projection of the test terminal on the substrate; etching the third conductive material thin film layer based on the third photoresist pattern, and the remaining part of the third conductive material thin film layer in the second scribe region and the first scribe region is formed into a second sub-test line, and the first sub-test line and the second sub-test line constitute a test line.

[0027] A third aspect of the present disclosure provides a display device, which includes a display panel obtained by the manufacturing method according to any one of the above second aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 FIG. is a schematic plan view of a display panel mother board provided by an embodiment of the present disclosure.

[0029] Figure 2 is Figure 1 FIG. is a schematic plan view of a daughter board area of the display panel mother board shown in a certain design.

[0030] Figure 3 is Figure 2 FIG. is a cross-sectional view of the daughter board area of the display panel mother board shown along M1-N1 in a certain design.

[0031] Figure 4 is Figure 1 FIG. is a schematic plan view of the display panel mother board shown in a certain design.

[0032] Figure 5 is Figure 4 FIG. is a cross-sectional view of the display panel mother board shown along M2-N2 in a certain design.

[0033] Figure 6 is Figure 1 FIG. is a schematic plan view of the display panel mother board shown in a certain design.

[0034] Figure 7 is Figure 6 FIG. is a cross-sectional view of the display panel mother board shown along M3-N3 in a certain design.

[0035] Figure 8 FIG. is a flowchart of a manufacturing method of a display panel provided by an embodiment of the present disclosure.

[0036] Figure 9 FIG. is a flowchart of another manufacturing method of a display panel provided by an embodiment of the present disclosure.

[0037] Figure 10 FIG. is a partial flowchart of a manufacturing method of a display panel provided by an embodiment of the present disclosure.

[0038] Figure 11 FIG. is a partial flowchart of a manufacturing method of a display panel provided by an embodiment of the present disclosure.

[0039] Figure 12 FIG. is a flowchart of a manufacturing method of a display panel provided by an embodiment of the present disclosure.

[0040] Figure 13Flow chart of another manufacturing method of a display panel provided by an embodiment of the present disclosure.

[0041] Figure 14 Cross-sectional schematic diagram under a design of a display panel provided by an embodiment of the present disclosure.

[0042] Description of reference numerals: 10 - Display panel mother board; 100 - Substrate; 101 - Panel area; 101a - Second cuttable area; 101b - Daughter board area; 101c - Display area; 101d - Bonding area; 102 - First cuttable area; 200 - Test terminal; 200a - First test terminal; 200b - Second test terminal; 210 - First layer sub - test terminal; 220 - Second layer sub - test terminal; 300 - Test line; 310 - First sub - test line; 320 Second sub - test line; V1 - Via hole; 400 - Isolation structure; 401 - Isolation opening; 410 - Support part; 420 - Crown part; 430 - Bottom part; 500 - Light - emitting device; 500a - First light - emitting device; 500b - Second light - emitting device; 500c - Third light - emitting device; 510 - First electrode; 520 - Light - emitting functional layer; 530 - Second electrode; 600 - Encapsulation structure; 600a - Initial first encapsulation layer; 610 - First encapsulation layer; 610a - Encapsulation material film layer; 611 - Encapsulation unit; 620 - Second encapsulation layer; 630 - Third encapsulation layer; 700 - Connection terminal; TFT - Thin - film transistor; 800a - First planarization layer; 800b - Second planarization layer; 900a - First signal line; 900b - Second signal line. Detailed implementation manners

[0043] Next, the technical solutions in the embodiments of this specification will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of this specification.

[0044] In the present disclosure, an isolation structure is provided at the gap between the light-emitting devices to separate the functional film layers of adjacent light-emitting devices. Thus, in the evaporation process of the functional film layer, it is only necessary to perform whole-surface evaporation on the display panel without the need to prepare the functional film layer of each light-emitting device separately with the aid of a mask plate. This process does not need to consider the problem of positioning accuracy during evaporation, so that the gap between the light-emitting devices can be designed to be smaller in size to increase the PPI.

[0045] In the preparation process of traditional display panels, the optical parameter monitoring of the display panel is carried out for independent light-emitting devices, which means that in the preparation process of the display panel corresponding to the present disclosure, it is necessary to etch the film layer formed after the whole-surface vapor deposition to form an independent packaging unit, and then monitor the optical parameters of the corresponding light-emitting devices in each packaging unit. Therefore, it is impossible to monitor the optical parameters of the entire film layer corresponding to the structure of the light-emitting device (such as the light-emitting functional layer and the second electrode) of the entire surface formed during the whole-surface vapor deposition process. If the monitoring cannot be carried out in time, problems cannot be discovered in time. For example, the light-emitting efficiency of a light-emitting device of a certain output light color is low or the color deviation is large under some signal parameters, and the discovered problems cannot be improved by adjusting the structure, material or process parameters of the light-emitting device, which is not conducive to improving the quality of the display panel.

[0046] In view of this, at least one embodiment of the present disclosure provides a display panel motherboard, a method for preparing a display panel, and a display device to at least solve the above technical problems. The display panel motherboard includes a substrate, at least one test terminal, and at least one test line. The substrate is divided into a panel area and a first cuttable area located outside the panel area. The panel area includes a second cuttable area and a plurality of sub-board areas, each of which is separated by the second cuttable area. At least one test terminal is located on the substrate and located in the first cuttable area outside the panel area. The test terminal is exposed away from the surface of the substrate so that the test terminal is connected to an external test signal. At least one test line is located on the substrate. The test line extends from the second cuttable area to the first cuttable area. One end of the test line is connected to the corresponding sub-board area, and the other end of the test line extends to the first cuttable area to connect to the test terminal. In this way, by utilizing the test terminals exposed on the substrate, optical parameters of the entire film layer (including the light-emitting functional layer and the second electrode of the light-emitting device) corresponding to a light-emitting device of an emitting light color formed in the sub-board area of ​​the display panel motherboard can be monitored, that is, optical parameters can be monitored during the evaporation process, and the test terminals are arranged in the first cuttable area of ​​the display panel motherboard, which does not affect the entire-surface evaporation process on the panel area on the display panel motherboard, thereby improving the quality of the display panel formed by the display panel motherboard while not affecting the production efficiency.

[0047] Next, the structure of the display panel mother board according to at least one embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, in these drawings, a spatial rectangular coordinate system is established based on the substrate to more intuitively present the positional relationship of the relevant structures in the display panel mother board. In this spatial rectangular coordinate system, the X-axis and the Y-axis are parallel to the plane where the substrate is located, and the Z-axis is perpendicular to the plane where the substrate is located.

[0048] In one embodiment of the present disclosure, as Figure 1 shown, the display panel mother board 10 includes a substrate 100, at least one test terminal 200, and at least one test line 300.

[0049] The substrate 100 is divided into a panel area 101 and a first cuttable area 102 located outside the panel area 101. The panel area 101 includes a second cuttable area 101a and a plurality of sub-board areas 101b, and each sub-board area 101b is separated by the second cuttable area 101a. The plurality of sub-board areas 101b correspond to a plurality of display panels. A plurality of display panels are formed on the same display panel mother board 10, that is, the plurality of display panels are processed and prepared based on the same display panel mother board 10. This can better control the process parameters, reduce the performance differences caused by factors such as different batches and different devices, maintain the stability of the display panel performance, and improve the production efficiency at the same time.

[0050] At least one test terminal 200, for example, a plurality of test terminals 200, is disposed on the substrate 100. The test terminal 200 is located in the first cuttable area 102 outside the panel area 101, and the surface of the test terminal 200 away from the substrate 100 is exposed so that the test terminal 200 can be connected to an external test signal. The exposure of the surface of the test terminal 200 away from the substrate 100 means that the test terminal 200 will not be covered by the film layers formed during the evaporation process, such as the film layers corresponding to the light-emitting devices 500, the first encapsulation layer 610, the second encapsulation layer 620, and the third encapsulation layer 630 mentioned later. Thus, the exposed test terminal 200 is connected to an external test signal to monitor the optical parameters of the display panel mother board 10 during the evaporation process.

[0051] For example, the test terminal 200 is mostly arranged to be connected to the input end or the output end corresponding to the sub-board area 101b (corresponding to the physical structure display panel) in the display panel mother board 10. For example, the test terminal 200 is connected to the electrode of the light-emitting device 500 mentioned later on the sub-board area 101b, so that it is convenient to monitor the optical performance of the light-emitting device 500 after the test terminal 200 is connected to an external test signal.

[0052] At least one test line 300, for example, multiple test lines 300, is located on the substrate 100. The test line 300 extends from the second scribe area 101a to the first scribe area 102. One end of the test line 300 is connected to the corresponding daughter board area 101b, and the other end of the test line 300 extends to the first scribe area 102 and is connected to the test terminal 200. The test line 300 is used to connect the test terminal 200 to a preset position on the circuit wire corresponding to the electrode of the light-emitting device 500 in the corresponding daughter board area 101b.

[0053] The embodiments of the present disclosure do not specifically introduce the case where the display panel mother board 10 includes one test terminal 200 and one test line 300. For example, one test line 300 can be used as a summary detection line and connected to one test terminal 200 to monitor the optical parameters of the display panels corresponding to all the daughter board areas 101b of the display panel mother board 10. This can be designed according to actual needs and will not be elaborated here.

[0054] In an embodiment of the present disclosure, as Figure 1 、 Figure 4 and Figure 6 shown, multiple test terminals 200 are provided, and multiple test lines 300 are provided. As Figure 2 and Figure 3 shown, the daughter board area 101b is divided into a display area 101c and a bonding area 101d located on at least one side of the display area 101c. The display panel mother board 10 further includes multiple isolation structures 400 and multiple light-emitting devices 500. The multiple isolation structures 400 are located on the substrate 100 and at least partially located in the display area 101c. The isolation structures 400 enclose multiple isolation openings 401 formed in the display area 101c. At least part of the light-emitting devices 500 is located in the isolation openings 401, and the film layer of the light-emitting devices 500 at least covers the panel area 101 of the display panel mother board 10.

[0055] In this way, multiple test lines 300 correspond to display panel connections formed by different sub-panel areas 101b, respectively, and are used to monitor optical parameters of different display panels at the same time to ensure the consistency of the test, which is conducive to unified evaluation and control of product quality. At the same time, compared with the situation of testing multiple display panels connected together, this solution can more easily and quickly locate the specific area where the fault occurs when a test problem occurs, which helps to carry out repairs or replacements in time and reduce production costs and time costs. In addition, this solution can obtain test data of multiple display panels at the same time, which is convenient for parallel analysis and comparison, and can more comprehensively understand the performance distribution of the product, providing richer data support for product optimization and improvement. At the same time, the functional film layers of adjacent light-emitting devices 500 are separated by the isolation structure 400. In this way, in the evaporation process of the functional film layer, it is only necessary to perform evaporation on the entire surface of the display panel without the need to use a mask plate to separately prepare the functional film layer of each light-emitting device 500. This process does not need to consider the alignment accuracy during evaporation, so that the gap between the light-emitting devices 500 can be designed to be smaller in size, so as to increase the PPI (Pixels Per Inch, pixel density) of the display panel corresponding to the display panel motherboard 10.

[0056] In at least one embodiment of the present disclosure, the light-emitting device 500 includes a first electrode 510 , a light-emitting functional layer 520 and a second electrode 530 sequentially stacked on a substrate 100 , and at least a portion of the light-emitting functional layer 520 of the light-emitting device 500 is located in the corresponding isolation opening 401 .

[0057] The embodiment of the present disclosure does not specifically limit the light-emitting functional layer 520 of the light-emitting device 500 in the display panel motherboard 10. For example, the light-emitting functional layer 520 may also include a first functional layer, a light-emitting layer, and a second functional layer, which are sequentially stacked on the first electrode 510. The first functional layer may include a hole injection layer, a hole transport layer, an electron blocking layer, etc. The second functional layer may include an electron injection layer, an electron transport layer, a hole blocking layer, etc. It should be noted that since carriers (holes, electrons) mainly crosstalk between adjacent light-emitting devices 500 through the first functional layer, the isolation structure 400 needs to be set so that the first functional layers of each light-emitting device 500 are electrically disconnected from each other.

[0058] In at least one embodiment of the present disclosure, the film layers corresponding to the first electrode 510 , the light-emitting functional layer 520 , and the second electrode 530 at least respectively cover the panel area 101 of the display panel motherboard 10 .

[0059] For example, Figure 4 and Figure 5As shown, after the film layers corresponding to the first electrode 510, the light-emitting functional layer 520, and the second electrode 530 are formed, they cover the panel area 101 of the display panel mother board 10 and do not cover the first scribe area 102. At this time, the test terminal 200 is on the evaporation side of the substrate 100 and on the same side as the light-emitting device 500. The surface of the test terminal 200 away from the substrate 100 is not covered by the film layers corresponding to the first electrode 510, the light-emitting functional layer 520, and the second electrode 530, so that the surface of the test terminal 200 on the substrate 100 away from the substrate 100 is exposed to connect to an external test signal.

[0060] Exemplarily, as Figure 6 and Figure 7 shown, after the film layers corresponding to the first electrode 510, the light-emitting functional layer 520, and the second electrode 530 are formed, they cover the panel area 101 and the first scribe area 102 of the display panel mother board 10, while the test terminal 200 is on the non-evaporation side of the substrate 100 and in the first scribe area 102, that is, the test terminal 200 and the light-emitting device 500 are on different sides of the substrate 100. Therefore, although on the evaporation side of the substrate 100, the film layers corresponding to the first electrode 510, the light-emitting functional layer 520, and the second electrode 530 cover the panel area 101 and the first scribe area 102 of the substrate 100, they do not cover the test terminal 200 on the non-evaporation side of the substrate 100, so that the surface of the test terminal 200 away from the substrate 100 is exposed to connect to an external test signal.

[0061] In at least one embodiment, as Figure 3 shown, the second electrode 530 is electrically connected to the isolation structure 400. That is, the second electrodes 530 of multiple light-emitting devices 500 are connected to each other through the isolation structure 400 to act as a common electrode, thereby alleviating the voltage drop problem generated when driving the second electrode 530.

[0062] Based on the above embodiments, the embodiments of the present disclosure also introduce a design scheme based on different structures of the display panel mother board 10 corresponding to different light-emitting colors of the light-emitting device 500. The specific content is as follows.

[0063] In an embodiment of the present disclosure, multiple light-emitting devices 500 at least include a first light-emitting device 500a and a second light-emitting device 500b that emit lights of different colors. The second light-emitting device 500b is limited in part of the isolation openings 401, and the first light-emitting device 500a and the second light-emitting device 500b are limited in the remaining isolation openings 401. The second light-emitting device 500b is on the side of the first light-emitting device 500a away from the substrate 100. Among them, the film layers of the light-emitting device 500 that at least cover the panel area 101 are the same as the film layers corresponding to the second light-emitting device 500b.

[0064] In at least one disclosed embodiment, a plurality of light-emitting devices 500 include a first light-emitting device 500a, a second light-emitting device 500b, and a third light-emitting device 500c that emit light of different colors. The first light-emitting device 500a and the third light-emitting device 500c are positioned in a partial isolation opening 401. The third light-emitting device 500c is located on a side of the first light-emitting device 500a away from the substrate 100. The second light-emitting device 500b and the third light-emitting device 500c are positioned in a partial isolation opening 401. The third light-emitting device 500c is located on a side of the second light-emitting device 500b away from the substrate 100. The remaining partial isolation openings 401 position the third light-emitting device 500c. Among them, the film layer of the light-emitting device 500 that at least covers the panel area 101 is the same as the film layer corresponding to the third light-emitting device 500c.

[0065] Exemplarily, as Figure 1 , Figure 2 and Figure 3 shown, the planar area of the sub-panel area 101b can be divided into a display area 101c and a non-display area located on at least one side of the display area 101c. Sub-pixels (which can be referred to as sub-pixels, etc.) can be arranged in the display area 101c. The physical structure of the sub-pixel can be the light-emitting device 500 in the following embodiments. Adjacent sub-pixels that emit light of different colors form a pixel (which can be referred to as a pixel unit, a large pixel, etc.). The arrangement density of the pixels in the display area 101c represents the pixel density.

[0066] The light-emitting devices 500 are classified into a first light-emitting device 500a, a second light-emitting device 500b, and a third light-emitting device 500c that emit light of different colors. During the manufacturing process, the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c are manufactured in sequence. The structure of the display panel mother board 10 includes a substrate 100, an isolation structure 400, a first light-emitting device 500a, a second light-emitting device 500b, and a third light-emitting device 500c. The first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c respectively include a first electrode 510, a light-emitting functional layer 520, and a second electrode 530. The isolation structure 400 is at least located on the display area 101c of the sub-panel area 101b of the panel area 101 of the substrate 100. A plurality of isolation structures 400 are formed with isolation openings 401. The isolation openings 401 are respectively used to position the light-emitting functional layer 520 and the second electrode 530 corresponding to the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c.

[0067] Specifically, the first electrodes 510 corresponding to the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c are on the same layer. For example, the first electrodes 510 corresponding to the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c are formed by the same process. Based on the formation process of the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c in sequence, the first electrode 510, the light-emitting functional layer 520, and the second electrode 530 corresponding to the first light-emitting device 500a, as well as the light-emitting functional layer 520 and the second electrode 530 of the second light-emitting device 500b located on the side of the first light-emitting device 500a away from the substrate 100, are limited within a partial isolation opening 401. The first electrode 510, the light-emitting functional layer 520, and the second electrode 530 corresponding to the second light-emitting device 500b, as well as the light-emitting functional layer 520 and the second electrode 530 of the third light-emitting device 500c located on the side of the second light-emitting device 500b away from the substrate 100, are limited within a partial isolation opening 401. The first electrode 510, the light-emitting functional layer 520, and the second electrode 530 corresponding to the third light-emitting device 500c are limited within the remaining isolation opening 401. At the same time, the light-emitting functional layer 520 and the second electrode 530 corresponding to the third light-emitting device 500c cover not only outside the sub-panel area 101b but also at least the second scribe area 101a, that is, the light-emitting functional layer 520 and the second electrode 530 corresponding to the third light-emitting device 500c cover at least the panel area 101.

[0068] In this way, the test terminals 200 exposed on the substrate 100 can be used to monitor the optical properties of the functional film layers corresponding to the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c obtained after full-surface evaporation, such as the light-emitting functional layer 520 and the second electrode 530, and can monitor the performance of the display panel mother board 10, timely detect problems in the full-surface evaporation process, and timely solve the problems and optimize the process.

[0069] In at least one embodiment of the present disclosure, the first light-emitting device 500a is a red light-emitting device, the second light-emitting device 500b is a blue light-emitting device, and the third light-emitting device 500c is a green light-emitting device.

[0070] Based on the above embodiments, in at least one embodiment of the present disclosure, as Figure 3As shown, the display panel mother board 10 further includes an initial first encapsulation layer 600a, which is located on the side of the isolation structure 400 away from the substrate 100. Among them, the initial first encapsulation layer 600a includes a plurality of encapsulation units 611 and an encapsulation material film layer 610a. The orthographic projection of the encapsulation unit 611 on the substrate 100 covers the orthographic projection of the light-emitting device 500 of one kind of light-emitting color on the substrate 100. The encapsulation material film layer 610a covers the side of the encapsulation unit 611 away from the substrate 100, and the orthographic projection of the encapsulation material film layer 610a on the substrate 100 at least covers the panel area 101.

[0071] For example, when preparing the first light-emitting device 500a, the first light-emitting device 500a is formed in each isolation opening 401, and an encapsulation material film layer 610a is formed to cover all the isolation openings 401. Then, the second electrode 530 and the light-emitting functional layer 520 of the first light-emitting device 500a in some of the isolation openings 401 (used to form the second light-emitting device 500b and the third light-emitting device 500c in the final product) are removed to form an encapsulation structure 600 with an independent structure. Based on this method, the second light-emitting device 500b and the third light-emitting device 500c are prepared in turn. In the case where the film layer on the part of the isolation openings 401 corresponding to the third light-emitting device 500c (where the first light-emitting device 500a and the second light-emitting device 500b are formed) is not removed, the first light-emitting device 500a and the second light-emitting device 500b respectively correspond to the encapsulation units 611, and the side of the third light-emitting device 500c away from the substrate 100 is covered with the encapsulation material film layer 610a. The encapsulation material film layer 610a is located on the side of the encapsulation unit 611 away from the substrate 100 and covers the encapsulation unit 611 in the area of the isolation opening 401 corresponding to the first light-emitting device 500a and the second light-emitting device 500b of the third light-emitting device 500c.

[0072] In at least one embodiment of the present disclosure, the initial first encapsulation layer 600a is an inorganic film layer. The initial first encapsulation layer 600a using the inorganic film layer will be formed into the encapsulation unit 611 of the third light-emitting device 500c later. The encapsulation unit 611, the encapsulation unit 611 corresponding to the first light-emitting device 500a, and the encapsulation unit 611 corresponding to the second light-emitting device 500b together form the first encapsulation layer 610. That is to say, the first encapsulation layer 610 is an inorganic film layer. Therefore, the first encapsulation layer 610 not only has good barrier performance, can effectively block water vapor and oxygen, improve the encapsulation effect, but also has advantages such as good chemical stability and high thermal stability, can effectively improve the protection effect on the light-emitting device 500, and thus improve the lifespan of the light-emitting device 500.

[0073] Based on different preparation processes of the display panel (specifically, the following embodiments can be referred to), the structure of the display panel mother board 10 has different design schemes, and the specific content is as follows.

[0074] In one embodiment of the present disclosure, as Figure 5 shown, the test terminal 200 and the light-emitting device 500 are located on the same side of the substrate 100. The orthographic projection of the film layer corresponding to the light-emitting device 500 on the substrate 100 is located outside the orthographic projection of the test terminal 200 on the substrate 100. The orthographic projection of the encapsulation material film layer 610a on the substrate 100 is located outside the orthographic projection of the portion of the test line 300 in the first scribe area 102 on the substrate 100, and the orthographic projection of the encapsulation material film layer 610a on the substrate 100 is located outside the orthographic projection of the test terminal 200 on the substrate 100.

[0075] Exemplarily, as Figure 5 shown, the display panel mother board 10 includes a substrate 100, a plurality of isolation structures 400, a plurality of light-emitting devices 500, a plurality of test lines 300, and a plurality of test terminals 200. The test terminals 200 are located on the same side of the substrate 100 as the light-emitting devices 500, the isolation structures 400, and the test lines 300, that is, the above structures are all located on the evaporation side of the substrate 100. At least a part of the plurality of isolation structures 400 is located in the display area 101c of the daughter board area 101b of the substrate 100. The plurality of light-emitting devices 500 are classified into a plurality of first light-emitting devices 500a, a plurality of second light-emitting devices 500b, and a plurality of third light-emitting devices 500c that emit light of different colors. Taking the preparation of the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c in sequence as an example, the orthographic projection of the film layer corresponding to the third light-emitting device 500c on the substrate 100 is located outside the orthographic projection of the test terminal 200 on the substrate 100 and outside the orthographic projection of the portion of the test line 300 in the first scribe area 102 on the substrate 100.

[0076] In the display area 101c, the isolation structure 400 encloses a plurality of isolation openings 401. In some of the isolation openings 401, a first light-emitting device 500a, a packaging unit 611, and a light-emitting functional layer 520 and a second electrode 530 of a third light-emitting device 500c are sequentially limited. In some of the isolation openings 401, a second light-emitting device 500b, a packaging unit 611, and a light-emitting functional layer 520 and a second electrode 530 of a third light-emitting device 500c are sequentially limited. In the remaining isolation openings 401, a third light-emitting device 500c is limited. The display panel mother board 10 further includes a packaging material film layer 610a. The packaging material film layer 610a covers the panel area 101 of the display panel mother board 10, that is, the orthographic projection of the packaging material film layer 610a on the substrate 100 is located outside the orthographic projection of the test terminal 200 on the substrate 100 and outside the orthographic projection of the part of the test line 300 in the first cuttable area 102 on the substrate 100. The packaging material film layer 610a and the packaging unit 611 corresponding to the first light-emitting device 500a and the second light-emitting device 500b form an initial first packaging layer 600a, and the part of the packaging material film layer 610a corresponding to the third light-emitting device 500c will form a packaging unit 611 corresponding to the third light-emitting unit subsequently. In this way, the test terminal 200 is exposed on the substrate 100 to monitor the optical parameters of the entire surface functional layer formed by the light-emitting device 500, such as the light-emitting functional layer 520 and the second electrode 530, by externally connecting a test signal to the test terminal 200 after the entire surface evaporation during the preparation process of the light-emitting device 500.

[0077] In another embodiment of the present disclosure, as Figure 7 shown, the test terminal 200 and the light-emitting device 500 are located on opposite sides of the substrate 100. The orthographic projection of the film layer corresponding to the light-emitting device 500 on the substrate 100 completely covers the orthographic projection of the test terminal 200 on the substrate 100. The orthographic projection of the packaging material film layer 610a on the substrate 100 completely covers the orthographic projections of the test terminal 200 and the test line 300 on the substrate 100.

[0078] Exemplarily, as Figure 7As shown in the figure, the display panel mother board 10 includes a substrate 100, a plurality of isolation structures 400, a plurality of light-emitting devices 500, a plurality of test lines 300, and a plurality of test terminals 200. The test terminals 200 are located on different sides of the substrate 100 relative to the light-emitting devices 500 and the isolation structures 400, that is, the non-evaporation side of the substrate 100. At least a part of the plurality of isolation structures 400 is located in the display area 101c of the daughter board area 101b of the substrate 100. The plurality of light-emitting devices 500 are classified into a plurality of first light-emitting devices 500a, a plurality of second light-emitting devices 500b, and a plurality of third light-emitting devices 500c that emit light of different colors. Taking the sequential preparation of the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c as an example, it can be known that the film layer corresponding to the third light-emitting device 500c covers the panel area 101 and the first scribe area 102 of the substrate 100, that is, the positive projection of the film layer corresponding to the third light-emitting device 500c, such as the light-emitting functional layer 520 and the second electrode 530, completely covers the positive projection of the test terminal 200 on the substrate 100 and the positive projection of the test line 300 on the substrate 100.

[0079] In the display area 101c, the isolation structures 400 enclose to form a plurality of isolation openings 401. The light-emitting functional layer 520 and the second electrode 530 of the first light-emitting device 500a, the encapsulation unit 611, and the third light-emitting device 500c are sequentially limited in some of the isolation openings 401. The light-emitting functional layer 520 and the second electrode 530 of the second light-emitting device 500b, the encapsulation unit 611, and the third light-emitting device 500c are sequentially limited in some of the isolation openings 401. The third light-emitting device 500c is limited in the remaining isolation openings 401. The display panel mother board 10 further includes an encapsulation material film layer 610a. The encapsulation material film layer 610a covers the panel area 101 and the first scribe area 102 of the display panel mother board 10, that is, the positive projection of the encapsulation material film layer 610a on the substrate 100 covers the positive projection of the test terminal 200 on the substrate 100 and the positive projection of the test line 300 on the substrate 100. The encapsulation material film layer 610a and the encapsulation unit 611 corresponding to the first light-emitting device 500a and the second light-emitting device 500b form an initial first encapsulation layer 600a, and the part of the encapsulation material film layer 610a corresponding to the third light-emitting device 500c will form the encapsulation unit 611 corresponding to the third light-emitting unit subsequently. In this way, the test terminal 200 is exposed on the substrate 100 to monitor the optical parameters of the entire surface functional layer formed by the light-emitting device 500, such as the light-emitting functional layer 520 and the second electrode 530, by connecting an external test signal to the test terminal 200 after the entire surface evaporation during the preparation process of the light-emitting device 500.

[0080] It should be noted that the structure of the display panel mother board 10 provided in the present disclosure is not limited to the structures shown in the above examples and illustrations. For example, gaps may be formed between the encapsulation units 611 corresponding to adjacent light-emitting devices 500, or they may overlap each other. For example, the first electrode 510 corresponding to the light-emitting device 500 is not limited to being disposed in the display area 101c, and may also be disposed in the first scribe area 102 and / or the second scribe area 101a. For example, the display panel mother board 10 may further include a pixel defining layer disposed on the substrate 100, and this pixel defining layer is not limited to being located in the display area 101c, and may also be disposed in the first scribe area 102 and / or the second scribe area 101a. In addition, the test terminals 200 and the test lines 300 are not limited to the structures shown in the above examples. They may be single-layer structures or more-layer structures, not limited to double-layer structures, and they may also be prepared using different conductive material layers according to the specific structure of the display panel mother board 10. All of the above can be designed according to actual needs and will not be elaborated here.

[0081] In at least one embodiment of the present disclosure, multiple test lines 300 are respectively connected to the corresponding test terminals 200 through different vias V1 to achieve signal connection.

[0082] For example, multiple test lines 300 are provided, and multiple test terminals 200 are provided. Every two test lines 300 are respectively electrically connected to the same test terminal 200. Specifically, each test line 300 is electrically connected to the test terminal 200 through a via V1, that is, there is a one-to-one correspondence between the via V1 and the test line 300. In addition, the structure and preparation method of the via V1 can be designed according to actual needs and will not be elaborated here.

[0083] In one embodiment of the present disclosure, as Figure 2 shown, the display panel mother board 10 further includes connection terminals 700 located in the bonding area 101d. Multiple test lines 300 are provided, and one end of each of the multiple test lines 300 is respectively electrically connected to the connection terminals 700 in the corresponding sub-board area 101b.

[0084] The embodiments of the present disclosure do not limit the number, structure, and arrangement manner of the connection terminals 700. It only provides an implementation manner, that is, the connection terminals 700 on the bonding area 101d are used to achieve electrical connection with the test lines 300, and finally signal transmission between the connection terminals 700 and the test terminals 200 is realized.

[0085] In at least one embodiment of the present disclosure, as Figure 1As shown, the daughter board areas 101b are arranged in an array in the panel area 101. A plurality of test lines 300 extend along a first direction, for example, the X direction, and are arranged along a second direction, for example, the Y direction. Each row of daughter board areas 101b is arranged along the first direction, for example, the X direction. At least one test line 300 is correspondingly arranged for each row of daughter board areas 101b. At least one test terminal 200 is arranged at intervals in the second direction, for example, the Y direction. The first direction and the second direction intersect, that is, the X direction and the Y direction intersect.

[0086] In at least one embodiment of the present disclosure, each row of daughter board areas 101b corresponds to two test lines 300 and two test terminals 200. Every two test terminals 200 form a group. Each group of test terminals 200 includes a first test terminal 200a and a second test terminal 200b. Each group of test terminals 200 is arranged at intervals in the second direction, that is, the Y direction. The first test terminal 200a and the second test terminal 200b are respectively electrically connected to different connection terminals 700 of the corresponding daughter board area 101b through different test lines 300.

[0087] For example, the first test terminal 200a is an input terminal, and the connection terminal 700 of the corresponding daughter board area 101b is a signal input end. The second test terminal 200b is an output terminal, and the connection terminal 700 of the corresponding daughter board area 101b is a signal output end. The test device inputs various test signals to the display panel mother board 10 through the input terminal. The test signals include but are not limited to image data signals, control signals, clock signals, etc. After receiving the test signals, the display panel mother board 10 will perform corresponding operations according to the requirements of the test signals, and feedback the processed signals to the test device through the output terminal. These feedback signals include but are not limited to performance parameters such as the brightness, color, and contrast of the display panel mother board 10, as well as defect information such as whether there are dead pixels and bright spots. The test device evaluates the performance and quality of the display panel mother board 10 by analyzing and processing these feedback signals, and adjusts the production process. The selection of test signals and specific test methods can be selected according to actual needs and will not be elaborated here.

[0088] In at least one embodiment of the present disclosure, the distance between the test terminals 200 within each group is smaller than the distance between each group of test terminals 200.

[0089] In at least one embodiment of the present disclosure, the test terminals 200 are located in the first scribe area 102 on the same side of the periphery of the panel area 101.

[0090] In at least one embodiment of the present disclosure, the first direction and the second direction are perpendicular. For example, the first direction is the X direction, the second direction is the Y direction, and the X direction and the Y direction are perpendicular.

[0091] In one embodiment of the present disclosure, the test line 300 includes at least two conductive layers.

[0092] In at least one embodiment of the present disclosure, as Figure 3 shown, the mother board 10 of the display panel further includes a thin film transistor TFT, a first planar layer 800a, a first signal line 900a, a second signal line 900b, and a second planar layer 800b that are sequentially stacked on the substrate 100. The second planar layer 800b is located on the side of the light-emitting device 500 close to the substrate 100. The test line 300 includes a first sub-test line 310 located on the substrate 100 and a second sub-test line 320 located on the side of the first sub-test line 310 away from the substrate 100. The first sub-test line 310 is on the same layer and made of the same material as the first signal line 900a, and the second sub-test line 320 is on the same layer and made of the same material as the second signal line 900b.

[0093] In at least one embodiment of the present disclosure, as Figure 5 shown, the test terminal 200 and the light-emitting device 500 are on the same side of the substrate 100. The orthographic projection of the second planar layer 800b on the substrate 100 is outside the orthographic projection of the test terminal 200 on the substrate 100. The test terminal 200 includes a first-layer sub-test terminal 210 and a second-layer sub-test terminal 220. The first-layer sub-test terminal 210 is on the same layer and made of the same material as the first signal line 900a, and the second-layer sub-test terminal 220 is on the same layer and made of the same material as the second signal line 900b. In this way, the test terminal 200 is configured to include a structure of different layers stacked, which can not only reduce the impedance of the test terminal 200, reduce the attenuation during the transmission of the test signal, thereby improving the test accuracy, but also increase the strength of the test terminal 200 and reduce the risk of breakage of the test terminal 200.

[0094] In at least one embodiment of the present disclosure, the first signal line 900a and the second signal line 900b are used to transmit a power signal or a data signal.

[0095] In at least one embodiment of the present disclosure, an insulating layer is further included, and the insulating layer is located between the first signal line 900a and the second signal line 900b.

[0096] In one embodiment of the present disclosure, as Figure 3 shown, the isolation structure 400 includes a support portion 410 and a crown portion 420. The support portion 410 is located between the crown portion 420 and the substrate 100. The orthographic projection of the surface of the support portion 410 away from the substrate 100 on the substrate 100 is within the orthographic projection of the crown portion 420 on the substrate 100. In this way, the width of the crown portion 420 is greater than the width of the support portion 410, thereby improving the isolation effect of the isolation structure 400.

[0097] In at least one embodiment of the present disclosure, the support portion 410 is a conductive structure, and the second electrode 530 is connected to the side surface of the support portion 410. The setting of the support portion 410 does not need to consider light transmission, so it can have a relatively large design thickness (greater than that of the second electrode 530), that is, the sheet resistance of the support portion 410 is less than that of the second electrode 530. In this solution, the support portion 410 can be connected to the second electrode 530 of the light-emitting device 500 to have the same potential, thereby reducing the voltage drop generated on the second electrode 530.

[0098] In at least one embodiment of the present disclosure, as Figure 5 , Figure 7 shown, the isolation structure 400 further includes a bottom portion 430, the bottom portion 430 is located between the support portion 410 and the substrate 100, and the orthographic projection of the support portion 410 on the substrate 100 is located within the orthographic projection of the bottom portion 430 on the substrate 100.

[0099] In at least one embodiment of the present disclosure, the bottom portion 430 is a conductive structure, and the second electrode 530 is electrically connected to a portion of the surface of the bottom portion 430 away from the substrate 100 that is not covered by the support portion 410. Relative to the side wall of the support portion 410, the second electrode 530 is more likely to be deposited on the surface area of the bottom portion 430 away from the substrate 100, thereby reducing the impedance at the connection between the second electrode 530 and the isolation structure 400.

[0100] In at least one embodiment of the present disclosure, the orthographic projection of the bottom portion 430 on the substrate 100 is located within the orthographic projection of the crown portion 420 on the substrate 100.

[0101] It should be noted that the structure of the display panel mother board 10 in the embodiments of the present disclosure is not limited to the above structure. For example, the display mother board further includes a pixel defining layer, which is at least located in the display area 101c and is between the isolation structure 400 and the substrate 100. The pixel defining layer includes pixel openings corresponding to the isolation openings 401 respectively, and at least a part of the light-emitting device 500 is located in the pixel openings. For example, the pixel defining layer is an inorganic film layer. In the process of manufacturing the light-emitting device 500 based on the isolation structure 400, the pixel defining layer does not need to have a high thickness to accommodate the light-emitting device 500, which is beneficial to the thinning design of the display panel; in addition, as an inorganic film layer, the pixel defining layer can have a high bonding strength with the isolation structure 400 and the first electrode 510 to reduce the risk of the isolation structure 400 and the first electrode 510 falling off; in addition, the inorganic film layer has a high density and good barrier effects on water and gas to encapsulate and protect the first overlapping portion of the overlapping terminals. In addition, the display panel mother board 10 may further include other structures, which can be designed according to actual needs and will not be elaborated here.

[0102] An embodiment of the present disclosure also provides a method for manufacturing a display panel. The manufacturing method includes: providing a substrate, which is divided into a panel area and a first cuttable area located outside the panel area. The panel area includes a second cuttable area and a plurality of sub-panel areas, and each sub-panel area is separated by the second cuttable area; forming at least one test terminal in the first cuttable area of the substrate, and the surface of the test terminal away from the substrate is exposed so that the test terminal can be connected to an external test signal; forming at least one test line on the substrate, the test line extends from the second cuttable area to the first cuttable area, one end of the test line is connected to the corresponding display panel, and the other end of the test line extends to the first cuttable area and is connected to the test terminal; cutting off the first cuttable area and the second cuttable area of the display panel mother board to obtain a plurality of display panels.

[0103] At least one embodiment of the present disclosure provides a method for manufacturing the above display panel. The manufacturing method may include steps S100 to S400 as Figure 8 shown below.

[0104] S100: Provide a substrate, which is divided into a panel area and a first cuttable area located outside the panel area. The panel area includes a second cuttable area and a plurality of sub-panel areas, and each sub-panel area is separated by the second cuttable area.

[0105] S200: Form at least one test terminal in the first cuttable area of the substrate, and the surface of the test terminal away from the substrate is exposed so that the test terminal can be connected to an external test signal.

[0106] S300: Form at least one test line on the substrate. The test line extends from the second cuttable area to the first cuttable area. One end of the test line is connected to the corresponding display panel, and the other end of the test line extends to the first cuttable area and is connected to the test terminal.

[0107] S400: Cut off the first cuttable area and the second cuttable area of the display panel mother board to obtain a plurality of display panels.

[0108] For the display panel obtained by the above method for manufacturing a display panel, during the manufacturing process, the optical parameters can be monitored using the test terminals exposed on the substrate during the evaporation process (mainly referring to the process of forming a light-emitting device by full-surface evaporation). This can promptly detect problems and solve them, and is conducive to providing data support for improving the performance of the light-emitting device, and is conducive to improving the quality of the display panel.

[0109] It should be noted that the method for manufacturing the display panel provided by the present disclosure is not limited to the above examples. The sequence of forming the test terminals and the test lines can be designed according to actual needs and will not be elaborated here.

[0110] In at least one embodiment of the present disclosure, the sub-board area is divided into a display area and a bonding area located on at least one side of the display area. The manufacturing method further includes: before cutting the display panel mother board, forming a plurality of isolation structures on the evaporation side of the substrate, at least part of the isolation structures are located in the display area, and the isolation structures enclose a plurality of isolation openings located in the display area; forming a plurality of light-emitting devices, at least part of the light-emitting devices are located in the isolation openings.

[0111] Exemplarily, a manufacturing method of a display panel may include steps S010 to S060 as shown below, specifically as follows. Figure 9 as shown below.

[0112] S010, providing a substrate, the substrate is divided into a panel area and a first cuttable area located on the periphery of the panel area, the panel area includes a second cuttable area and a plurality of sub-board areas, and each sub-board area is separated by the second cuttable area.

[0113] S020, forming at least one test terminal in the first cuttable area of the substrate, the test terminal is exposed away from the surface of the substrate so that the test terminal is connected to an external test signal.

[0114] S030, forming at least one test line on the substrate, the test line extends from the second cuttable area to the first cuttable area, one end of the test line is connected to the corresponding display panel, and the other end of the test line extends to the first cuttable area and is connected to the test terminal.

[0115] S040, forming a plurality of isolation structures on the evaporation side of the substrate, at least part of the isolation structures are located in the display area, and the isolation structures enclose a plurality of isolation openings located in the display area.

[0116] S050, forming a plurality of light-emitting devices, at least part of the light-emitting devices are located in the isolation openings.

[0117] S060, cutting off the first cuttable area and the second cuttable area of the display panel mother board to obtain a plurality of display panels.

[0118] It should be noted that the steps between step S020, step S030, and step S040 are not limited to the above examples. They can be completed in the same process or in different front-back orders. For example, the steps S020 and S030 of forming the test terminal and the test line can be completed in the same process, and then the step S040 of forming the isolation structure is carried out. For example, the step S030 of the test line can be executed first, then the step S020 of forming the test terminal can be completed, and then the step S040 of forming the isolation structure can be completed. These can be designed according to actual needs and will not be elaborated here.

[0119] In at least one embodiment of the present disclosure, forming a plurality of light-emitting devices in step S050 may include steps S050a to S050b as shown below. Figure 10 Specifically, steps S050a to S050b are as follows.

[0120] S050a: Form a plurality of spaced-apart first electrodes in the display area, with at least a portion of the first electrodes located within the isolation openings.

[0121] S050b: Prepare a light-emitting functional layer and a second electrode located within the isolation openings based on the isolation structure. Each stack of the first electrode, the light-emitting functional layer, and the second electrode within each isolation opening constitutes a light-emitting device.

[0122] In at least one embodiment of the present disclosure, preparing the light-emitting functional layer and the second electrode located within the isolation openings based on the isolation structure in step S050b may include steps S051 to S056 as shown below. Figure 11 Specifically, steps S051 to S056 are as follows.

[0123] S051: Deposit a light-emitting material thin film and a first conductive material thin film. The light-emitting material thin film and the first conductive material thin film cover the isolation structure and the isolation openings. Among them, the portions of the light-emitting material thin film and the first conductive material thin film located within the isolation openings respectively form the light-emitting functional layer and the second electrode.

[0124] S052: Deposit a packaging material film layer to cover the light-emitting device.

[0125] S053: Test the formed light-emitting device based on at least one test terminal exposed on the substrate.

[0126] S054: Form a first photoresist layer on the packaging material film layer and perform a patterning process on the first photoresist layer to form a first photoresist pattern, and the first photoresist pattern covers a part of the isolation openings.

[0127] S055: Etch the packaging material film layer, the light-emitting material thin film, and the first conductive material thin film based on the first photoresist pattern. Among them, the remaining part of the packaging material film layer is formed into a packaging unit, and the light-emitting functional layer and the second electrode not covered by the packaging unit are etched.

[0128] S056: Repeat the above process to form a light-emitting device and a packaging unit at the isolation openings where no light-emitting device has been formed. All the packaging units constitute a first packaging layer.

[0129] In at least one embodiment of the present disclosure, in step S020 of forming at least one test terminal in the first scribe area of the substrate, at least one test terminal is formed on the evaporation side of the substrate, the test terminal and the light-emitting device are located on the same side of the substrate. During the deposition of the light-emitting material thin film and the first conductive material thin film, the first scribe area is shielded, so that the orthographic projections of the light-emitting material thin film and the first conductive material thin film on the substrate are located outside the first scribe area to expose the test terminal; in step S052 of depositing the encapsulation material film layer to cover the light-emitting device, the first scribe area is shielded, so that the orthographic projection of the encapsulation material film layer on the substrate is located outside the first scribe area to expose the test terminal. For example, during the evaporation process, a mechanical structure in the evaporation device, such as a baffle, is used to shield the first scribe area on the evaporation side of the substrate, thus preventing the evaporated film layer from covering the test terminal.

[0130] In at least one embodiment of the present disclosure, the manufacturing method further includes: before forming a plurality of light-emitting devices, sequentially forming a thin-film transistor and a first planarization layer on the evaporation side of the substrate, the thin-film transistor is at least located in the display area, and the first planarization layer at least covers the panel area; depositing a second conductive material thin film layer on the substrate with the first planarization layer formed thereon; forming a second photoresist layer on the second conductive material thin film layer, and performing a patterning process on the second photoresist layer to form a second photoresist pattern, and the second photoresist pattern covers a part of the display area; etching the second conductive material thin film layer based on the second photoresist pattern, wherein the remaining part of the second conductive material thin film layer in the display area is formed into a first signal line; depositing a third conductive material thin film layer on the substrate with the second conductive material thin film layer formed thereon; forming a third photoresist layer on the third conductive material thin film layer, and performing a patterning process on the third photoresist layer to form a third photoresist pattern, and the third photoresist pattern covers a part of the display area; etching the third conductive material thin film layer based on the third photoresist pattern, wherein the remaining part of the third conductive material thin film layer in the display area is formed into a second signal line.

[0131] In at least one embodiment of the present disclosure, in forming the second photoresist layer on the second conductive material thin film layer, the second photoresist pattern also covers a part of the second scribe area and a part of the first scribe area; in etching the second conductive material thin film layer based on the second photoresist pattern, the remaining part of the second conductive material thin film layer in the second scribe area and the first scribe area is formed into a first sub-test line; in forming the third photoresist layer on the third conductive material thin film layer, the third photoresist pattern also covers a part of the second scribe area and a part of the first scribe area; in etching the third conductive material thin film layer based on the third photoresist pattern, the remaining part of the third conductive material thin film layer in the second scribe area and the first scribe area is formed into a second sub-test line, and the first sub-test line and the second sub-test line constitute a test line.

[0132] In at least one embodiment of the present disclosure, the remaining portion of the second conductive material thin film layer in the first scribe area further forms a first sub-test terminal, and the remaining portion of the third conductive material thin film layer in the first scribe area further forms a second sub-test terminal. The first sub-test terminal and the second sub-test terminal constitute a test terminal.

[0133] Exemplarily, the method for manufacturing the display panel may include steps S10 to S70 as Figure 12 shown.

[0134] S10: Provide a substrate, which is divided into a panel area and a first scribe area located at the periphery of the panel area. The panel area includes a second scribe area and a plurality of sub-panel areas, and each sub-panel area is separated by the second scribe area.

[0135] S20: Sequentially form thin film transistors and a first planarization layer on the evaporation side of the substrate. The thin film transistors are at least located in the display area, and the first planarization layer at least covers the panel area.

[0136] S31: Deposit a second conductive material thin film layer on the substrate on which the first planarization layer is formed.

[0137] S32: Form a second photoresist layer on the second conductive material thin film layer, and perform a patterning process on the second photoresist layer to form a second photoresist pattern. The second photoresist pattern covers a part of the display area, a part of the second scribe area, and a part of the first scribe area.

[0138] S33: Etch the second conductive material thin film layer based on the second photoresist pattern. Among them, the remaining portion of the second conductive material thin film layer in the display area forms a first signal line, the remaining portion of the second conductive material thin film layer in a part of the first scribe area and the remaining portion of the second scribe area form a first sub-test line, and the remaining portion of the second conductive material thin film layer in the first scribe area forms a first sub-test terminal.

[0139] S34: Deposit a third conductive material thin film layer on the substrate on which the second conductive material thin film layer is formed.

[0140] S35: Form a third photoresist layer on the third conductive material thin film layer, and perform a patterning process on the third photoresist layer to form a third photoresist pattern. The third photoresist pattern covers a part of the display area, a part of the second scribe area, and a part of the first scribe area.

[0141] S36. Etch the third conductive material thin film layer based on the third photoresist pattern. Among them, the remaining part of the third conductive material thin film layer in the display area is formed into the second signal line, the partial remaining part of the third conductive material thin film layer in the first scribe area and the remaining part of the second scribe area are formed into the second sub-test line, the remaining part of the third conductive material thin film layer in the first scribe area is formed into the second layer of sub-test terminals, the first sub-test line and the second sub-test line constitute the test line, and the first layer of sub-test terminals and the second layer of sub-test terminals constitute the test terminals.

[0142] S40. Form a plurality of spaced-apart first electrodes on the evaporation side of the substrate having the test line, and the first electrodes are at least located in the display area.

[0143] S50. Form a plurality of isolation structures on the evaporation side of the substrate, at least part of the isolation structures are located in the display area, and the isolation structures enclose to form a plurality of isolation openings located in the display area, wherein at least part of the first electrodes are located within the isolation openings.

[0144] S61. Deposit a light-emitting material thin film and a first conductive material thin film, and the light-emitting material thin film and the first conductive material thin film cover the isolation structures and the isolation openings. Among them, the parts of the light-emitting material thin film and the first conductive material thin film located in the isolation openings are respectively formed into a light-emitting functional layer and a second electrode.

[0145] S62. Deposit a packaging material film layer to cover the light-emitting device.

[0146] S63. Test the formed light-emitting device based on at least one test terminal pair exposed on the substrate.

[0147] S64. Form a first photoresist layer on the packaging material film layer and perform a patterning process on the first photoresist layer to form a first photoresist pattern, and the first photoresist pattern covers part of the isolation openings.

[0148] S65. Etch the packaging material film layer, the light-emitting material thin film and the first conductive material thin film based on the first photoresist pattern. Among them, the remaining part of the packaging material film layer is formed into a packaging unit, and the light-emitting functional layer and the second electrode not covered by the packaging unit are etched.

[0149] S66. Repeat the above process to form a light-emitting device and a packaging unit at the isolation openings where no light-emitting device is formed, and all the packaging units constitute the first packaging layer.

[0150] S70. Cut off the first scribe area and the second scribe area of the display panel mother board to obtain a plurality of display panels.

[0151] In at least one embodiment of the present disclosure, before depositing the third conductive material thin film layer on the substrate formed with the second conductive material thin film layer, it further includes: forming an insulating layer on the substrate formed with the second conductive material thin film layer, and the insulating layer covers the second conductive material thin film layer.

[0152] In at least one embodiment of the present disclosure, in step S020 of forming at least one test terminal in the first scribe area of the substrate, at least one test terminal is formed on the non-evaporation side of the substrate, the test terminal and the light-emitting device are located on different sides of the substrate, in depositing the light-emitting material thin film and the first conductive material thin film, the orthographic projections of the light-emitting material thin film and the first conductive material thin film on the substrate cover the panel area and the first scribe area of the substrate; in step S052 of depositing the encapsulation material film layer to cover the light-emitting device, the orthographic projection of the encapsulation material film layer on the substrate covers the panel area and the first scribe area of the substrate.

[0153] In at least one embodiment of the present disclosure, the manufacturing method further includes: before forming a plurality of light-emitting devices, sequentially forming a thin-film transistor and a first planarization layer on the evaporation side of the substrate, the thin-film transistor is at least located in the display area, and the first planarization layer covers the panel area and the first scribe area; forming a via hole on the substrate, and the via hole exposes a partial surface of the test terminal close to the substrate; depositing a second conductive material thin film layer on the substrate formed with the first planarization layer, and the second conductive material thin film layer fills the via hole; forming a second photoresist layer on the second conductive material thin film layer, and performing a patterning process on the second photoresist layer to form a second photoresist pattern, and the second photoresist pattern covers a part of the display area; etching the second conductive material thin film layer based on the second photoresist pattern, wherein the remaining part of the second conductive material thin film layer in the display area is formed as a first signal line; depositing a third conductive material thin film layer on the substrate formed with the second conductive material thin film layer; forming a third photoresist layer on the third conductive material thin film layer, and performing a patterning process on the third photoresist layer to form a third photoresist pattern, and the third photoresist pattern covers a part of the display area; etching the third conductive material thin film layer based on the third photoresist pattern, wherein the remaining part of the third conductive material thin film layer in the display area is formed as a second signal line.

[0154] In at least one embodiment of the present disclosure, when forming a second photoresist layer on the second conductive material thin film layer, the second photoresist pattern further covers a part of the second scribe area and a part of the first scribe area, and a positive projection of the second photoresist pattern on the substrate overlaps with a positive projection of the test terminal on the substrate; etching the second conductive material thin film layer based on the second photoresist pattern, and the remaining parts of the second conductive material thin film layer in the second scribe area and the first scribe area are formed into a first sub-test line; when forming a third photoresist layer on the third conductive material thin film layer, the third photoresist pattern further covers a part of the second scribe area and a part of the first scribe area, and a positive projection of the third photoresist pattern on the substrate overlaps with a positive projection of the test terminal on the substrate; etching the third conductive material thin film layer based on the third photoresist pattern, and the remaining parts of the third conductive material thin film layer in the second scribe area and the first scribe area are formed into a second sub-test line, and the first sub-test line and the second sub-test line constitute a test line.

[0155] Exemplarily, the method for manufacturing the display panel may include steps S10a to S70a as Figure 13 shown.

[0156] S10a, providing a substrate, the substrate is divided into a panel area and a first scribe area located outside the panel area, the panel area includes a second scribe area and a plurality of sub-panel areas, and each sub-panel area is separated by the second scribe area.

[0157] S20a, forming a test terminal on the non-evaporation side of the substrate, wherein the test terminal is located in the first scribe area of the substrate.

[0158] For example, the test terminal may be a single-layer structure or a multi-layer structure, and can be designed according to actual requirements, which will not be elaborated here.

[0159] S31a, sequentially forming a thin film transistor and a first planarization layer on the evaporation side of the substrate, the thin film transistor is at least located in the display area, and the first planarization layer covers the panel area and the first scribe area.

[0160] It should be noted that the evaporation side of the substrate and the non-evaporation side of the substrate are oppositely arranged.

[0161] S32a, forming a via hole on the substrate, and the via hole exposes a part of the surface of the test terminal close to the substrate.

[0162] For example, forming a via hole in a corresponding area of the first planarization layer located in the first scribe area and a corresponding substrate area, the via hole can be formed step by step or in one step, and the specific formation process of the via hole can be designed according to actual requirements, which will not be designed here.

[0163] For example, multiple test lines are provided, multiple test terminals are provided, and multiple vias are provided. The multiple vias correspond to the multiple test lines one by one, and are used to implement electrical connection between each test line and the test terminals on the non - same side.

[0164] S33a: Deposit a second conductive material thin film layer on the substrate with the first flat layer formed. The second conductive material thin film layer fills the vias.

[0165] S34a: Form a second photoresist layer on the second conductive material thin film layer, and perform a patterning process on the second photoresist layer to form a second photoresist pattern. The second photoresist pattern covers part of the display area, part of the second scribe area, and part of the first scribe area. The orthographic projection of the second photoresist pattern on the substrate overlaps with the orthographic projection of the test terminals on the substrate.

[0166] S35a: Etch the second conductive material thin film layer based on the second photoresist pattern. Among them, the remaining part of the second conductive material thin film layer in the display area forms the first signal line, and the remaining part of the second conductive material thin film layer in the second scribe area and the first scribe area forms the first sub - test line.

[0167] S36a: Deposit a third conductive material thin film layer on the substrate with the second conductive material thin film layer formed.

[0168] S37a: Form a third photoresist layer on the third conductive material thin film layer, and perform a patterning process on the third photoresist layer to form a third photoresist pattern. The third photoresist pattern covers part of the display area, part of the second scribe area, and part of the first scribe area. The orthographic projection of the third photoresist pattern on the substrate overlaps with the orthographic projection of the test terminals on the substrate.

[0169] S38a: Etch the third conductive material thin film layer based on the third photoresist pattern. Among them, the remaining part of the third conductive material thin film layer in the display area forms the second signal line, and the remaining part of the third conductive material thin film layer in the second scribe area and the first scribe area forms the second sub - test line. The first sub - test line and the second sub - test line constitute the test line.

[0170] S40a: Form a plurality of spaced - apart first electrodes on the evaporation side of the substrate with the test line formed. The first electrodes are at least located in the display area.

[0171] S50a: Form a plurality of isolation structures on the evaporation side of the substrate. At least part of the isolation structures are located in the display area. The isolation structures enclose a plurality of isolation openings located in the display area. Among them, at least part of the first electrodes are located within the isolation openings.

[0172] S61a, deposit a light-emitting material thin film and a first conductive material thin film. The light-emitting material thin film and the first conductive material thin film cover the isolation structure and the isolation opening. Among them, the parts of the light-emitting material thin film and the first conductive material thin film located in the isolation opening respectively form a light-emitting functional layer and a second electrode.

[0173] S62a, deposit a packaging material film layer to cover the light-emitting device.

[0174] S63a, test the formed light-emitting device based on at least one test terminal pair exposed on the substrate.

[0175] S64a, form a first photoresist layer on the packaging material film layer, and perform a patterning process on the first photoresist layer to form a first photoresist pattern. The first photoresist pattern covers a part of the isolation opening.

[0176] S65a, etch the packaging material film layer, the light-emitting material thin film, and the first conductive material thin film based on the first photoresist pattern. Among them, the remaining part of the packaging material film layer is formed into a packaging unit, and the light-emitting functional layer and the second electrode not covered by the packaging unit are etched.

[0177] S66a, repeat the above process to form a light-emitting device and a packaging unit at the isolation opening where no light-emitting device is formed. All the packaging units constitute a first packaging layer.

[0178] S70a, cut off the first cuttable area and the second cuttable area of the display panel mother board to obtain a plurality of display panels.

[0179] It should be noted that the method for manufacturing the display panel according to the embodiments of the present disclosure is not limited to the above examples. For example, step S20a forms test terminals on the non-evaporation side of the substrate, which can be formed in any step before the step of forming the light-emitting functional layer of the light-emitting device, such as before step S61a. Specifically, it can be designed according to actual needs and will not be elaborated here.

[0180] In at least one embodiment of the present disclosure, before depositing a third conductive material thin film layer on the substrate formed with a second conductive material thin film layer, it further includes: forming an insulating layer on the substrate formed with a second conductive material thin film layer, the insulating layer covering the second conductive material thin film layer; forming a second via hole in the insulating layer. Among them, when depositing a third conductive material thin film layer on the substrate formed with a second conductive material thin film layer, the third conductive material thin film layer fills the second via hole to electrically connect the third conductive material thin film layer and the second conductive material thin film layer.

[0181] In at least one embodiment of the present disclosure, after forming the test terminals and before forming the light-emitting devices, the manufacturing method further includes forming a second planarization layer on the substrate. In at least one embodiment of the present disclosure, when both the light-emitting devices and the test terminals are located on the evaporation side of the substrate, the orthographic projection of the second planarization layer on the substrate is located outside the orthographic projection of the test terminals on the substrate.

[0182] An embodiment of the present disclosure further provides a display device, which includes a display panel obtained by the manufacturing method of any one of the above embodiments.

[0183] It should be noted that the display panel in the embodiment of the present disclosure is not limited to the above structure. For example, the non-display area of the display panel is not limited to the bonding area mentioned above, and may further include a bending area, which bends at least part of the non-display area to the back of the display panel, so that the display panel presents a narrow border or no border when in use.

[0184] For example, the display panel in the display device is as Figure 14 shown, and includes a substrate 100, an isolation structure 400, light-emitting devices 500, a first encapsulation layer 610, a second encapsulation layer 620, and a third encapsulation layer 630. The isolation structure 400 is located on the substrate 100, and the isolation structure 400 encloses to form a plurality of isolation openings 401 at least located in the display area. The light-emitting devices 500 are located on the substrate 100 and correspond to the isolation openings 401 respectively, and at least part of the light-emitting devices 500 is located in the corresponding isolation openings 401. The first encapsulation layer 610 is located on the side of the isolation structure 400 and the light-emitting devices 500 away from the substrate 100. Among them, the first encapsulation layer 610 includes a plurality of encapsulation units 611, and the encapsulation units 611 correspond to the isolation openings 401 respectively to cover the light-emitting devices 500 limited by the corresponding isolation openings 401. The second encapsulation layer 620 and the third encapsulation layer 630 are sequentially stacked on the side of the first encapsulation layer 610 away from the substrate 100. For the structures of the isolation structure 400 and the light-emitting devices 500, reference may be made to the above embodiments, and details are not described herein again.

[0185] For example, the orthographic projection of the third encapsulation layer 630 on the substrate 100 covers the orthographic projection of the second encapsulation layer 620 on the substrate 100.

[0186] For example, the second encapsulation layer 620 may be an organic film layer to planarize the surface of the display panel, so that the encapsulation structure has a planarized surface for setting other structures (such as a touch structure, etc.). In addition, the organic film layer can also be used for stress release, thereby reducing the risk of stress damage to the encapsulation structure.

[0187] For example, the third encapsulation layer 630 is an inorganic film layer, so as to encapsulate and protect the second encapsulation layer 620 to reduce the risk of intrusion of water vapor and the like.

[0188] At least one embodiment of the present disclosure provides a display device, which may include the display panel in the above embodiment or a display panel obtained by the preparation method in the above embodiment. For example, the display device may include structures such as a touch control structure, optical film pieces (such as microlenses, polarizers), and a cover plate disposed on the light-emitting side of the display panel.

[0189] For example, the display device may be any product or component with a display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, navigator, etc.

[0190] It should be understood that various forms of the processes shown above may be used, with steps reordered, added, or deleted. For example, the steps recited in the present invention may be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0191] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A display panel mother board, characterized in that, Comprising: A substrate, which is divided into a panel area and a first scribe area located on the periphery of the panel area. The panel area includes a second scribe area and a plurality of sub-panel areas, and each of the sub-panel areas is separated by the second scribe area; At least one test terminal, which is located on the substrate and in the first scribe area on the periphery of the panel area. The surface of the test terminal away from the substrate is exposed so that the test terminal can be connected to an external test signal; And At least one test line, which is located on the substrate. The test line extends from the second scribe area to the first scribe area. One end of the test line is connected to the corresponding sub-panel area, and the other end of the test line extends to the first scribe area to be connected to the test terminal.

2. The display panel mother board according to claim 1, wherein A plurality of the test terminals are provided, and a plurality of the test lines are provided. The sub-panel area is divided into a display area and a bonding area located on at least one side of the display area. The display panel mother board further includes: A plurality of isolation structures, which are located on the substrate and at least partially located in the display area. The isolation structures enclose and form a plurality of isolation openings located in the display area; and A plurality of light-emitting devices, at least a part of the light-emitting devices is located in the isolation openings, and the film layer of the light-emitting devices at least covers the panel area of the display panel mother board.

3. The display panel mother board according to claim 2, characterized in that, The plurality of light-emitting devices at least include a first light-emitting device and a second light-emitting device that emit light of different colors. The second light-emitting device is limited in a part of the isolation openings, and the first light-emitting device and the second light-emitting device are limited in the remaining part of the isolation openings. And the second light-emitting device is located on the side of the first light-emitting device away from the substrate. Among them, the film layer of the light-emitting device that at least covers the panel area is the same as the film layer corresponding to the second light-emitting device.

4. The display panel mother board according to claim 3, wherein The display panel mother board further includes an initial first encapsulation layer, which is located on the side of the isolation structure away from the substrate. Among them, the initial first encapsulation layer includes a plurality of encapsulation units and an encapsulation material film layer. The orthographic projection of the encapsulation unit on the substrate covers the orthographic projection of the light-emitting device of one color of emitted light on the substrate. The encapsulation material film layer covers on the side of the encapsulation unit away from the substrate, and the orthographic projection of the encapsulation material film layer on the substrate at least covers the panel area.

5. The display panel mother board according to claim 4, wherein The test terminal and the light-emitting device are located on the same side of the substrate, and the orthographic projection of the film layer corresponding to the light-emitting device on the substrate is located outside the orthographic projection of the test terminal on the substrate; And The orthographic projection of the encapsulation material film layer on the substrate is located outside the orthographic projection of the part of the test line in the first scribe area on the substrate, and the orthographic projection of the encapsulation material film layer on the substrate is located outside the orthographic projection of the test terminal on the substrate.

6. The display panel mother board according to claim 4, wherein The test terminal and the light-emitting device are located on opposite sides of the substrate, and the orthographic projection of the film layer corresponding to the light-emitting device on the substrate covers the entire orthographic projection of the test terminal on the substrate; And The orthographic projection of the encapsulation material film layer on the substrate covers the orthographic projections of the test terminals and the test lines on the substrate.

7. The display panel mother board according to any one of claims 2 to 6, characterized in that, The test line includes at least two conductive layers.

8. The display panel mother board according to claim 7, wherein, The display panel mother board further includes a thin film transistor, a first planarization layer, a first signal line, a second signal line, and a second planarization layer sequentially stacked on the substrate. The second planarization layer is located on the side of the light-emitting device close to the substrate, and The test line includes a first sub-test line located on the substrate and a second sub-test line located on the side of the first sub-test line away from the substrate. The first sub-test line is on the same layer and made of the same material as the first signal line, and the second sub-test line is on the same layer and made of the same material as the second signal line; and / or, The test terminal and the light-emitting device are located on the same side of the substrate. The orthographic projection of the second planarization layer on the substrate is located outside the orthographic projection of the test terminal on the substrate. The test terminal includes a first-layer sub-test terminal and a second-layer sub-test terminal. The first-layer sub-test terminal is on the same layer and made of the same material as the first signal line, and the second-layer sub-test terminal is on the same layer and made of the same material as the second signal line.

9. The display panel mother board according to any one of claims 2 to 6, characterized in that, The isolation structure includes a support portion and a crown portion. The support portion is located between the crown portion and the substrate, and The orthographic projection of the surface of the support portion away from the substrate on the substrate is located within the orthographic projection of the crown portion on the substrate.

10. The display panel mother board according to claim 9, wherein, The isolation structure further includes a bottom portion. The bottom portion is located between the support portion and the substrate. The orthographic projection of the support portion on the substrate is located within the orthographic projection of the bottom portion on the substrate.

11. A method for preparing a display panel, characterized in that, Comprising: Providing a substrate, the substrate being divided into a panel area and a first scribe area located on the periphery of the panel area. The panel area includes a second scribe area and a plurality of sub-panel areas, and each of the sub-panel areas is separated by the second scribe area; Forming at least one test terminal in the first scribe area of the substrate. The surface of the test terminal away from the substrate is exposed so that the test terminal can be connected to an external test signal; Forming at least one test line on the substrate. The test line extends from the second scribe area to the first scribe area. One end of the test line is connected to the corresponding display panel, and the other end of the test line extends to the first scribe area and is connected to the test terminal; Cutting off the first scribe area and the second scribe area of the display panel mother board to obtain a plurality of display panels.

12. The preparation method according to claim 11, wherein, The sub-panel area is divided into a display area and a bonding area located on at least one side of the display area. The manufacturing method further includes: Before cutting the display panel mother board, forming a plurality of isolation structures on the evaporation side of the substrate. At least part of the isolation structures are located in the display area, and the isolation structures enclose a plurality of isolation openings formed in the display area; Forming a plurality of light-emitting devices, at least part of the light-emitting devices being located in the isolation openings; Wherein, the forming of the plurality of light-emitting devices includes: Forming a plurality of spaced-apart first electrodes in the display area, at least part of the first electrodes being located within the isolation openings; A light-emitting functional layer and a second electrode located in the isolation opening are prepared based on the isolation structure, and the first electrode, the light-emitting functional layer, and the second electrode stacked on each other in each isolation opening constitute a light-emitting device.

13. The preparation method according to claim 12, wherein, The preparation of the light-emitting functional layer and the second electrode located in the isolation opening based on the isolation structure includes: Depositing a light-emitting material thin film and a first conductive material thin film, the light-emitting material thin film and the first conductive material thin film covering the isolation structure and the isolation opening, wherein the portions of the light-emitting material thin film and the first conductive material thin film located in the isolation opening respectively form the light-emitting functional layer and the second electrode; Depositing a packaging material film layer to cover the light-emitting device; Testing the formed light-emitting device based on the test terminals formed on the substrate; Forming a first photoresist layer on the packaging material film layer and performing a patterning process on the first photoresist layer to form a first photoresist pattern, the first photoresist pattern covering a part of the isolation opening; Etching the packaging material film layer, the light-emitting material thin film, and the first conductive material thin film based on the first photoresist pattern, wherein the remaining portion of the packaging material film layer is formed into a packaging unit, and the light-emitting functional layer and the second electrode not covered by the packaging unit are etched; Repeating the above process to form the light-emitting device and the packaging unit at the isolation opening where the light-emitting device is not formed, and all the packaging units constitute a first packaging layer.

14. The preparation method according to claim 13, wherein In the formation of at least one test terminal in the first scribe area of the substrate, a plurality of the test terminals are formed on the evaporation side of the substrate, the test terminals and the light-emitting device are located on the same side of the substrate, and In the deposition of the light-emitting material thin film and the first conductive material thin film, the first scribe area is blocked so that the orthographic projection of the light-emitting material thin film and the first conductive material thin film on the substrate is located outside the first scribe area to expose the test terminals; In the deposition of the packaging material film layer to cover the light-emitting device, the first scribe area is blocked so that the orthographic projection of the packaging material film layer on the substrate is located outside the first scribe area to expose the test terminals.

15. The preparation method according to claim 14, characterized in that, The preparation method further includes: Before forming a plurality of the light-emitting devices, a thin-film transistor and a first planarization layer are sequentially formed on the evaporation side of the substrate, the thin-film transistor is at least located in the display area, and the first planarization layer at least covers the panel area; Depositing a second conductive material thin film layer on the substrate having the first planarization layer; Forming a second photoresist layer on the second conductive material thin film layer and performing a patterning process on the second photoresist layer to form a second photoresist pattern, the second photoresist pattern covering a part of the display area; Etching the second conductive material thin film layer based on the second photoresist pattern, wherein the remaining portion of the second conductive material thin film layer in the display area is formed into a first signal line; Depositing a third conductive material thin film layer on the substrate having the second conductive material thin film layer; Form a third photoresist layer on the third conductive material thin film layer, and perform a patterning process on the third photoresist layer to form a third photoresist pattern, where the third photoresist pattern covers a part of the display area; Etch the third conductive material thin film layer based on the third photoresist pattern. Among them, the remaining part of the third conductive material thin film layer in the display area is formed into a second signal line.

16. The preparation method according to claim 15, characterized in that, In forming the second photoresist layer on the second conductive material thin film layer, the second photoresist pattern also covers a part of the second scribe area and a part of the first scribe area; In etching the second conductive material thin film layer based on the second photoresist pattern, the remaining part of the second conductive material thin film layer in the second scribe area and the first scribe area is formed into a first sub-test line; In forming the third photoresist layer on the third conductive material thin film layer, the third photoresist pattern also covers a part of the second scribe area and a part of the first scribe area; In etching the third conductive material thin film layer based on the third photoresist pattern, the remaining part of the third conductive material thin film layer in the second scribe area and the first scribe area is formed into a second sub-test line, and the first sub-test line and the second sub-test line constitute the test line; and / or, The remaining part of the second conductive material thin film layer in the first scribe area is also formed into a first layer of sub-test terminals, and the remaining part of the third conductive material thin film layer in the first scribe area is also formed into a second layer of sub-test terminals. The first layer of sub-test terminals and the second layer of sub-test terminals constitute the test terminals.

17. The preparation method according to claim 13, wherein, In forming at least one test terminal in the first scribe area of the substrate, a plurality of the test terminals are formed on the non-evaporation side of the substrate, and the test terminals and the light-emitting device are on different sides of the substrate, and In depositing the light-emitting material thin film and the first conductive material thin film, the orthographic projections of the light-emitting material thin film and the first conductive material thin film on the substrate cover the panel area and the first scribe area of the substrate; In depositing the encapsulation material film layer to cover the light-emitting device, the orthographic projection of the encapsulation material film layer on the substrate covers the panel area and the first scribe area of the substrate.

18. The preparation method according to claim 17, wherein The preparation method further includes: Before forming a plurality of the light-emitting devices, sequentially form a thin film transistor and a first planarization layer on the evaporation side of the substrate. The thin film transistor is at least located in the display area, and the first planarization layer covers the panel area and the first scribe area; Form a via hole on the substrate, and the via hole exposes a part of the surface of the test terminal close to the substrate; Deposit a second conductive material thin film layer on the substrate with the first planarization layer formed thereon, and the second conductive material thin film layer fills the via hole; Form a second photoresist layer on the second conductive material thin film layer, and perform a patterning process on the second photoresist layer to form a second photoresist pattern, where the second photoresist pattern covers a part of the display area; Etch the second conductive material thin film layer based on the second photoresist pattern, wherein the remaining portion of the second conductive material thin film layer in the display area is formed into a first signal line; Deposit a third conductive material thin film layer on the substrate on which the second conductive material thin film layer is formed; Form a third photoresist layer on the third conductive material thin film layer, and perform a patterning process on the third photoresist layer to form a third photoresist pattern, and the third photoresist pattern covers a part of the display area; Etch the third conductive material thin film layer based on the third photoresist pattern, wherein the remaining portion of the third conductive material thin film layer in the display area is formed into a second signal line.

19. The preparation method according to claim 18, wherein, In forming the second photoresist layer on the second conductive material thin film layer, the second photoresist pattern also covers a part of the second scribe area and a part of the first scribe area, and the orthographic projection of the second photoresist pattern on the substrate overlaps with the orthographic projection of the test terminal on the substrate; Etch the second conductive material thin film layer based on the second photoresist pattern, and the remaining portions of the second conductive material thin film layer in the second scribe area and the first scribe area are formed into first sub-test lines; In forming the third photoresist layer on the third conductive material thin film layer, the third photoresist pattern also covers a part of the second scribe area and a part of the first scribe area, and the orthographic projection of the third photoresist pattern on the substrate overlaps with the orthographic projection of the test terminal on the substrate; Etch the third conductive material thin film layer based on the third photoresist pattern, and the remaining portions of the third conductive material thin film layer in the second scribe area and the first scribe area are formed into second sub-test lines, and the first sub-test lines and the second sub-test lines constitute the test lines.

20. A display device, characterized in that, A display panel obtained by the manufacturing method according to any one of claims 11 to 19 is included.

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