Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel includes: a substrate; the light-emitting device is arranged on one side of the substrate, the light-emitting device comprises a first electrode, a light-emitting function layer and a second electrode which are stacked in sequence, the first electrode comprises a main body part and a connecting part which is connected with the main body part and protrudes relative to the main body part, and the light-emitting device comprises a plurality of first-class devices and a plurality of second-class devices; the first type of devices and the second type of devices are alternately arranged in the first direction to form a first device column, the first type of devices and the second type of devices are alternately arranged in the second direction to form a first device row, and in the same first device column, the connecting parts of the first type of devices are connected to one side of the main body part in the second direction, and the connecting parts of the second type of devices are connected to the other side of the main body part in the second direction. The connecting parts of the second type of devices are all connected to the other side of the main body part in the second direction, and in the same first device row, the connecting parts of the first electrodes are all located on the same side of the main body part in the second direction.

Description

Technical Field

[0001] This application belongs to the field of display technologies, and particularly relates to a display panel and a display device. Background Art

[0002] Liquid Crystal Display (LCD) panels, Organic Light Emitting Display (OLED) panels, and display panels using Light Emitting Diode (LED) devices are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptop computers, and desktop computers because of their advantages such as high picture quality, power saving, thin body, and wide application range, and have become the mainstream in display devices.

[0003] However, the working effect of current display products needs to be improved. Summary of the Invention

[0004] Embodiments of this application provide a display panel and a display device, aiming to improve the working effect of the display panel.

[0005] An embodiment of the first aspect of this application provides a display panel, including: a substrate; a light-emitting device disposed on one side of the substrate. In a direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode stacked in sequence. The first electrode includes a main body portion and a connecting portion connected to and protruding from the main body portion. Among them, the light-emitting device includes a plurality of first-type devices and a plurality of second-type devices. The first-type devices and the second-type devices are alternately arranged along a first direction to form a first device column, and the first-type devices and the second-type devices are alternately arranged along a second direction to form a first device row. The light-emitting color of the first-type devices is different from that of the second-type devices. The first direction intersects with the second direction. In the same first device column, the connecting portions of the first-type devices are all connected to one side of the main body portion in the second direction, and the connecting portions of the second-type devices are all connected to the other side of the main body portion in the second direction. In the same first device row, the connecting portions of each first electrode are all located on the same side of the main body portion in the second direction.

[0006] An embodiment of the second aspect of this application provides a display device, and the display device includes the display panel of the above embodiment.

[0007] In a display panel provided in an embodiment of the present application, the display panel includes a substrate and a light-emitting device. The light-emitting device is disposed on one side of the substrate. In a direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode that are sequentially stacked. The first electrode and the second electrode located on both sides of the light-emitting functional layer can be used to drive the light emission of the light-emitting functional layer, thereby realizing the light-emitting display of the display panel. The first electrode includes a main body portion and a connecting portion connected to the main body portion and protruding relative to the main body portion. The connecting portion protruding from the main body portion can be used to electrically connect to a device structure in the substrate to receive a driving current, and the main body portion can be used to transfer the driving current received by the connecting portion to the light-emitting functional layer to participate in driving the light emission of the light-emitting functional layer.

[0008] The light-emitting device includes a plurality of first-type devices and a plurality of second-type devices. The light-emitting color of the first-type devices is different from that of the second-type devices, so as to realize the color display of the display panel. The first-type devices and the second-type devices are alternately arranged along a first direction to form a first device column, and the first-type devices and the second-type devices are alternately arranged along a second direction to form a first device row.

[0009] By setting that in the same first device column, the connecting portions of the first-type devices are all connected to one side of the main body portion in the second direction, and the connecting portions of the second-type devices are all connected to the other side of the main body portion in the second direction, the first-type devices and the second-type devices can be respectively electrically connected to device structures in different columns in the substrate, so that it is convenient to drive the first-type devices and the second-type devices relatively independently, and further beneficial to improving the display effect of the display panel.

[0010] By setting that in the same first device row, the connecting portions of each first electrode are all located on the same side of the main body portion in the second direction, there can be only one connecting portion of the first electrode between the main body portions of the first electrodes adjacent in the second direction, so that the distances between the main body portions in the first device row can be relatively approximate or the same, which is beneficial to improving the arrangement effect of the light-emitting devices in the display panel, and further beneficial to improving the display effect of the display panel. Description of the Drawings

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. Obviously, the following described drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0012] Figure 1 is a partial cross-sectional view of a display panel provided in an embodiment of the present application; Figure 2 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present application; Figure 3 It is a schematic layout diagram of a light-emitting device provided by an embodiment of the present application; Figure 4 It is a schematic layout diagram of a pixel circuit provided by an embodiment of the present application; Figure 5 It is a schematic partial structure diagram of a display panel provided by an embodiment of the present application; Figure 6 It is a schematic connection relationship diagram of a pixel circuit, a light-emitting device, and a data signal line provided by an embodiment of the present application; Figure 7 It is a schematic partial structure diagram of a pixel circuit provided by an embodiment of the present application; Figures 8 to 12 It is a schematic partial structure diagram of each film layer in a substrate provided by an embodiment of the present application; Figure 13 It is a schematic structure diagram of a pixel circuit provided by another embodiment of the present application; Figure 14 It is a schematic partial structure diagram of a shielding structure provided by an embodiment of the present application; Figure 15 It is a schematic partial structure diagram of a display panel provided by another embodiment of the present application; Figure 16 It is a schematic enlarged partial structure diagram of a display panel provided by an embodiment of the present application.

[0013] Explanation of reference numerals: 10, display panel; 100, substrate; 110, substrate; 120, first insulating layer; 130, second insulating layer; 140, third insulating layer; 150, fourth insulating layer; 160, fifth insulating layer; 170, sixth insulating layer; 171, first sub-layer; 172, second sub-layer; 180, pixel circuit; 181, transistor; 181a, semiconductor; 181b, gate; 181c, source; 181d, drain; 182, storage capacitor; 182a, first electrode plate; 182b, second electrode plate; 190, connection structure; 191, first connection structure; 192, second connection structure; 193, third connection structure; 200, pixel definition layer; 200a, pixel opening; 300, light-emitting device; 301, first type of device; 302, second type of device; 303, third type of device; 310, first electrode; 311, main body part; 312, connection part; 320, light-emitting functional layer; 321, light-emitting structure, 322, common layer; 330, second electrode; T1, driving transistor; T2, data writing transistor; T3, threshold compensation transistor; T4, first reset transistor; T5, second control transistor; T6, first control transistor; T7, second reset transistor; T8, bias adjustment transistor; ELVDD, first power supply voltage signal line; Hole, relief opening; ELVSS, second power supply voltage signal line; Vdata, data signal line; FIAA, in-plane trace; VREFP1, bias signal line; VREFN1, first reset signal line; VREFN2, second reset signal line; EM, light emission control signal line; S1, first scan signal line; S2, second scan signal line; S3, third scan signal line; S4, fourth scan signal line; ES, conductive structure; ES1, conductive part; ES2, shielding part; BS, shielding structure; L1, first device column; L2, second device column; R1, first device row; R2, second device row; E1, first circuit column; E2, second circuit column; E3, third circuit column; DL, virtual symmetry axis; EG, circuit repeating unit; LG, device repeating unit; X, first direction; Y, second direction; Z, thickness direction. Detailed implementation manners

[0014] The features and exemplary embodiments of various aspects of the present application will be described in detail below. To make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0015] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed, or elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "comprising..." do not exclude the existence of additional identical elements in the process, method, article or device comprising the elements.

[0016] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or this region will be "below" or "beneath" the other layer or another region.

[0017] The embodiments of the present application provide a display panel and a display device. The following will describe the embodiments of the display panel and the display device with reference to the accompanying drawings.

[0018] Figure 1 is a partial cross-sectional view of a display panel 10 provided by an embodiment of the present application, Figure 2 is a schematic structural diagram of a pixel circuit 180 provided by an embodiment of the present application, Figure 3 is a schematic layout diagram of light-emitting devices 300 provided by an embodiment of the present application. In the figure, the X direction can schematically represent the first direction X, the Y direction in the figure can schematically represent the second direction Y, and the Z direction in the figure can be shown as the thickness direction Z of the display panel 10. The first direction X, the second direction Y and the thickness direction Z of the display panel 10 can intersect pairwise. Exemplarily, the first direction X, the second direction Y and the thickness direction Z of the display panel 10 can be perpendicular to each other pairwise. For the convenience of showing the specific layout of the light-emitting devices 300, the light-emitting functional layer 320 and the second electrode 330 are hidden in some of the drawings of the present application.

[0019] Such as Figures 1 to 3As shown in the figure, an embodiment of the first aspect of the present application provides a display panel 10, including: a substrate 100; a light-emitting device 300 disposed on one side of the substrate 100. In the direction away from the substrate 100, the light-emitting device 300 includes a first electrode 310, a light-emitting functional layer 320, and a second electrode 330 stacked in sequence. The first electrode 310 includes a main body portion 311 and a connection portion 312 connected to the main body portion 311 and protruding relative to the main body portion 311. Among them, the light-emitting device 300 includes a plurality of first-type devices 301 and a plurality of second-type devices 302. The first-type devices 301 and the second-type devices 302 are alternately arranged along the first direction X to form a first device column L1, and the first-type devices 301 and the second-type devices 302 are alternately arranged along the second direction Y to form a first device row R1. The light-emitting colors of the first-type devices 301 are different from those of the second-type devices 302. The first direction X intersects with the second direction Y. In the same first device column L1, the connection portions 312 of the first-type devices 301 are all connected to one side of the main body portion 311 in the second direction Y, and the connection portions 312 of the second-type devices 302 are all connected to the other side of the main body portion 311 in the second direction Y. In the same first device row R1, the connection portions 312 of each first electrode 310 are all located on the same side of the main body portion 311 in the second direction Y.

[0020] In a display panel 10 provided by an embodiment of the present application, the display panel 10 includes a substrate 100 and a light-emitting device 300.

[0021] Optionally, there are various ways to arrange the substrate 100. For example, the substrate 100 may include a substrate 110 and a plurality of pixel circuits 180 disposed on one side of the substrate 110. Exemplarily, the pixel circuit 180 may include a transistor 181, a storage capacitor 182, and driving signal lines for connecting various devices.

[0022] Optionally, the transistor 181 may include a semiconductor 181a, a gate 181b, a source 181c, and a drain 181d. Exemplarily, the semiconductor 181a may have a channel region and source and drain regions respectively disposed on both sides of the channel region. The gate 181b may be disposed on at least one side of the channel region in the thickness direction Z of the display panel 10. The source 181c may be connected to the source region via a via, and the drain 181d may be connected to the drain region via a via.

[0023] Optionally, the storage capacitor 182 may include a first electrode plate 182a and a second electrode plate 182b located on the side of the first electrode plate 182a away from the substrate 110.

[0024] Optionally, the substrate 100 may include a first insulating layer 120, a second insulating layer 130, a third insulating layer 140, a fourth insulating layer 150, a fifth insulating layer 160, and a sixth insulating layer 170 that are sequentially stacked on the substrate 110. Each device in the pixel circuit 180 may be disposed between any two of the third insulating layer 140, the fourth insulating layer 150, the fifth insulating layer 160, and the sixth insulating layer 170. The third insulating layer 140, the fourth insulating layer 150, the fifth insulating layer 160, and the sixth insulating layer 170 may be used to implement the arrangement and insulation of each device in the pixel circuit 180.

[0025] Optionally, the sixth insulating layer 170 may serve as a planarization layer of the display panel 10, that is, the surface of the sixth insulating layer 170 facing away from the substrate 110 may be relatively flat, which can facilitate the subsequent preparation of other film layers on the substrate 100. Exemplarily, the material of the sixth insulating layer 170 may include an organic material, so that during the preparation process of the sixth insulating layer 170, the material of the sixth insulating layer 170 may have good fluidity, and the surface of the prepared sixth insulating layer 170 facing away from the substrate 110 may be relatively flat.

[0026] The light-emitting device 300 is disposed on one side of the substrate 100. Exemplarily, the light-emitting device 300 may be disposed on the side of the sixth insulating layer 170 facing away from the substrate 110.

[0027] Optionally, the number of the light-emitting devices 300 may be multiple, and the multiple light-emitting devices 300 may be arranged in an array along the first direction X and the second direction Y.

[0028] In the direction away from the substrate 100, the light-emitting device 300 includes a first electrode 310, a light-emitting functional layer 320, and a second electrode 330 that are sequentially stacked. The first electrode 310 and the second electrode 330 located on both sides of the light-emitting functional layer 320 may be used to drive the light emission of the light-emitting functional layer 320, thereby realizing the light-emitting display of the display panel 10.

[0029] Optionally, the light-emitting functional layer 320 may include a light-emitting structure 321 and a common layer 322 disposed on at least one side of the light-emitting structure 321 in the thickness direction Z of the display panel 10. Exemplarily, the common layer 322 may be disposed on both sides of the light-emitting structure 321 in the thickness direction Z of the display panel 10. The common layer 322 disposed on the side of the light-emitting structure 321 facing the substrate 110 may include a hole injection layer (Hole Inject Layer, HIL) and a hole transport layer (Hole Transport Layer, HTL). The common layer 322 disposed on the side of the light-emitting structure 321 facing away from the substrate 110 may include an electron injection layer (Electron Inject Layer, EIL) and an electron transport layer (Electron Transport Layer, ETL).

[0030] Optionally, the first electrode 310 and the second electrode 330 may serve as pixel electrodes of the display panel 10. One of the first electrode 310 and the second electrode 330 may serve as the anode, and the other may serve as the cathode to drive the light-emitting functional layer 320 to emit light. In the embodiments of the present application, an example is given in which the first electrode 310 is the anode of the display panel 10 and the second electrode 330 is the cathode of the display panel 10.

[0031] Optionally, the second electrodes 330 of the respective light-emitting devices 300 may be electrically connected to each other, thereby facilitating the control of the display panel 10. Exemplarily, the second electrodes 330 of the respective light-emitting devices 300 may be integrally formed. Optionally, the common layers 322 of the respective light-emitting devices 300 may be integrally formed to facilitate the preparation of the display panel 10.

[0032] Optionally, the display panel 10 may further include a pixel definition layer 200 disposed on a side of the first electrode 310 facing away from the substrate 110. The pixel definition layer 200 may be provided with a pixel opening 200a. The light-emitting functional layer 320 and the second electrode 330 may extend from within the pixel opening 200a to outside the pixel opening 200a. At least a part of the surface of the first electrode 310 facing away from the substrate 110 may be exposed from the pixel opening 200a and connected to the light-emitting functional layer 320. The pixel definition layer 200 may be used to participate in dividing the sub-pixels of the display panel 10.

[0033] The first electrode 310 includes a main body portion 311 and a connection portion 312 connected to the main body portion 311 and protruding relative to the main body portion 311. The connection portion 312 protruding from the main body portion 311 may be used to be electrically connected to the device structure in the substrate 100 to receive a driving current. The main body portion 311 may be used to transfer the driving current received by the connection portion 312 to the light-emitting functional layer 320 to participate in driving the light-emitting functional layer 320 to emit light.

[0034] Optionally, at least a part of the surface of the main body portion 311 facing away from the substrate 110 may be exposed from the pixel opening 200a and connected to the light-emitting functional layer 320. The connection portion 312 may be located on a side of the pixel definition layer 200 facing the substrate 100.

[0035] Optionally, the connection portion 312 protruding relative to the main body portion 311 may mean that the connection portion 312 may protrude relative to the main body portion 311 along the first direction X or the second direction Y.

[0036] Optionally, in the embodiments of the present application, the electrical connection between a certain one and another one may mean that a certain one is directly in contact with another one to achieve electrical connection, or may mean that electrical connection is achieved between a certain one and another one through other device structures. The present application does not make specific limitations thereto.

[0037] Optionally, the connection portion 312 can be electrically connected to the pixel circuit 180 to receive a driving current. Exemplarily, the pixel circuit 180 includes a first control transistor T6 electrically connected to the connection portion 312. When the first control transistor T6 is turned on, the pixel circuit 180 can provide a driving current to the main body portion 311 through the connection portion 312 to drive the light-emitting function layer 320 to emit light.

[0038] Optionally, a single pixel circuit 180 can correspond to a single light-emitting device 300, that is, a single pixel circuit 180 can be electrically connected to the first electrode 310 of a single light-emitting device 300, so that a single pixel circuit 180 can drive and control the light emission of a single light-emitting device 300.

[0039] Optionally, there are various ways of setting the operating principle and circuit structure of the pixel circuit 180.

[0040] As an example, the pixel circuit 180 may further include a driving transistor T1 electrically connected to the first control transistor T6 and a second control transistor T5 electrically connected to an end of the driving transistor T1 away from the first control transistor T6. The pixel circuit 180 may further include a data writing transistor T2 electrically connected to an end of the second control transistor T5 close to the driving transistor T1 and an end of the driving transistor T1 away from the first control transistor T6.

[0041] The display panel 10 may further include a data signal line Vdata. An end of the data writing transistor T2 away from the driving transistor T1 is electrically connected to the data signal line Vdata, and the data signal line Vdata can be used to provide a data signal to the pixel circuit 180.

[0042] The display panel 10 may further include a first power supply voltage signal line ELVDD. An end of the second control transistor T5 away from the driving transistor T1 can be electrically connected to the first power supply voltage signal line ELVDD, and the first power supply voltage signal line ELVDD can be used to provide a positive power supply voltage signal to the pixel circuit 180.

[0043] As a further example, the pixel circuit 180 may further include a threshold compensation transistor T3, a first reset transistor T4, a second reset transistor T7, and a bias adjustment transistor 181. The display panel 10 may further include a second power supply voltage signal line ELVSS, a bias signal line VREFP1, a first reset signal line VREFN1, a second reset signal line VREFN2, a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, and a light emission control signal line EM.

[0044] The first terminal of the second control transistor T5 may be electrically connected to the second plate 182b of the storage capacitor 182, and the first terminal of the second control transistor T5 and the second plate 182b of the storage capacitor 182 may both be electrically connected to the first power supply voltage signal line ELVDD (which may be a positive power supply voltage signal line, for example). The first power supply voltage signal line ELVDD may supply a positive power supply voltage signal to the second control transistor T5 and the storage capacitor 182. The first terminal of the data writing transistor T2 may be electrically connected to the data signal line Vdata, and the data signal line Vdata may supply a data signal to the data writing transistor T2. The first terminal of the bias adjustment transistor T8 may be electrically connected to the bias signal line VREFP1, and the bias signal line VREFP1 may supply a bias signal to the bias adjustment transistor T8. The second terminal of the data writing transistor T2, the second terminal of the second control transistor T5, the second terminal of the bias adjustment transistor T8, and the first terminal of the driving transistor T1 may be electrically connected to each other.

[0045] The first terminal of the threshold compensation transistor T3, the second terminal of the driving transistor T1, and the first terminal of the first control transistor T6 may be electrically connected to each other. The first terminal of the first reset transistor T4 may be electrically connected to the first reset signal line VREFN1, and the first reset signal line VREFN1 may supply a first reset signal to the first reset transistor T4. The second terminal of the first reset transistor T4, the second terminal of the threshold compensation transistor T3, the control terminal of the driving transistor T1, and the first plate 182a of the storage capacitor 182 may be electrically connected to each other. The first terminal of the second reset transistor T7 may be electrically connected to the second reset signal line VREFN2, and the second reset signal line VREFN2 may supply a second reset signal to the second reset transistor T7. The second terminal of the second reset transistor T7, the second terminal of the first control transistor T6, and the first electrode 310 of the light emitting device 300 may be electrically connected to each other. The second electrode 330 of the light emitting device 300 may be electrically connected to the second power supply voltage signal line ELVSS (which may be a negative power supply voltage signal line, for example).

[0046] The control terminal of the first control transistor T6 may be electrically connected to the control terminal of the second control transistor T5, and the control terminal of the first control transistor T6 and the control terminal of the second control transistor T5 may both be electrically connected to the light emitting control signal line EM. The control terminal of the first reset transistor T4 may be electrically connected to the first scan signal line S1, the control terminal of the data writing transistor T2 may be electrically connected to the second scan signal line S2, and the control terminal of the threshold compensation transistor T3 may be electrically connected to the third scan signal line S3. The control terminal of the second reset transistor T7 and the control terminal of the bias adjustment transistor T8 may be electrically connected to each other, and the control terminal of the second reset transistor T7 and the control terminal of the bias adjustment transistor T8 may both be electrically connected to the fourth scan signal line S4.

[0047] Optionally, during the operation of the pixel circuit 180, the pixel circuit 180 may have a gate 181b reset stage, a data writing stage, a light emitting stage, and a bias stage. During the gate 181b reset stage, the first scan signal line S1 provides an effective level to the control terminal of the first reset transistor T4, so that the first reset transistor T4 is turned on. The first reset signal provided by the first reset signal line VREFN1 may be input to the control terminal of the driving transistor T1 via the first reset transistor T4, realizing the reset of the control terminal of the driving transistor T1.

[0048] During the data writing stage, the second scan signal line S2 provides an effective level to the control terminal of the data writing transistor T2, so that the data writing transistor T2 is turned on. At the same time, the third scan signal line S3 provides an effective level to the control terminal of the threshold compensation transistor T3, so that the threshold compensation transistor T3 is turned on. The data signal provided by the data signal line Vdata may be sequentially input to the first electrode 182a of the storage capacitor 182 via the data writing transistor T2, the driving transistor T1, and the threshold compensation transistor T3, and stored by the storage capacitor 182.

[0049] Before and / or after the data writing stage, a bias stage may be provided. During the bias stage, the fourth scan signal line S4 may provide an effective level to the control terminal of the second reset transistor T7 and the control terminal of the bias adjustment transistor 181, so that the second reset transistor T7 and the bias adjustment transistor 181 are turned on. The second reset signal line VREFN2 may provide a second reset signal to the first electrode 310 of the light emitting device 300 through the second reset transistor T7, realizing the reset of the first electrode 310 of the light emitting device 300. The bias signal line VREFP1 may write a bias signal to the first end of the driving transistor T1 through the bias adjustment transistor T8, so as to adjust the reverse bias of the driving transistor T1 through the bias signal and compensate for the characteristic curve drift caused by the forward bias.

[0050] During the light emitting stage, the light emission control signal line EM provides an effective level to the control terminal of the first control transistor T6 and the control terminal of the second control transistor T5, so that the first control transistor T6 and the second control transistor T5 are turned on. The driving transistor T1 provides a corresponding driving current to the first electrode 310 of the light emitting device 300 according to the data signal stored in the storage capacitor 182, so that the light emitting device 300 can emit light at a target brightness.

[0051] Optionally, one of the first end and the second end of the transistor 181 described in any of the foregoing embodiments may refer to the source electrode 181c of the transistor 181, and the other may refer to the drain electrode 181d of the transistor 181. The control terminal of the transistor 181 may refer to the gate 181b of the transistor 181.

[0052] Optionally, the semiconductor material type of the transistor 181 in any of the foregoing embodiments may be N-type or P-type. Exemplarily, except for the threshold compensation transistor T3 and the first reset transistor T4 in the pixel circuit 180 which are N-type semiconductor material transistors 181, the remaining transistors 181 may all adopt P-type semiconductor material transistors 181. For example, except that the materials of the semiconductors 181a of the threshold compensation transistor T3 and the first reset transistor T4 in the pixel circuit 180 both include indium gallium zinc oxide (IGZO), the materials of the semiconductors 181a of the remaining transistors 181 may all include amorphous silicon (a-Si).

[0053] The light-emitting device 300 includes a plurality of first-type devices 301 and a plurality of second-type devices 302. The light-emitting colors of the first-type devices 301 are different from those of the second-type devices 302, so as to facilitate color display of the display panel 10.

[0054] Exemplarily, the light-emitting color of the first-type devices 301 may be red, and the light-emitting color of the second-type devices 302 may be blue.

[0055] The first-type devices 301 and the second-type devices 302 are alternately arranged along the first direction X to form a first device column L1, and the first-type devices 301 and the second-type devices 302 are alternately arranged along the second direction Y to form a first device row R1.

[0056] By setting that in the same first device column L1, the connection parts 312 of the first-type devices 301 are all connected to one side of the main body part 311 in the second direction Y, and the connection parts 312 of the second-type devices 302 are all connected to the other side of the main body part 311 in the second direction Y, the first-type devices 301 and the second-type devices 302 can be respectively electrically connected to device structures (such as the pixel circuit 180) located in different columns in the substrate 100, so as to facilitate relatively independent driving of the first-type devices 301 and the second-type devices 302, and further contribute to improving the display effect of the display panel 10.

[0057] Exemplarily, as Figure 3 shown, in the same first device column L1, the connection parts 312 of the first-type devices 301 can all be connected to the left side of the main body part 311, and the connection parts 312 of the second-type devices 302 can all be connected to the right side of the main body part 311; or, in the same first device column L1, the connection parts 312 of the first-type devices 301 can all be connected to the right side of the main body part 311, and the connection parts 312 of the second-type devices 302 can all be connected to the left side of the main body part 311.

[0058] Optionally, in two adjacent first device columns L1, the connection portions 312 of the first type of devices 301 in one of the first device columns L1 can all be connected to the left side of the main body portion 311, and the connection portions 312 of the second type of devices 302 can all be connected to the right side of the main body portion 311. In the other first device column L1, the connection portions 312 of the first type of devices 301 can all be connected to the right side of the main body portion 311, and the connection portions 312 of the second type of devices 302 can all be connected to the left side of the main body portion 311.

[0059] By setting that in the same first device row R1, the connection portions 312 of the respective first electrodes 310 are all located on the same side of the main body portion 311 in the second direction Y, there can be only one connection portion 312 of the first electrode 310 between the main body portions 311 of the adjacent first electrodes 310 in the second direction Y. Thus, the spacing between the respective main body portions 311 in the first device row R1 can be relatively approximate or the same, which is beneficial to improving the arrangement effect of the light-emitting devices 300 in the display panel 10, and further beneficial to improving the display effect of the display panel 10.

[0060] Exemplarily, as Figure 3 shown, in the same first device row R1, the connection portions 312 of the first type of devices 301 and the second type of devices 302 can both be connected to the left side of the main body portion 311; or, the connection portions 312 of the first type of devices 301 and the second type of devices 302 can both be connected to the right side of the main body portion 311.

[0061] Optionally, in two adjacent first device rows R1, the connection portions 312 of the first electrodes 310 in different first device rows R1 are located on different sides of the main body portion 311 in the second direction Y. Exemplarily, in two adjacent first device rows R1, the connection portions 312 of the first type of devices 301 and the second type of devices 302 in one of the first device rows R1 can both be connected to the left side of the main body portion 311, and the connection portions 312 of the first type of devices 301 and the second type of devices 302 in the other first device row R1 can both be connected to the right side of the main body portion 311.

[0062] Figure 4 is a schematic layout diagram of a pixel circuit 180 provided by an embodiment of the present application, Figure 5 is a schematic partial structure diagram of a display panel 10 provided by an embodiment of the present application, Figure 6 is a schematic connection relationship diagram of a pixel circuit 180, a light-emitting device 300 and a data signal line Vdata provided by an embodiment of the present application. Exemplarily, for easy distinction Figure 4 among the first circuit column E1, the second circuit column E2 and the third circuit column E3 in Figure 4 the pixel circuits 180 in the first circuit column E1, the second circuit column E2 and the third circuit column E3 in

[0063] As Figures 4 to 6 shown, in some alternative embodiments, at least two pixel circuits 180 are arranged in the first direction X to form a circuit column. The data signal line Vdata can extend along the first direction X. Each pixel circuit 180 in the same circuit column is electrically connected to the same data signal line Vdata, so that a single data signal line Vdata can provide data signals to each pixel circuit 180 located in the same circuit column, which is beneficial to improving the working efficiency of the data signal line Vdata and is convenient for controlling the display panel 10.

[0064] Optionally, each pixel circuit 180 in the same circuit column being electrically connected to the same data signal line Vdata may mean that the first ends of the data writing transistors T2 of each pixel circuit 180 in the same circuit column can be electrically connected to the same data signal line Vdata.

[0065] Optionally, the number of data signal lines Vdata may be multiple. Exemplarily, the number of data signal lines Vdata may be the same as the number of circuit columns, and a single data signal line Vdata can be correspondingly arranged with a single circuit column.

[0066] Optionally, multiple data signal lines Vdata can be spaced apart in the second direction Y.

[0067] Optionally, the data signal line Vdata can be disposed in the substrate 100, and there are various ways to set the position of the data signal line Vdata in the substrate 100. Exemplarily, the sixth insulating layer 170 may include a first sub-layer 171 and a second sub-layer 172 disposed on the side of the first sub-layer 171 facing away from the substrate 110, and the data signal line Vdata can be disposed between the first sub-layer 171 and the second sub-layer 172.

[0068] Optionally, the first power supply voltage signal line ELVDD can be set on the same layer and made of the same material as the data signal line Vdata, so that the first power supply voltage signal line ELVDD and the data signal line Vdata can be prepared together in the same manufacturing step, which is beneficial to improving the manufacturing efficiency of the display panel 10. Exemplarily, both the first power supply voltage signal line ELVDD and the data signal line Vdata can be disposed between the first sub-layer 171 and the second sub-layer 172.

[0069] Optionally, the first power supply voltage signal line ELVDD may extend along the first direction X, and each pixel circuit 180 in the same circuit column may be electrically connected to the same first power supply voltage signal line ELVDD. Exemplarily, the first ends of the second control transistors T5 of each pixel circuit 180 in the same circuit column may be electrically connected to the same first power supply voltage signal line ELVDD, so that a single first power supply voltage signal line ELVDD can provide a positive power supply voltage signal to each pixel circuit 180 located in the same circuit column, which is beneficial to improving the working efficiency of the first power supply voltage signal line ELVDD and facilitating the control of the display panel 10.

[0070] Optionally, the number of the first power supply voltage signal lines ELVDD may be multiple, and a single first power supply voltage signal line ELVDD may be correspondingly arranged with at least one circuit column. Exemplarily, a single first power supply voltage signal line ELVDD may be correspondingly arranged with two adjacent circuit columns in the second direction Y, that is, each pixel circuit 180 in two adjacent circuit columns in the second direction Y may be electrically connected to the same first power supply voltage signal line ELVDD.

[0071] Optionally, multiple first power supply voltage signal lines ELVDD may be arranged at intervals in the second direction Y.

[0072] Optionally, signal lines (not shown in the figure) for electrically connecting at least two adjacent first power supply voltage signal lines ELVDD in the second direction Y may further be provided in the substrate 100, so that each first power supply voltage signal line ELVDD can be electrically connected to each other, which is beneficial to facilitating the control of each first power supply voltage signal line ELVDD and reducing the voltage drop and resistance of the first power supply voltage signal line ELVDD.

[0073] Optionally, at least one data signal line Vdata may be arranged between the first power supply voltage signal lines ELVDD adjacent in the second direction Y. Exemplarily, two data signal lines Vdata may be arranged between the first power supply voltage signal lines ELVDD adjacent in the second direction Y, which is beneficial to facilitating the corresponding arrangement of a single first power supply voltage signal line ELVDD with two adjacent circuit columns in the second direction Y and also facilitating the corresponding arrangement of a single data signal line Vdata with a single circuit column.

[0074] Optionally, the display panel 10 may further include an in-plane antenna (FIAA) to facilitate reducing the border of the display panel 10.

[0075] Optionally, at least a portion of the in-plane trace FIAA may extend along the first direction X. The in-plane trace FIAA extending along the first direction X may be provided on the same layer and made of the same material as the data signal line Vdata, such that the in-plane trace FIAA extending along the first direction X and the data signal line Vdata can be fabricated in the same fabrication step, which is beneficial to improving the fabrication efficiency of the display panel 10. Exemplarily, the first power supply voltage signal line ELVDD, the data signal line Vdata, and the in-plane trace FIAA extending along the first direction X may all be provided between the first sub-layer 171 and the second sub-layer 172.

[0076] Optionally, a portion of the in-plane trace FIAA may also extend along the second direction Y (not shown in the figure) to further increase the layout density of the in-plane trace FIAA. Optionally, the in-plane trace FIAA extending along the second direction Y may be arranged on a different layer from the in-plane trace FIAA extending along the first direction X.

[0077] Optionally, the in-plane trace FIAA extending along the first direction X may be located between adjacent data signal lines Vdata in the second direction Y. Exemplarily, two in-plane traces FIAA extending along the first direction X may be provided between adjacent data signal lines Vdata in the second direction Y, which is beneficial to increasing the layout density of the in-plane trace FIAA.

[0078] In some alternative embodiments, the circuit columns include a first circuit column E1 and a second circuit column E2, and the first circuit column E1 and the second circuit column E2 are alternately arranged along the second direction Y. The connection portions 312 of the first type of devices 301 in the first device column L1 are respectively electrically connected to the pixel circuits 180 in the same first circuit column E1, and / or the connection portions 312 of the second type of devices 302 in the first device column L1 are respectively electrically connected to the pixel circuits 180 in the same second circuit column E2.

[0079] Optionally, the connection portions 312 of the first type of devices 301 in the first device column L1 are respectively electrically connected to the second ends of the first control transistors T6 of the pixel circuits 180 in the same first circuit column E1.

[0080] Optionally, the connection portions 312 of the second type of devices 302 in the first device column L1 are respectively electrically connected to the second ends of the first control transistors T6 of the pixel circuits 180 in the same second circuit column E2.

[0081] Optionally, a single data signal line Vdata may be electrically connected to the pixel circuits 180 in a single first circuit column E1. Exemplarily, a single data signal line Vdata may be electrically connected to the first ends of the data writing transistors T2 of the pixel circuits 180 in a single first circuit column E1.

[0082] Optionally, a single data signal line Vdata may be electrically connected to each pixel circuit 180 in a single second circuit column E2. Exemplarily, a single data signal line Vdata may be electrically connected to the first end of a data writing transistor T2 of each pixel circuit 180 in a single second circuit column E2.

[0083] Optionally, the data signal lines Vdata electrically connected to the first circuit column E1 and the data signal lines Vdata electrically connected to the second circuit column E2 may be alternately arranged along the second direction Y, so as to facilitate the electrical connection between the data signal lines Vdata and the corresponding circuit columns.

[0084] Optionally, during the operation of the pixel circuit 180, the voltage of the data signal provided by the data signal line Vdata electrically connected to the first circuit column E1 may be different from the voltage of the data signal provided by the data signal line Vdata electrically connected to the second circuit column E2.

[0085] In these optional embodiments, by respectively electrically connecting the connection portions 312 of the first type of devices 301 in the first device column L1 to each pixel circuit 180 in the same first circuit column E1, and respectively electrically connecting the connection portions 312 of the second type of devices 302 in the first device column L1 to each pixel circuit 180 in the same second circuit column E2, the first circuit column E1 and the second circuit column E2 can be respectively used to relatively independently drive and control the light emission of the first type of devices 301 and the second type of devices 302, that is, it is possible to facilitate the relatively independent driving and control of the light emission of the first type of devices 301 and the second type of devices 302 with different light emission colors, thereby being beneficial to reducing the power consumption of the display panel 10 and improving the display effect of the display panel 10.

[0086] In some optional embodiments, in two adjacent first device columns L1, the connection portions 312 of the first type of devices 301 are respectively electrically connected to each pixel circuit 180 in the same first circuit column E1, or the connection portions 312 of the second type of devices 302 are respectively electrically connected to each pixel circuit 180 in the same second circuit column E2.

[0087] Optionally, in two adjacent first device columns L1, the connection portions 312 of the first type of devices 301 are respectively electrically connected to each pixel circuit 180 in the same first circuit column E1, and the connection portions 312 of the second type of devices 302 located in different first device columns L1 are respectively electrically connected to each pixel circuit 180 located in different second circuit columns E2; or the connection portions 312 of the second type of devices 302 are respectively electrically connected to each pixel circuit 180 in the same second circuit column E2, and the connection portions 312 of the first type of devices 301 located in different first device columns L1 are respectively electrically connected to each pixel circuit 180 located in different first circuit columns E1.

[0088] Exemplarily, in two adjacent columns of first device columns L1, the connection portions 312 of the first type of devices 301 are respectively electrically connected to the second ends of the first control transistors T6 of the pixel circuits 180 in the same first circuit column E1, and the connection portions 312 of the second type of devices 302 located in different first device columns L1 are respectively electrically connected to the second ends of the first control transistors T6 of the pixel circuits 180 located in different second circuit columns E2; alternatively, the connection portions 312 of the second type of devices 302 are respectively electrically connected to the second ends of the first control transistors T6 of the pixel circuits 180 in the same second circuit column E2, and the connection portions 312 of the first type of devices 301 located in different first device columns L1 are respectively electrically connected to the second ends of the first control transistors T6 of the pixel circuits 180 located in different first circuit columns E1.

[0089] Optionally, the orthographic projection of the first circuit column E1 on the substrate 110 may be located between the orthographic projections of the main body portions 311 of two adjacent columns of first device columns L1 on the substrate 110, so as to facilitate the connection portions 312 of the first type of devices 301 in two adjacent columns of first device columns L1 to be respectively electrically connected to the pixel circuits 180 in the same first circuit column E1.

[0090] Optionally, the orthographic projection of the second circuit column E2 on the substrate 110 may be located between the orthographic projections of the main body portions 311 of two adjacent columns of first device columns L1 on the substrate 110, so as to facilitate the connection portions 312 of the second type of devices 302 in two adjacent columns of first device columns L1 to be respectively electrically connected to the pixel circuits 180 in the same second circuit column E2.

[0091] In these optional embodiments, by setting the connection portions 312 of the first type of devices 301 in two adjacent columns of first device columns L1 to be respectively electrically connected to the pixel circuits 180 in the same first circuit column E1, each pixel circuit 180 in a single first circuit column E1 can respectively drive and control the light-emitting operation of the first type of devices 301 in two adjacent columns of first device columns L1, so that the number of pixel circuits 180 arranged in the first direction X in the first circuit column E1 can be increased to reduce the number of first circuit columns E1 arranged in the second direction Y, thereby facilitating the improvement of the pixel arrangement density of the display panel 10, and further improving the display effect of the display panel 10.

[0092] Similarly, by setting the connection parts 312 of the second type of devices 302 in two adjacent first device columns L1 to be electrically connected to the pixel circuits 180 in the same second circuit column E2 respectively, each pixel circuit 180 in a single second circuit column E2 can drive and control the light-emitting operations of the second type of devices 302 in two adjacent first device columns L1 respectively. Thus, by increasing the number of pixel circuits 180 arranged in the first direction X in the second circuit column E2, the number of second circuit columns arranged in the second direction Y can be reduced, which is beneficial to improving the pixel arrangement density of the display panel 10 and further enhancing the display effect of the display panel 10.

[0093] In some alternative embodiments, the connection part 312 of the first type of device 301 can be located between the main body part 311 of the first type of device 301 and the main body part 311 of the second type of device 302 adjacent in the second direction Y, and / or the connection part 312 of the second type of device 302 can be located between the main body part 311 of the first type of device 301 and the main body part 311 of the second type of device 302 adjacent in the second direction Y.

[0094] In this alternative embodiment, by setting the connection part 312 of the first type of device 301 and the connection part 312 of the second type of device 302 between the main body part 311 of the first type of device 301 and the main body part 311 of the second type of device 302 adjacent in the second direction Y, it is possible to prevent the connection parts 312 of the first type of device 301 and the second type of device 302 from having overly large sizes (for example, the connection part 312 of the first type of device 301 may not extend around to the side of the main body part 311 of the second type of device 302 in the first direction X, and the connection part 312 of the second type of device 302 may not extend around to the side of the main body part 311 of the first type of device 301 in the first direction X). This is beneficial to reducing the possibility of disconnection between the first electrode 310 of the first type of device 301 and the first electrode 310 of the second type of device 302, and is also beneficial to reducing the coupling interference effect between the light-emitting devices 300, thereby improving the working effect of the display panel 10.

[0095] In some alternative embodiments, at least a part of the first control transistor T6 is located on one side of the main body part 311 of the first type of device 301 and / or the second type of device 302 in the second direction Y.

[0096] Optionally, at least a part of the first control transistor T6 being located on one side of the main body part 311 of the first type of device 301 and / or the second type of device 302 in the second direction Y may mean that the orthographic projection of the first control transistor T6 on the substrate 110 can at least partially be located on one side of the orthographic projection of the main body part 311 of the first type of device 301 and / or the second type of device 302 on the substrate 110 in the second direction Y.

[0097] Exemplarily, the positive projection of the source 181c and / or the drain 181d of the first control transistor T6 on the substrate 110 may be at least partially located on one side of the positive projection of the main body 311 of the first type of device 301 and / or the second type of device 302 on the substrate 110 in the second direction Y.

[0098] Optionally, the first control transistors T6 of at least one column of the first circuit columns E1 may be at least partially located on one side of the main body 311 of the first type of device 301 and / or the second type of device 302 in the second direction Y. Exemplarily, the first control transistors T6 of the first circuit column E1 may be at least partially located on one side of the main body 311 of the first type of device 301 and / or the second type of device 302 in the second direction Y. The first control transistors T6 of the second circuit column E2 may be at least partially located on one side of the main body 311 of the first type of device 301 and / or the second type of device 302 in the second direction Y.

[0099] Optionally, the positive projection of the source 181c and / or the drain 181d of the first control transistors T6 of at least one column of circuit columns on the substrate 110 may be at least partially located between the positive projection of the main body 311 of the first type of device 301 adjacent in the second direction Y and the positive projection of the main body 311 of the second type of device 302 on the substrate 110. Exemplarily, the positive projection of the source 181c and / or the drain 181d of the first control transistors T6 of the first circuit column E1 on the substrate 110 may be at least partially located between the positive projection of the main body 311 of the first type of device 301 adjacent in the second direction Y and the positive projection of the main body 311 of the second type of device 302 on the substrate 110, and / or, the positive projection of the source 181c and / or the drain 181d of the first control transistors T6 of the second circuit column E2 on the substrate 110 may be at least partially located between the positive projection of the main body 311 of the first type of device 301 adjacent in the second direction Y and the positive projection of the main body 311 of the second type of device 302 on the substrate 110.

[0100] In these alternative embodiments, by disposing the first control transistor T6 connected to the connection portion 312 on one side of the main body portion 311 of the first type of device 301 and the second type of device 302 in the second direction Y, it is beneficial for the electrical connection between the connection portion 312 protruding from the main body portion 311 of the first type of device 301 and the second type of device 302 in the second direction Y and the first control transistor T6. Moreover, it is beneficial for the connection point between the connection portion 312 of the first type of device 301 and the pixel circuit 180 to be located between the main body portion 311 of the first type of device 301 and the main body portion 311 of the second type of device 302 adjacent in the second direction Y. It is also beneficial for the connection point between the connection portion 312 of the second type of device 302 and the pixel circuit 180 to be located between the main body portion 311 of the first type of device 301 and the main body portion 311 of the second type of device 302 adjacent in the second direction Y, such that the connection portions 312 of the first type of device 301 and the second type of device 302 are not likely to have too large a size. Thus, it is beneficial to reduce the possibility of disconnection between the first electrode 310 of the first type of device 301 and the first electrode 310 of the second type of device 302, and it is beneficial to reduce the coupling interference effect between the respective light-emitting devices 300, and further beneficial to improve the working effect of the display panel 10.

[0101] In some alternative embodiments, the light-emitting device 300 further includes a plurality of third type of devices 303 whose light-emitting colors are different from both the light-emitting color of the first type of device 301 and the light-emitting color of the second type of device 302, so as to facilitate color display of the display panel 10.

[0102] Exemplarily, the light-emitting color of the third type of device 303 may be green.

[0103] Optionally, the orthographic projection area of the main body portion 311 of the first type of device 301 on the substrate 110 may be greater than the orthographic projection area of the main body portion 311 of the third type of device 303 on the substrate 110, and / or the orthographic projection area of the main body portion 311 of the second type of device 302 on the substrate 110 may be greater than the orthographic projection area of the main body portion 311 of the third type of device 303 on the substrate 110, such that when the light-emitting color of the first type of device 301 is red, the light-emitting color of the second type of device 302 is blue, and the light-emitting color of the third type of device 303 is green, the light-emitting effects of the first type of device 301 and the second type of device 302 with relatively low light-emitting efficiency can be better improved.

[0104] Optionally, the orthographic projection area of the main body portion 311 of the second type of device 302 on the substrate 110 may be greater than the orthographic projection area of the main body portion 311 of the first type of device 301 on the substrate 110, such that when the light-emitting color of the first type of device 301 is red and the light-emitting color of the second type of device 302 is blue, the light-emitting effect of the second type of device 302 with relatively low light-emitting efficiency can be better improved.

[0105] In some alternative embodiments, a plurality of third-type devices 303 are arranged along a first direction X to form a second device column L2, the first device column L1 and the second device column L2 are alternately arranged along a second direction Y, the circuit column further includes a third circuit column E3, the first circuit column E1, the second circuit column E2 and the third circuit column E3 are alternately arranged along the second direction Y, and at least one column of the third circuit column E3 is provided between the adjacent first circuit column E1 and the second circuit column E2. Connection portions 312 of the third-type devices 303 in the second device column L2 are respectively electrically connected to pixel circuits 180 in the same third circuit column E3.

[0106] Optionally, the first circuit column E1, the second circuit column E2 and the third circuit column E3 being alternately arranged along the second direction Y may mean that the respective first circuit columns E1 arranged in the second direction Y may not be directly adjacent to each other, that is, a second circuit column E2 or a third circuit column E3 may be provided between the respective first circuit columns E1 arranged in the second direction Y. Similarly, the respective second circuit columns E2 arranged in the second direction Y may not be directly adjacent to each other, that is, a first circuit column E1 or a third circuit column E3 may be provided between the respective second circuit columns E2 arranged in the second direction Y. The respective third circuit columns E3 arranged in the second direction Y may not be directly adjacent to each other, that is, a first circuit column E1 or a second circuit column E2 may be provided between the respective third circuit columns E3 arranged in the second direction Y.

[0107] Optionally, in the display panel 10, a single first circuit column E1, a single second circuit column E2 and two third circuit columns E3 may form a circuit repeating unit EG in the circuit column arrangement. The number of the circuit repeating units EG may be multiple, and the multiple circuit repeating units EG may be arranged along the second direction Y. Exemplarily, as Figure 4 shown, in the direction from left to right, a third circuit column E3, a first circuit column E1, a third circuit column E3 and a second circuit column E2 may be sequentially arranged in the circuit repeating unit EG.

[0108] Optionally, in the display panel 10, two first device columns L1 and two second device columns L2 may form a device repeating unit LG in the light-emitting device 300 arrangement. The number of the device repeating units LG may be multiple, and the multiple device repeating units LG may be arranged along the second direction Y. Exemplarily, as Figure 5 shown, in the direction from left to right, a first device column L1, a second device column L2, a first device column L1 and a second device column L2 may be sequentially arranged in the device repeating unit LG.

[0109] Optionally, the data signal line Vdata electrically connected to the third circuit column E3 may be adjacent to the data signal line Vdata electrically connected to the second circuit column E2, or the data signal line Vdata electrically connected to the third circuit column E3 may be adjacent to the data signal line Vdata electrically connected to the first circuit column E1.

[0110] Exemplarily, a single data signal line Vdata electrically connected to the third circuit column E3 and a single data signal line Vdata electrically connected to the second circuit column E2 may be provided between the first power supply voltage signal lines ELVDD adjacent in the second direction Y, or a single data signal line Vdata electrically connected to the third circuit column E3 and a single data signal line Vdata electrically connected to the first circuit column E1 may be provided between the first power supply voltage signal lines ELVDD adjacent in the second direction Y.

[0111] In these alternative embodiments, by respectively connecting the connection portions 312 of the third type of devices 303 in the second device column L2 to the pixel circuits 180 in the same third circuit column E3, the third circuit column E3 can be used to relatively independently drive and control the light emission of the third type of devices 303, thereby facilitating reducing the power consumption of the display panel 10 and improving the display effect of the display panel 10. By arranging the first device column L1 and the second device column L2 alternately along the second direction Y, arranging the first circuit column E1, the second circuit column E2 and the third circuit column E3 alternately along the second direction Y, and providing at least one third circuit column E3 between the adjacent first circuit column E1 and the second circuit column E2, it is convenient for each second device column L2 to be electrically connected to the pixel circuit 180 in the third circuit column E3.

[0112] In some alternative embodiments, in two adjacent columns of the first device columns L1, the positive projection of the first electrode 310 of one of the first device columns L1 on the substrate 110 partially overlaps with the positive projection of the first circuit column E1 on the substrate 110 and partially overlaps with the positive projection of the third circuit column E3 on the substrate 110. The positive projection of the first electrode 310 of the other first device column L1 on the substrate 110 partially overlaps with the positive projection of the second circuit column E2 on the substrate 110 and partially overlaps with the positive projection of the third circuit column E3 on the substrate 110, such that one of the first device columns L1 in the device repeating unit LG can be preferably located between the first circuit column E1 and one of the third circuit columns E3 in the circuit repeating unit EG, and the other first device column L1 in the device repeating unit LG can be preferably located between the second circuit column E2 and the other third circuit column E3 in the circuit repeating unit EG, which is conducive to electrically connecting the first type of devices 301 in the two first device columns L1 to the respective pixel circuits 180 in the same first circuit column E1 and is conducive to electrically connecting the second type of devices 302 in the two first device columns L1 to the respective pixel circuits 180 in the same first circuit column E1.

[0113] In some alternative embodiments, in two adjacent columns of the second device columns L2, the positive projection of the first electrode 310 of one of the second device columns L2 on the substrate 110 partially overlaps with the positive projection of the first circuit column E1 on the substrate 110 and partially overlaps with the positive projection of the third circuit column E3 on the substrate 110. The positive projection of the first electrode 310 of the other second device column L2 on the substrate 110 partially overlaps with the positive projection of the second circuit column E2 on the substrate 110 and partially overlaps with the positive projection of the third circuit column E3 on the substrate 110, which is conducive to electrically connecting the third type of devices 303 in each of the second device columns L2 to the respective pixel circuits 180 in each of the third circuit columns E3.

[0114] In some alternative embodiments, a plurality of the third type of devices 303 are arranged along the second direction Y to form a second device row R2, and the first device row R1 and the second device row R2 are alternately arranged along the first direction X. The connecting portion 312 of the third type of device 303 is connected to one side of the main body portion 311 in the first direction X.

[0115] Optionally, in the same second device column L2, the connecting portions 312 of the respective first electrodes 310 are all located on the same side of the main body portion 311 in the first direction X, and / or, in the same second device row R2, the connecting portions 312 of the respective first electrodes 310 are all located on the same side of the main body portion 311 in the first direction X, which can facilitate the arrangement of the respective third type of devices 303.

[0116] Exemplarily, such as Figure 5As shown, in the same second device column L2, the connection portions 312 of the first electrodes 310 are all located on the upper side of the main body portion 311, and / or, in the same second device row R2, the connection portions 312 of the first electrodes 310 are all located on the upper side of the main body portion 311.

[0117] Optionally, the first control transistor T6 of the third circuit column E3 may be at least partially located on one side of the main body portion 311 of the first type of device 301 and / or the second type of device 302 in the second direction Y.

[0118] Optionally, the positive projection of the source electrode 181c and / or the drain electrode 181d of the first control transistor T6 of the third circuit column E3 on the substrate 110 may be at least partially located between the positive projection of the main body portion 311 of the first type of device 301 adjacent in the second direction Y on the substrate 110 and the positive projection of the main body portion 311 of the second type of device 302 on the substrate 110.

[0119] Optionally, the connection portion 312 of the third type of device 303 may be located between the main body portion 311 of the first type of device 301 and the main body portion 311 of the second type of device 302 adjacent in the second direction Y.

[0120] In these optional embodiments, by connecting the connection portion 312 of the third type of device 303 to one side of the main body portion 311 in the first direction X, it is convenient to connect the connection portion 312 of the third type of device 303 to the first control transistor T6 in the third circuit column E3 provided on one side of the main body portions 311 of the first type of device 301 and the second type of device 302 in the second direction Y. And, it is beneficial to make the connection point between the connection portion 312 of the third type of device 303 and the pixel circuit 180 be located between the main body portion 311 of the first type of device 301 and the main body portion 311 of the second type of device 302 adjacent in the second direction Y, so that the connection portion 312 of the third type of device 303 is not likely to have an overly large size, thereby being beneficial to reducing the possibility of disconnection of the first electrode 310 of the third type of device 303, and being beneficial to reducing the coupling interference effect between the light-emitting devices 300, and further being beneficial to improving the working effect of the display panel 10.

[0121] In some optional embodiments, the connection portion 312 of the third type of device 303 may be located on one side of the connection portion 312 of the first type of device 301 in the first direction X, or the connection portion 312 of the third type of device 303 may be located on one side of the connection portion 312 of the second type of device 302 in the first direction X.

[0122] Optionally, as Figure 5As shown, the connecting portion 312 of the third type of device 303 may be located below the connecting portion 312 of the first type of device 301, or the connecting portion 312 of the third type of device 303 may be located below the connecting portion 312 of the second type of device 302.

[0123] Optionally, when the orthographic projection of the first electrode 310 of the second device column L2 on the substrate 110 overlaps with the orthographic projection of the first circuit column E1 on the substrate 110 and also overlaps with the orthographic projection of the third circuit column E3 on the substrate 110, the connecting portion 312 of the third type of device 303 may be located on one side of the connecting portion 312 of the first type of device 301 in the first direction X. When the orthographic projection of the first electrode 310 of the second device column L2 on the substrate 110 overlaps with the orthographic projection of the second circuit column E2 on the substrate 110 and also overlaps with the orthographic projection of the third circuit column E3 on the substrate 110, the connecting portion 312 of the third type of device 303 may be located on one side of the connecting portion 312 of the second type of device 302 in the first direction X.

[0124] In these optional embodiments, by arranging the connecting portion 312 of the third type of device 303 on one side of the connecting portion 312 of the first type of device 301 in the first direction X, or by arranging the connecting portion 312 of the third type of device 303 on one side of the connecting portion 312 of the second type of device 302 in the first direction X, the interference effect between the connecting portion 312 of the third type of device 303 and the connecting portion 312 of the first type of device 301 can be better reduced, and the interference effect between the connecting portion 312 of the third type of device 303 and the connecting portion 312 of the second type of device 302 can be better reduced, which is beneficial to the arrangement of each light-emitting device 300, and thus beneficial to improving the pixel arrangement density of the display panel 10.

[0125] In some optional embodiments, the substrate 100 further includes a connection structure 190 disposed between the light-emitting device 300 and the pixel circuit 180. The connection structure 190 includes a first connection structure 191, a second connection structure 192, and a third connection structure 193. The connecting portion 312 of the first type of device 301 is electrically connected to the pixel circuit 180 through the first connection structure 191, the connecting portion 312 of the second type of device 302 is electrically connected to the pixel circuit 180 through the second connection structure 192, and the connecting portion 312 of the third type of device 303 is electrically connected to the pixel circuit 180 through the third connection structure 193.

[0126] Optionally, the connection portion 312 of the first type of device 301 is electrically connected to the second end of the first control transistor T6 in the first circuit column E1 through the first connection structure 191, the connection portion 312 of the second type of device 302 is electrically connected to the second end of the first control transistor T6 in the second circuit column E2 through the second connection structure 192, and the connection portion 312 of the third type of device 303 is electrically connected to the second end of the first control transistor T6 in the third circuit column E3 through the third connection structure 193.

[0127] Optionally, the connection structure 190 can be disposed within the substrate 100, and there are various ways to set the position of the connection structure 190 in the substrate 100. Exemplarily, the connection structure 190 can be disposed between the first sub-layer 171 and the second sub-layer 172.

[0128] Optionally, the connection structure 190 can be set on the same layer and made of the same material as the data signal line Vdata, so that the connection structure 190 and the data signal line Vdata can be prepared in the same manufacturing step, which is beneficial to improving the manufacturing efficiency of the display panel 10. Exemplarily, the first power supply voltage signal line ELVDD, the data signal line Vdata, the connection structure 190, and the in-plane trace FIAA extending along the first direction X can all be disposed between the first sub-layer 171 and the second sub-layer 172.

[0129] In some optional embodiments, one end of the first connection structure 191 away from the connection portion 312 of the first type of device 301 and one end of the third connection structure 193 away from the connection portion 312 of the third type of device 303 are adjacent and spaced apart in the second direction Y, and / or one end of the second connection structure 192 away from the connection portion 312 of the second type of device 302 and one end of the third connection structure 193 away from the connection portion 312 of the third type of device 303 are adjacent and spaced apart in the second direction Y.

[0130] Exemplarily, when the positive projection of the first electrode 310 of the second device column L2 on the substrate 110 overlaps with a part of the positive projection of the first circuit column E1 on the substrate 110 and also overlaps with a part of the positive projection of the third circuit column E3 on the substrate 110, one end of the third connection structure 193 connected to the first electrode 310 corresponding to the second device column L2 and away from the connection portion 312 of the third type of device 303 can be adjacent and spaced apart in the second direction Y from one end of the first connection structure 191 away from the connection portion 312 of the first type of device 301.

[0131] When the positive projection of the first electrode 310 of the second device column L2 on the substrate 110 partially overlaps with the positive projection of the second circuit column E2 on the substrate 110 and partially overlaps with the positive projection of the third circuit column E3 on the substrate 110, one end of the third connection structure 193 connected to the first electrode 310 corresponding to the second device column L2, which is far from the connection portion 312 of the third type of device 303, can be adjacent and spaced in the second direction Y to the one end of the second connection structure 192 that is far from the connection portion 312 of the second type of device 302.

[0132] Optionally, the first connection structure 191 may have certain dimensions in the first direction X and the second direction Y, so that the first electrode 310 of the first type of device 301 can be electrically connected to the pixel circuit 180 through the first connection structure 191. The second connection structure 192 may have certain dimensions in the first direction X and the second direction Y, so that the first electrode 310 of the second type of device 302 can be electrically connected to the pixel circuit 180 through the first connection structure 191.

[0133] Optionally, the first control transistor T6 in the first circuit column E1 may be adjacent to the first control transistor T6 in the third circuit column E3 in the second direction Y, and / or the first control transistor T6 in the second circuit column E2 may be adjacent to the first control transistor T6 in the third circuit column E3 in the second direction Y.

[0134] In these optional embodiments, by setting one end of the first connection structure 191 that is far from the connection portion 312 of the first type of device 301 and one end of the third connection structure 193 that is far from the connection portion 312 of the third type of device 303 to be adjacent and spaced in the second direction Y, the connection position between the first connection structure 191 and the pixel circuit 180 can be adjacent and spaced in the second direction Y to the connection position between the third connection structure 193 and the pixel circuit 180, which is beneficial to adapting to the arrangement of the first circuit column E1 and the third circuit column E3 along the second direction Y, facilitating the electrical connection between the first connection structure 191 and the second end of the first control transistor T6 in the first circuit column E1, and facilitating the electrical connection between the third connection structure 193 and the second end of the first control transistor T6 in the third circuit column E3.

[0135] Similarly, by setting one end of the second connection structure 192 away from the connection portion 312 of the second type of device 302 and one end of the third connection structure 193 away from the connection portion 312 of the third type of device 303 to be adjacent and spaced apart in the second direction Y, the connection positions between the second connection structure 192 and the pixel circuit 180 can be arranged to be adjacent and spaced apart in the second direction Y from the connection positions between the third connection structure 193 and the pixel circuit 180, which is beneficial to adapting to the arrangement of the second circuit column E2 and the third circuit column E3 along the second direction Y, facilitating the electrical connection between the second connection structure 192 and the second end of the first control transistor T6 in the second circuit column E2, and facilitating the electrical connection between the third connection structure 193 and the second end of the first control transistor T6 in the third circuit column E3.

[0136] Figure 7 FIG. is a partial schematic structural diagram of a pixel circuit 180 provided by an embodiment of the present application. Figures 8 to 12 FIG. is a partial schematic structural diagram of each film layer in a substrate 100 provided by an embodiment of the present application. Figure 7 The dashed boxes at the film layer junctions in FIG. can indicate the connection positions between the film layers.

[0137] Such as Figures 5 to 12 As shown, in some alternative embodiments, a virtual symmetry axis DL extending along the first direction X extends through the first electrode 310 of the first device column L1, and the adjacent first circuit column E1 and the third circuit column E3 are symmetrically arranged with respect to the virtual symmetry axis DL extending along the first direction X, and / or, the adjacent second circuit column E2 and the third circuit column E3 are symmetrically arranged with respect to the virtual symmetry axis DL extending along the first direction X, and / or, the adjacent data signal lines Vdata are symmetrically arranged with respect to the virtual symmetry axis DL extending along the first direction X.

[0138] Optionally, the virtual symmetry axis DL extending along the first direction X can extend through the first electrode 310 of the first type of device 301 and / or the first electrode 310 of the second type of device 302.

[0139] Optionally, the virtual symmetry axis DL extending along the first direction X can extend through the main body portion 311 of the first electrode 310 of the first device column L1. Exemplarily, the virtual symmetry axis DL extending along the first direction X can extend through the main body portion 311 of the first electrode 310 of the first type of device 301, and / or, the virtual symmetry axis DL extending along the first direction X can extend through the main body portion 311 of the first electrode 310 of the second type of device 302.

[0140] Optionally, the adjacent first circuit column E1 and the third circuit column E3 are symmetrically arranged with respect to a virtual symmetry axis DL extending along the first direction X, which may mean that the first circuit column E1 and the third circuit column E3 adjacent in the second direction Y and located on both sides of the virtual symmetry axis DL in the second direction Y can be symmetrically arranged with respect to the virtual symmetry axis DL extending along the first direction X.

[0141] Optionally, the adjacent second circuit column E2 and the third circuit column E3 are symmetrically arranged with respect to a virtual symmetry axis DL extending along the first direction X, which may mean that the second circuit column E2 and the third circuit column E3 adjacent in the second direction Y and located on both sides of the virtual symmetry axis DL in the second direction Y can be symmetrically arranged with respect to the virtual symmetry axis DL extending along the first direction X.

[0142] Optionally, the adjacent data signal lines Vdata are symmetrically arranged with respect to a virtual symmetry axis DL extending along the first direction X, which may mean that the data signal lines Vdata adjacent in the second direction Y and located on both sides of the virtual symmetry axis DL in the second direction Y can be symmetrically arranged with respect to the virtual symmetry axis DL extending along the first direction X.

[0143] Optionally, the adjacent in-plane traces FIAA can also be symmetrically arranged with respect to a virtual symmetry axis DL extending along the first direction X. Exemplarily, the in-plane traces FIAA adjacent in the second direction Y and located on both sides of the virtual symmetry axis DL in the second direction Y can be symmetrically arranged with respect to the virtual symmetry axis DL extending along the first direction X.

[0144] Optionally, any two circuit columns described in the embodiments of the present application being symmetrically arranged with respect to a virtual symmetry axis DL extending along the first direction X may mean that each transistor 181 in one circuit column can be respectively symmetrically arranged with respect to the virtual symmetry axis DL extending along the first direction X with the corresponding transistors 181 in the other circuit column, and the storage capacitor 182 in one circuit column can be symmetrically arranged with respect to the virtual symmetry axis DL extending along the first direction X with the storage capacitor 182 in the other circuit column.

[0145] In these alternative embodiments, by arranging the adjacent first circuit column E1 and the third circuit column E3 symmetrically with respect to a virtual symmetry axis DL extending along the first direction X, the first control transistors T6 of the first circuit column E1 and the third circuit column E3 can be distributed more symmetrically on both sides of the first electrode 310 of the first device column L1, which is beneficial for the connection part 312 of the first type of device 301 in the first device column L1 to extend along the second direction Y and be electrically connected to the first control transistor T6 of the first circuit column E1, and is also beneficial for the connection part 312 of the third type of device 303 in the second device column L2 adjacent to the first device column L1 to extend along the first direction X and be electrically connected to the first control transistor T6 of the third circuit column E3.

[0146] Similarly, by arranging the adjacent second circuit column E2 and the third circuit column E3 symmetrically with respect to a virtual symmetry axis DL extending along the first direction X, the first control transistors T6 of the second circuit column E2 and the third circuit column E3 can be distributed more symmetrically on both sides of the first electrode 310 of the first device column L1, which is beneficial for the connection part 312 of the second type of device 302 in the first device column L1 to extend along the second direction Y and be electrically connected to the first control transistor T6 of the second circuit column E2, and is also beneficial for the connection part 312 of the third type of device 303 in the second device column L2 adjacent to the first device column L1 to extend along the first direction X and be electrically connected to the first control transistor T6 of the third circuit column E3.

[0147] Therefore, through the above-mentioned symmetric relationship setting, it is beneficial to arrange the main body part 311 of the third type of device 303 below the gap between the main body parts 311 of the first type of device 301 and the second type of device 302 adjacent in the second direction Y, which is beneficial to improving the pixel arrangement density of the display panel 10, and further beneficial to improving the display effect of the display panel 10.

[0148] In some alternative embodiments, the second control transistor T5 is located on the side of the first control transistor T6 close to the virtual symmetry axis DL, the positive projection of the first power supply voltage signal line ELVDD on the substrate 110 is spaced from the positive projection of the first control transistor T6 on the substrate 110, and a part of the positive projection of the first power supply voltage signal line ELVDD on the substrate 110 is located between the positive projection of the first control transistor T6 on the substrate 110 and the positive projection of the virtual symmetry axis DL on the substrate 110.

[0149] In this optional embodiment, by setting the orthogonal projection of the first power supply voltage signal line ELVDD on the substrate 110 at an interval from the orthogonal projection of the first control transistor T6 on the substrate 110, the arrangement of the first power supply voltage signal line ELVDD is less likely to interfere with the electrical connection between the first electrode 310 and the first control transistor T6. By arranging the second control transistor T5 on the side of the first control transistor T6 closer to the virtual symmetry axis DL and setting the orthogonal projection of a part of the first power supply voltage signal line ELVDD on the substrate 110 between the orthogonal projection of the first control transistor T6 on the substrate 110 and the orthogonal projection of the virtual symmetry axis DL on the substrate 110, the second control transistor T5 can be electrically connected to the first power supply voltage signal line ELVDD in the region between the first control transistor T6 and the virtual symmetry axis DL, which helps to reduce the interference of other devices in the substrate 100 on the electrical connection between the second control transistor T5 and the first power supply voltage signal line ELVDD.

[0150] In some optional embodiments, the orthogonal projection of the first power supply voltage signal line ELVDD on the substrate 110 at least partially overlaps with the orthogonal projection of the first electrode 310 of the third type of device 303 on the substrate 110. A relief opening Hole is formed on the side of the first control transistor T6 facing away from the substrate 110 in the first power supply voltage signal line ELVDD. The connecting portion 312 of the first electrode 310 is electrically connected to the first control transistor T6 via the relief opening Hole.

[0151] Optionally, the relief opening Hole may be at least partially located between the main body portions 311 of two adjacent third type of devices 303 in the first direction X.

[0152] Optionally, the connecting structure 190 may be located within the relief opening Hole, and the first power supply voltage signal line ELVDD may be arranged to surround the connecting structure 190.

[0153] Optionally, the relief opening Hole may be at least partially located between the main body portions 311 of the first device column L1 adjacent in the first direction X. Optionally, the connecting portions 312 of the first type of device 301, the second type of device 302, and the third type of device 303 may all extend to the side of the relief opening Hole facing away from the substrate 110.

[0154] Optionally, the line width of the first power supply voltage signal line ELVDD on both sides of the relief opening Hole in the second direction Y may be smaller than the line width of the first power supply voltage signal line ELVDD on both sides of the relief opening Hole in the first direction X.

[0155] Optionally, in two adjacent circuit columns below the yielding opening Hole, the second control transistor T5 of one of the circuit columns can be electrically connected to the first power supply voltage signal line ELVDD located on one side of the yielding opening Hole in the second direction Y, and the second control transistor T5 of the other circuit column can be electrically connected to the first power supply voltage signal line ELVDD located on the other side of the yielding opening Hole in the second direction Y. For example, in the first circuit column E1 and the third circuit column E3 adjacent below the yielding opening Hole, the second control transistor T5 of the first circuit column E1 can be electrically connected to the first power supply voltage signal line ELVDD located on one side of the yielding opening Hole in the second direction Y, and the second control transistor T5 of the third circuit column E3 can be electrically connected to the first power supply voltage signal line ELVDD located on the other side of the yielding opening Hole in the second direction Y. For another example, in the second circuit column E2 and the third circuit column E3 adjacent below the yielding opening Hole, the second control transistor T5 of the second circuit column E2 can be electrically connected to the first power supply voltage signal line ELVDD located on one side of the yielding opening Hole in the second direction Y, and the second control transistor T5 of the third circuit column E3 can be electrically connected to the first power supply voltage signal line ELVDD located on the other side of the yielding opening Hole in the second direction Y.

[0156] In these optional embodiments, the first power supply voltage signal line ELVDD can extend under the first electrode 310 of the third type of device 303. By opening the yielding opening Hole on the first power supply voltage signal line ELVDD, it is beneficial to reduce the layout interference between the first power supply voltage signal line ELVDD and other device structures in the display panel 10, so that the first electrode 310 of each light-emitting device 300 can be electrically connected to the pixel circuit 180 via the yielding opening Hole. For example, the first electrode 310 of each light-emitting device 300 can be electrically connected to the connection structure 190 via the yielding opening Hole, so as to be electrically connected to the first control transistor T6 in the pixel circuit 180 through the connection structure 190.

[0157] In some optional embodiments, a single yielding opening Hole is located on the side of the first control transistor T6 of at least two adjacent pixel circuits 180 in the second direction Y, facing away from the substrate 110.

[0158] Exemplarily, a single yielding opening Hole can be located on the side of the first control transistor T6 of the first circuit column E1 and the third circuit column E3 adjacent in the second direction Y, facing away from the substrate 110, or a single yielding opening Hole can be located on the side of the first control transistor T6 of the second circuit column and the third circuit column E3 adjacent in the second direction Y, facing away from the substrate 110.

[0159] Optionally, a single hole can contain at least two connection structures 190. Exemplarily, a single hole can contain a single first connection structure 191 and a single third connection structure 193, or a single hole can contain a single second connection structure 192 and a single third connection structure 193.

[0160] In these optional embodiments, a single clearance opening Hole is provided to be located on the side of the first control transistor T6 of at least two pixel circuits 180 adjacent to each other in the second direction Y away from the substrate 110, so that at least two pairs of pixel circuits 180 and the light-emitting device 300 can be electrically connected at the single clearance opening Hole, which can facilitate the arrangement of the first power supply voltage signal line ELVDD and can also help reduce the spacing between the pixel circuits 180 adjacent to each other in the second direction Y, for example, it is helpful to reduce the spacing between the first control transistors T6 of the pixel circuits 180 adjacent to each other in the second direction Y, thereby helping to improve the arrangement effect of each light-emitting device 300 in the display panel 10.

[0161] In some optional embodiments, the data write transistor T2 is located on a side of the first control transistor T6 close to the virtual symmetry axis DL, the orthographic projection of the data signal line Vdata on the substrate 110 is spaced apart from the orthographic projection of the first control transistor T6 on the substrate 110, and the orthographic projection of part of the data signal line Vdata on the substrate 110 is located between the orthographic projection of the first control transistor T6 on the substrate 110 and the orthographic projection of the virtual symmetry axis DL on the substrate 110.

[0162] Optionally, the data signal line Vdata may be located on a side of the first power voltage signal line ELVDD facing the virtual symmetry axis DL.

[0163] In this optional embodiment, the orthographic projection of the data signal line Vdata on the substrate 110 is arranged to be spaced from the orthographic projection of the first control transistor T6 on the substrate 110, so that the arrangement of the data signal line Vdata is not likely to interfere with the electrical connection between the first electrode 310 and the first control transistor T6. By arranging the data writing transistor T2 to be located on the side of the first control transistor T6 close to the virtual symmetry axis DL, and arranging the orthographic projection of part of the data signal line Vdata on the substrate 110 to be located between the orthographic projection of the first control transistor T6 on the substrate 110 and the orthographic projection of the virtual symmetry axis DL on the substrate 110, the data writing transistor T2 can be electrically connected to the data signal line Vdata in the area between the first control transistor T6 and the virtual symmetry axis DL, which is conducive to reducing the interference of other devices in the substrate 100 on the electrical connection between the data writing transistor T2 and the data signal line Vdata.

[0164] Optionally, in a single pixel circuit 180, the threshold compensation transistor T3 and the second reset transistor T7 may be separately disposed on both sides of the first control transistor T6 in the first direction X, and the first reset transistor T4 may be disposed on a side of the threshold compensation transistor T3 away from the first control transistor T6 in the first direction X. The driving transistor T1 may be disposed on a side of the first control transistor T6 and / or the threshold compensation transistor T3 close to the virtual symmetry axis DL in the second direction Y. The second control transistor T5 and the data writing transistor T2 may also be separately disposed on both sides of the driving transistor T1 in the first direction X. The bias adjustment transistor T8 may be disposed on a side of the second control transistor T5 away from the driving transistor T1 in the first direction X. The first electrode plate 182a and the second electrode plate 182b of the storage capacitor 182 may be located on a side of the semiconductor 181a of the driving transistor T1 facing away from the substrate 110.

[0165] By reasonably setting the relative positional relationship between each transistor 181 and the storage capacitor 182 in the pixel circuit 180, it is possible not only to facilitate the electrical connection between the various device structures in the pixel circuit 180, but also to facilitate the connection between the light-emitting device 300 and the pixel circuit 180, the electrical connection between the first power supply voltage signal line ELVDD and the pixel circuit 180, and the electrical connection between the data signal line Vdata and the pixel circuit 180.

[0166] In some embodiments of the present application, there are various ways to arrange the storage capacitor 182 and each transistor 181 in the pixel circuit 180 in the substrate 100.

[0167] Optionally, as Figure 8 shown, the semiconductors 181a of the driving transistor T1, the data writing transistor T2, the second control transistor T5, the first control transistor T6, the second reset transistor T7, and the bias adjustment transistor T8 may all be located in the same layer. For example, the semiconductor 181a of the driving transistor T1, the semiconductor 181a of the data writing transistor T2, the semiconductor 181a of the second control transistor T5, the semiconductor 181a of the first control transistor T6, the semiconductor 181a of the second reset transistor T7, and the semiconductor 181a of the bias adjustment transistor T8 may all be located between the substrate 110 and the first insulating layer 120.

[0168] As Figure 9As shown, the first electrode plate 182a of the storage capacitor 182, the gate 181b of the data writing transistor T2, the gate 181b of the first control transistor T6, the gate 181b of the second control transistor T5, the gate 181b of the second reset transistor T7, the gate 181b of the bias adjustment transistor T8, the second scanning signal line S2, the fourth scanning signal line S4, and the light emission control signal line EM can all be located on the same layer. For example, the gate 181b of the data writing transistor T2, the gate 181b of the first control transistor T6, the gate 181b of the second control transistor T5, the gate 181b of the second reset transistor T7, the gate 181b of the bias adjustment transistor T8, the second scanning signal line S2, the fourth scanning signal line S4, and the light emission control signal line EM can all be located between the first insulating layer 120 and the second insulating layer 130.

[0169] As Figure 10 shown, the second electrode plate 182b of the storage capacitor 182, the first scanning signal line S1, and the third scanning signal line S3 can all be located on the same layer. For example, the second electrode plate 182b of the storage capacitor 182, the first scanning signal line S1, and the third scanning signal line S3 can all be located between the second insulating layer 130 and the third insulating layer 140.

[0170] As Figure 11 shown, the semiconductor 181a of the threshold compensation transistor T3 and the semiconductor 181a of the first reset transistor T4 can be located on the same layer. For example, the semiconductor 181a of the threshold compensation transistor T3 and the semiconductor 181a of the first reset transistor T4 can be located on the same layer between the third insulating layer 140 and the fourth insulating layer 150.

[0171] As Figure 12 shown, the sources 181c and the drains 181d of the respective transistors 181 (for example, the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T4, the second control transistor T5, the first control transistor T6, the second reset transistor T7, and the bias adjustment transistor T8) in the pixel circuit 180 can all be located on the same layer. For example, the sources 181c and the drains 181d of the respective transistors 181 in the pixel circuit 180 can all be located between the fourth insulating layer 150 and the fifth insulating layer 160.

[0172] Optionally, vias can be formed on the second electrode plate 182b of the storage capacitor 182, so that the second ends of the first reset transistor T4 and the threshold compensation transistor T3 can be electrically connected to the first electrode plate 182a of the storage capacitor 182 via the vias on the second electrode plate 182b.

[0173] Figure 13 is a schematic structural diagram of a pixel circuit 180 provided by another embodiment of the present application.Figure 14 It is a partial structural schematic diagram of a shielding structure BS provided by an embodiment of the present application. Figure 15 It is a partial structural schematic diagram of a display panel 10 provided by another embodiment of the present application. Figure 16 It is a partial enlarged structural schematic diagram of a display panel 10 provided by an embodiment of the present application. Figure 13 The dashed box at the junction of the film layers can indicate the connection position between the film layers.

[0174] Optionally, Figure 15 and Figure 16 the area within the dashed box in Figure 15 and Figure 16 can indicate the layout position of the second end of part of the driving transistor T1 or the layout position of the first end of part of the first control transistor T6. Exemplarily, Figure 15 and Figure 16 the area within the dashed box in

[0175] such as Figures 13 to 16 shown, in some optional embodiments, the substrate 100 further includes a shielding structure BS disposed between the first electrode 310 and the pixel circuit 180.

[0176] Optionally, the shielding structure BS can be disposed between the pixel circuit 180 and the first electrode 310 in at least one of the first circuit column E1, the second circuit column E2, and the third circuit column E3.

[0177] In some embodiments of the present application, since in the same first device column L1, the connection portions 312 of the first type of devices 301 are all connected to one side of the main body portion 311 in the second direction Y, and the connection portions 312 of the second type of devices 302 are all connected to the other side of the main body portion 311 in the second direction Y. Therefore, in two adjacent pixel circuits 180 in the first direction X (for example, in two adjacent pixel circuits 180 in the first direction X in the first circuit column E1, the second circuit column E2, or the third circuit column E3), the overlapping area between one pixel circuit 180 and the first electrode 310 can be different from the overlapping area between the other pixel circuit 180 and the first electrode 310 (for example, in two adjacent first device rows R1, the overlapping area between the positive projection of the first electrode 310 on the substrate 110 and the second end of the corresponding driving transistor T1 on the substrate 110 in one first device row R1 is greater than the overlapping area between the positive projection of the first electrode 310 on the substrate 110 and the second end of the corresponding driving transistor T1 on the substrate 110 in the other first device row R1), making the interference effects of the first electrode 310 on two adjacent pixel circuits 180 in the first direction X different, thus easily causing a difference in the light-emitting effects between two light-emitting devices 300 with the same light-emitting color that are electrically connected to adjacent pixel circuits 180 in the first direction X, and further easily resulting in uneven display of the display panel 10.

[0178] Therefore, by providing a shielding structure BS between the first electrode 310 and the pixel circuit 180, the interference of the first electrode 310 on the pixel circuit 180 can be preferably restricted, such that two adjacent pixel circuits 180 in the first direction X are not easily affected by the signal interference of the first electrode 310 and have good working stability, so that the light-emitting effects between two light-emitting devices 300 with the same light-emitting color that are electrically connected to adjacent pixel circuits 180 in the first direction X can be the same or approximate, which is beneficial to improving the display uniformity of the display panel 10.

[0179] As an example, when the light-emitting color of the third type of devices 303 is green, compared with the first type of devices 301 and the second type of devices 302, since the third type of devices 303 are more easily affected by the fluctuation of the working stability of the pixel circuit 180, when the position arrangement of the shielding structure BS is limited, the shielding structure BS can be preferably provided between the pixel circuit 180 electrically connected to the third type of devices 303 and the first electrode 310 of the third type of devices 303, that is, the shielding structure BS can be preferably provided between the pixel circuit 180 in the third circuit column E3 and the first electrode 310 of the third type of devices 303, thereby being able to preferably improve the working stability of the second device column L2, and further being beneficial to improving the display uniformity of the third type of devices 303 in the first direction X of the display panel 10.

[0180] In some embodiments of the present application, the shielding structure BS may be arranged without completely covering the pixel circuit 180, that is, the orthographic projection of a part of the pixel circuit 180 on the substrate 110 may be located outside the orthographic projection of the shielding structure BS on the substrate 110, so as to facilitate the electrical connection between various device structures in the display panel 10 and the pixel circuit 180.

[0181] Exemplarily, the shielding structure BS may be arranged only above the positions in the pixel circuit 180 that are greatly affected by the signal interference in the first electrode 310.

[0182] In some alternative embodiments, the orthographic projection of the shielding structure BS on the substrate 110 and the orthographic projection of the first control transistor T6 on the substrate 110 at least partially overlap, and / or the orthographic projection of the shielding structure BS on the substrate 110 and the orthographic projection of the driving transistor T1 on the substrate 110 at least partially overlap.

[0183] Optionally, when the second end of the driving transistor T1 is electrically connected to the first end of the first control transistor T6, and the second end of the first control transistor T6 is electrically connected to the first electrode 310, the orthographic projection of the shielding structure BS on the substrate 110 may at least partially overlap with the orthographic projection of the first end of the first control transistor T6 on the substrate 110, and / or the orthographic projection of the shielding structure BS on the substrate 110 may at least partially overlap with the orthographic projection of the second end of the driving transistor T1 on the substrate 110.

[0184] Exemplarily, the orthographic projection of the shielding structure BS on the substrate 110 may at least partially overlap with the orthographic projection of the source electrode 181c of the first control transistor T6 on the substrate 110, and / or the orthographic projection of the shielding structure BS on the substrate 110 may at least partially overlap with the orthographic projection of the drain electrode 181d of the driving transistor T1 on the substrate 110.

[0185] Optionally, the orthographic projection of the shielding structure BS on the substrate 110 may at least partially overlap with the orthographic projection of the first control transistor T6 in at least one of the first circuit column E1, the second circuit column E2, and the third circuit column E3 on the substrate 110, and / or the orthographic projection of the shielding structure BS on the substrate 110 may at least partially overlap with the orthographic projection of the driving transistor T1 in at least one of the first circuit column E1, the second circuit column E2, and the third circuit column E3 on the substrate 110.

[0186] Optionally, in two adjacent first device rows R1, the overlapping area of the positive projection of the first electrode 310 in one of the first device rows R1 on the substrate 110 and the positive projection of the second end of the corresponding driving transistor T1 on the substrate 110 is greater than that of the other first device row R1. The positive projection of the shielding structure BS on the substrate 110 may at least partially overlap with the positive projection of the second end of the driving transistor T1 on the substrate 110.

[0187] In these optional embodiments, since the first control transistor T6 and the driving transistor T1 in the pixel circuit 180 are more susceptible to signal interference in the first electrode 310, by disposing the shielding structure BS between the first control transistor T6 and the first electrode 310, and disposing the shielding structure BS between the driving transistor T1 and the first electrode 310, the limiting effect of the shielding structure BS on signal interference can be better improved, which is beneficial to improving the display uniformity of the display panel 10.

[0188] In some optional embodiments, the display panel 10 includes a DC signal terminal, and the shielding structure BS is electrically connected to the DC signal terminal, so that the shielding structure BS can have a relatively stable potential, which is beneficial to improving the limiting effect of the shielding structure BS on signal interference.

[0189] Exemplarily, the DC signal terminal includes a power supply voltage signal terminal. The first power supply voltage signal line ELVDD can be electrically connected to the power supply voltage signal terminal, and the shielding structure BS can be electrically connected to the DC signal terminal through the first power supply voltage signal line ELVDD.

[0190] Optionally, in the circuit repeating unit EG, a single shielding structure BS can be correspondingly disposed for the first circuit column E1 and the third circuit column E3 adjacent in the second direction Y, that is, the single shielding structure BS is disposed on the side away from the substrate 110 of the first circuit column E1 and the third circuit column E3 adjacent in the second direction Y, so that the single shielding structure BS can be used to limit the interference of the signal in the first electrode 310 to the first circuit column E1 and the third circuit column E3 at the same time.

[0191] Similarly, in the circuit repeating unit EG, a single shielding structure BS can be correspondingly disposed for the second circuit column E2 and the third circuit column E3 adjacent in the second direction Y, that is, the single shielding structure BS is disposed on the side away from the substrate 110 of the second circuit column E2 and the third circuit column E3 adjacent in the second direction Y, so that the single shielding structure BS can be used to limit the interference of the signal in the first electrode 310 to the second circuit column E2 and the third circuit column E3 at the same time.

[0192] Optionally, the shielding structure BS can be arranged in the substrate 100 in various ways. Exemplarily, the shielding structure BS can be arranged between the fifth insulating layer 160 and the sixth insulating layer 170.

[0193] In some alternative embodiments, the substrate 100 further includes a conductive structure ES arranged between the first power supply voltage signal line ELVDD and the pixel circuit 180. The first power supply voltage signal line ELVDD can be electrically connected to the pixel circuit 180 through the conductive structure ES, and at least part of the conductive structure ES is reused as the shielding structure BS.

[0194] Exemplarily, the conductive structure ES can be arranged between the fifth insulating layer 160 and the sixth insulating layer 170. The first power supply voltage signal line ELVDD can be electrically connected to the second control transistor T5 and the second electrode plate 182b of the storage capacitor 182 in the pixel circuit 180 through the conductive structure ES.

[0195] Optionally, the conductive structure ES can include an integrally formed conductive part ES1 and a shielding part ES2. The conductive part ES1 can be electrically connected to the second control transistor T5 and the second electrode plate 182b of the storage capacitor 182 in the pixel circuit 180. The positive projection of the virtual symmetry axis DL on the substrate 110 can pass through the positive projection of the conductive part ES1 on the substrate 110, and the shielding part ES2 can be arranged on both sides of the conductive part ES1 in the second direction Y.

[0196] Optionally, the shielding part ES2 can be arranged between the first electrode 310 and the pixel circuit 180. Exemplarily, the positive projection of the shielding part ES2 on the substrate 110 and the positive projection of the first control transistor T6 on the substrate 110 overlap at least partially, and / or the positive projection of the shielding part ES2 on the substrate 110 and the positive projection of the driving transistor T1 on the substrate 110 overlap at least partially.

[0197] In these alternative embodiments, by reusing at least part of the conductive structure ES for electrically connecting the first power supply voltage signal line ELVDD and the pixel circuit 180 as the shielding structure BS, it is convenient to realize the electrical connection between the shielding structure BS and the DC signal terminal, and at the same time, it is beneficial to improve the manufacturing efficiency of the display panel 10. And by setting at least part of the conductive structure ES to be reused as the shielding structure BS, it is also unnecessary to add a film layer for serving as the shielding structure BS in the display panel 10, which is beneficial to reducing the thickness of the display panel 10.

[0198] Embodiments of the second aspect of the present application provide a display device, which includes the display panel 10 of any of the above embodiments. Since the display device provided by the embodiments of the second aspect of the present application includes the display panel 10 of any of the embodiments of the first aspect above. Therefore, the display device provided by the embodiments of the second aspect of the present application has the beneficial effects of the display panel 10 of any of the embodiments of the first aspect above, which will not be elaborated here.

[0199] The display devices in the embodiments of the present application include, but are not limited to, devices with display functions such as mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control devices, smart landline phones, consoles, etc.

[0200] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to only the specific embodiments. Obviously, according to the above description, many modifications and variations can be made. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, Comprising: Substrate; A light-emitting device disposed on one side of the substrate. In a direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode stacked in sequence. The first electrode includes a main body portion and a connecting portion connected to the main body portion and protruding relative to the main body portion. Wherein, the light-emitting device includes a plurality of first-type devices and a plurality of second-type devices. The first-type devices and the second-type devices are alternately arranged in a first direction to form a first device column, and the first-type devices and the second-type devices are alternately arranged in a second direction to form a first device row. The light-emitting color of the first-type devices is different from the light-emitting color of the second-type devices. The first direction intersects the second direction. In the same first device column, the connecting portions of the first-type devices are all connected to one side of the main body portion in the second direction, and the connecting portions of the second-type devices are all connected to the other side of the main body portion in the second direction. In the same first device row, the connecting portions of each of the first electrodes are all located on the same side of the main body portion in the second direction.

2. The display panel according to claim 1, wherein The substrate includes a substrate and a plurality of pixel circuits disposed on one side of the substrate. At least two of the pixel circuits are arranged in a first direction to form a circuit column. The display panel further includes a data signal line extending in the first direction. Each of the pixel circuits in the same circuit column is electrically connected to the same data signal line. The circuit column includes a first circuit column and a second circuit column. The first circuit column and the second circuit column are alternately arranged in the second direction. The connecting portions of each of the first-type devices in the first device column are respectively electrically connected to each of the pixel circuits in the same first circuit column, and / or the connecting portions of each of the second-type devices in the first device column are respectively electrically connected to each of the pixel circuits in the same second circuit column.

3. The display panel according to claim 2, characterized in that, In two adjacent first device columns, the connecting portions of each of the first-type devices are respectively electrically connected to each of the pixel circuits in the same first circuit column, or the connecting portions of each of the second-type devices are respectively electrically connected to each of the pixel circuits in the same second circuit column.

4. The display panel according to claim 2, wherein The pixel circuit includes a first control transistor electrically connected to the connecting portion. The first control transistor is at least partially located on one side of the main body portion of the first-type device and / or the second-type device in the second direction.

5. The display panel according to claim 2, wherein The light-emitting device further includes a plurality of third-type devices whose light-emitting colors are different from both the light-emitting color of the first-type devices and the light-emitting color of the second-type devices. The plurality of third-type devices are arranged in the first direction to form a second device column. The first device column and the second device column are alternately arranged in the second direction. The circuit column further includes a third circuit column. The first circuit column, the second circuit column, and the third circuit column are alternately arranged in the second direction, and at least one column of the third circuit column is provided between the adjacent first circuit column and the second circuit column. The connection parts of the third type of devices in each of the second device columns are respectively electrically connected to the pixel circuits in the same third circuit column.

6. The display panel according to claim 5, wherein In two adjacent first device columns, the positive projection of the first electrode of one of the first device columns on the substrate overlaps with the positive projection of the first circuit column on the substrate and also overlaps with the positive projection of the third circuit column on the substrate. The positive projection of the first electrode of the other first device column on the substrate overlaps with the positive projection of the second circuit column on the substrate and also overlaps with the positive projection of the third circuit column on the substrate. And / or, in two adjacent second device columns, the positive projection of the first electrode of one of the second device columns on the substrate overlaps with the positive projection of the first circuit column on the substrate and also overlaps with the positive projection of the third circuit column on the substrate. The positive projection of the first electrode of the other second device column on the substrate overlaps with the positive projection of the second circuit column on the substrate and also overlaps with the positive projection of the third circuit column on the substrate.

7. The display panel according to claim 5, characterized in that, A plurality of the third type of devices are arranged along the second direction to form a second device row, and the first device row and the second device row are alternately arranged along the first direction. The connection part of the third type of device is connected to one side of the main body part in the first direction.

8. The display panel according to claim 7, wherein In the same second device column, the connection parts of the first electrodes are all located on the same side of the main body part in the first direction. And / or, in the same second device row, the connection parts of the first electrodes are all located on the same side of the main body part in the first direction.

9. The display panel according to claim 8, wherein The connection part of the third type of device is located on one side of the connection part of the first type of device in the first direction. Or the connection part of the third type of device is located on one side of the connection part of the second type of device in the first direction.

10. The display panel according to claim 9, wherein The substrate further includes a connection structure disposed between the light-emitting device and the pixel circuit. The connection structure includes a first connection structure, a second connection structure, and a third connection structure. The connection part of the first type of device is electrically connected to the pixel circuit through the first connection structure, the connection part of the second type of device is electrically connected to the pixel circuit through the second connection structure, and the connection part of the third type of device is electrically connected to the pixel circuit through the third connection structure. One end of the first connection structure away from the connection part of the first type of device and one end of the third connection structure away from the connection part of the third type of device are adjacent and spaced apart in the second direction. And / or, one end of the second connection structure away from the connection part of the second type of device and one end of the third connection structure away from the connection part of the third type of device are adjacent and spaced apart in the second direction.

11. The display panel according to claim 5, wherein, A virtual symmetry axis extending along the first direction extends through the first electrode of the first device column. The adjacent first circuit column and the third circuit column are symmetrically arranged with respect to the virtual symmetry axis extending along the first direction, and / or, the adjacent second circuit column and the third circuit column are symmetrically arranged with respect to the virtual symmetry axis extending along the first direction, and / or, the adjacent data signal lines are symmetrically arranged with respect to the virtual symmetry axis extending along the first direction.

12. The display panel according to claim 11, wherein The pixel circuit includes a first control transistor electrically connected to the connection portion, a driving transistor electrically connected to the first control transistor, and a second control transistor electrically connected to an end of the driving transistor away from the first control transistor. The second control transistor is located on a side of the first control transistor close to the virtual symmetry axis. The display panel further includes a first power supply voltage signal line, and an end of the second control transistor away from the driving transistor is electrically connected to the first power supply voltage signal line. A positive projection of the first power supply voltage signal line on the substrate is spaced apart from a positive projection of the first control transistor on the substrate, and a part of the positive projection of the first power supply voltage signal line on the substrate is located between the positive projection of the first control transistor on the substrate and the positive projection of the virtual symmetry axis on the substrate.

13. The display panel according to claim 12, wherein, The first power supply voltage signal line extends along the first direction, and a plurality of the first power supply voltage signal lines are arranged at intervals along the second direction. A positive projection of the first power supply voltage signal line on the substrate at least partially overlaps with a positive projection of the first electrode of the third type of device on the substrate. A relief opening is provided on a side of the first power supply voltage signal line away from the substrate, and the connection portion of the first electrode is electrically connected to the first control transistor through the relief opening.

14. The display panel according to claim 13, wherein A single relief opening is located on a side of the first control transistors of at least two adjacent pixel circuits in the second direction away from the substrate.

15. The display panel according to claim 12, characterized in that, The pixel circuit further includes a data writing transistor electrically connected to an end of the second control transistor close to the driving transistor and an end of the driving transistor away from the first control transistor. An end of the data writing transistor away from the driving transistor is electrically connected to the data signal line. The data writing transistor is located on a side of the first control transistor close to the virtual symmetry axis. A positive projection of the data signal line on the substrate is spaced apart from a positive projection of the first control transistor on the substrate, and a part of the positive projection of the data signal line on the substrate is located between the positive projection of the first control transistor on the substrate and the positive projection of the virtual symmetry axis on the substrate.

16. The display panel according to any one of claims 2 to 15, characterized in that, The substrate further includes a shielding structure provided between the first electrode and the pixel circuit.

17. The display panel according to claim 16, wherein The display panel includes a DC signal terminal, the shielding structure is electrically connected to the DC signal terminal, the DC signal terminal includes a power supply voltage signal terminal, the display panel further includes a first power supply voltage signal line electrically connected to the power supply voltage signal terminal, the substrate further includes a conductive structure disposed between the first power supply voltage signal line and the pixel circuit, the first power supply voltage signal line is electrically connected to the pixel circuit through the conductive structure, and at least part of the conductive structure is reused as the shielding structure.

18. The display panel according to claim 16, wherein The pixel circuit includes a first control transistor electrically connected to the connection portion and a driving transistor electrically connected to the first control transistor. The positive projection of the shielding structure on the substrate at least partially overlaps with the positive projection of the first control transistor on the substrate. And / or, the positive projection of the shielding structure on the substrate at least partially overlaps with the positive projection of the driving transistor on the substrate. And / or, the second end of the driving transistor is electrically connected to the first end of the first control transistor, the second end of the first control transistor is electrically connected to the first electrode, and the positive projection of the shielding structure on the substrate at least partially overlaps with the positive projection of the second end of the driving transistor on the substrate.

19. The display panel according to any one of claims 1 to 15, characterized in that, The substrate includes a substrate, a plurality of pixel circuits disposed on one side of the substrate, and a shielding structure disposed between the first electrode and the pixel circuit, and the pixel circuit includes a driving transistor. In two adjacent first device rows, the overlapping area of the positive projection of the first electrode in one of the first device rows on the substrate and the positive projection of the corresponding second end of the driving transistor on the substrate is greater than the overlapping area of the positive projection of the first electrode in the other first device row on the substrate and the positive projection of the corresponding second end of the driving transistor on the substrate. The positive projection of the shielding structure on the substrate at least partially overlaps with the positive projection of the second end of the driving transistor on the substrate.

20. A display device, characterized in that, A display panel includes any one of claims 1 to 19.

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