Display device and manufacturing method thereof

Abstract

The invention relates to a display device and a manufacturing method thereof. Disclosed is a display device in which a power connection line contact is provided on a structure provided in each sub-pixel and is thus electrically connected to a cathode electrode layer such that power is supplied to each of a plurality of sub-pixels through the power connection line electrically connected to a power line.

Description

[0001] This application is a divisional application of the invention patent application with the application number 202311769588.2, the application date of December 21, 2023, and the invention title of "Display Device and Manufacturing Method Thereof". Technical Field

[0002] The present disclosure relates to a display device and a manufacturing method thereof. More specifically, the present disclosure relates to a display device having a structure for applying power to a cathode electrode and a manufacturing method thereof. Background Art

[0003] Display devices are implemented in a very diverse form. For example, televisions, monitors, smartphones, tablet personal computers (PCs), laptop computers, and wearable devices.

[0004] An organic light-emitting display device (OLED), as an example of a display device, is a self-luminous display device, and is not only advantageous in terms of power consumption due to its low operating voltage, but also has excellent advantages in terms of color rendering, response speed, viewing angle, and contrast.

[0005] The organic light-emitting display device may include a plurality of pixels located at a pixel region defined by intersecting gate lines and data lines.

[0006] In this case, power may be applied to each of the plurality of pixels to drive each of the plurality of pixels. Summary of the Invention

[0007] The display device may include a power supply for applying power to a plurality of pixels and a power line for supplying power from the power supply thereto.

[0008] The power line may be a high-potential voltage (VDD) line or a low-potential voltage (VSS) line.

[0009] For example, when the display device is embodied as an organic light-emitting display device, the low-potential voltage line may apply a low-potential voltage to the cathode electrode constituting the organic light-emitting diode.

[0010] Applying a low-potential voltage to the cathode electrode may allow each pixel including the organic light-emitting diode connected to the cathode electrode to emit light.

[0011] In order to cause the plurality of pixels provided in the display area to emit light, a low-potential voltage should be applied to the cathode electrodes connected to the plurality of pixels. For this reason, cathode electrodes may be formed throughout the display area.

[0012] For example, the cathode electrode may be formed in the form of a surface electrode covering the entire surface of the display area, and the cathode electrode may be formed as a common electrode for the plurality of pixels.

[0013] However, when forming the cathode electrode in the form of a surface electrode covering the entire surface of the display region, a parasitic capacitance may be generated between the cathode electrode and the data line that are set to overlap each other.

[0014] When a parasitic capacitance is generated between the cathode electrode and the data line, a decrease in the electrical transmission rate (RC (resistance - capacitance) delay) occurs. Accordingly, high - speed operation of the display device may not be achieved.

[0015] Accordingly, in order to reduce the decrease in the electrical transmission rate of the display device, the inventors of the present disclosure conducted several experiments.

[0016] Based on these several experiments, the inventors of the present disclosure invented a display device having a structure capable of stably supplying power to the cathode electrode layer, while reducing the generation of parasitic capacitance between the cathode electrode layer and the data line, and also invented a method of manufacturing the display device.

[0017] The technical object according to an embodiment of the present disclosure is to provide a display device having a structure capable of stably supplying power to a plurality of sub - pixels and a method of manufacturing the display device.

[0018] In addition, the technical object according to an embodiment of the present disclosure is to provide a display device capable of improving the light extraction efficiency in the organic light - emitting layer included in each of the plurality of sub - pixels and a method of manufacturing the display device.

[0019] In addition, the technical object according to an embodiment of the present disclosure is to provide a display device capable of reducing the generation of lateral leakage current in the organic light - emitting layer and a method of manufacturing the display device.

[0020] In addition, the technical object according to an embodiment of the present disclosure is to provide a display device capable of reducing the generation of parasitic capacitance between the cathode electrode layer and the data line and a method of manufacturing the display device.

[0021] In addition, the technical object according to an embodiment of the present disclosure is to provide a display device capable of reducing the generation of parasitic capacitance between the power connection line and the data line and a method of manufacturing the display device.

[0022] In addition, the technical object according to an embodiment of the present disclosure is to provide a display device capable of reducing damage to the organic light - emitting layer that may occur during the formation process of the organic light - emitting layer included in each of the plurality of sub - pixels and a method of manufacturing the display device.

[0023] The objects according to the present disclosure are not limited to those mentioned above. Other objects and advantages according to the present disclosure that are not mentioned can be understood based on the following description and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the objects and advantages according to the present disclosure can be achieved by the means shown in the claims and their combinations.

[0024] In one embodiment, a display device includes: a plurality of sub-pixels; a power line configured to provide a voltage; a plurality of structures, each structure being respectively disposed in a corresponding one of the plurality of sub-pixels; and a power connection line overlapping with the plurality of structures, the power connection line being electrically connected to the plurality of sub-pixels and the power line and supplying the voltage from the power line to the plurality of sub-pixels, wherein each of the plurality of sub-pixels includes an organic light-emitting layer, a cathode electrode layer located on the organic light-emitting layer, and a passivation layer located on the cathode electrode layer, the passivation layer including an opening exposing a portion of the cathode electrode layer located on the corresponding structure among the plurality of structures, such that the portion of the cathode electrode layer is in contact with the power connection line, and wherein the organic light-emitting layers of adjacent sub-pixels among the plurality of sub-pixels are disconnected from each other, the cathode electrode layers of adjacent sub-pixels are disconnected from each other, and the passivation layers of adjacent sub-pixels are disconnected from each other.

[0025] In one embodiment, a display device includes: a substrate; a plurality of sub-pixels located on the substrate; a bank layer located on the substrate; a structure located on the bank layer; an organic light-emitting layer, a cathode electrode layer located on the organic light-emitting layer, and a passivation layer located on the cathode electrode layer in a sub-pixel among the plurality of sub-pixels, such that a portion of the organic light-emitting layer, a portion of the cathode electrode layer, and a portion of the passivation layer overlap with the bank layer and the structure, the passivation layer including a portion exposing the cathode electrode layer located on the structure; and a power connection line overlapping with the structure, such that the structure is located between the power connection line and the substrate, wherein the portion of the cathode electrode layer is in contact with the power connection line.

[0026] In one embodiment, a method for manufacturing a display device includes: forming a plurality of data lines on a substrate; forming a plurality of anode electrode layers, each anode electrode layer being formed in a corresponding one of a plurality of sub-pixels; forming a bank layer on the plurality of anode electrode layers, the bank layer including a plurality of openings, each opening exposing a portion of the corresponding anode electrode layer among the plurality of anode electrode layers; forming a plurality of structures on the bank layer, each structure being formed in a corresponding one of the plurality of sub-pixels; forming a first protective layer and a first photoresist film on the bank layer and exposing a first opening corresponding to a first sub-pixel among the plurality of sub-pixels in the plurality of openings; sequentially forming a first organic light-emitting layer configured to emit light of a first color in the first opening, a first cathode electrode layer on the first organic light-emitting layer, and a first passivation layer on the first cathode electrode layer, and removing the first protective layer and the first photoresist film; forming a second protective layer and a second photoresist film on the bank layer and exposing a second opening corresponding to a second sub-pixel among the plurality of sub-pixels in the plurality of openings; sequentially forming a second organic light-emitting layer configured to emit light of a second color in the second opening, a second cathode electrode layer on the second organic light-emitting layer, and a second passivation layer on the second cathode electrode layer, and removing the second protective layer and the second photoresist film; forming a third protective layer and a third photoresist film on the bank layer and exposing a third opening corresponding to a third sub-pixel among the plurality of sub-pixels in the plurality of openings; sequentially forming a third organic light-emitting layer configured to emit light of a third color in the third opening, a third cathode electrode layer on the third organic light-emitting layer, and a third passivation layer on the third cathode electrode layer, and removing the third protective layer and the third photoresist film; forming a first cover layer covering the first passivation layer, the second passivation layer, and the third passivation layer; etching partial regions of each of the first cover layer, the first passivation layer, the second passivation layer, and the third passivation layer to expose partial regions of each of the first cathode electrode layer, the second cathode electrode layer, and the third cathode electrode layer that overlap with the structures; and forming a power connection line on the first cover layer, the power connection line being connected to the exposed partial regions of the first cathode electrode layer, the exposed partial regions of the second cathode electrode layer, and the exposed partial regions of the third cathode electrode layer.

[0027] In one embodiment, a display device includes: a substrate; a bank portion on the substrate, the bank portion including an opening; a structure on the bank portion that does not overlap with the opening; a power connection line including a portion that overlaps with the structure, the power connection line being configured to provide a voltage; an anode electrode layer in the opening; an organic light-emitting layer including a first portion and a second portion, the first portion of the organic light-emitting layer being on the anode electrode layer in the opening, and the second portion of the organic light-emitting layer being on the structure; a cathode electrode layer including a first portion and a second portion, the first portion of the cathode electrode layer being on the first portion of the organic light-emitting layer in the opening, the second portion of the cathode electrode layer being on the second portion of the organic light-emitting layer and the structure, the second portion of the cathode electrode layer being in contact with the portion of the power connection line that overlaps with the structure and receiving the voltage from the power connection line; and a passivation layer including a first portion and a second portion, wherein the first portion of the passivation layer is on the first portion of the cathode electrode layer in the opening, the second portion of the passivation layer is on the second portion of the cathode electrode layer and the structure, and not between the second portion of the cathode electrode layer and the portion of the power connection line that is in contact with the second portion of the cathode electrode layer.

[0028] According to an embodiment of the present disclosure, the cathode electrode layer and the power connection line are electrically connected to each other at a cathode contact portion on the structure provided in each sub-pixel. Thus, power can be stably applied to each of the plurality of sub-pixels through the power connection line electrically connected to the power line.

[0029] In addition, according to an embodiment of the present disclosure, the adjacent organic light-emitting layers, adjacent cathode electrode layers, and adjacent passivation layers of adjacent sub-pixels are respectively disconnected from each other. Thus, the light extraction efficiency of the organic light-emitting layer can be improved due to an out-coupling phenomenon that allows light from the organic light-emitting layer to escape to the outside from the disconnected ends. Thus, a low-power display device can be implemented.

[0030] In addition, according to an embodiment of the present disclosure, the adjacent organic light-emitting layers, adjacent cathode electrode layers, and adjacent passivation layers of adjacent sub-pixels are disconnected from each other. Thus, the occurrence of lateral leakage current in the organic light-emitting layer that may occur when the organic light-emitting layers are integrally and continuously extended and connected to each other can be reduced.

[0031] In addition, according to an embodiment of the present disclosure, the cathode electrode layer and the data line are arranged not to overlap with each other in the vertical direction, thereby reducing the generation of parasitic capacitance between the cathode electrode layer and the data line. Thus, the occurrence of a decrease in the electrical transmission rate (RC delay) can be reduced.

[0032] In addition, according to an embodiment of the present disclosure, a bank layer and a capping layer are disposed between a power connection line and a data line, thereby increasing the distance between the power connection line and the data line, thereby reducing the generation of parasitic capacitance between the power connection line and the data line, and thus reducing the occurrence of a decrease in the electrical transmission rate (RC delay).

[0033] In addition, according to an embodiment of the present disclosure, an organic light-emitting layer, a cathode electrode layer, and a passivation layer that render a first color may be formed, and then an organic light-emitting layer that renders a second color may be additionally formed using the same process as for the organic light-emitting layer that renders the first color, and then an organic light-emitting layer that renders a third color may be additionally formed using the same process as for the organic light-emitting layer that renders the first color. Therefore, the passivation layer disposed on the organic light-emitting layer may serve as a protective film, which reduces the deterioration that may occur in the organic light-emitting layer during the continuous process of forming the organic light-emitting layers corresponding to the respective sub-pixels. Thus, damage to the organic light-emitting layer can be reduced.

[0034] The effects of the present disclosure are not limited to the effects mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the following description.

[0035] In addition to the above effects, while describing the specific details for implementing the present disclosure, the specific effects of the present disclosure are also described together. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1A and Figure 1B are schematic plan views of a display device according to an embodiment of the present disclosure, respectively.

[0037] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0038] Figure 3A is according to an embodiment of the present disclosure Figure 1A an enlarged plan view of a plurality of sub-pixels of the display device shown in.

[0039] Figure 3B is according to another embodiment of the present disclosure Figure 1A an enlarged plan view of a plurality of sub-pixels of the display device shown in.

[0040] Figure 3C is according to still another embodiment of the present disclosure Figure 1B an enlarged plan view of a plurality of sub-pixels of the display device shown in.

[0041] Figure 4 is according to an embodiment of the present disclosure Figure 3A and Figure 3B a cross-sectional view of a plurality of sub-pixels of the display device shown in.

[0042] Figure 5 is of another embodiment according to the present disclosure Figure 3C A cross-sectional view of a plurality of sub-pixels of the display device shown in

[0043] Figures 6A to 6K is a plan view of a plurality of sub-pixels during the process of manufacturing a display device according to an embodiment of the present disclosure

[0044] Figures 7A to 7K is respectively corresponding to according to an embodiment of the present disclosure Figures 6A to 6K A cross-sectional view of Detailed description of specific embodiments

[0045] Referring to the embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for realizing these advantages and features will become apparent. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. Therefore, these embodiments are described only to make the present disclosure complete and to fully convey the scope of the present disclosure to those skilled in the art to which the present disclosure pertains. The present disclosure is limited only by the scope of the claims

[0046] For simplicity and clarity of illustration, the elements in the figures are not necessarily drawn to scale. The same reference numerals in different figures denote the same or similar elements and thus perform similar functions. In addition, for simplicity of description, the description and details of well-known steps and elements are omitted. Furthermore, many specific details are set forth in the following detailed description of the present disclosure in order to provide a thorough understanding of the present disclosure. However, it should be understood that the present disclosure can be practiced without these specific details. In other cases, well-known methods, processes, components, and circuits are not described in detail so as not to unnecessarily obscure various aspects of the present disclosure. Examples of the embodiments are further illustrated and described below. It should be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the present disclosure as defined by the appended claims

[0047] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the accompanying drawings for illustrating the embodiments of the present disclosure are only illustrative, and the present disclosure is not limited thereto. The same elements are denoted by the same reference numerals herein. In addition, for simplicity of description, the description and details of well-known steps and elements are omitted. Furthermore, many specific details are set forth in the following detailed description of the present disclosure in order to provide a thorough understanding of the present invention. However, it should be understood that the present disclosure can be practiced without these specific details. In other cases, well-known methods, processes, components, and circuits are not described in detail so as not to unnecessarily obscure various aspects of the present disclosure

[0048] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "comprises", "comprising", "has" and "having", when used in this specification, specify the presence of stated features, integers, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components and / or portions thereof. As used herein, the phrase "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of..." can modify the entire list of elements when modifying the list of elements, and can also modify individual elements in the list. When interpreting numerical values, there may be errors or tolerances, even if not explicitly described.

[0049] In addition, it should also be understood that when a first element or layer is referred to as being "on" a second element or layer, the first element may be directly disposed on the second element, or may be indirectly disposed on the second element, in which case a third element or layer is disposed between the first and second elements or layers. It should be understood that when an element or layer is referred to as "connected to" or "coupled to" another element or layer, the element or layer may be directly located on the other element or layer, directly connected or directly coupled thereto, or there may be one or more intervening elements or layers. In addition, it should also be understood that when an element or layer is referred to as being "between" two elements or layers, only the element or layer may be between the two elements or layers, or there may also be one or more intervening elements or layers.

[0050] In addition, as used herein, when a layer, film, region, or plate, etc. is disposed "on" or "above" another layer, film, region, or plate, etc., the former may directly contact the latter or another layer, film, region, or plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, or plate, etc. is directly disposed "on" or "above" another layer, film, region, or plate, etc., the former directly contacts the latter and no other layer, film, region, or plate, etc. is disposed between the former and the latter. In addition, as used herein, when a layer, film, region, or plate, etc. is disposed "below" or "beneath" another layer, film, region, or plate, etc., the former may directly contact the latter or another layer, film, region, or plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, or plate, etc. is directly disposed "below" or "beneath" another layer, film, region, or plate, etc., the former directly contacts the latter and no other layer, film, region, or plate, etc. is disposed between the former and the latter.

[0051] In the description of temporal relationships, such as the chronological relationship between two events, such as "after", "then", "before", etc., another event may occur between these two events, unless it is specified as "directly after", "then directly", or "directly before".

[0052] When a particular embodiment can be implemented in different ways, the functions or operations specified in a particular block may occur in a different order than the order specified in the flowchart. For example, depending on the functions or operations involved, two consecutive blocks may actually be executed substantially simultaneously, or the two blocks may be executed in the reverse order.

[0053] It should be understood that although terms such as "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section described hereinafter may be referred to as a second element, component, region, layer, or section without departing from the essence and scope of the present disclosure.

[0054] The features of various embodiments of the present disclosure may be partially or fully combined with each other, and may be technically related or interoperable. The embodiments may be implemented independently of each other, and may be implemented together in a related relationship.

[0055] When interpreting a numerical value, the value is interpreted as including a certain error range, unless there is a separate and clear statement made about it.

[0056] It should be understood that when an element or layer is referred to as "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intermediate elements or layers. In addition, it should also be understood that when an element or layer is referred to as being "between" two elements or layers, it may be only the element or layer that is between the two elements or layers, or there may also be one or more intermediate elements or layers.

[0057] The features of various embodiments of the present disclosure may be partially or fully combined with each other, and may be technically related or interoperable. The embodiments may be implemented independently of each other, and may be implemented together in a related relationship.

[0058] Unless otherwise defined, all terms (including technical terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the principles of the present invention pertain. It will also be understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0059] As used herein, terms such as "embodiment," "example," "aspect," etc. should not be construed as any aspect or design being superior or more advantageous than other aspects or designs.

[0060] In addition, the term "or" means "inclusive or" rather than "exclusive or." That is, unless otherwise stated or clear from the context, the statement "x uses a or b" means any of the natural inclusive arrangements.

[0061] The terms used in the following description are chosen to be general and common in the relevant technical field. However, depending on the development and / or changes in technology, conventions, preferences of those skilled in the art, etc., there may be other terms besides those described. Therefore, the terms used in the following description should not be construed as limiting the technical concept, but should be understood as examples of terms for illustrating embodiments.

[0062] In addition, in specific cases, the terms may be arbitrarily chosen by the applicant, and in such cases, their detailed meanings will be described in the corresponding description section. Therefore, the terms used in the following description should be understood based not only on the names of the terms, but also on their meanings and the content of the entire specific implementation section.

[0063] In the description of signal flow, for example, when a signal is conveyed from node A to node B, this may include the case where the signal is transmitted from node A to node B via another node, unless the phrase "immediately transmitted" or "directly transmitted" is used.

[0064] Hereinafter, a display device according to an embodiment of the present disclosure will be described in detail with reference to FIGS. 1 to Figure 5 FIGS. 26 and 27 are schematic plan views of a display device according to an embodiment of the present disclosure, respectively.

[0065] Figure 1A and Figure 1B FIGS. 26 and 27 are schematic plan views of a display device according to an embodiment of the present disclosure, respectively.

[0066] An example will be described in which the display device 1 as described below is embodied as an organic light-emitting diode display device. However, the present disclosure is not limited thereto.

[0067] The display device 1 may include a display area AA configured to display an image and a non-display area NA surrounding the display area AA. An image is not displayed in the non-display area NA.

[0068] In the display area AA, a plurality of data lines DL extending in a first direction and a plurality of gate lines GL extending in a second direction intersecting the first direction may be provided.

[0069] Each sub-pixel SP1, SP2, or SP3 may be provided in each pixel area, and each pixel area is each of the intersection areas where the data line DL and the gate line GL intersect each other.

[0070] The sub-pixels SP1, SP2, and SP3 may be implemented to emit light of the same color, for example, white (W) light. Alternatively, the sub-pixels SP1, SP2, and SP3 may be implemented to emit light of different colors, for example, red (R), green (G), and blue (B).

[0071] For example, the combination of the colors of the light emitted by the sub-pixels SP1, SP2, and SP3 may be implemented as a combination of red (R), green (G), and blue (B) or a combination of red (R), green (G), blue (B), and white (W).

[0072] One sub-pixel P may be configured as a combination of the plurality of sub-pixels SP1, SP2, and SP3 as described above.

[0073] Hereinafter, an example in which one pixel P is composed of a first sub-pixel SP1 that renders a first color, a second sub-pixel SP2 that renders a second color, and a third sub-pixel SP3 that renders a third color will be described.

[0074] In this case, the first color may be red (R), the second color may be green (G), and the third color may be blue (B). However, the present disclosure is not limited thereto.

[0075] The plurality of sub-pixels SP1, SP2, and SP3 may be arranged in a matrix form composed of a plurality of rows and a plurality of columns.

[0076] As used herein, the first direction may be the column direction and may be defined as the Y-axis direction. The second direction may be the row direction and may be defined as the X-axis direction.

[0077] In the non-display area NA, a plurality of lines and pads for supplying various signals and power to the pixels may be provided.

[0078] The data driver circuit (D-IC) 10 may be provided on one side of the non-display area NA.

[0079] The data driver circuit 10 can apply a data signal to the data line DL and can apply a driving voltage, such as a high-potential voltage VDD or a low-potential voltage VSS, to the pixel P.

[0080] The power line 20 can extend along the edge of the display area AA, except for the side where the data driver circuit 10 is provided in the non-display area NA.

[0081] For example, the gate driver 30 for applying a gate signal to the gate line GL can be provided in each part of the non-display area NA located on the opposite side of the display area AA. The power line 20 capable of applying a voltage to the anode electrode or the cathode electrode in the pixel P can extend along the outer edge of the gate driver 30.

[0082] The power line 20 can be a low-potential voltage line capable of applying a low-potential voltage VSS to the cathode electrode of the pixel P. However, the present disclosure is not limited thereto. A high-potential voltage line capable of applying a high-potential voltage VDD to the thin-film transistor of the pixel can be additionally provided.

[0083] In the display area AA, a plurality of power connection lines 112 respectively electrically connected to the power line 20 and the plurality of sub-pixels SP1, SP2, SP3 can be provided, so that a low-potential voltage can be applied to the plurality of sub-pixels SP1, SP2, SP3.

[0084] Reference Figure 1A , the power connection lines 112 can cover the display area AA. The power connection lines 112 can be arranged in a grid pattern and can extend across a plurality of sub-pixels.

[0085] For example, the power connection lines 112 can extend across a plurality of sub-pixels arranged in the first direction and can extend across a plurality of sub-pixels arranged in the second direction. The power connection lines 112 can be arranged in a grid pattern so as to intersect each other to define line openings 112h respectively corresponding to the light-emitting regions of the respective sub-pixels.

[0086] The outer ends of the power connection lines 112 can be connected to the power line 20 located outside the display area AA. Thus, the power line 20 can apply a voltage to the power connection lines 112.

[0087] Also referring to Figure 1B , the power connection lines 112 can cover the entire surface of the display area AA.

[0088] For example, the power connection lines 112 can be formed in the form of a single integral electrode covering all sub-pixels.

[0089] The outer end of the power connection line 112 can be connected to the power line 20 located outside the display area AA. Thus, the power line 20 can apply a voltage to the power connection line 112.

[0090] In this case, the power connection line 112 can be embodied as a transparent line made of a transparent material. Thus, the light from the light-emitting regions of the plurality of sub-pixels can be emitted therethrough.

[0091] The transparent material may include an indium zinc oxide (IZO)-based oxide or an indium tin oxide (ITO)-based oxide. However, the present disclosure is not limited thereto, and the power connection line 112 can be made of various types of transparent materials.

[0092] In another embodiment, the plurality of power connection lines 112 may extend in a first direction in which the plurality of data lines DL extend.

[0093] The plurality of power connection lines 112 and the plurality of data lines DL may be alternately arranged with each other in a second direction.

[0094] One power connection line 112 may extend across a plurality of sub-pixels in the column direction, and thus may be electrically connected to a portion of the power line 20 disposed adjacent to the lower end of the display area AA.

[0095] Accordingly, a plurality of sub-pixels arranged in the same column direction may be electrically connected to a single power connection line 112, and may receive a low-potential voltage from the power line 20 through the single power connection line 112.

[0096] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0097] Each of the sub-pixels SP1, SP2, and SP3 provided in each of the intersections of the gate line GL and the data line DL intersecting with each other as described above may include a switching thin-film transistor Ts, a driving thin-film transistor Td, a storage capacitor Cst, and a light-emitting diode De.

[0098] The gate electrode of the switching thin-film transistor Ts may be connected to the gate line GL, and its source electrode may be connected to the data line DL.

[0099] The gate electrode of the driving thin-film transistor Td may be connected to the drain electrode of the switching thin-film transistor Ts, and its source electrode may be connected to the high-potential voltage VDD.

[0100] The anode electrode of the light-emitting diode De may be connected to the drain electrode of the driving thin-film transistor Td, and its cathode electrode may be connected to the low-potential voltage VSS.

[0101] One side and the other side of the storage capacitor Cst can be connected to the gate electrode and the drain electrode of the driving thin film transistor Td, respectively.

[0102] The display device 1 including sub-pixels SP1, SP2, and SP3 (each including a structure having such a circuit diagram) can display an image as follows.

[0103] The switching thin film transistor Ts can be turned on based on a gate signal applied through the gate line GL. The data signal applied to the data line DL can be applied to the gate electrode of the driving thin film transistor Td and one electrode of the storage capacitor Cst through the switching thin film transistor Ts.

[0104] The driving thin film transistor Td can be turned on based on the data signal, thereby controlling the current flowing through the light-emitting diode De. Thus, an image can be displayed.

[0105] The light-emitting diode De can emit light based on the current of the high potential voltage (VDD) transmitted through the driving thin film transistor Td.

[0106] Figure 3A and Figure 3B are respectively enlarged plan views of a plurality of sub-pixels of the display device according to an embodiment of the present disclosure. Figure 1A shown in Figure 3C is an enlarged plan view of a plurality of sub-pixels of the display device shown in Figure 1B according to another embodiment of the present disclosure.

[0107] Figure 4 is an enlarged cross-sectional view of a plurality of sub-pixels of the display device according to an embodiment of the present disclosure. Figure 3A and Figure 3B shown in

[0108] Specifically, Figure 3A and Figure 3B each of Figure 1A is an enlarged view of a plurality of sub-pixels corresponding to the area indicated by reference numeral 3 in Figure 3C is an enlarged view of a plurality of sub-pixels corresponding to the area indicated by reference numeral 3 in Figure 1B shown in

[0109] Hereinafter, a sub-pixel will be described by way of example. Without special description, this description can also be applied to other sub-pixels.

[0110] Referring to Figure 3A and Figure 4 , a plurality of data lines DL can be provided on the substrate 100, and an insulating layer 103 can be provided on the plurality of data lines DL. As Figure 4 shown in

[0111] In addition, although not shown in the figures, thin-film transistors including an active layer, a gate electrode, and source and drain electrodes may be provided on the substrate 100.

[0112] A buffer layer may be additionally provided between the substrate 100 and the thin-film transistors.

[0113] In this case, the thin-film transistors may be driving thin-film transistors Td or switching thin-film transistors Ts.

[0114] Each of the data lines DL and the source and drain electrodes may be made of the same material and may be provided in the same layer. However, the present disclosure is not limited thereto.

[0115] The anode electrode layer 130 may be provided on the insulating layer 103.

[0116] The anode electrode layer 130 may be electrically connected to the source and drain electrodes of the thin-film transistors.

[0117] The bank layer 140 may be formed on the anode electrode layer 130.

[0118] The bank layer 140 may serve as a pixel defining layer for each of the plurality of sub-pixels SP1, SP2, and SP3.

[0119] Therefore, the bank layer 140 serving as a pixel defining layer may be provided between adjacent sub-pixels among the sub-pixels SP1, SP2, and SP3, thereby defining the boundaries between adjacent sub-pixels among the sub-pixels SP1, SP2, and SP3 that render different colors, and preventing color mixing of light beams respectively emitted from adjacent sub-pixels among the sub-pixels SP1, SP2, and SP3.

[0120] The bank layer 140 may include openings 1402 that are opened to expose a partial region of the anode electrode layer 130.

[0121] The opening 1402 formed in the first sub-pixel SP1 may define a first light-emitting region OLE1. The opening 1402 formed in the second sub-pixel SP2 may define a second light-emitting region OLE2. In addition, the opening 1402 formed in the third sub-pixel SP3 may define a third light-emitting region OLE3.

[0122] A structure ST that protrudes upward and has a predetermined height may be provided on the bank layer 140.

[0123] The structure ST may be formed to have an island structure and may be formed in a tapered shape, where the width in its left-right direction (e.g., horizontal direction) increases as the structure ST extends from its bottom to its top.

[0124] The structure ST is formed in a conical shape in this way so that even when an organic light-emitting layer, a cathode electrode layer, and a passivation layer, which will be described below, are formed on the structure ST, each of the organic light-emitting layer, the cathode electrode layer, and the passivation layer can continuously extend across each sub-pixel without being disconnected.

[0125] The structure ST may be made of an organic material. The material may not be particularly limited.

[0126] The structure ST may be made of a material different from that of the bank layer 140 and may be formed in a process separate from the process of forming the bank layer 140. However, the present disclosure is not limited thereto.

[0127] For example, the structure ST may be integrally formed with the bank layer 140 and may be made of the same material as that of the conductive layer 140. In this case, the structure ST and the bank layer 140 may be formed in the same patterning process.

[0128] In this case, the bank layer 140 may be formed to include the structure ST through a patterning process using a halftone mask.

[0129] The entire region of the structure ST may be disposed on the bank layer 140. However, the present invention is not limited thereto, and only a partial region of the structure ST may be disposed on the bank layer 140, and the remaining region thereof may be disposed on the same plane as the bank layer 140.

[0130] The structure ST may be disposed in a side portion of each light-emitting region and may be placed in each sub-pixel without overlapping with the side of the light-emitting region. However, the present disclosure is not limited thereto.

[0131] Reference Figure 3B , the structure ST may be formed in a side portion of each light-emitting region, and another structure ST may be formed in the other side portion of each light-emitting region.

[0132] Accordingly, the structure ST may discontinuously extend along the outer region of each light-emitting region. However, the configuration of the structure ST is not particularly limited.

[0133] Alternatively, the structure ST may continuously extend along the outer region of each light-emitting region.

[0134] For example, the structure ST of the first sub-pixel SP1 may continuously extend along the outer region of the first light-emitting region OLE1. The structure ST of the second sub-pixel SP2 may continuously extend along the outer region of the second light-emitting region OLE2. The structure ST of the third sub-pixel SP3 may continuously extend along the outer region of the third light-emitting region OLE3.

[0135] The organic light-emitting layer, the cathode electrode layer, and the passivation layer may be sequentially stacked on the bank layer 140 to cover the structure ST. That is, a first portion of the first organic light-emitting layer 151 is located above the anode electrode layer 130, a first portion of the first cathode electrode layer 161 is located above the first portion of the first organic light-emitting layer 151 and the anode electrode layer, and a first portion of the first passivation layer 171 is located above the first portion of the first cathode electrode layer 161, the first portion of the first organic light-emitting layer 151, and the anode electrode layer.

[0136] Specifically, the first organic light-emitting layer 151 that renders the first color, the first cathode electrode layer 161, and the first passivation layer 171 may be disposed in the first sub-pixel SP1. In the second sub-pixel SP2, the second organic light-emitting layer 152 that renders the second color, the second cathode electrode layer 162, and the second passivation layer 172 may be disposed. In the third sub-pixel SP3, the third organic light-emitting layer 153 that renders the third color, the third cathode electrode layer 163, and the third passivation layer 173 may be disposed.

[0137] In this case, the organic light-emitting layers, the cathode electrode layers, and the passivation layers of adjacent sub-pixels may be disconnected from each other.

[0138] As used herein, the disconnection between two components may mean that the two components are physically separated from each other, and may mean that the two components are not electrically connected to each other.

[0139] However, even when the two components are disconnected from each other, the two components may be indirectly electrically connected to each other through another intermediate medium.

[0140] For example, the first organic light-emitting layer 151 and the second organic light-emitting layer 152 adjacent to each other may be disconnected from each other. The second organic light-emitting layer 152 and the third organic light-emitting layer 153 adjacent to each other may be disconnected from each other. The third organic light-emitting layer 153 and the first organic light-emitting layer 151 adjacent to each other may be disconnected from each other.

[0141] In addition, the first cathode electrode layer 161 and the second cathode electrode layer 162 adjacent to each other may be disconnected from each other. The second cathode electrode layer 162 and the third cathode electrode layer 163 adjacent to each other may be disconnected from each other. The third cathode electrode layer 163 and the first cathode electrode layer 161 adjacent to each other may be disconnected from each other.

[0142] In addition, the first passivation layer 171 and the second passivation layer 172 adjacent to each other may be disconnected from each other. The second passivation layer 172 and the third passivation layer 173 adjacent to each other may be disconnected from each other. The third passivation layer 173 and the first passivation layer 171 adjacent to each other may be disconnected from each other.

[0143] The outermost boundary 1511 of the first organic light-emitting layer 151, the outermost boundary 1611 of the first cathode electrode layer 161, and the outermost boundary 1711 of the first passivation layer 171 may be disposed in the first sub-pixel SP1 formed between adjacent data lines DL.

[0144] Accordingly, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 may not overlap with the data line DL in the vertical direction (e.g., non-overlapping).

[0145] The first cathode electrode layer 161 may include a material having a relatively better step coverage than the material of the first organic light-emitting layer 151, and accordingly, the end of the first cathode electrode layer 161 may be located at a position outside the end of the first organic light-emitting layer 151. That is, the end of the first cathode electrode layer 161 extends beyond the end of the first organic light-emitting layer 151.

[0146] Therefore, the first cathode electrode layer 161 may be formed to cover the entire first organic light-emitting layer 151, such that the outermost boundary 1611 of the first cathode electrode layer 161 may be located at a position outside the outermost boundary 1511 of the first organic light-emitting layer 151. Thus, the outermost boundary 1511 of the first organic light-emitting layer 151 is inset from the outermost boundary 1611 of the first cathode electrode layer 161.

[0147] The first passivation layer 171 may include a material having a relatively better step coverage than the material of the first cathode electrode layer 161, and accordingly, the end of the first passivation layer 171 may be located at a position outside the end of the first cathode electrode layer 161. That is, the end of the first passivation layer 171 extends beyond the end of the first cathode electrode layer 161.

[0148] Therefore, the first passivation layer 171 may be formed to cover the entire first cathode electrode layer 1611, such that the outermost boundary 1711 of the first passivation layer 171 may be located at a position outside the outermost boundary 1611 of the first cathode electrode layer 161. Thus, the outermost boundary 1611 of the first cathode electrode layer 161 is inset from the outermost boundary 1711 of the first passivation layer 171.

[0149] In addition, the outermost boundary 1521 of the second organic light-emitting layer 152, the outermost boundary 1621 of the second cathode electrode layer 162, and the outermost boundary 1721 of the second passivation layer 172 may be disposed in the second sub-pixel SP2 formed between adjacent data lines DL.

[0150] Accordingly, the second organic light-emitting layer 152, the second cathode electrode layer 162, and the second passivation layer 172 may not overlap with the data line DL in the vertical direction (e.g., non-overlapping).

[0151] The second cathode electrode layer 162 may include a material having a step coverage relatively better than that of the material of the second organic light-emitting layer 152, and accordingly, the end of the second cathode electrode layer 162 may be located at a position outside the end of the second organic light-emitting layer 152. That is, the end of the second cathode electrode layer 162 extends beyond the end of the second organic light-emitting layer 152.

[0152] Therefore, the second cathode electrode layer 162 may be formed to cover the entire second organic light-emitting layer 152, such that the outermost boundary 1621 of the second cathode electrode layer 162 may be located at a position outside the outermost boundary 1521 of the second organic light-emitting layer 152.

[0153] The second passivation layer 172 may include a material having a step coverage relatively better than that of the material of the second cathode electrode layer 162, and the end of the second passivation layer 172 may be located at a position outside the end of the second cathode electrode layer 162. That is, the end of the second passivation layer 172 extends beyond the end of the second cathode electrode layer 162.

[0154] Therefore, the second passivation layer 172 may be formed to cover the entire second cathode electrode layer 162, such that the outermost boundary 1721 of the second passivation layer 172 may be located at a position outside the outermost boundary 1621 of the second cathode electrode layer 162.

[0155] In addition, the outermost boundary 1531 of the third organic light-emitting layer 153, the outermost boundary 1631 of the third cathode electrode layer 163, and the outermost boundary 1731 of the third passivation layer 173 may be provided in the third sub-pixel SP3 formed between adjacent data lines DL.

[0156] Accordingly, the third organic light-emitting layer 153, the third cathode electrode layer 163, and the third passivation layer 173 may not overlap with the data line DL in the vertical direction (e.g., non-overlapping).

[0157] The third cathode electrode layer 163 may include a material having a step coverage relatively better than that of the material of the third organic light-emitting layer 153, and accordingly, the end of the third cathode electrode layer 163 may be located at a position outside the end of the third organic light-emitting layer 153. That is, the end of the third cathode electrode layer 163 extends beyond the end of the third organic light-emitting layer 153.

[0158] Accordingly, the third cathode electrode layer 163 may be formed to cover the entirety of the third organic light-emitting layer 153 such that the outermost boundary 1631 of the third cathode electrode layer 163 may be positioned outside the outermost boundary 1531 of the third organic light-emitting layer 153.

[0159] The third passivation layer 173 may include a material having a relatively better step coverage than that of the material of the third cathode electrode layer 163, and the end of the third passivation layer 173 may be positioned outside the end of the third cathode electrode layer 163. That is, the end of the third passivation layer 173 extends beyond the end of the third cathode electrode layer 163.

[0160] Accordingly, the third passivation layer 173 may be formed to cover the entirety of the third cathode electrode layer 163 such that the outermost boundary 1731 of the third passivation layer 173 may be positioned outside the outermost boundary 1631 of the third cathode electrode layer 163.

[0161] When the cathode electrode layers adjacent to each other are not disconnected from each other but are integrally continuous with each other to cover the entire display area as a single electrode structure, the cathode electrode is disposed to overlap with the data line, and thus an unwanted parasitic capacitance may be generated between the cathode electrode layer and the data line.

[0162] When the parasitic capacitance is generated in this way, the RC delay may increase.

[0163] The RC delay refers to a value obtained by multiplying a resistance R by a capacitance C and means a decrease in the electrical transmission rate.

[0164] Accordingly, when the RC delay increases, the decrease in the electrical transmission rate increases. Thus, the display device cannot operate at a high speed.

[0165] However, according to an embodiment of the present disclosure, the cathode electrode layer and the data line may be disposed not to overlap with each other in the vertical direction (e.g., non-overlapping), thereby reducing the parasitic capacitance that may be generated between the cathode electrode layer and the data line.

[0166] Accordingly, according to an embodiment of the present disclosure, a significant reduction in the occurrence of the RC delay may allow the display device to operate at a high speed.

[0167] In a region corresponding to the opening 1402 of the first sub-pixel SP1 of the bank layer 140, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 may be sequentially stacked. The region where the anode electrode layer 130, the first organic light-emitting layer 151, and the first cathode electrode layer 161 overlap each other may be the first light-emitting region OLE1 that emits light.

[0168] In addition, in a region corresponding to the opening 1402 of the second sub-pixel SP2 of the bank layer 140, a second organic light-emitting layer 152, a second cathode electrode layer 162, and a second passivation layer 172 can be sequentially stacked. A region where the anode electrode layer 130, the second organic light-emitting layer 152, and the second cathode electrode layer 162 overlap each other can be a second light-emitting region OLE2 that emits light.

[0169] In addition, in a region corresponding to the opening 1402 of the third sub-pixel SP3 of the bank layer 140, a third organic light-emitting layer 153, a third cathode electrode layer 163, and a third passivation layer 173 can be sequentially stacked. A region where the anode electrode layer 130, the third organic light-emitting layer 153, and the third cathode electrode layer 163 overlap each other can be a third light-emitting region OLE3 that emits light.

[0170] The first organic light-emitting layer 151, the second organic light-emitting layer 152, and the third organic light-emitting layer 153 can include light-emitting layers (EML) that emit red, green, and blue light beams, respectively. The light-emitting layer can be made of a phosphorescent material or a fluorescent material. Its specific material is not particularly limited.

[0171] For example, a hole injection layer (HIL) and / or a hole transport layer (HTL) can be additionally provided between the anode electrode layer 130 and the organic light-emitting layer EML. An electron transport layer (ETL) and an electron injection layer (HIL) can be provided between the light-emitting layer (EML) and the cathode electrode layer.

[0172] When the adjacent organic light-emitting layers are not disconnected from each other but are integrally continuous and extend to cover the entire display area as a single structure, the light generated from the light-emitting region but not escaping to the outside can continue to be reflected by the interface, propagate to the side surface, and then disappear.

[0173] However, according to an embodiment of the present disclosure, the organic light-emitting layers of adjacent sub-pixels are disconnected from each other, the cathode electrode layers of adjacent sub-pixels are disconnected from each other, and the passivation layers of adjacent sub-pixels are disconnected from each other. Therefore, the propagation path of the light from the organic light-emitting layer changes at the disconnection end, so that the light can escape to the outside.

[0174] Accordingly, according to an embodiment of the present disclosure, the light extraction efficiency from the organic light-emitting layer can be further improved based on the occurrence of the external coupling phenomenon.

[0175] In addition, according to an embodiment of the present disclosure, the organic light-emitting layers of adjacent sub-pixels are disconnected from each other, the cathode electrode layers of adjacent sub-pixels are disconnected from each other, and the passivation layers of adjacent sub-pixels are disconnected from each other. Therefore, the occurrence of lateral leakage current in the organic light-emitting layer that may occur when the organic light-emitting layers are connected and continuously extended can be reduced.

[0176] As described above, the structure ST is formed in a conical shape. Accordingly, each of the organic light-emitting layer, the cathode electrode layer, and the passivation layer formed on the structure ST can be continuous without being disconnected, but can extend continuously in each sub-pixel.

[0177] However, a partial region of the passivation layer 171 disposed on (e.g., overlapping) the structure ST can be opened to expose a portion of the cathode electrode layer. That is, the passivation layer 171 includes a first portion and a second portion. Among them, the first portion of the passivation layer 171 is located on the first portion of the cathode electrode layer 161 that is in the opening of the bank layer 140, and the second portion of the passivation layer 171 is located on the second portion of the cathode electrode layer 161 and the structure ST, but not between the second portion of the cathode electrode layer 161 and the portion of the power connection line 112 that contacts the second portion of the cathode electrode layer 161.

[0178] This will be further described below.

[0179] The first cover layer 170 can be disposed on the bank layer 140.

[0180] The first cover layer 170 can be made of an organic material. However, the present disclosure is not limited thereto.

[0181] The first cover layer 170 can act as a planarization layer. Accordingly, the first cover layer 170 can be formed to have a thickness sufficient to cover the bank layer 140 and the first passivation layer 171.

[0182] Therefore, the first cover layer 170 and the structure ST can be formed in the same layer based on the bank layer 140.

[0183] The first cover layer 170 formed to cover the sequentially stacked first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 can cover the first passivation layer 171. At the same time, the portions corresponding to the structure ST of each of the first passivation layer 171 and the first cover layer 170 can be removed.

[0184] Specifically, the portions of the first passivation layer 171 and the first cover layer 170 corresponding to the upper surface (e.g., overlapping) of the structure ST can be removed to define an opening area.

[0185] In this case, the first passivation layer 171 and the first cover layer 170 can be formed to cover the side surface of the structure ST, but not the upper surface of the structure ST.

[0186] The width in the left-right direction of the opening area obtained by removing the portions corresponding to the upper surface of the structure ST of each of the first passivation layer 171 and the first cover layer 170 can be greater than the width in the left-right direction of the upper surface of the structure ST.

[0187] For example, the uppermost surface of the first capping layer 170 may be coplanar with the end of the uppermost surface of the first passivation layer 171 (specifically, with the uppermost level of the first passivation layer 171).

[0188] In addition, the upper surface of the first capping layer 170 may be coplanar with the upper surface of the first cathode electrode layer 161 exposed through the opening region of the first passivation layer 171. That is, the upper surface of the first capping layer 170 may be coplanar with the portion of the cathode electrode layer 161 that contacts the power connection line 112.

[0189] Accordingly, the upper surface of the first capping layer 170 may be coplanar with the upper surface of the end of the first passivation layer 171 and the upper surface of the first cathode electrode layer 161.

[0190] In the present disclosure, the phrase "A is coplanar with B" may mean that no step is formed between A and B, but a planarized surface is defined by A and B.

[0191] In this way, the portion of the first cathode electrode layer 161 exposed through the opening region obtained by removing the portions of each of the first capping layer 170 and the first passivation layer 171 provided on the structure ST may function as the first cathode contact portion 161c.

[0192] The first cathode contact portion 161c refers to an exposed partial region (or portion) of the first cathode electrode layer 161, and may not be physically separated from the main region of the first cathode electrode layer 161, but is conceptually distinguishable therefrom.

[0193] The power connection line 112, which is provided to overlap the structure ST in the vertical direction, may be formed on the first capping layer 170 formed as described above.

[0194] The power connection line 112 may be provided to directly contact the first cathode contact portion 161c and may be electrically connected to the first cathode electrode layer 161 through the first cathode contact portion 161c.

[0195] As described above, the upper surface of the first cathode contact portion 161c is coplanar with the upper surface of the first capping layer 170, so that the power connection line 112 can contact the first cathode contact portion 161c more stably.

[0196] For the operation of each of the sub-pixels SP1, SP2, and SP3, a low-potential voltage VSS should be applied to the cathode electrode layer.

[0197] However, according to embodiments of the present disclosure, the cathode electrode layers in adjacent sub-pixels respectively included in sub-pixels SP1, SP2, and SP3 are disconnected from each other. For this reason, the low-potential voltage VSS can be applied to each of the cathode electrode layers respectively included in sub-pixels SP1, SP2, and SP3 through the electrical connection between the power connection line 112 and the cathode contact portion.

[0198] When the power connection lines 112 are arranged in a grid pattern, some regions of the power connection lines 112 may not overlap with the data lines DL in the vertical direction, while the remaining regions thereof may overlap with the data lines DL in the vertical direction.

[0199] However, according to the present disclosure, the power connection lines 112 are formed on the first cover layer 170, and the data lines DL are provided under the bank layer 140. Accordingly, the bank layer 140 and the first cover layer 170 can be provided between the power connection lines 112 and the data lines DL.

[0200] Accordingly, the distance between the power connection lines 112 and the data lines DL can be increased, thereby reducing the parasitic capacitance that may occur between the power connection lines 112 and the data lines DL that overlap each other in the vertical direction, and thus reducing the occurrence of a decrease in the electrical transmission rate (RC delay).

[0201] In addition, referring to Figure 3C and Figure 5 showing another embodiment, the power connection lines 112 provided on the first cover layer 170 may be formed in the form of a single integral electrode that covers the entire display area AA.

[0202] When the power connection lines 112 are formed in the form of a single integral electrode that covers the entire surface of the display area AA in this way so as to cover a plurality of sub-pixels, the power connection lines 112 may be made of a transparent material.

[0203] Even in this case, the bank layer 140 and the first cover layer 170 can be provided between the power connection lines 112 and the data lines DL, thereby increasing the distance between the power connection lines 112 and the data lines DL, thereby reducing the generation of parasitic capacitance between the power connection lines 112 and the data lines DL, and thus reducing the occurrence of a decrease in the electrical transmission rate (RC delay).

[0204] A second cover layer 180 and a passivation layer 190 may be additionally provided on the power connection lines 112.

[0205] In this case, the second cover layer 180 may be made of an organic material and may be made of the same material as the material of the first cover layer 170. However, the present disclosure is not limited thereto, and the second cover layer 180 and the first cover layer 170 may be made of different materials.

[0206] The connection structure between the first cathode contact portion 161c in the first sub-pixel SP1 as described above and the power connection line 112 can be similarly applied to each of the second sub-pixel SP2 and the third sub-pixel SP3. Therefore, redundant description thereof can be omitted.

[0207] Figures 6A to 6K is a plan view of a plurality of sub-pixels in the process of manufacturing a display device according to an embodiment of the present disclosure.

[0208] Figures 7A to 7K is respectively corresponding to according to an embodiment of the present disclosure Figures 6A to 6K is a cross-sectional view.

[0209] For the sake of easy illustration, Figures 6A to 6K each of the plan views of Figures 7A to 7K only shows some components shown in each of the cross-sectional views of

[0210] The scheme for forming patterns in each of the layers as described below can adopt techniques performed by those skilled in the art, for example, photolithography processes including deposition, application of photoresist (PR coating), exposure, development, etching, and photoresist stripping (PR stripping). Detailed description thereof will be omitted.

[0211] For example, sputtering can be used to perform deposition of metal materials. PECVD (plasma enhanced chemical vapor deposition) can be used to perform deposition of semiconductor or insulating films. Dry etching or wet etching can be selected based on the material to be etched. Techniques performed by those skilled in the art can be applied thereto.

[0212] Referring to Figure 6A and Figure 7A , a plurality of data lines DL can be formed on the substrate 100 and an insulating layer 103 can be formed to cover the plurality of data lines DL.

[0213] After that, a plurality of anode electrode layers 130 respectively located at positions corresponding to the sub-pixels and included therein can be formed on the insulating layer 103.

[0214] In addition, a bank layer 140 including a plurality of second openings 1402 respectively exposing portions of the plurality of anode electrode layers 130 can be formed.

[0215] The pixel resolution PDL can be defined by the openings 1402 of the bank layer 140 and can be formed in each sub-pixel.

[0216] The bank layer 140 can be formed to cover the entire display area AA except for the regions corresponding to the plurality of openings 1402.

[0217] Reference Figure 6B and Figure 7B , a plurality of structures ST may be formed on the bank layer 140 such that they are respectively located in the plurality of sub-pixels.

[0218] The structure ST may protrude upward so as to have a predetermined thickness and may thus act as a contact spacer, and may be formed in a tapered shape.

[0219] Reference Figure 6C and Figure 7C , a first protective film 142a may be formed to cover the entire substrate 100.

[0220] The first protective film 142a may include a fluorine-based material.

[0221] For example, the first protective film 142a may be composed of a fluoropolymer material having a carbon-carbon main chain and functional groups containing a large amount of fluorine (F).

[0222] According to an example of the present disclosure, the chemical structure of the fluoropolymer material having functional groups containing a large amount of fluorine (F) has the following [Chemical Formula 1]:

[0223] [Chemical Formula 1]

[0224]

[0225] As shown in [Chemical Formula 1], the fluoropolymer used as the protective film material has functional groups containing a large amount of fluorine (F).

[0226] The fluoropolymer having functional groups containing a large amount of fluorine (F) may have orthogonality.

[0227] Orthogonality may be understood as a characteristic in which two elements are independent of each other.

[0228] Accordingly, the first protective film 142a may have both hydrophobicity with low affinity for water and oleophobicity with low affinity for oil.

[0229] Due to this orthogonality, the first protective film 142a may block the path of moisture penetration due to the property of repelling moisture.

[0230] In addition, the first protective film 142a may be less affected by the developer containing an organic solvent used in the process steps. This may reduce the damage of the organic solvent to the organic material.

[0231] Reference Figure 6D and Figure 7D , a first photoresist film 143 may be formed on the first protective film 142a.

[0232] For example, the first photoresist film 143 may be formed by depositing a photoresist material and patterning it to have a predetermined pattern.

[0233] The first photoresist film 143 may have a predetermined pattern, where the first photoresist film 143 has an opening in the region corresponding to the first sub-pixel SP1, while the first photoresist film 143 does not have an opening but covers the second sub-pixel SP2 and the third sub-pixel SP3 in the region corresponding to each of the second sub-pixel SP2 and the third sub-pixel SP3.

[0234] Specifically, the first photoresist film 143 may be formed in this pattern so as to expose a part of the upper surface of the first protective film 142a corresponding to the opening 1402 of the first sub-pixel SP1.

[0235] Reference Figure 6E and Figure 7E , the first protective layer 142 having a predetermined pattern may be formed by patterning the underlying first protective film 142a using the first photoresist film 143 as a photomask.

[0236] The first protective layer 142 formed in this way may not cover the opening 1402 of the bank layer 140, thus exposing it to the outside. Accordingly, the structure ST may be exposed to the outside.

[0237] In this case, since the first protective layer 142 is located inside the first photoresist film 143 provided thereon, the first photoresist film 143 may have an overhang structure located on the first protective layer 142.

[0238] In this case, since the first protective layer 142 is located inside the first photoresist layer 143 provided thereon, the first photoresist layer 143 may provide an overhang structure located on the first protective layer 142.

[0239] Accordingly, the first photoresist layer 143 may include an overhang 144 protruding inward with respect to the first protective layer 142.

[0240] Reference Figure 6F and Figure 7F , the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 that render the first color may be sequentially stacked and provided.

[0241] For example, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 that render the first color may be sequentially deposited on the entire surface of the substrate 100.

[0242] Accordingly, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 can be sequentially stacked in the opening 1402 of the bank layer 140. The first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 stacked in this way can extend to cover the structure ST and continuously extend.

[0243] However, due to the reason that the first photoresist film 143 has an overhang structure including an overhang 144 located on the first protective layer 142, each of the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 may be disconnected or discontinuous.

[0244] The first cathode electrode layer 161 can include a material having a relatively better step coverage than the material of the first organic light-emitting layer 151, and accordingly, the end of the first cathode electrode layer 161 can be located at a position outside the end of the first organic light-emitting layer 151.

[0245] Therefore, the first cathode electrode layer 161 can be formed to cover all of the first organic light-emitting layer 151, so that the outermost boundary 1611 of the first cathode electrode layer 161 can be located at a position outside the outermost boundary 1511 of the first organic light-emitting layer 151.

[0246] The first passivation layer 171 can include a material having a relatively better step coverage than the material of the first cathode electrode layer 161, and accordingly, the end of the first passivation layer 171 can be located at a position outside the end of the first cathode electrode layer 161.

[0247] Therefore, the first passivation layer 171 can be formed to cover all of the first cathode electrode layer 161, so that the outermost boundary 1711 of the first passivation layer 171 can be located at a position outside the outermost boundary 1611 of the first cathode electrode layer 161.

[0248] The first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 can be sequentially stacked in the opening 1402. Thus, the region where the first organic light-emitting layer 151, the first cathode electrode layer 161, and the anode electrode layer 130 overlap each other can be embodied as the first light-emitting region OLE1.

[0249] Reference Figure 6G and Figure 7G , the first protective layer 142 and the first photoresist layer 143 can be removed.

[0250] Specifically, during the process of peeling off the first protective layer 142, the first photoresist film 143, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 stacked on the first protective layer 142 can be removed together.

[0251] Reference Figure 6H and Figure 7H , the same process as that applied to the first sub-pixel SP1 as described in connection with Figures 6C to 6G and Figures 7C to 7G can be equivalently performed for each of the second sub-pixel SP2 and the third sub-pixel SP3.

[0252] Specifically, a second protective layer and a second photoresist film can be formed to expose the opening 1402 corresponding to the second sub-pixel SP2. The second organic light-emitting layer 152, the second cathode electrode layer 162, and the second passivation layer 172 for rendering the second color can be sequentially stacked. Thereafter, the second protective layer and the second photoresist film can be removed.

[0253] Accordingly, a second light-emitting region OLE2 of the second sub-pixel SP2 can be formed. The second organic light-emitting layer 152, the second cathode electrode layer 162, and the second passivation layer 172 can be sequentially formed on the structure ST of the second sub-pixel SP2.

[0254] After performing this process on the second sub-pixel SP2 in this manner, a third protective layer and a third photoresist film can be formed to expose the first opening 1401 and the opening 1402 corresponding to the third sub-pixel SP3. The third organic light-emitting layer 153, the third cathode electrode layer 163, and the third passivation layer 173 for rendering the third color can be sequentially stacked. Thereafter, the third protective layer and the third photoresist film can be removed.

[0255] Accordingly, a third light-emitting region OLE3 of the third sub-pixel SP3 can be formed. The power connection lines 112 extending across the third sub-pixel SP3 and the third cathode electrode layer 163 can be electrically connected to each other at the undercut UC of the structure ST in each of the third sub-pixels SP3.

[0256] In this way, according to an embodiment of the present disclosure, an organic light-emitting layer, a cathode electrode layer, and a passivation layer for rendering the first color can be formed, and then an organic light-emitting layer for rendering the second color can be additionally formed using the same process as that for the organic light-emitting layer for rendering the first color, and then an organic light-emitting layer for rendering the third color can be additionally formed using the same process as that for the organic light-emitting layer for rendering the first color.

[0257] Accordingly, the passivation layer disposed on the organic light-emitting layer can act as a protective film, which reduces the degradation that may occur in the organic light-emitting layer during the continuous process of forming the organic light-emitting layer corresponding to each sub-pixel. Thus, damage to the organic light-emitting layer can be reduced.

[0258] A first planarization film 170a can be formed to cover the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0259] The first planarization film 170a can be formed to cover the first passivation layer 171, the second passivation layer 172, and the third passivation layer 173.

[0260] In the present disclosure, the first planarization film 170a can be referred to as the first capping layer 170. The first planarization film 170a that has been processed by the etching process described below can be referred to as the first capping layer 170.

[0261] Reference Figure 6I and Figure 7I , partial regions of each of the first capping layer 170, the first passivation layer 171, the second passivation layer 172, and the third passivation layer 173 can be etched to expose regions of each of the first cathode electrode layer 161, the second cathode electrode layer 162, and the third cathode electrode layer 163 corresponding to each of the plurality of structures ST located in the respective sub-pixels.

[0262] Specifically, the first planarization film 170a can be etched such that its thickness is reduced by a predetermined thickness. The etching of the first planarization film 170a can be performed until the portion of the passivation layer corresponding to the structure ST is completely removed, so that a partial region of the cathode electrode layer is exposed to the outside.

[0263] As this portion of the passivation layer is removed in this way, a cathode contact portion can be formed as the portion of the cathode electrode layer exposed to the outside.

[0264] Accordingly, a first cathode contact portion 161c can be formed as a part of the first cathode electrode layer 161. A second cathode contact portion 162c can be formed as a part of the second cathode electrode layer 162, and a third cathode contact portion 163c can be formed as a part of the third cathode electrode layer 163.

[0265] Reference Figure 6J and Figure 7J , a power connection line 112 can be formed on the first capping layer 170 and electrically connected to the exposed portions of each of the first cathode electrode layer 161, the second cathode electrode layer 162, and the third cathode electrode layer 163.

[0266] Accordingly, the power connection line 112 is in direct contact with the first cathode contact portion 161c of the first cathode electrode layer 161, in direct contact with the second cathode contact portion 162c of the second cathode electrode layer 162, and in direct contact with the third cathode contact portion 163c of the third cathode electrode layer 163. Thus, the voltage from the power line 20 can be applied to the cathode electrode layer through the power connection line 112.

[0267] Reference Figure 6K and Figure 7K , a second capping layer 180 and a passivation layer 190 may be additionally formed to cover the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0268] A display device and a method for manufacturing the display device according to an embodiment of the present disclosure as described above will be described below.

[0269] A first aspect of the present disclosure provides a display device, including: a plurality of sub-pixels; a power line for applying a voltage to the plurality of sub-pixels; a plurality of structures respectively disposed in the plurality of sub-pixels; and a power connection line disposed on the plurality of structures to electrically connect the plurality of sub-pixels to the power line, wherein each of the sub-pixels includes an organic light-emitting layer, a cathode electrode layer, and a passivation layer stacked in sequence, wherein the organic light-emitting layers of adjacent sub-pixels are disconnected from each other, wherein the cathode electrode layers of adjacent sub-pixels are disconnected from each other, wherein the passivation layers of adjacent sub-pixels are disconnected from each other, wherein a cathode contact portion, which is a portion of the cathode electrode layer exposed through an opening defined in the passivation layer, is disposed on the structure, wherein the power connection line is disposed to overlap with the plurality of structures, and wherein the power connection line contacts the cathode contact portion and is thus electrically connected to the cathode electrode layer.

[0270] In an implementation manner of the first aspect, the display device further includes a plurality of data lines, each data line being disposed between adjacent sub-pixels, wherein each of the data lines is disposed not to overlap with the cathode electrode layer.

[0271] In an implementation manner of the first aspect, the plurality of sub-pixels are arranged in a matrix form along a first direction and a second direction intersecting the first direction, wherein the power connection line is formed in a grid pattern extending across the cathode contact portions respectively disposed in the plurality of sub-pixels.

[0272] In an implementation manner of the first aspect, the power connection line is formed to cover the entire area of all the plurality of sub-pixels, and the power connection line is made of a transparent material.

[0273] In one embodiment of the first aspect, each of the sub-pixels includes the outermost boundary of the organic light-emitting layer, the outermost boundary of the cathode electrode layer, and the outermost boundary of the passivation layer, wherein the outermost boundary of the organic light-emitting layer is located at a position within the outermost boundary of the passivation layer, and wherein the outermost boundary of the cathode electrode layer is disposed between the outermost boundary of the organic light-emitting layer and the outermost boundary of the passivation layer.

[0274] In one embodiment of the first aspect, the structure included in each of the sub-pixels is located at a position inside the outermost boundary of the organic light-emitting layer, the outermost boundary of the cathode electrode layer, and the outermost boundary of the passivation layer.

[0275] In one embodiment of the first aspect, each of the sub-pixels includes a light-emitting region, wherein the structure is disposed in at least one side portion of the light-emitting region.

[0276] In one embodiment of the first aspect, the power line is a low-potential voltage (VSS) line, wherein the low-potential voltage is applied to the cathode electrode layer included in each of the sub-pixels through a power connection line.

[0277] A second aspect of the present disclosure provides a display device, which includes: a substrate having a plurality of sub-pixel regions defined thereon; a bank layer disposed on the substrate; a structure having at least a partial region disposed on the bank layer; an organic light-emitting layer, a cathode electrode layer, and a passivation layer sequentially stacked to cover the bank layer and the structure; and a power connection line disposed on the structure so as to overlap with the structure, wherein a cathode contact portion, which is a portion of the cathode electrode layer exposed through an opening defined in the passivation layer, is disposed on the structure, and wherein the power connection line contacts the cathode contact portion and is thus electrically connected to the cathode electrode layer.

[0278] In one embodiment of the second aspect, the organic light-emitting layers of adjacent sub-pixels are disconnected from each other, wherein the cathode electrode layers of adjacent sub-pixels are disconnected from each other, and wherein the passivation layers of adjacent sub-pixels are disconnected from each other.

[0279] In one embodiment of the second aspect, the display device further includes a data line disposed on the substrate, wherein the data line is disposed so as not to overlap with the cathode electrode layer.

[0280] In one embodiment of the second aspect, the display device further includes: a data line disposed on the substrate; and a first cover layer disposed between the bank layer and the power connection line, wherein the bank layer and the first cover layer are disposed between the data line and the power connection line.

[0281] In one embodiment of the second aspect, at least a partial region of the data line does not overlap with the power connection line.

[0282] In an embodiment of the second aspect, the first cover layer and the structure are disposed in the same layer as the embankment layer.

[0283] In an embodiment of the second aspect, the display device further includes a second cover layer disposed on the first cover layer so as to cover the power connection lines.

[0284] In an embodiment of the second aspect, the structure has a conical shape.

[0285] In an embodiment of the second aspect, the display device further includes a power line serving as a low-potential voltage (VSS) line, wherein the low-potential voltage is applied to the cathode electrode layer included in each of the sub-pixels through the power connection lines.

[0286] A third aspect of the present disclosure provides a method for manufacturing a display device, the method including: forming a plurality of data lines on a substrate; forming a plurality of anode electrode layers respectively in the plurality of sub-pixels; forming an embankment layer including a plurality of openings respectively exposing portions of the plurality of anode electrode layers; forming a plurality of structures on the embankment layer respectively in the plurality of sub-pixels; forming a first protective layer and a first photoresist film so as to cover the opening corresponding to the first sub-pixel, sequentially forming a first organic light-emitting layer, a first cathode electrode layer, and a first passivation layer that render a first color, and then removing the first protective layer and the first photoresist film; forming a second protective layer and a second photoresist film so as to expose the opening corresponding to the second sub-pixel, sequentially forming a second organic light-emitting layer, a second cathode electrode layer, and a second passivation layer that render a second color, and then removing the second protective layer and the second photoresist film; forming a third protective layer and a third photoresist film so as to expose the opening corresponding to the third sub-pixel, sequentially forming a third organic light-emitting layer, a third cathode electrode layer, and a third passivation layer that render a third color, and then removing the third protective layer and the third photoresist film; forming a first cover layer so as to cover the first passivation layer, the second passivation layer, and the third passivation layer; etching partial regions of each of the first cover layer, the first passivation layer, the second passivation layer, and the third passivation layer so as to expose partial regions of each of the first cathode electrode, the second cathode electrode, and the third cathode electrode that overlap with the structure; and forming power connection lines on the first cover layer so as to electrically connect to the exposed partial regions of each of the first cathode electrode layer, the second cathode electrode layer, and the third cathode electrode layer.

[0287] In an embodiment of the third aspect, forming the first cover layer includes forming the first cover layer such that the first cover layer and the structure are disposed in the same layer as the embankment layer.

[0288] In one embodiment of the third aspect, the first organic light-emitting layer, the second organic light-emitting layer, and the third organic light-emitting layer are formed to be disconnected from each other. Among them, the first cathode electrode layer, the second cathode electrode layer, and the third cathode electrode layer are formed to be disconnected from each other. Among them, the first passivation layer, the second passivation layer, and the third passivation layer are formed to be disconnected from each other.

[0289] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and various modifications can be made within the scope of the technical essence of the present disclosure. Accordingly, the embodiments disclosed in the present disclosure are intended to describe rather than limit the technical concept of the present disclosure, and the scope of the technical concept of the present disclosure is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative rather than restrictive in all respects.

Claims

1. A display device, comprising: a substrate having a plurality of sub-pixels defined thereon; a power line configured to provide a voltage; a plurality of structures, each structure being disposed in a corresponding one of the plurality of sub-pixels; and a power connection line overlapping with the plurality of structures, the power connection line being electrically connected to the plurality of sub-pixels and the power line and supplying the voltage from the power line to the plurality of sub-pixels, wherein each of the plurality of sub-pixels includes an anode electrode layer, an organic light-emitting layer on the anode electrode layer, a cathode electrode layer on the organic light-emitting layer, and a passivation layer on the cathode electrode layer, the passivation layer including an opening exposing a part of the cathode electrode layer such that the part of the cathode electrode layer contacts the power connection line.

2. The display device according to claim 1, wherein, The opening is disposed on the organic light-emitting layer.

3. The display device according to claim 2, wherein, The organic light-emitting layer includes a hole injection layer and / or a hole transport layer, a light-emitting layer, and an electron transport layer and / or an electron injection layer.

4. The display device according to claim 1, wherein, The display device further includes: a bank layer disposed on the substrate, wherein the bank layer is disposed below the opening.

5. The display device according to claim 4, wherein, The bank layer includes an opening overlapping with the anode electrode layer, and the part of the cathode electrode layer is disposed outside the opening of the bank layer.

6. The display device according to claim 1, wherein, The passivation layer covers the ends of the organic light-emitting layer and the ends of the cathode electrode layer.

7. The display device according to claim 6, wherein, The passivation layer contacts the bank layer at the ends of the organic light-emitting layer and the ends of the cathode electrode layer.

8. The display device according to claim 1, wherein, The part of the cathode electrode layer is located on the structure.

9. The display device according to claim 8, wherein, The organic light-emitting layer and the cathode electrode layer are disposed on the structure.

10. The display device according to claim 4, wherein, The display device further includes: a first cover layer including an opening, wherein the opening of the first cover layer exposes the part of the cathode electrode layer.

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