Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a substrate, a driving layer and a light-emitting device, the driving layer and the light-emitting device are located on one side of the substrate, the driving layer comprises a plurality of inorganic layers, and at least one inorganic layer is hollowed out; the display area comprises a first area and a second area, and the first area comprises a hollow part; the first area comprises a light-emitting device, and the light-emitting device and the hollowed-out part are at least partially overlapped in the direction perpendicular to the plane where the substrate is located; the second area comprises a light-emitting device and a pixel circuit located in the driving layer, and the pixel circuit coupled with the light-emitting device in the first area is located in the second area; the display area comprises signal lines located on the driving layer, the signal lines are coupled with the multiple pixel circuits, and at least one signal line penetrates through the first area and the second area in the extending direction of the signal line. The impact resistance of the display panel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] An organic light-emitting diode (OLED) is a device that uses a multi-layer organic thin film structure to generate electroluminescence. It is very easy to fabricate and only requires a low driving voltage. These characteristics make OLEDs stand out in meeting the applications of flat panel displays. OLED displays are thinner, brighter, lower in power consumption, faster in response, higher in clarity, better in flexibility, and higher in luminous efficiency than liquid crystal displays, and can meet the new demands of consumers for display technologies. OLED displays are not only used in conventional daily electronic consumer products such as mobile phones and tablets, but also have extensive applications in the field of in-vehicle displays.

[0003] In some special usage scenarios, the display screen is faced with a relatively high frequency and amplitude of impact, and is prone to a relatively high risk of screen breakage. How to improve its impact resistance and ensure its normal display is an urgent problem to be solved. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a display device to solve the technical problem of improving the impact resistance of the display panel.

[0005] In a first aspect, embodiments of the present invention provide a display panel. The display panel includes a substrate, a driving layer located on one side of the substrate, and a light-emitting device. The driving layer includes a plurality of inorganic layers, and at least one inorganic layer has a hollow; The display panel includes a display area, the display area includes a first area and a second area, and the first area includes a hollow; The first area includes a light-emitting device. Along the direction perpendicular to the plane where the substrate is located, the light-emitting device and the hollow at least partially overlap; the second area includes a light-emitting device and a pixel circuit located in the driving layer, and the pixel circuit coupled to the light-emitting device in the first area is located in the second area; The display area includes signal lines located in the driving layer. The signal lines are coupled to a plurality of pixel circuits, and at least one signal line penetrates through the first area and the second area in its extending direction.

[0006] In a second aspect, based on the same inventive concept, embodiments of the present invention further provide a display device, including the display panel provided in any embodiment of the present invention.

[0007] The display panel and display device provided by the embodiments of the present invention have the following beneficial effects: By locally concentrating the pixel circuit in the second region, the embodiments of the present invention leave a position for making a hollow in the inorganic layer in the first region. The hollow in the inorganic layer truncates the inorganic layer at a local position, thereby providing a buffer when stress is applied. Moreover, when the display panel is impacted, even if cracks appear locally in the inorganic layer, the cracks will be stopped when they extend to the hollow position, preventing the cracks from spreading to the entire display area, thus improving the impact resistance. In addition, since the light-emitting device is located on the side of the driving layer away from the substrate, the hollow in the inorganic layer does not affect the fabrication of the light-emitting device in the display area. The embodiments of the present invention can not change the position and quantity of the light-emitting devices in the display area. And by locally concentrating the pixel circuit using the available layout space under the original PPI, the normal driving of the light-emitting devices in the first region is ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0009] Figure 1 Schematic diagram of a display panel provided by an embodiment of the present invention; Figure 2 For Figure 1 Enlarged schematic diagram at position Q1 in Figure 3 Cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention; Figure 4 Schematic diagram of a pixel circuit provided by an embodiment of the present invention; Figure 5 Pixel circuit layout provided by an embodiment of the present invention; Figure 6 Another pixel circuit layout provided by an embodiment of the present invention; Figure 7 Another cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention; Figure 8 Top view of a hollow pattern provided by an embodiment of the present invention; Figure 9 Another partial schematic diagram of a display panel provided by an embodiment of the present invention; Figure 10 Another schematic diagram of a display panel provided by an embodiment of the present invention; Figure 11 Another partial schematic diagram of a display panel provided by an embodiment of the present invention; Figure 12 Another partial schematic diagram of the display panel provided by an embodiment of the present invention; Figure 13 Another partial schematic diagram of the display panel provided by an embodiment of the present invention; Figure 14 Another schematic diagram of the display panel provided by an embodiment of the present invention; Figure 15 Another schematic diagram of the display panel provided by an embodiment of the present invention; Figure 16 Another schematic diagram of the display panel provided by an embodiment of the present invention; Figure 17 Another schematic diagram of the display panel provided by an embodiment of the present invention; Figure 18 Another partial schematic diagram of the display panel provided by an embodiment of the present invention; Figure 19 Another partial schematic diagram of the display panel provided by an embodiment of the present invention; Figure 20 Another partial schematic diagram of the display panel provided by an embodiment of the present invention; Figure 21 Another partial schematic diagram of the display panel provided by an embodiment of the present invention Figure 22 A schematic diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0010] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0011] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms of "a", "the", and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0012] An embodiment of the present invention provides a display panel, where at least one inorganic layer of the display panel has a hollow, and at least part of the hollow is disposed in the display area. At the position where the hollow is located in the display area, there is an overlap between the light-emitting device and the hollow, and the pixel circuits that originally needed to be disposed at the hollow position are centrally disposed in the area without the hollow of the inorganic layer. The present invention can truncate the inorganic layer at a local position by using the hollow of the inorganic layer without affecting the overall arrangement of the light-emitting devices in the display area, thereby providing a buffer when stress is applied. When the display panel is impacted, even if cracks appear locally in the inorganic layer, when the cracks extend to the hollow position, they will be stopped, preventing the cracks from spreading to the entire display area, thereby improving the impact resistance. The above is the main technical concept of the present invention, and the present invention will be illustrated by specific examples below.

[0013] Figure 1 FIG. is a schematic diagram of a display panel provided by an embodiment of the present invention. Figure 2 is Figure 1 an enlarged schematic diagram of the position of area Q1 in FIG. As Figure 1 shown, the display panel includes a display area AA and a non-display area NA. Figure 2 FIG. schematically shows a simplified schematic diagram of the position of area Q1. In the display area AA, a light-emitting device 20 and a pixel circuit 11 are disposed. The display area AA includes a first area A1 and a second area A2. The first area A1 includes the light-emitting device 20, and the second area A2 includes the light-emitting device 20 and the pixel circuit 11. The pixel circuit 11 coupled to the light-emitting device 20 in the first area A1 is located in the second area A2. The light-emitting device 20 includes a first light-emitting device 21, a second light-emitting device 22, and a third light-emitting device 23 with different colors. Optionally, the first light-emitting device 21 is a red light-emitting device, the second light-emitting device 22 is a green light-emitting device, and the third light-emitting device 23 is a blue light-emitting device. Figure 2 The arrangement of the light-emitting device 20 in FIG. is only schematically shown and is not a limitation to the present invention. Figure 2 FIG. only schematically shows the arrangement of the light-emitting device 20 at a local position in the display area AA. In the embodiment of the present invention, the light-emitting device 20 is arranged in a regular array throughout the display area AA.

[0014] It can be understood that Figure 2 in FIG., it is only schematically shown that the first area A1 includes 2 rows × two columns of pixel units, and each pixel unit includes 3 sub-pixels. In an actual product, multiple rows and multiple columns of pixel units can also be provided in the first area A1, and the specific number of settings can be adjusted according to actual situations, and the present invention does not make specific limitations.

[0015] Figure 3 FIG. is a cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention. Figure 3 FIG. schematically shows the film layer structure of the display panel. As Figure 3As shown, the display panel includes a substrate 00 and a driving layer 10 located on one side of the substrate 00. The pixel circuit 11 is located in the driving layer 10, and the light-emitting device 20 is located on the side of the driving layer 10 away from the substrate 00. The light-emitting device 20 includes a stacked first electrode 24, a light-emitting layer 25, and a second electrode 26. The first electrode 24 is located on the side closer to the substrate 00 than the second electrode 26. The first electrodes 24 of the respective light-emitting devices 20 are isolated from each other, and the second electrodes 26 of the respective light-emitting devices 20 are connected to each other to form a common electrode. The display panel further includes a pixel definition layer 24 for spacing adjacent light-emitting devices 20. A packaging layer 25 is further provided on the side of the light-emitting device 20 away from the substrate 00. The packaging layer 25 is used to isolate water and oxygen and extend the service life of the light-emitting device 20. The packaging layer 25 includes at least one inorganic packaging layer and at least one organic packaging layer.

[0016] The driving layer 10 includes a plurality of inorganic layers 12, and at least one inorganic layer 12 has a hollow K. The driving layer 10 includes a semiconductor layer and a plurality of metal layers, and the inorganic layer 12 is used for film isolation between the semiconductor layer and the metal layer, and between two adjacent metal layers. In the present invention, the hollow K can also be understood as the removed area of the inorganic layer 12. In the pixel circuit 11 structure of the display panel, some structures are connected through vias penetrating the inorganic layer 12, and the inorganic layer 12 is removed at the via positions. However, it is necessary to distinguish the hollow K of this case from the vias of the inorganic layer 12 here. A metal material is filled in the vias, and no metal material is filled in the hollow K of this case, but an organic material can be filled. In addition, the area of the hollow K in this case is much larger than the area of a single via.

[0017] The first region A1 includes the hollow K. In other words, at least a part of the hollow K is located in the first region A1. Figure 2 and Figure 3 It can be seen that along the direction e perpendicular to the plane where the substrate 00 is located, the light-emitting device 20 and the hollow K at least partially overlap. Optionally, the light-emitting devices 20 and the pixel circuits 11 in the display area AA are connected in one-to-one correspondence. After the hollow K of the inorganic layer 12 is provided in the display area AA, the number of pixel circuits 11 provided is not reduced. By providing the light-emitting device 20 and the hollow K with at least partial overlap, providing the hollow K of the inorganic layer 12 in the display area AA does not affect the original arrangement manner of the light-emitting devices 20 in the display area AA.

[0018] The display area AA includes signal lines 30 located in the driving layer 10. The signal lines 30 are coupled to a plurality of pixel circuits 11, and the signal lines 30 are traces for driving the pixel circuits 11 to operate. Figure 2It can be seen that at least one signal line 30 penetrates through the first region A1 and the second region A2 in its extending direction. In an embodiment of the present invention, one signal line 30 can be made of one metal layer, or one signal line 30 includes line segments located in different metal layers. For example, the routing portion of the signal line 30 located in the first region A1 and the routing portion located in the second region A2 are in different layers.

[0019] In the display panel provided by the embodiment of the present invention, at least one inorganic layer 12 is provided with a hollow K. The first region A1 of the display region AA includes the hollow K, and the light-emitting device 20 overlaps with the hollow K in the first region A1. The pixel circuit 11 for driving the light-emitting device 20 in the first region A1 is arranged in the second region A2 of the display region AA. That is, the hollow K of the inorganic layer 12 is made at the position where the pixel circuit 11 was originally arranged in the first region A1, and the pixel circuit 11 originally required to be arranged in the first region A1 is moved to the second region A2. The first region A1 is the region where the hollow K of the inorganic layer 12 is set in the display region AA, and the second region A2 is the region where the pixel circuits 11 are centrally arranged. By locally concentrating the pixel circuits 11 in the second region A2 in the embodiment of the present invention, a position for making the hollow K of the inorganic layer 12 in the first region A1 is left. The hollow K of the inorganic layer 12 is used to cut off the inorganic layer 12 at a local position, thereby providing a buffer when stress is applied and reducing the risk of fracture of the inorganic layer 12. Moreover, when the display panel is impacted, even if cracks appear locally in the inorganic layer 12, the cracks will be stopped when they extend to the position of the hollow K, preventing the cracks from spreading to the entire display region AA, thereby improving the impact resistance. In addition, since the light-emitting device 20 is located on the side of the driving layer 10 away from the substrate 00, the hollow K of the inorganic layer 12 does not affect the manufacture of the light-emitting device 20 in the display region AA. In the embodiment of the present invention, the position and number of the light-emitting devices 20 in the display region AA can be unchanged. And by locally concentrating the pixel circuits 11 using the available layout space under the original PPI (Pixels Per Inch), the normal driving of the light-emitting device 20 in the first region A1 is ensured.

[0020] The embodiment of the present invention can be applied to some medium-sized display panels, such as in-vehicle displays. The use scenario of the in-vehicle display device is special, facing a relatively high frequency and amplitude of impact, and is prone to a relatively high problem of broken screens. By adopting the display panel provided by the embodiment of the present invention, the impact resistance of the in-vehicle display can be improved, and the display panel can still display normally when the vehicle is subjected to a large impact, ensuring that the driver can obtain the vehicle state information.

[0021] In the embodiments of the present invention, the signal line 30 includes metal. That is, the routing portions of the signal line 30 in the first region A1 and in the second region A2 are both metal lines. The signal line 30 is arranged in the display area AA and is the routing for driving the pixel circuit 11 to work. In the embodiments of the present invention, the problem of the transmittance of the display area AA is not considered, so there is no need to make special designs for the materials of the signal line 30 in the first region A1 and the second region A2.

[0022] As Figure 3 shown, an organic structure 60 is filled in the hollow K. On the one hand, since the first region A1 includes the hollow K and the first region A1 is a display region, filling the organic structure 60 in the hollow K is beneficial to the flatness of the entire display area, making the light-emitting devices 20 in the first region A1 and the light-emitting devices 20 in the second region A2 basically fabricated on the substrate surface at the same height, which is beneficial to the uniform light emission of the display panel. On the other hand, the organic structure 60 can further play a stress buffering role at the position of the hollow K, improving the impact resistance of the display panel.

[0023] As Figure 2 shown, the signal line 30 penetrating the first region A1 and the second region A2 includes a first line segment 30a and a second line segment 30b. At least part of the first line segment 30a is located in the first region A1, the second line segment 30b is located in the second region A2, and the first line segment 30a and the second line segment 30b are connected to each other. In combination Figure 3 view, the first line segment 30a is located on the side of the organic structure 60 away from the substrate 00. Fabricating the first line segment 30a after the process of filling the hollow K with the organic structure 60 can avoid directly fabricating the first line segment 30a in the hollow K and the risk of disconnection at the climbing position of the first line segment 30a in the hollow K.

[0024] In some embodiments, the first line segment 30a and the second line segment 30b of at least one signal line 30 are located in different layers. As Figure 3 shown, the connection via V1 of the first line segment 30a and the second line segment 30b is located in the second region A2. The first line segment 30a and the second line segment 30b located in different layers are connected through the via V1 to ensure reliable electrical connection performance between the two. Setting the via V1 in the second region A2 can also make the depth of the connection via V1 between the two appropriate in the direction e perpendicular to the substrate 00. Avoiding drilling holes in the relatively thick organic structure 60 in the first region A1 increases the process difficulty.

[0025] In some embodiments, the first line segment 30a and the second line segment 30b of some signal lines 30 are located in different layers, that is, the signal line 30 adopts a wire-changing design when passing from the second region A2 through the first region A1; some signal lines 30 are fabricated with one metal layer, that is, this part of the signal line 30 does not change wires when passing from the second region A2 through the first region A1.

[0026] AsFigure 3 As shown, the driving layer 10 includes a first transistor T0 and a capacitor C. The driving layer 10 includes a semiconductor layer 15, a first metal layer 16, a second metal layer 17, and a first source-drain electrode layer 18. The first metal layer 16 is located on the side of the semiconductor layer 15 away from the substrate 00, the second metal layer 17 is located on the side of the first metal layer 16 away from the substrate 00, and the first source-drain electrode layer 18 is located on the side of the second metal layer 17 away from the substrate 00; wherein, the semiconductor layer 15 includes the active layer of the first transistor T0, the first metal layer 16 includes the gate of the first transistor T0 and the first electrode plate of the capacitor C, the second metal layer 17 includes the second electrode plate of the capacitor C, and the first source-drain electrode layer 18 includes a plurality of connection structures 181, and at least some of the connection structures 181 are electrically connected to the active layer of the first transistor T0 through vias V2; Figure 3 Some of the connection structures 181 are marked, and the connection structures 181 will be further illustrated in the following embodiments of designing the layout of the pixel circuit 11. Figure 3 The first transistor T0 shown in the figure may be a transistor in the pixel circuit 11, and the capacitor C may be, for example, a storage capacitor in the pixel circuit 11.

[0027] In one embodiment, the semiconductor layer 15 includes silicon, the first metal layer 16 and the second metal layer 17 include molybdenum, the first source-drain electrode layer 18 includes titanium and aluminum, and the first source-drain electrode layer 18 is a three-layer structure of titanium / aluminum / titanium.

[0028] As Figure 3 shown, the side of the first source-drain electrode layer 18 close to the substrate 00 includes a plurality of inorganic layers 12. For example, an inorganic layer 01 is provided between the semiconductor layer 15 and the first metal layer 16, an inorganic layer 02 is provided between the first metal layer 16 and the second metal layer 17, and an inorganic layer 03 is provided between the second metal layer 17 and the first source-drain electrode layer 18. The side of the first source-drain electrode layer 18 away from the substrate 00 includes a first organic layer 13, and the first organic layer 13 is filled in the hollow K. That is, the first organic layer 13 is reused as the organic structure 60. The film layer of the first source-drain electrode layer 18 has a relatively large thickness in the direction e perpendicular to the substrate 00. Fabricating the first organic layer 13 after the process of the first source-drain electrode layer 18 can well cover the pattern structure of the first source-drain electrode layer 18 and avoid metal exposure. At the same time, the first organic layer 13 can also play a planarizing role on the first source-drain electrode layer 18, so that the structure fabricated after the process of the first source-drain electrode layer 18 is formed on a relatively flat substrate. Therefore, the thickness of the first organic layer 13 is relatively thick. In the embodiment of the present invention, using the first organic layer 13 to fill the hollow K can further play a stress buffering role at the position of the hollow K, improve the impact resistance of the display panel, and without adding new process steps.

[0029] In some embodiments, such as Figure 3As shown, the driving layer 10 further includes a second source-drain electrode layer 19 and a second organic layer 14. The second source-drain electrode layer 19 is located on the side of the first organic layer 13 away from the substrate 00, and the second organic layer 14 is located on the side of the second source-drain electrode layer 19 away from the substrate 00; within the first region A1, the second source-drain electrode layer 19 includes at least one signal line 30. In other words, at least one signal line 30 within the first region A1 is located in the second source-drain electrode layer 19. As Figure 3 shown in Figure 3 , the first segment 30a of the signal line 30 is located in the second source-drain electrode layer 19. The second source-drain electrode layer 19 can be an existing metal layer in the display panel, or it can also be a newly added metal layer to meet the wiring requirements of the signal line 30 in the first region A1. The second source-drain electrode layer 19 can be made of the same material as the first source-drain electrode layer 18. The second organic layer 14 formed on the second source-drain electrode layer 19 serves as a planarization layer, which on the one hand well covers the pattern structure within the second source-drain electrode layer 19, and on the other hand provides a flat substrate for the light-emitting device 20 formed on the driving layer 10, ensuring the brightness uniformity within the display area.

[0030] In addition, in the embodiment of the present invention, the pixel circuit 11 for driving the light-emitting device 20 within the first region A1 is disposed in the second region A2, so that no wiring and related structures in the pixel circuit 11 are provided for the semiconductor layer 15, the first metal layer 16, the second metal layer 17, and the first source-drain electrode layer 18 within the first region A1.

[0031] Figure 4 This is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. As Figure 4As shown, the pixel circuit includes a driving transistor Tm, a gate reset transistor M1, an electrode reset transistor M2, a data writing transistor M3, a threshold compensation transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, and a storage capacitor Cst. The driving transistor Tm is connected in series between the first light-emitting control transistor M5 and the second light-emitting control transistor M6. The control terminals of the gate reset transistor M1 and the electrode reset transistor M2 receive a scan signal S1. The first pole of the gate reset transistor M1 receives a reset signal Vref1, and the second pole of the gate reset transistor M1 is connected to the control terminal of the driving transistor Tm. The first pole of the electrode reset transistor M2 receives a reset signal Vref2, and the second pole of the electrode reset transistor M2 is connected to the first electrode of the light-emitting device 20. The control terminals of the data writing transistor M3 and the threshold compensation transistor M4 receive a scan signal S2. The first pole of the data writing transistor M3 receives a data signal Data, and the second pole is connected to the first pole of the driving transistor Tm. The threshold compensation transistor M4 is connected between the control terminal and the second pole of the driving transistor Tm. The control terminals of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 receive a light-emitting control signal Emit. The first pole of the first light-emitting control transistor M5 receives a first power supply voltage Pvdd, and the second electrode of the light-emitting device 20 receives a second power supply voltage Pvee. Optionally, the first power supply voltage Pvdd is a positive power supply voltage, and the second power supply voltage Pvee is a negative power supply voltage.

[0032] Figure 4 In the figure, the control terminals of the electrode reset transistor M2 and the gate reset transistor M1 receive the same signal for illustration. In some other embodiments, the control terminal of the electrode reset transistor M2 may also receive the same signal as the control terminal of the data writing transistor M3 for illustration.

[0033] Figure 4 It is illustrated that the first poles of the electrode reset transistor M2 and the gate reset transistor M1 receive different reset signals, and the voltage values of the reset signal Vref1 and the reset signal Vref2 are different. Optionally, the voltage value of the reset signal Vref2 is less than the voltage value of the reset signal Vref1. By providing a lower reset voltage to the electrode of the light-emitting device 20, the light leakage of the light-emitting device 20 can be reduced, and the low gray-scale display effect can be improved. At the same time, by providing a higher reset voltage to the gate of the driving transistor Tm, the threshold capture of the gate of the driving transistor Tm can be faster. When applied to high-frequency display or low-brightness (or gray-scale) display, the threshold capture time of the gate of the driving transistor Tm is shorter, and the faster the threshold capture of the gate of the driving transistor Tm, the more accurate the threshold capture can be, so that the display unevenness can be reduced and the display effect can be improved.

[0034] In some other embodiments, the first pole of the electrode reset transistor M2 and the first pole of the gate reset transistor M1 receive the same reset voltage. Alternatively, the first pole of the electrode reset transistor M2 and the first pole of the gate reset transistor M1 can both be electrically connected to the same reset signal line.

[0035] In some embodiments, the gate reset transistor M1 and the threshold compensation transistor M4 are dual-gate transistors.

[0036] Figure 4 Only for illustration purposes, the pixel circuit includes seven transistors and a capacitor. Embodiments of the present invention are also applicable to other pixel circuit structures.

[0037] In some embodiments, Figure 5 An embodiment of the present invention provides a pixel circuit layout. In combination with Figure 4 understand the connection relationships of the various transistors in the pixel circuit 11. Figure 5 Schematically shows three pixel circuits 11 arranged in the first direction x. In this embodiment, it is shown that the first pole of the electrode reset transistor M2 and the first pole of the gate reset transistor M1 receive the same reset signal, provided by the reset signal line Vref. In the display panel, there are arranged a first scan line Scan1 and a second scan line Scan2 extending in the first direction x, a reset signal line Vref, a light emission control line Emit, a data line Data extending in the second direction y, and a first power supply signal line Pvdd. The first direction x and the second direction y intersect. Among them, the first scan line Scan1 provides a scan signal to the control terminals of the electrode reset transistor M2 and the gate reset transistor M1, the second scan line Scan2 provides a scan signal to the control terminals of the data writing transistor M3 and the threshold compensation transistor M4, the light emission control line Emit provides a light emission control signal Emit, the data line Data provides a data signal Data, and the first power supply signal line Pvdd provides a first power supply voltage Pvdd. Among them, the first scan line Scan1, the second scan line Scan2, and the light emission control line Emit are located in the first metal layer 16, the reset signal line Vref is located in the second metal layer 17, and the data line Data and the first power supply signal line Pvdd are located in the first source-drain electrode layer 18.

[0038] Figure 5 The first connection structure 1811 is marked. The first connection structure 1811 connects the control terminals of the threshold compensation transistor M4 and the driving transistor Tm. It can be seen that the first connection structure 1811 is located in the first source-drain electrode layer 18, and the first connection structure 1811 is electrically connected to the active layer of the threshold compensation transistor M4 located in the semiconductor layer 15 through a via V2.

[0039] In some other embodiments, Figure 6Another pixel circuit layout provided by the embodiment of the present invention. In combination with Figure 4 understand the connection relationships of the transistors in the pixel circuit 11. Figure 6 Schematically shows three pixel circuits 11 arranged in the first direction x. In this embodiment, it is shown that the first pole of the electrode reset transistor M2 and the first pole of the gate reset transistor M1 receive different reset signals. In the display panel, a first scan line Scan1, a second scan line Scan2, a third scan line Scan3, a first reset signal line Vref1, a second reset signal line Vref2, an emission control line Emit extending in the first direction x, a data line Data and a first power supply signal line Pvdd extending in the second direction y are arranged. The first scan line Scan1 provides a scan signal to the control terminal of the gate reset transistor M1, the second scan line Scan2 provides a scan signal to the control terminals of the data writing transistor M3 and the threshold compensation transistor M4, and the third scan line Scan3 provides a scan signal to the control terminal of the electrode reset transistor M2. The emission control line Emit provides an emission control signal Emit, the data line Data provides a data signal Data, and the first power supply signal line Pvdd provides a first power supply voltage Pvdd. The first reset signal line Vref1 provides a reset signal Vref1, and the second reset signal line Vref2 provides a reset signal Vref2. Figure 6 Schematically shows that a power supply auxiliary line FP is further arranged in the display panel, and the power supply auxiliary line FP is cross-connected to the first power supply signal line Pvdd.

[0040] Figure 6 The embodiment shows that the first scan line Scan1, the second scan line Scan2 and the third scan line Scan3 are located in the first source-drain electrode layer 18, and the gates of the transistors connected to these scan lines are located in the first metal layer 16. Taking the gate reset transistor M1 as an example, as Figure 6 shows, the gate M1g (i.e., the control terminal) of the gate reset transistor M1 is located in the first metal layer 16, and the gate M1g is electrically connected to the first scan line Scan1 through a via. The sheet resistance of the first source-drain electrode layer 18 is smaller than that of the first metal layer 16. Making the scan line in the first source-drain electrode layer 18 can reduce the voltage drop on the scan line and improve the display uniformity.

[0041] Figure 6 The embodiment shows that the first reset signal line Vref1, the second reset signal line Vref2 and the emission control line Emit are located in the first metal layer 16, the power supply auxiliary line FP is located in the first source-drain electrode layer 18, and the data line Data and the first power supply signal line Pvdd are located in the second source-drain electrode layer 19.

[0042] Figure 6The first connection structure 1811 and the second connection structure 1812 located in the first source-drain electrode layer 18 are indicated. The first connection structure 1811 connects the threshold compensation transistor M4 and the control end of the driving transistor Tm, and the second connection structure 1812 connects the signal output end of the pixel circuit 11 and the first electrode of the light-emitting device 20.

[0043] In some embodiments, the length of the display area AA of the display panel in the first direction x is relatively large, such as the number of pixel circuits 11 connected to a scan line in a medium-sized display panel is relatively large. Figure 6 The design of the embodiment sets three scan lines for one pixel circuit row, and the three scan lines drive the gate reset transistor M1, the data write transistor M3 and the electrode reset transistor M2 in the pixel circuit 11 respectively, which can ensure the driving ability of the scan line, reduce the voltage drop on the scan line, and improve the display uniformity.

[0044] Understandably, reference Figure 5 and Figure 6 The first reset signal line Vref1 and the second reset signal line Vref2 may also be arranged to be parallel to the extending direction of the data line Data, and may further be located in the same film layer as the data line Data.

[0045] In some embodiments, Figure 3 As shown, the inorganic layer 12 includes a first inorganic layer 121 and a second inorganic layer 122, and the first inorganic layer 121 and the second inorganic layer 122 respectively include a hollow K. The first inorganic layer 121 and the second inorganic layer 122 are in contact with each other in a partial area of ​​the display area AA, and the first inorganic layer 121 and the second inorganic layer 122 are two adjacent inorganic layers, that is, the hollow K of the first inorganic layer 121 and the hollow K of the second inorganic layer 122 are superimposed on each other to form a hollow with a greater depth along the direction e. Figure 3 The inorganic layer 01 between the semiconductor layer 15 and the first metal layer 16 is the first inorganic layer 121, and the inorganic layer 02 between the first metal layer 16 and the second metal layer 17 is the second inorganic layer 122. Figure 3 It can be seen that the edge of the hollow K of the first inorganic layer 121 and the edge of the hollow K of the second inorganic layer 122 form a step. Figure 3 It is shown that the inner wall of the hollow K is perpendicular to the plane of the substrate 00. When the organic structure 60 is filled in the hollow K, the step design can increase the contact area between the organic structure 60 and the inorganic layer, thereby enhancing the bonding strength between the two and improving the mechanical stability of the display panel.

[0046] In other embodiments, Figure 7 Another cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention. Figure 7As shown, the first inorganic layer 121 and the second inorganic layer 122 each include a hollow K. In a partial area of the display area AA, the first inorganic layer 121 and the second inorganic layer 122 are in contact with each other. The edges of the first inorganic layer 121 and the second inorganic layer 122 near the hollow K both include inclined surfaces. That is, the inner wall of the hollow K is a surface inclined relative to the substrate 00. Such a setting can increase the contact area between the organic structure 60 and the inorganic layer, thereby enhancing the bonding strength between the two and improving the mechanical stability of the display panel.

[0047] In some embodiments, such as Figure 2 As shown in the top view, the shape of the hollow K is rectangular. It can be understood that Figure 2 In the embodiment, the edge of the projection of the hollow K on the plane where the substrate 00 is located is a straight line.

[0048] In other embodiments, the edge of the projection of the hollow K on the plane where the substrate 00 is located is a curve. Figure 8 This is a top view of a hollow pattern provided by an embodiment of the present invention, Figure 8 Only the top view of one hollow K in the inorganic layer 12 is shown. The edge B1 is the hollow edge formed on the surface of the inorganic layer 12 on the side close to the substrate 00, and the edge B2 is the hollow edge formed on the surface of the inorganic layer 12 on the side far from the substrate 00. It can be understood that Figure 8 In the embodiment, the inner wall of the hollow K is a surface inclined relative to the substrate 00. Figure 8 In the embodiment, the edge of the projection of the hollow K on the plane where the substrate 00 is located is a curve. Such a setting can further improve the impact resistance of the display panel.

[0049] In some embodiments, the edge of the projection of the hollow K on the plane where the substrate 00 is located is a wavy line.

[0050] In some embodiments, such as Figure 2 As shown, the display panel includes a first connection line 41. One end of the first connection line 41 is coupled to the light-emitting device 20 located in the first area A1, and the other end is coupled to the pixel circuit 11 located in the second area A2. Combining Figure 3From the perspective of the schematic display panel film layer structure, the driving layer 10 includes a first organic layer 13, and the light-emitting device 20 is located on the side of the first organic layer 13 away from the substrate 00; the light-emitting device 20 includes a stacked first electrode 24, a light-emitting layer 25, and a second electrode 26, and the first electrode 24 is located on the side of the second electrode 26 close to the substrate 00. Among them, the first connection line 41 is located on the side of the first organic layer 13 away from the substrate 00. The first connection line 41 is introduced from the second region A2 to the first region A1. Considering the solution of filling the first organic layer 13 in the hollow K, setting the first connection line 41 on the side of the first organic layer 13 away from the substrate 00 can fabricate the first connection line 41 on a relatively flat substrate. On the one hand, it avoids breakage of the first connection line 41 due to climbing at the edge of the hollow K when wiring in the hollow K. On the other hand, it can also reduce the distance between the first connection line 41 and the light-emitting device 20 in the direction e perpendicular to the substrate 00, reducing the connection difficulty between the two.

[0051] In some embodiments, at least a partial segment of at least one first connection line 41 is on the same layer as the first electrode 24. The first connection line 41 extends from the first region A1 to the second region A2 to connect the corresponding pixel circuit 11. By setting the first connection line 41 and the first electrode 24 on the same layer, the first connection line 41 and the first electrode 24 can be fabricated in the same process and electrically connected. There is no need to make a hole in the first region A1 to connect the first connection line 41 and the first electrode 24, and the process is relatively simple.

[0052] In some embodiments, at least a partial segment of the first connection line 41 located in the first region A1 is on the same layer as the first electrode 24.

[0053] In other embodiments, at least a partial segment of at least one first connection line 41 is located in the first source-drain electrode layer 18. In other embodiments, at least a partial segment of at least one first connection line 41 is located in the second source-drain electrode layer 19. In application, the film layer where the first connection line 41 is located can be designed according to the wiring position of the first connection line 41. For example, when two first connection lines 41 cross during wiring, in order to avoid short circuit, one of the first connection lines 41 can be redesigned for wire replacement. For example, the first connection line 41 with wire replacement design includes a segment on the same layer as the first electrode 24 and also includes a segment located in the first source-drain electrode layer 18 (or the second source-drain electrode layer 19).

[0054] Such as Figure 2As shown, the display panel includes a second connection line 42, and the second connection line 42 is located in the second region A2. In the second region A2, at least one light-emitting device 20 and the pixel circuit 11 coupled thereto do not overlap in the direction perpendicular to the plane of the substrate 00, and the light-emitting device 20 is electrically connected to the pixel circuit 11 through the second connection line 42. In the embodiment of the present invention, the pixel circuit 11 for driving the light-emitting device 20 in the first region A1 is disposed in the second region A2, and the pixel circuit 11 for driving the light-emitting device 20 in the second region A2 is also disposed in the second region A2. Therefore, the pixel circuits 11 in the second region A2 are arranged relatively closely, such that some of the light-emitting devices 20 and the pixel circuits 11 connected thereto do not overlap. At this time, the two need to be electrically connected through the second connection line 42. Optionally, at least one second connection line 42 is arranged on the same layer as the first connection line 41. The second connection line 42, the first connection line 41, and the first electrode 24 are on the same layer. In the second region A2, there is sufficient wiring space in the film layer where the first electrode 24 is located. Arranging the second connection line 42 on the same layer as the first electrode 24 can facilitate the electrical connection between the second connection line 42 and the light-emitting device 20, and does not affect the wiring of the pixel circuit 11.

[0055] In some other embodiments, at least a part of at least one second connection line 42 is located in the first source-drain electrode layer 18. In some other embodiments, at least a part of at least one second connection line 42 is located in the second source-drain electrode layer 19.

[0056] In some embodiments, in combination with Figure 5 and Figure 6 it can be seen that the display area AA includes scan lines extending in the first direction x. Figure 5 It is schematically shown that the scan lines include a first scan line Scan1 and a second scan line Scan2. Figure 6 It is schematically shown that the scan lines include a first scan line Scan1, a second scan line Scan2, and a third scan line Scan3. In the display panel, the first region A1 and the second region A2 are arranged adjacent to each other in the first direction x.

[0057] Figure 9 This is another partial schematic diagram of the display panel provided by the embodiment of the present invention, schematically showing the partial position of the display area AA. As Figure 9 shown, the first region A1 and the second region A2 are adjacent to each other in the first direction x; in the second region A2, a plurality of pixel circuits 11 are arranged in the first direction x. The scan line Scan extending in the first direction x penetrates the first region A1 and the second region A2, and one scan line Scan is electrically connected to a plurality of pixel circuits 11 arranged in the first direction x. That is, the signal line 30 includes the scan line Scan, and the scan line Scan includes a first line segment 30a and a second line segment 30b. In combination with Figure 5 and Figure 6From the perspective of the layout diagram, the layout of the pixel circuit 11 is generally strip-shaped, and its length in the first direction x is less than its length in the second direction y. In order to ensure the driving ability of the driving transistor Tm, there are requirements for the channel width-to-length ratio of the driving transistor Tm, so the occupied area of the driving transistor Tm is relatively large. In order to cooperate with the connection of the driving transistor Tm, when arranging and designing the pixel circuit 11, its length in the first direction x is relatively easier to be compressed and designed. In the embodiment of the present invention, the first region A1 and the second region A2 are arranged adjacent to each other in the first direction x, and the pixel circuit 11 for driving the light-emitting device 20 in the first region A1 is arranged in the second region A2. It is easier to realize the close arrangement of the pixel circuit 11 in the second region A2.

[0058] In some embodiments, Figure 10 Another schematic diagram of the display panel provided by the embodiment of the present invention is shown in Figure 10 As shown, in the display area AA, the first region A1 and the second region A2 are arranged alternately in the first direction x. In the first region A1, the inorganic layer has a hollow K. This embodiment forms a plurality of strip-shaped inorganic layer removal areas in the display area AA. When the display panel is impacted, the hollow K is used to buffer the stress borne by the inorganic layer, reducing the risk of the inorganic layer breaking. In addition, when a crack appears in the inorganic layer in the second region A2 under impact, the crack will stop at the position of the hollow K in the first region A1 when conducting along the first direction x, preventing the crack from conducting to the adjacent second region A2, thereby further improving the overall impact resistance of the display panel.

[0059] In some embodiments, as Figure 9As shown in the figure, the display panel includes a first connection line 41. One end of the first connection line 41 is coupled to the light-emitting device 20 located in the first area A1, and the other end is coupled to the pixel circuit 11 located in the second area A2. The first area A1 is located between two second areas A2 adjacent in the first direction x. Among the multiple first connection lines 41 connected to the multiple light-emitting devices 20 in the first area A1, some first connection lines 41 extend to the second area A2 on one side of the first area A1, and some first connection lines 41 extend to the second area A2 on the other side. That is, the multiple light-emitting devices 20 in the first area A1 are respectively wired to the pixel circuits 11 in the two second areas A2 on both sides in the left and right directions. When the length of the first area A1 in the first direction x is determined, or when the width of the hollow K in the first direction x is determined, the design of the embodiment of the present invention is equivalent to dispersing the multiple pixel circuits 11 connected to the multiple light-emitting devices 20 in the first area A1 in the two second areas A2. On the one hand, it is beneficial to reduce the misalignment distance between the light-emitting device 20 in the first area A1 and the pixel circuit 11 connected thereto in the first direction x, thereby facilitating the reduction of the wiring length of the first connection line 41 and reducing the voltage drop. On the other hand, the number of first connection lines 41 introduced from the first area A1 to one second area A2 is reduced, which can reduce the wiring space for arranging the first connection line 41 on one side of the first area A1 in the first direction x and reduce the wiring difficulty of the first connection line 41.

[0060] In some embodiments, as Figure 9 shown, among the multiple first connection lines 41 connected to the multiple light-emitting devices 20 in the first area A1, the number of first connection lines 41 extending to the second areas A2 on both sides of the first area A1 is equal. As Figure 9 schematically shown in the figure, in a circuit row where the pixel circuits 11 are arranged in the first direction x, three first connection lines 41 in the first area A1 are connected to the second area A2 on the left side, and three first connection lines 41 are connected to the second area A2 on the right side. Such an arrangement can reduce the length difference of the first connection lines 41 wired to both sides of the first area A1, making the voltage drop difference on the first connection lines 41 small, which is beneficial to improving the display uniformity.

[0061] In other embodiments, Figure 11 is another partial schematic diagram of the display panel provided by the embodiment of the present invention. As Figure 11 shown, the display panel includes a first connection line 41. One end of the first connection line 41 is coupled to the light-emitting device 20 located in the first area A1, and the other end is coupled to the pixel circuit 11 located in the second area A2; the multiple first connection lines 41 connected to the multiple light-emitting devices 20 in the first area A1 extend to the second area A2 on the same side of the first area A1. This embodiment can make the wiring in the display area AA more regular. As Figure 11Two first regions A1 and two second regions A2 are schematically shown. Adjacent first region A1 and second region A2 form a group. The wiring patterns of the first connection lines 41 and the pixel circuit 11 layout patterns in the two groups are the same, which can improve the etching uniformity during the production of the display panel, and further improve the display uniformity.

[0062] In some embodiments, Figure 12 Another partial schematic diagram of the display panel provided by the embodiment of the present invention is Figure 12 in which the pixel circuit 11 is schematically shown in the Figure 6 schematic pixel circuit layout. As Figure 12 shown, the signal line 30 penetrates through the first region A1 and the second region A2 in its extending direction. The signal line 30 includes a first line segment 30a and a second line segment 30b that are electrically connected. At least part of the first line segment 30a is located in the first region A1, and the second line segment 30b is located in the second region A2; the signal line 30 includes a first signal line 31 extending along the first direction x; wherein, the first line segment 30a and the second line segment 30b of the first signal line 31 are on different layers. The first signal line 31 includes a first scan line Scan1, a second scan line Scan2, a third scan line Scan3, a first reset signal line Vref1, a second reset signal line Vref2, and a light emission control line Emit. Taking the first reset signal line Vref1 as an example, it can be seen from Figure 12 that the first line segment 30a of the first reset signal line Vref1 is located in the second source-drain electrode layer 19, and the second line segment 30b of the first reset signal line Vref1 is located in the first metal layer 16. It can be seen that the first line segment 30a and the second line segment 30b of the first reset signal line Vref1 are on different layers.

[0063] Combined with the Figure 3 schematic display panel film layer structure, the first metal layer 16, the second metal layer 17, and the first source-drain electrode layer 18 are all located on the side of the first organic layer 13 close to the substrate 00, that is, the first organic layer 13 is fabricated after the process of the first source-drain electrode layer 18. In the embodiment of the present invention, in order to avoid the risk of signal line climbing and breaking due to fabricating the signal line inside the hollow K of the inorganic layer 12, the signal line 30 in the first region A1 is arranged on the side of the first organic layer 13 away from the substrate 00. Therefore, the first line segment 30a of the signal line 30 located in the first region A1 needs to be fabricated after the process of the first organic layer 13, so that the first signal line 31 extending along the first direction x adopts a wire-changing design to ensure that the first signal line 31 penetrates through the first region A1 and the second region A2 in its extending direction.

[0064] Figure 12 The first line segment 30a of the first signal line 31 is schematically shown in the second source-drain electrode layer 19. In other embodiments, a new metal layer can also be added to fabricate the first line segment 30a of the first signal line 31.

[0065] In some other embodiments, first segments 30a of a plurality of first signal lines 31 are arranged in two metal layers to avoid over-concentration of connection vias between the first segment 30a and the second segment 30b caused by in-layer fabrication.

[0066] Figure 12 It is shown that the second electrode plate C2 of the storage capacitor Cst located in the second metal layer 17 is electrically connected through a line segment 30a1 spanning the first region A1, and the line segment 30a1 is in the same layer as the first line segment 30a. In this way, the second electrode plates C2 in two adjacent second regions A2 in the first direction x are electrically connected to each other, which can further reduce the voltage drop of the transmitted power signal and improve the in-plane uniformity.

[0067] In some other embodiments, a power supply auxiliary line FP extending in the first direction x and a first power supply voltage Pvdd extending in the second direction y are arranged in the display panel. The power supply auxiliary line FP is connected to the first power supply voltage Pvdd through a via, and the power supply auxiliary line FP is electrically connected to the second electrode plate C2 of the storage capacitor Cst located in the second metal layer 17 through a via. The power supply auxiliary line FP and the first power supply signal line Pvdd are electrically connected in a horizontal and vertical cross manner, which can reduce the voltage drop of the transmitted power signal. Then, a line segment connecting the second electrode plates C2 in the two second regions A2 may not be provided in the first region A1, which can reduce the wiring density in the first region A1.

[0068] In some embodiments, Figure 13 Another partial schematic diagram of a display panel provided by an embodiment of the present invention. As Figure 13 shown, at least one first region A1 is located between two adjacent second regions A2 in the first direction x, and the first region A1 is located between two adjacent second regions A2 in the second direction y, and the second direction y intersects with the first direction x. In this embodiment, second regions A2 are arranged around the first region A1, and the inorganic layer hollow K in the first region A1 is used to buffer the stress borne in its surrounding directions. In addition, the hollow K in the first region A1 can also block the inorganic layer cracks extending from the second region A2 to the first region A1 in the first direction x and the inorganic layer cracks extending from the second region A2 to the first region A1 in the second direction y, and can block the cracks extending in multiple directions, improving the impact resistance of the display panel.

[0069] As Figure 13As shown, the signal line 30 includes a first signal line 31 extending along the first direction x and a second signal line 32 extending along the second direction y; in the first region A1, the first signal line 31 and the second signal line 32 are insulated and cross each other. In the first region A1, the first signal line 31 electrically connects the lines on both sides of the first direction x in the first region A1, and in the first region A1, the second signal line 32 electrically connects the lines on both sides of the second direction y in the first region A1. For example, the first signal line 31 includes a first scan line Scan1, a second scan line Scan2, a third scan line Scan3, a first reset signal line Vref1, a second reset signal line Vref2, and a light emission control line Emit, and the second signal line 32 includes a data line Data and a first power supply signal line Pvdd.

[0070] In some embodiments, such as Figure 13 As shown, the signal line 30 includes an electrically connected first segment 30a and a second segment 30b. At least part of the first segment 30a is located in the first region A1, and the second segment 30b is located in the second region A2. Among them, the first segment 30a and the second segment 30b of the first signal line 31 are located in different layers; the first segment 30a and the second segment 30b of the second signal line 32 are located in the same layer. Combining Figure 3 Looking at the schematic film layer structure, the second segment 30b of the first signal line 31 located in the second region A2 can be fabricated in the manufacturing process of the first transistor T0 and the capacitor C in the driving layer 10. By setting the first segment 30a and the second segment 30b of the first signal line 31 in different layers, the first segment 30a of the first signal line 31 can be fabricated on the side of the first organic layer 13 away from the substrate 00, which can avoid the first signal line 31 from breaking due to climbing in the hollow K. In addition, for the second signal line 32, by setting the data line Data and the first power supply signal line Pvdd in the second source-drain electrode layer 19, and the second source-drain electrode layer 19 is located on the side of the first organic layer 13 away from the substrate 00. Since there is no transistor structure of the pixel circuit in the first region A, the second signal line 32 does not need to adopt a wire-changing design when extending from the second region A2 to the first region A1 along the second direction y, that is, the first segment 30a and the second segment 30b of the second signal line 32 can be set in the same layer, which can reduce the number of holes punched in the insulating layer in the second region A2 and save the space occupied by wiring in the second region A2.

[0071] In some embodiments, the first segment 30a of the first signal line 31 is located in the third metal layer 201, and the first segment 30a of the second signal line 32 is located in the second source-drain electrode layer 19. The third metal layer 201 is a newly added metal layer in the display panel, and the third metal layer 201 is located on the side of the second source-drain electrode layer 19 close to the substrate 00, or the third metal layer 201 is located on the side of the second source-drain electrode layer 19 away from the substrate 00.

[0072] In some other embodiments, the first signal line 31 and the second signal line 32 are insulatively crossed within the first region A1. The first segment 30a and the second segment 30b of the first signal line 31 are located on different layers, and the first segment 30a and the second segment 30b of the second signal line 32 are located on different layers. No schematic diagram is provided in the accompanying drawings here.

[0073] In some embodiments, Figure 14 This is another schematic diagram of a display panel provided by an embodiment of the present invention. As Figure 14 shown, within the display area AA, the first region A1 and the second region A2 are alternately arranged in the first direction x, and the first region A1 and the second region A2 are alternately arranged in the second direction y. The first region A1 and the second region A2 are staggered within the display area AA to form an arrangement similar to a chessboard pattern. In this embodiment, the hollow-out K within the first region A1 is uniformly arrayed within the display area AA. The second region A2 is surrounded by the first region A1 on all four sides, and the stress borne by the inorganic layer within the second region A2 can be dispersed in four directions, effectively reducing the risk of fracture of the inorganic layer. Moreover, the hollow-out K within the four first regions A1 in the four directions can cooperate to block the cracks of the inorganic layer extending from the second region A2 along the first direction x to the first region A1, and can also block the cracks of the inorganic layer extending from the second region A2 along the second direction y to the first region A1, and can block the cracks extending in multiple directions, improving the impact resistance of the display panel.

[0074] The above embodiment describes the solution in which the first region A1 within the display area AA includes the hollow-out K of the inorganic layer 12. In some embodiments of the present invention, a hollow-out K of the inorganic layer 12 is further provided within the non-display area NA.

[0075] In some embodiments, Figure 15 This is another schematic diagram of a display panel provided by an embodiment of the present invention. As Figure 15 shown, the display panel further includes a shift register unit 50, and the shift register unit 50 is located within the non-display area NA; the shift register unit 50 includes a first shift register unit 51, and a plurality of first shift register units 51 are cascaded. A hollow-out K is provided on the side of the first shift register unit 51 close to the display area AA. The shift register unit 50 can be any circuit structure in the prior art that can implement the signal shift function. Figure 15 In the embodiment, only a simplified schematic illustration of the shift register unit 50 is made.

[0076] Figure 15The schematic display area AA is provided with first shift register units 51 on both sides in the first direction x. In the non-display area NA on one side of the display area AA, a plurality of first shift register units 51 are arranged along the second direction y. In the display area AA, a gate line X extending along the first direction x is provided. The gate line X is electrically connected to the output ends of the first shift register units 51, and the gate line X is connected to a plurality of pixel circuits arranged in the first direction x. The gate line X can be Figure 6 any one of the first scan line Scan1, the second scan line Scan2, the third scan line Scan3, and the emission control line Emit schematically shown in the embodiment. Figure 15 The arrangement of the first area A1 and the second area A2 in the display area AA is not shown, nor is the pixel circuit shown. Figure 15 In the embodiment, the first area A1 and the second area A2 can be designed as Figure 10 or Figure 14 performed.

[0077] In the embodiment of the present invention, at least one inorganic layer 12 is provided in the area between the first shift register unit 51 and the display area AA, and has a hollow K. The hollow K disconnects the inorganic layer at the position of the first shift register unit 51 and the inorganic layer in the display area AA. When the display panel bears stress, the hollow K provided in the non-display area NA provides stress buffering. Moreover, the cracks that appear locally in the inorganic layer will not extend from the position of the first shift register unit 51 to the display area AA, nor will they extend from the display area AA to the position of the first shift register unit 51, thereby further improving the impact resistance of the display panel.

[0078] In addition, as Figure 15 schematically shown, a third connection line 43 located in the non-display area NA connects the output end of the first shift register unit 51 and the gate line X located in the display area AA. From Figure 15 the top view, it can be seen that along the direction perpendicular to the plane of the substrate 00, the third connection line 43 overlaps with the hollow K. Optionally, a first organic layer 13 as Figure 3 schematically shown is filled in the hollow K, and the third connection line 43 is located on the side of the first organic layer 13 away from the substrate 00.

[0079] Figure 15 Schematically shows that a long strip-shaped hollow K is provided in the non-display area NA, and the hollow K is adjacent to a plurality of cascaded first shift register units 51. In some other embodiments, Figure 16 This is another schematic diagram of the display panel provided by the embodiment of the present invention. As Figure 16 shown, in the non-display area NA on one side of the display area AA in the first direction x, a plurality of hollow Ks arranged along the first direction x are provided between the cascaded first shift register units 51 and the display area AA.

[0080] Figure 17 Another schematic diagram of a display panel provided by an embodiment of the present invention Figure 17 mainly shows the setting manner of a plurality of shift register units 50 in the non-display area NA of the display panel. As Figure 17 shown, the shift register unit 50 includes a first scan shift register unit 50-Scan1, a second scan shift register unit 50-Scan2, a third scan shift register unit 50-Scan3, and a light-emitting shift register unit 50-Emit. Combining Figure 6 to see, the output end of the first scan shift register unit 50-Scan1 is connected to the first scan line Scan1, the output end of the second scan shift register unit 50-Scan2 is connected to the second scan line Scan2, the output end of the third scan shift register unit 50-Scan3 is connected to the third scan line Scan3, and the output end of the light-emitting shift register unit 50-Emit is connected to the light-emitting control line Emit. In the non-display area NA on one side of the display area AA, the third scan shift register unit 50-Scan3, the second scan shift register unit 50-Scan2, the first scan shift register unit 50-Scan1, and the light-emitting shift register unit 50-Emit are arranged away from the display area AA in sequence.

[0081] Figure 17 schematically shows the nth pixel circuit row 11H(n), the (n + 1)th pixel circuit row 11H(n + 1), and the (n + 2)th pixel circuit row 11H(n + 2) in the display area AA, where n is a positive integer. A plurality of pixel circuits 11 are arranged in a pixel circuit row 11H in the first direction x. A group of the second scan shift register unit 50-Scan2, the first scan shift register unit 50-Scan1, the third scan shift register unit 50-Scan3, and the light-emitting shift register unit 50-Emit drive one pixel circuit row.

[0082] As Figure 17 shown, a hollow K is provided between the third scan shift register unit 50-Scan3 and the display area AA. The third scan shift register unit 50-Scan3 is equivalent to Figure 15 the first shift register unit 51 in the embodiment. In other words, the first shift register unit 51 includes the third scan shift register unit 50-Scan3.

[0083] In an embodiment of the present invention, the first shift register unit 51 includes any one of the second scan shift register unit 50-Scan2, the first scan shift register unit 50-Scan1, the third scan shift register unit 50-Scan3, and the light-emitting shift register unit 50-Emit.

[0084] In some embodiments, Figure 18Another partial schematic diagram of the display panel provided by the embodiment of the present invention. As Figure 18 shown, a plurality of first shift register units 51 are arranged and cascaded in the second direction y; along the arrangement direction of the first shift register units 51, a hollow K is provided between two adjacent first shift register units 51. In this embodiment, a hollow K is provided on the side of the first shift register unit 51 close to the display area AA, and a hollow K is provided between two adjacent first shift register units 51. That is, stress buffer structures are provided at positions adjacent to the first shift register unit 51 in the first direction x and adjacent positions in the second direction y, which can better disperse the stress around the first shift register unit 51, better protect the first shift register unit 51 when the display panel is impacted, and improve the impact resistance of the display panel.

[0085] Figure 18 It is shown in that the hollow K provided on the side of the first shift register unit 51 close to the display area AA and the hollow K provided between two adjacent first shift register units 51 are not connected. In some other embodiments, the hollow K provided on the side of the first shift register unit 51 close to the display area AA and the hollow K provided between two adjacent first shift register units 51 are interconnected, which is not shown here.

[0086] As Figure 18 shown, a cascade signal line 44 is connected between two adjacent stages of the first shift register units 51. It can be seen from the top view that the cascade signal line 44 overlaps with the hollow K. Optionally, a first organic layer 13 as Figure 3 shown is filled in the hollow K, and the cascade signal line 44 is located on the side of the first organic layer 13 away from the substrate 00. Such a setting can avoid the cascade signal line 44 climbing and breaking in the hollow K, ensuring the transmission of the cascade signal.

[0087] In some embodiments, Figure 19 Another partial schematic diagram of the display panel provided by the embodiment of the present invention, as Figure 19 shown, the shift register unit 50 includes a second shift register unit 52, and the second shift register unit 52 is located on the side of the first shift register unit 51 away from the display area AA; a hollow K is provided between the first shift register unit 51 and the second shift register unit 52. In this embodiment, the hollow K can play a role in buffering stress between the first shift register unit 51 and the second shift register unit 52, and can block the crack generated after the inorganic layer is impacted from conducting between the first shift register unit 51 and the second shift register unit 52, thereby ensuring the electrical stability of the first shift register unit 51 and the second shift register unit 52 respectively, and further improving the impact resistance of the display panel.

[0088] From Figure 19It can be seen that at least a part of the lead wire 45 connected to the output end of the second shift register unit 52 overlaps with the hollow K. Optionally, the first organic layer 13 fills the hollow K, and at least a part of the lead wire 45 is arranged on the side of the first organic layer 13 away from the substrate 00, which can further improve the impact resistance and avoid breakage of the lead wire 45 caused by climbing in the hollow K.

[0089] Combined with Figure 17 In the embodiment, the first shift register unit 51 can be, for example, the third scan shift register unit 50-Scan3, and the second shift register unit 52 is the second scan shift register unit 50-Scan2. Alternatively, the first shift register unit 51 is the first scan shift register unit 50-Scan1, and the second shift register unit 52 is the light-emitting shift register unit 50-Emit.

[0090] In some embodiments, the circuit structures of the first shift register unit 51 and the second shift register unit 52 are the same.

[0091] In other embodiments, the circuit structures of the first shift register unit 51 and the second shift register unit 52 are different. For example, the first shift register unit 51 includes any one of the first scan shift register unit 50-Scan1, the second scan shift register unit 50-Scan2, and the third scan shift register unit 50-Scan3, and the second shift register unit 52 includes the light-emitting shift register unit 50-Emit. Both the first shift register unit 51 and the second shift register unit 52 have the function of signal shifting, but the number of transistors and / or the number of capacitors included in the two are different.

[0092] In some embodiments, Figure 20 Another partial schematic diagram of the display panel provided by the embodiment of the present invention is shown as Figure 20 shown. The shift register unit 50 includes a first shift register unit 51 and a second shift register unit 52, and is illustrated with the length of the second shift register unit 52 in the second direction y being greater than the length of the first shift register unit 51 in the second direction y. The display area AA includes data lines Data, and the data lines Data are located in the driving layer 10 and extend along the second direction y. The hollow K includes a first hollow K1, and the first hollow K1 is located between the first shift register unit 51 and the second shift register unit 52. Figure 20It can be seen that in the second direction y extending along the data line Data, the length of the first hollow K1 is greater than the length of the first shift register unit 51. Such a setting can buffer the stress borne within the length range of the first shift register unit 51 in the second direction y by means of the first hollow K1, and can effectively block the cracks in the inorganic layer on one side of the first shift register unit 51, preventing the cracks in the inorganic layer from extending from the first shift register unit 51 towards the direction where the second shift register unit 52 is located, thereby enhancing the impact resistance of the display panel.

[0093] In some other embodiments, Figure 21 is another partial schematic diagram of the display panel provided by an embodiment of the present invention. As Figure 21 shown, the shift register unit 50 includes a first shift register unit 51 and a second shift register unit 52, and is illustrated with the length of the second shift register unit 52 in the second direction y being greater than the length of the first shift register unit 51 in the second direction y. The hollow K includes a second hollow K2, and the second hollow K2 is located between the first shift register unit 51 and the second shift register unit 52. It can be Figure 21 seen that in the second direction y extending along the data line Data, the length of the second hollow K2 is greater than the length of the second shift register unit 52. Such a setting can buffer the stress within the length range of the second shift register unit 52 in the second direction y by means of the second hollow K2, and can effectively block the cracks in the inorganic layer on one side of the second shift register unit 52. It can not only prevent the cracks in the inorganic layer from extending from the second shift register unit 52 towards the direction where the first shift register unit 51 is located, but also prevent the cracks in the inorganic layer from extending from the first shift register unit 51 towards the direction where the second shift register unit 52 is located, effectively enhancing the impact resistance of the display panel.

[0094] In some embodiments, a plurality of hollows K are provided between the cascaded multiple first shift register units 51 and the cascaded multiple second shift register units 52. As Figure 21 shown, in the arrangement direction of the cascaded multiple shift register units 50, one hollow K is provided between each adjacent first shift register unit 51 and second shift register unit 52.

[0095] In some other embodiments, a plurality of hollows K are provided between the cascaded multiple first shift register units 51 and the cascaded multiple second shift register units 52. As Figure 19 shown, the length of the hollow K in the second direction y is greater than the length of two or three second shift register units 52 in the second direction y.

[0096] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 22 is a schematic diagram of a display device provided by an embodiment of the present invention. As Figure 22As shown in the figure, the display device includes the display panel 100 provided in any embodiment of the present invention. The structure of the display panel has been described in the above embodiments and will not be elaborated here. The display device provided by the embodiments of the present invention may also be a vehicle-mounted display device. The display device provided by the embodiments of the present invention may also be an electronic device with a display function, such as a tablet, a mobile phone, a computer, a television, etc.

[0097] The foregoing are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of protection of the present invention.

[0098] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a substrate, a driving layer located on one side of the substrate, and light-emitting devices. The driving layer includes a plurality of inorganic layers, and at least one of the inorganic layers has a hollow-out; The display panel includes a display area, the display area includes a first area and a second area, and the first area includes the hollow-out; The first area includes the light-emitting devices. Along a direction perpendicular to the plane of the substrate, the light-emitting devices and the hollow-out at least partially overlap; the second area includes the light-emitting devices and pixel circuits located in the driving layer, and the pixel circuits coupled to the light-emitting devices in the first area are located in the second area; The display area includes signal lines located in the driving layer. The signal lines are coupled to a plurality of the pixel circuits, and at least one of the signal lines penetrates through the first area and the second area in its extending direction.

2. The display panel according to claim 1, wherein The signal lines include metal.

3. The display panel according to claim 1, wherein The edge of the projection of the hollow-out on the plane of the substrate is a straight line or a curve.

4. The display panel according to claim 1, wherein The inorganic layer includes a first inorganic layer and a second inorganic layer, and the first inorganic layer and the second inorganic layer respectively include the hollow-out; In a partial area of the display area, the first inorganic layer and the second inorganic layer are in contact, and the edge of the hollow-out of the first inorganic layer and the edge of the hollow-out of the second inorganic layer form a step; Or, the edges of the first inorganic layer and the second inorganic layer close to the hollow-out both include inclined surfaces.

5. The display panel according to claim 1, wherein The signal lines include electrically connected first line segments and second line segments. At least part of the first line segments is located in the first area, and the second line segments are located in the second area; At least one of the first line segments and the second line segments of the signal lines is located in different layers, and the connection vias of the first line segments and the second line segments are located in the second area.

6. The display panel according to claim 1, wherein The hollow-out is filled with an organic structure.

7. The display panel according to claim 6, wherein The signal lines include first line segments, and at least part of the first line segments is located in the first area; The first line segments are located on a side of the organic structure away from the substrate.

8. The display panel according to claim 1, wherein The display panel includes a first connection line. One end of the first connection line is coupled to the light-emitting devices located in the first area, and the other end is coupled to the pixel circuits located in the second area; The driving layer includes a first organic layer, and the light-emitting devices are located on a side of the first organic layer away from the substrate; The light-emitting devices include stacked first electrodes, light-emitting layers, and second electrodes. The first electrodes are located on a side of the second electrodes close to the substrate; The first connection line is located on a side of the first organic layer away from the substrate.

9. The display panel according to claim 8, wherein At least a part of at least one of the first connection lines is in the same layer as the first electrode.

10. The display panel according to claim 8, wherein the display panel includes a second connection line, and the second connection line is located in the second region; in the second region, at least one of the light-emitting devices and the pixel circuit coupled thereto do not overlap in a direction perpendicular to the plane of the substrate, and the light-emitting device is electrically connected to the pixel circuit through the second connection line; at least one of the second connection lines is in the same layer as the first connection line.

11. The display panel according to claim 1, wherein the driving layer includes a first transistor and a capacitor; the driving layer includes a semiconductor layer, a first metal layer, a second metal layer, and a first source-drain electrode layer. The first metal layer is located on a side of the semiconductor layer away from the substrate, the second metal layer is located on a side of the first metal layer away from the substrate, and the first source-drain electrode layer is located on a side of the second metal layer away from the substrate; wherein, the semiconductor layer includes the active layer of the first transistor, the first metal layer includes the gate of the first transistor and the first electrode plate of the capacitor, the second metal layer includes the second electrode plate of the capacitor, the first source-drain electrode layer includes a plurality of connection structures, and at least a part of the connection structures are electrically connected to the active layer of the first transistor through vias; a side of the first source-drain electrode layer close to the substrate includes a plurality of the inorganic layers, a side of the first source-drain electrode layer away from the substrate includes a first organic layer, and the hollow is filled with the first organic layer.

12. The display panel according to claim 11, wherein the driving layer further includes a second source-drain electrode layer and a second organic layer. The second source-drain electrode layer is located on a side of the first organic layer away from the substrate, and the second organic layer is located on a side of the second source-drain electrode layer away from the substrate; in the first region, the second source-drain electrode layer includes at least one of the signal lines.

13. The display panel according to claim 1, wherein the display region includes scan lines extending in a first direction; in the second region, a plurality of the pixel circuits are arranged in the first direction; the first region and the second region are adjacent in the first direction.

14. The display panel according to claim 13, wherein the first region and the second region are alternately arranged in the first direction.

15. The display panel according to claim 13, wherein the display panel includes a first connection line, one end of the first connection line is coupled to the light-emitting device located in the first region, and the other end is coupled to the pixel circuit located in the second region; a plurality of the first connection lines connected to the plurality of light-emitting devices in the first region extend to the second region on the same side of the first region.

16. The display panel according to claim 13, wherein The display panel includes a first connection line, one end of the first connection line is coupled to the light-emitting device located in the first region, and the other end is coupled to the pixel circuit located in the second region; The first region is located between two adjacent second regions; Among the multiple first connection lines connected to the multiple light-emitting devices in the first region, some of the first connection lines extend to the second region on one side of the first region, and some of the first connection lines extend to the second region on the other side.

17. The display panel according to claim 16, wherein, Among the multiple first connection lines connected to the multiple light-emitting devices in the first region, the number of the first connection lines extending to the second regions on both sides of the first region is equal.

18. The display panel according to claim 13, wherein, The signal line includes an electrically connected first line segment and second line segment, at least a part of the first line segment is located in the first region, and the second line segment is located in the second region; The signal line includes a first signal line extending along the first direction; The first line segment and the second line segment of the first signal line are on different layers.

19. The display panel according to claim 13, wherein, At least one of the first regions is located between two second regions adjacent in the first direction, and this first region is located between two second regions adjacent in the second direction, and the second direction intersects with the first direction.

20. The display panel according to claim 19, wherein, In the display area, the first regions and the second regions are alternately arranged in the first direction, and the first regions and the second regions are alternately arranged in the second direction.

21. The display panel according to claim 19, wherein, The signal line includes a first signal line extending along the first direction and a second signal line extending along the second direction; In the first region, the first signal line and the second signal line are insulated and cross each other.

22. The display panel according to claim 21, wherein, The signal line includes an electrically connected first line segment and second line segment, at least a part of the first line segment is located in the first region, and the second line segment is located in the second region; The first line segment and the second line segment of the first signal line are on different layers; The first line segment and the second line segment of the second signal line are on the same layer, or the first line segment and the second line segment of the second signal line are on different layers.

23. The display panel according to claim 1, wherein, The display panel further includes a shift register unit, and the shift register unit is located in the non-display area; The shift register unit includes a first shift register unit, and a hollow is provided on one side of the first shift register unit close to the display area.

24. The display panel according to claim 23, wherein, Multiple first shift register units are cascaded; Along the arrangement direction of the first shift register units, a hollow is provided between two adjacent first shift register units.

25. The display panel according to claim 23, wherein: The shift register unit includes a second shift register unit, and the second shift register unit is located on a side of the first shift register unit away from the display area; A hollow is provided between the first shift register unit and the second shift register unit.

26. The display panel according to claim 25, wherein: The display panel includes data lines located in the driving layer; The hollow includes a first hollow, and the first hollow is located between the first shift register unit and the second shift register unit; along the extending direction of the data lines, the length of the first hollow is greater than the length of the first shift register unit; And / or, the hollow includes a second hollow, and the second hollow is located between the first shift register unit and the second shift register unit; along the extending direction of the data lines, the length of the second hollow is greater than the length of the second shift register unit.

27. A display device, characterized in that, Including the display panel according to any one of claims 1 to 26.

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