Display device

Abstract

The present disclosure provides a display device capable of simultaneously driving a plurality of adjacent gate line groups in a pixel configuration in which sub-pixels adjacent in an arrangement direction of gate lines have different colors. A display device includes: a plurality of pixels arranged in a matrix in a first direction and a second direction of a display region; a plurality of gate lines extending in the first direction and arranged in the second direction; a plurality of signal lines extending in the second direction and arranged in the first direction; and a driving circuit that supplies a pixel signal to the pixel via the signal line and drives the pixel via the gate line. The total number of pixels arranged in an ascending order of 1 to m from one end to the other end in the first direction is M, the total number of pixels arranged in an ascending order of 1 to n from one end to the other end in the second direction is N, the total numbers of gate lines and signal lines are respectively N and M + 1, the n-th gate line is connected to the pixels arranged in n rows in each column, and the n-th gate line is connected to the pixels arranged in n rows in each column. The mth signal line is connected to pixels arranged on odd rows (m-1) and even rows (m).

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] In recent years, in configurations such as VR (Virtual Reality), AR (Augmented Reality), and MR (Mixed Reality) that use lenses to magnify and display images, further high definition of display panels has been pursued. Conventionally, as a configuration for achieving a high frame rate using such a high-definition panel, a display device capable of simultaneously driving a plurality of adjacent gate line groups has been disclosed (for example, Patent Document 1).

[0003] On the other hand, in a pixel configuration with a normal square-shaped RGB stripe arrangement, the widths in the arrangement directions of the respective sub-pixels of R, G, and B become narrow, making it difficult to ensure the aperture area. Therefore, a pixel configuration that uses the same pixel area as the pixel configuration with an RGB stripe arrangement and is easy to ensure the aperture areas of the respective sub-pixels of R, G, and B has been disclosed (for example, Patent Document 2). In the pixel arrangement described in Patent Document 2, high definition can be achieved with respect to the pixel configuration with an RGB stripe arrangement.

[0004] Prior Art Documents

[0005] Patent Document 1: JP-A-2010-271366

[0006] Patent Document 2: WO 2021 / 200650 Summary of the Invention

[0007] In the pixel arrangement described in Patent Document 2 above, the colors of sub-pixels adjacent in the arrangement direction of the gate lines are different. In addition, common signal lines are connected to sub-pixels of different colors. In a display device with such a pixel configuration, a configuration for simultaneously driving a plurality of adjacent gate line groups cannot be adopted.

[0008] An object of the present invention is to provide a display device that can simultaneously drive a plurality of adjacent gate line groups in a pixel configuration in which the colors of sub-pixels adjacent in the arrangement direction of the gate lines are different.

[0009] A display device according to one aspect of the present disclosure includes: a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction in a display area; a plurality of gate lines extending in the first direction and arranged in the second direction; a plurality of signal lines extending in the second direction and arranged in the first direction; and a driving circuit that supplies pixel signals to the pixels via the signal lines and drives the pixels via the gate lines. When the total number of pixels arranged in ascending order from one end to the other end in the first direction from the first column to the m-th column is M, and the total number of pixels arranged in ascending order from one end to the other end in the second direction from the first row to the n-th row is N, the total number of the gate lines is N, and the total number of the signal lines is M + 1, where m is a natural number, n is a natural number, the n-th gate line is connected to the pixels arranged in the n-th row of each column, and the m-th signal line is connected to the pixels arranged in the (m - 1)-th column of odd rows and the pixels arranged in the m-th column of even rows. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 FIG. is a diagram showing an example of a schematic configuration of a display device according to an embodiment.

[0011] Figure 2 FIG. is a diagram showing an example of a pixel configuration in a display area.

[0012] Figure 3 FIG. is a cross-sectional view showing a schematic cross-sectional structure of a display device.

[0013] Figure 4 FIG. is a block diagram showing a configuration example of a gate driver.

[0014] Figure 5 FIG. is a circuit diagram showing an example of a circuit configuration of a shift register circuit.

[0015] Figure 6 FIG. is a circuit diagram showing an example of a circuit configuration of a gate line driving circuit.

[0016] Figure 7 FIG. is a timing chart showing a first driving example of a display device according to an embodiment.

[0017] Figure 8 FIG. is a timing chart showing a second driving example of a display device according to an embodiment.

[0018] Figure 9 FIG. is a diagram showing an example of a schematic configuration of a display device according to a comparative example.

[0019] Among them, the reference numerals are explained as follows:

[0020] 1, 1a Display device

[0021] 4 Driver IC

[0022] 11 Display panel

[0023] 12 Power supply device

[0024] 13 Control device

[0025] 40 Driver circuit

[0026] 42 Gate driver

[0027] 43 Signal line selection circuit

[0028] 44 Display control circuit

[0029] 421, 421_1, 421_p, 421_P shift register circuit

[0030] 422, 422_1, 422_p, 422_P gate line driver circuit

[0031] AA Display area

[0032] Cgs1 The first parasitic capacitance

[0033] Cgs2 The second parasitic capacitance

[0034] CKV Shift clock signal

[0035] COML Common electrode

[0036] Cs Holding capacitance

[0037] DTL Signal line

[0038] ENB Enable signal

[0039] ENB1 The first enable signal

[0040] ENB2 The second enable signal

[0041] ENB3 The third enable signal

[0042] ENB4 The fourth enable signal

[0043] GATE Gate signal

[0044] Pix Pixel

[0045] PX Pixel electrode

[0046] Source Video signal

[0047] SCL Gate line

[0048] SIG Pixel signal

[0049] STV Start pulse signal

[0050] Tr pixel transistor

[0051] VCOM common potential

[0052] VGH second potential

[0053] VGL first potential

[0054] Vsig image signal Detailed implementation manner

[0055] The manner (embodiment) for implementing the invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the content described in the following embodiments. In addition, the constituent elements described below include constituent elements that are substantially the same and can be easily conceived by those skilled in the art. Moreover, the constituent elements described below can be appropriately combined. It should be noted that the disclosure is only an example, and appropriate changes that can be easily conceived by those skilled in the art and maintain the gist of the invention are of course included in the scope of the present invention. In addition, in order to make the description clearer, the width, thickness, shape, etc. of each part of the accompanying drawings are sometimes shown schematically compared with the actual form, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, sometimes the same reference numerals are given to elements that are the same as those already described in the accompanying drawings, and the detailed description is appropriately omitted.

[0056] Figure 1 It is a diagram showing an example of the schematic configuration of the display device of the embodiment. Figure 2 It is a diagram showing an example of the pixel configuration in the display area.

[0057] The display device 1 of the present embodiment is, for example, a liquid crystal display device that uses a liquid crystal display element as a display element. In addition, in the present disclosure, the display device 1 can adopt, for example, a column inversion drive method, a frame inversion method, etc. as the drive method. As the drive method in the display device 1, it is not limited to the column inversion drive method and the frame inversion method.

[0058] The display device 1 is provided with a display area AA on the display panel 11, and a drive circuit 40 is provided in the peripheral area of the display area AA. Power is supplied to the display device 1 from the power supply device 12.

[0059] The driving circuit 40 includes a gate driver 42, a signal line selection circuit 43, and a display control circuit 44. The gate driver 42 and the signal line selection circuit 43 are thin film transistor (TFT) circuits formed in the peripheral region of the display area AA. The display control circuit 44 is included in the driver IC 4 mounted in the peripheral region of the display area AA. The driver IC 4 is connected to the control device 13 via a relay substrate formed of, for example, a flexible printed circuit (FPC).

[0060] The control device 13 controls the power supply from the power supply device 12 to the display device 1. In addition, the control device 13 controls the power-on and power-off of the display device 1. The power supply device 12 and the control device 13 are mounted, for example, on a machine (not shown) on which the display device 1 is mounted.

[0061] In the display area AA, a plurality of pixels Pix are arranged in the Dx direction (first direction) and the Dy direction (second direction). In addition, in the display area AA, a gate line SCL for supplying a gate signal GATE to the pixel Pix, a signal line DTL for supplying a pixel signal SIG to the pixel Pix, and a common electrode COML for supplying a common potential VCOM to the pixel Pix are provided. In the present embodiment, the gate line SCL extends in the Dx direction (first direction). In addition, in the present embodiment, the signal line DTL extends in the Dy direction (second direction).

[0062] In Figure 1 it, the total number of pixels Pix arranged in ascending order from one end to the other end in the Dx direction (first direction) from the first column to the m-th column (m is a natural number) is set as M, and the total number of pixels Pix arranged in ascending order from one end to the other end in the Dy direction (second direction) from the first row to the n-th row (n is a natural number) is set as N. At this time, in the display device 1 of the embodiment, the total number of gate lines SCL arranged in the Dy direction (second direction) is N, and the total number of signal lines DTL arranged in the Dx direction (first direction) is M + 1. Hereinafter, the n-th gate line SCL will also be referred to as "gate line SCL" <n>", and also record the m-th signal line as "signal line DTL" <m>”.

[0063] In Figure 1 In the configuration of the display device 1 of the illustrated embodiment, the gate line SCL <n>Connects to the pixel Pix arranged in the n-th row on each column. Additionally, the signal line DTL <m>It is connected to the pixel Pix arranged in the (m-1)-th column of the odd-numbered row and the pixel Pix arranged in the m-th column of the even-numbered row. Hereinafter, the pixel Pix provided in the m-th column of the n-th row will also be simply referred to as "the pixel Pix of the n-th row and m-th column".

[0064] As Figure 2 shown, each pixel Pix has a pixel transistor Tr and a pixel electrode PX. The pixel transistor Tr is formed of a thin-film transistor (TFT), for example, formed of an n-channel MOS (Metal Oxide Semiconductor) type TFT (hereinafter, also referred to as "n-type TFT").

[0065] In Figure 2 , the pixels Pix arranged in the n-th row to the (n+3)-th row are illustrated. In addition, in Figure 2 , the pixels Pix arranged in the (m-1)-th column and the m-th column are illustrated.

[0066] In addition, in Figure 2 , the n-th row ((n+2)-th row) is set as an odd-numbered row, and the (n+1)-th row ((n+3)-th row) is set as an even-numbered row.

[0067] The source electrode of the pixel transistor Tr of the pixel Pix of the n-th row and (m-1)-th column is connected to the signal line DTL <m>Connection, gate to gate line SCL <n>Connection. In addition, the source electrode of the pixel transistor Tr of the pixel Pix in the n+1th row and the m-1th column is connected to the signal line DTL <m-1>is connected, and the gate is connected to the gate line SCL<n+1>. In addition, the source of the pixel transistor Tr of the pixel Pix in the (n+2)-th row and (m-1)-th column is connected to the signal line DTL <m>is connected, and the gate is connected to the gate line SCL<n+2>. Additionally, the source of the pixel transistor Tr of the pixel Pix at the (n+3)th row and (m-1)th column is connected to the signal line DTL <m-1>is connected, and the gate is connected to the gate line SCL<n+3>.

[0068] The source of the pixel transistor Tr of the pixel Pix of n rows and m columns is connected to the signal line DTL<m+1>, and the gate is connected to the gate line SCL <n>Connection. In addition, the source electrode of the pixel transistor Tr of the pixel Pix with n + 1 rows and m columns is connected to the signal line DTL <m>is connected, and the gate is connected to the gate line SCL<n+1>. Additionally, the source of the pixel transistor Tr of the pixel Pix in the (n+2)-th row and m-th column is connected to the signal line DTL<m+1>, and the gate is connected to the gate line SCL<n+2>. Additionally, the source of the pixel transistor Tr of the pixel Pix in the (n+3)-th row and m-th column is connected to the signal line DTL <m>The gate is connected to the gate line SCL<n+3>.

[0069] The drain of the pixel transistor Tr of each pixel Pix is connected to the pixel electrode PX. A holding capacitor Cs is formed between the pixel electrode PX and the common electrode COML.

[0070] The gate signal GATE is supplied to the gate of the pixel transistor Tr of the pixels Pix arranged in the Dx direction (first direction) via the gate line SCL, and the pixel signal SIG is supplied to the source of the pixel transistor Tr of the pixels Pix arranged in the Dy direction (second direction) via the signal line DTL. Hereinafter, the gate signal GATE supplied to the pixels Pix arranged in the n-th row will also be referred to as "gate signal GATE". <n>”, also record the pixel signal SIG supplied to the pixels Pix arranged in the m-th column as "pixel signal SIG" <m>”.

[0071] Via the gate line SCL <n>, a gate signal GATE is supplied to a pixel Pix arranged in the n-th row on each column <n>。

[0072] Via the signal line DTL <m>Supply a common pixel signal SIG to a pixel Pix arranged in the (m-1)th column of an odd-numbered row and a pixel Pix arranged in the mth column of an even-numbered row <m>。

[0073] In the present disclosure, a pixel Pix includes, for example, a first pixel PixR for displaying red (R), a second pixel PixG for displaying green (G), and a third pixel PixB for displaying blue (B).

[0074] As Figure 1 shown, in the present disclosure, the first pixel PixR, the second pixel PixG, and the third pixel PixB are arranged in ascending order in the Dx direction (the first direction) in the order of the first pixel PixR, the second pixel PixG, and the third pixel PixB.

[0075] In addition, as Figure 1 shown, in the present disclosure, the first pixel PixR, the second pixel PixG, and the third pixel PixB are arranged in descending order in the Dy direction (the second direction) in the order of the first pixel PixR, the second pixel PixG, and the third pixel PixB.

[0076] In the pixel configuration of the above-described embodiment, the display colors of the pixels Pix in the n-th row and m-th column are different from the display colors of the pixels Pix in the n-th row and (m + 1)-th column, respectively.

[0077] In addition, in the pixel configuration of the above-described embodiment, the display colors of the pixels Pix in the n-th row and m-th column are different from the display colors of the pixels Pix in the (n + 1)-th row and m-th column, respectively.

[0078] In addition, in the pixel configuration of the above-described embodiment, the display colors of the pixels Pix in the n-th row and m-th column are the same as the display colors of the pixels Pix in the (n + 1)-th row and (m + 1)-th column.

[0079] The power supply device 12 generates a negative first potential VGL and a positive second potential VGH and supplies them to the display device 1. The first potential VGL is set to, for example, -8V. The second potential VGH is set to, for example, +8V. The first potential VGL and the second potential VGH are supplied to the gate driver 42. It should be noted that the first potential VGL supplied to the gate driver 42 is not limited to -8V. In addition, the second potential VGH supplied to the gate driver 42 is not limited to +8V.

[0080] In addition, the power supply device 12 generates a negative third potential VL and a positive fourth potential VH and supplies them to the display device 1. The third potential VL is set to, for example, -5V. The fourth potential VH is set to, for example, +5V. The third potential VL and the fourth potential VH are supplied to the driver IC 4. It should be noted that the third potential VL supplied to the driver IC 4 is not limited to -5V. In addition, the fourth potential VH supplied to the driver IC 4 is not limited to +5V.

[0081] The control device 13 sends the video signal Source, which is the original signal of the video displayed on the display device 1, to the display device 1.

[0082] The control device 13 includes, for example, a CPU (Central Processing Unit) and a storage device such as a memory. By executing a program using these hardware resources such as the CPU and the storage device, the control device 13 can implement the display function of the display device 1. The control device 13 performs control according to the execution result of the program so that the driver IC 4 processes the image displayed on the display device 1 into information of the input grayscale of the image.

[0083] The display control circuit 44 controls the display operation in the display area AA by controlling the gate driver 42 and the signal line selection circuit 43. The display control circuit 44 receives the video signal Source and various control signals from the control device 13. In addition, the display control circuit 44 converts the video signal Source from the control device 13 into an image signal Vsig and outputs it. The image signal Vsig is, for example, a signal obtained by time-division multiplexing pixel signals Sig corresponding to the pixel arrangement of RGB(W). In addition, the display control circuit 44 supplies a common potential VCOM to the common electrode COML.

[0084] In addition, the display control circuit 44 has functions as an interface (I / F) between the signal line selection circuit 43 and the control device 13 and a timing generator. It should be noted that the driver IC 4 including the display control circuit 44 may not be mounted on the display panel 11 but on a relay substrate connected to the display panel 11. In addition, the gate driver 42 and the signal line selection circuit 43 may also be included in the driver IC 4.

[0085] Next, the schematic structure of the display device 1 of the embodiment will be described. Figure 3 It is a cross-sectional view showing the schematic cross-sectional structure of the display device.

[0086] The array substrate 2 includes a first substrate 21 made of glass or a transparent resin, a plurality of pixel electrodes PX, a common electrode COML, and an insulating layer 24 that insulates the pixel electrodes PX and the common electrode COML. The plurality of pixel electrodes PX are arranged above the first substrate 21 in, for example, a row-column shape (matrix shape). The common electrode COML is provided between the first substrate 21 and the pixel electrodes PX.

[0087] The pixel electrode PX is provided corresponding to each pixel Pix. The pixel signal SIG for performing the display operation is supplied from the signal line selection circuit 43 to the pixel electrode PX via the signal line DTL and the pixel transistor Tr. In addition, when performing the display operation, the common potential VCOM for display, which is a voltage signal, is supplied from the driver IC4 to the common electrode COML. The common potential VCOM is preferably a potential different from the GND potential, and is set to about -0.08V, for example. The set value of the common potential VCOM is set to the optimum value that does not cause flicker in driving methods such as the column inversion driving method and the frame inversion method. In addition, the common potential VCOM is preferably a fixed potential, but may also have a waveform composed of an AC rectangular wave.

[0088] The pixel electrode PX and the common electrode COML are made of a light-transmissive conductive material such as ITO (Indium Tin Oxide), for example. A polarizer 35B is provided on the lower side of the first substrate 21 with a bonding layer (not shown).

[0089] The counter substrate 3 includes a second substrate 31 made of glass or a transparent resin, and a color filter 32 and a light-shielding layer (not shown) formed on one surface of the second substrate 31. In addition, a polarizer 35A is provided on the upper side of the second substrate 31 with a bonding layer (not shown).

[0090] The color filter 32 is provided corresponding to each pixel Pix. Specifically, a red (R) color filter is provided at a position corresponding to the pixel electrode PX of the first pixel PixR. In addition, a green (G) color filter is provided at a position corresponding to the pixel electrode PX of the second pixel PixG. In addition, a blue (B) color filter is provided at a position corresponding to the pixel electrode PX of the third pixel PixB.

[0091] The array substrate 2 and the counter substrate 3 are disposed opposite to each other with a predetermined interval (cell gap). A liquid crystal layer 6 is provided as a display functional layer in the space between the first substrate 21 and the second substrate 31. The liquid crystal layer 6 changes the alignment state of the liquid crystal molecules for each pixel Pix according to the state of the electric field between the pixel electrodes PX to the common electrode COML, and thereby adjusts the light passing through the liquid crystal layer 6. In the present embodiment, for example, a liquid crystal applicable to a horizontal electric field mode such as IPS (In-Plane Switching) including FFS (Fringe Field Switching) is used.

[0092] The array substrate 2 includes wirings such as pixel transistors Tr of each pixel Pix, gate lines SCL that supply gate signals GATE for driving each pixel transistor Tr, and signal lines DTL that supply pixel signals SIG to each pixel electrode PX. The gate lines SCL extend in the Dx direction (first direction) on a plane parallel to the surface of the first substrate 21. The signal lines DTL extend in the Dy direction (second direction) on a plane parallel to the surface of the first substrate 21.

[0093] Figure 4 It is a block diagram showing a configuration example of a gate driver. As Figure 4 shown, the gate driver 42 includes a shift register circuit 421 and a gate line driving circuit 422.

[0094] The gate line driving circuit 422 is a circuit that generates a scan signal GATE supplied to the gate of the pixel transistor Tr based on an output signal SRout output from the shift register circuit 421 and an enable signal ENB output from the display control circuit 44. The gate line driving circuit 422 includes gate line driving circuits 422_1,..., 422_p,..., 422_P. The shift register circuit 421 includes shift register circuits 421_1,..., 421_p,..., 421_P.

[0095] In Figure 4 the shown configuration example, the total number P of the gate line driving circuits 422 corresponds to 1 / 4 of the total number M of the pixels Pix arranged in the Dy direction (second direction) (P × 4 = M). The gate line driving circuits 422_p (p is a natural number from 1 to P) are respectively circuits that drive 4 gate lines SCL arranged continuously in the Dy direction (second direction). Specifically, the gate line driving circuit 422_1 supplies gate signals GATE<1>, GATE<2>, GATE<3>, GATE<4>. The gate line driving circuit 422_p supplies gate signals GATE <n>, GATE<n+1>, GATE<n+2>, GATE<n+3>. The gate line driving circuit 422_P supplies the gate signal GATE <n-3>, GATE <n-2>, GATE <n-1>, GATE <n>Note that the number of gate lines SCL to which the gate line driving circuit 422_p supplies the gate signal GATE is not limited to 4. When the number of gate lines SCL to which the gate line driving circuit 422_p supplies the gate signal GATE is Q, the total number P of the gate line driving circuits 422 is equivalent to 1 / Q of the total number M of the pixels Pix arranged in the Dy direction (the second direction) (P × Q = M).

[0096] In addition, in Figure 4 In the illustrated configuration example, the shift register circuits 421_1, ……, 421_p, ……, 421_P are respectively provided corresponding to the gate line driving circuits 422_1, ……, 422_p, ……, 422_P. Specifically, the output signal SRout(1) of the shift register circuit 421_1 is supplied to the gate line driving circuit 422_1, the output signal SRout(p) of the shift register circuit 421_p is supplied to the gate line driving circuit 422_p, and the output signal SRout(P) of the shift register circuit 421_P is supplied to the gate line driving circuit 422_P.

[0097] Figure 5 FIG. is a circuit diagram showing an example of the circuit configuration of the shift register circuit. The start pulse signal STV and the shift clock signal CKV are supplied from the display control circuit 44 to the shift register circuit 421.

[0098] The start pulse signal STV and the shift clock signal CKV are binary logic signals of high potential and low potential.

[0099] The start pulse signal STV is a signal that defines one frame period 1F of the display device 1. Specifically, in the display device 1 of the embodiment, the rising edge of the start pulse signal STV is defined as the starting point of one frame period 1F. In other words, one frame period 1F is a period for displaying an image signal Vsig of one frame amount.

[0100] The shift clock signal CKV is a signal that logically inverts at a prescribed period. More specifically, the shift clock signal CKV is a signal that changes from low potential to high potential with the high potential period of the start pulse signal STV as one period.

[0101] The start pulse signal STV and the shift clock signal CKV are input to the shift register circuit 421_1. Instead of the start pulse signal STV, the output signal SROUT(p - 1) of the previous-stage shift register circuit 421_p - 1 (not shown) is input to the shift register circuit 421_p. Instead of the start pulse signal STV, the output signal SROUT(P - 1) of the previous-stage shift register circuit 421_P - 1 (not shown) is input to the shift register circuit 421_P.

[0102] The shift register circuits 421_1, ……, 421_p, ……, 421_P respectively include clock inverters 51, 53, 54, 56, and inverters 52, 55. The shift register circuits 421_1, ……, 421_p, ……, 421_P generate an inverted shift clock signal xCKV that logically inverts the shift clock signal CKV.

[0103] When the shift clock signal CKV is at a high level and the inverted shift clock signal xCKV is at a low level, the clock inverters 51, 56 are turned on, and the clock inverters 53, 54 are turned off. At this time, when the start pulse signal STV (or the output signal SROUT(p - 1) of the previous-stage shift register circuit 421_p - 1 (not shown)) becomes high, it is held at a high level as the output potential of the inverter 52.

[0104] In this state, when the shift clock signal CKV becomes low and the inverted shift clock signal xCKV becomes high, the clock inverters 51, 56 are turned off, and the clock inverters 53, 54 are turned on. Thus, the high level held as the output potential of the inverter 52 becomes the output potential of the output signal SRout(p).

[0105] When the shift clock signal CKV is at a high level and the inverted shift clock signal xCKV is at a low level, the clock inverters 51, 56 are turned on, and the clock inverters 53, 54 are turned off. At this time, when the start pulse signal STV (or the output signal SROUT(p - 1) of the previous-stage shift register circuit 421_p - 1 (not shown)) becomes low, it is held at a low level as the output potential of the inverter 52.

[0106] In this state, when the shift clock signal CKV becomes low and the inverted shift clock signal xCKV becomes high, the clock inverters 51, 56 are turned off, and the clock inverters 53, 54 are turned on. Thus, the low level held as the output potential of the inverter 52 becomes the output potential of the output signal SRout(p).

[0107] Figure 6 It is a circuit diagram showing an example of the circuit configuration of the gate line driving circuit. The first enable signal ENB1, the second enable signal ENB2, the third enable signal ENB3, and the fourth enable signal ENB4 are supplied from the display control circuit 44 to the gate line driving circuit 422.

[0108] The output signal SRout(1) of the shift register circuit 421_1 is input to the gate line driving circuit 422_1. The output signal SRout(p) of the shift register circuit 421_p is input to the gate line driving circuit 422_p. The output signal SRout(P) of the shift register circuit 421_P is input to the gate line driving circuit 422_P.

[0109] Next, the configuration of the gate line driving circuit 422_p will be described. The gate line driving circuit 422_p generates an inverted output signal xSRout(p) obtained by logically inverting the output signal SRout(p) output from the shift register circuit 421_p.

[0110] The gate line driving circuit 422_p includes a gate signal GATE that is generated to be supplied to the pixel Pix arranged in the n-th position in the Dx direction (first direction) in the Dy direction (second direction). <n>The first buffer circuit 61_1, the second buffer circuit 61_2 that generates the gate signal GATE<n+1> supplied to the pixel Pix arranged in the Dx direction (the first direction) at the (n+1)-th in the Dy direction (the second direction), the third buffer circuit 61_3 that generates the gate signal GATE<n+2> supplied to the pixel Pix arranged in the Dx direction (the first direction) at the (n+2)-th in the Dy direction (the second direction), and the fourth buffer circuit 61_4 that generates the gate signal GATE<n+3> supplied to the pixel Pix arranged in the Dx direction (the first direction) at the (n+3)-th in the Dy direction (the second direction).

[0111] When the output signal SRout(p) output from the shift register circuit 421_p is at a low potential (the first potential VGL), the first transistor Tr1 and the second transistor Tr2 of the first buffer circuit 61_1 are turned off, and the third transistor Tr3 is turned on. As a result, the output potential of the first buffer circuit 61_1 becomes the first potential VGL, and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (the first direction) at the n-th in the Dy direction (the second direction) is turned off.

[0112] In addition, when the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (the second potential VGH), the first transistor Tr1 and the second transistor Tr2 of the first buffer circuit 61_1 are turned on, and the third transistor Tr3 is turned off. As a result, the output potential of the first buffer circuit 61_1 is a potential depending on the first enable signal ENB1 (for example, the second potential VGH), and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (the first direction) at the n-th in the Dy direction (the second direction) is turned on.

[0113] When the output signal SRout(p) output from the shift register circuit 421_p is at a low potential (the first potential VGL), the first transistor Tr1 and the second transistor Tr2 of the second buffer circuit 61_2 are turned off, and the third transistor Tr3 is turned on. As a result, the output potential of the second buffer circuit 61_2 becomes the first potential VGL, and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (the first direction) at the (n+1)-th in the Dy direction (the second direction) is turned off.

[0114] In addition, when the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (second potential VGH), the first transistor Tr1 and the second transistor Tr2 of the second buffer circuit 61_2 are controlled to be turned on, and the third transistor Tr3 is controlled to be turned off. As a result, the output potential of the second buffer circuit 61_2 becomes a potential depending on the potential of the second enable signal ENB2 (for example, the second potential VGH), and the pixel transistor Tr of the (n + 1)-th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) is controlled to be turned on.

[0115] When the output signal SRout(p) output from the shift register circuit 421_p is at a low potential (first potential VGL), the first transistor Tr1 and the second transistor Tr2 of the third buffer circuit 61_3 are controlled to be turned off, and the third transistor Tr3 is controlled to be turned on. As a result, the output potential of the third buffer circuit 61_3 becomes the first potential VGL, and the pixel transistor Tr of the (n + 2)-th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) is controlled to be turned off.

[0116] In addition, when the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (second potential VGH), the first transistor Tr1 and the second transistor Tr2 of the third buffer circuit 61_3 are controlled to be turned on, and the third transistor Tr3 is controlled to be turned off. As a result, the output potential of the third buffer circuit 61_3 becomes a potential depending on the potential of the third enable signal ENB3 (for example, the second potential VGH), and the pixel transistor Tr of the (n + 2)-th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) is controlled to be turned on.

[0117] When the output signal SRout(p) output from the shift register circuit 421_p is at a low potential (first potential VGL), the first transistor Tr1 and the second transistor Tr2 of the fourth buffer circuit 61_4 are controlled to be turned off, and the third transistor Tr3 is controlled to be turned on. As a result, the output potential of the fourth buffer circuit 61_4 becomes the first potential VGL, and the pixel transistor Tr of the (n + 3)-th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) is controlled to be turned off.

[0118] Further, when the output signal SRout(p) output from the shift register circuit 421_p is at a high level (second potential VGH), the first transistor Tr1 and the second transistor Tr2 of the fourth buffer circuit 61_4 are turned on, and the third transistor Tr3 is turned off. As a result, the output potential of the fourth buffer circuit 61_4 becomes a potential depending on the potential of the fourth enable signal ENB4 (for example, the second potential VGH), and the pixel transistor Tr of the (n + 3)-th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) is turned on.

[0119] Figure 7 is a timing chart showing a first driving example of the display device according to the embodiment. Figure 8 is a timing chart showing a second driving example of the display device according to the embodiment.

[0120] In Figure 7 the first driving example shown, an example of a method of driving the pixels Pix connected to the gate lines SCL arranged in the Dy direction (second direction) in sequence every one horizontal period 1H is illustrated. In Figure 8 the second driving example shown, an example of a method of driving the pixels Pix connected to two gate lines SCL arranged in the Dy direction (second direction) simultaneously every one horizontal period 1H is illustrated.

[0121] More specifically, in Figure 8 during one horizontal period in the first half of two horizontal periods when the output signal SRout(p) output from the shift register circuit 421_p becomes a high level (second potential VGH), the gate signal GATE <n>At the same time as the gate signal GATE<n+1> changes from the low potential (first potential VGL) to the high potential (second potential VGH). As a result, the pixel transistor Tr of the n-th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) and the pixel transistor Tr of the (n+1)-th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) are simultaneously turned on and controlled.

[0122] In addition, in Figure 8 during the first one horizontal period of the first half of the two horizontal periods when the output signal SRout(p) output from the shift register circuit 421_p becomes the high potential (second potential VGH), the gate signal GATE <n>At the same time as the gate signal GATE<n+1> changes from the high potential (second potential VGH) to the low potential (first potential VGL). As a result, the pixel transistors Tr of the nth pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) and the pixel transistors Tr of the (n+1)th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) are simultaneously turned off.

[0123] In addition, during one horizontal period in the second half of the two-level period when the output signal SRout(p) output from the shift register circuit 421_p becomes the high potential (second potential VGH), the gate signals GATE<n+2> and GATE<n+3> simultaneously change from the low potential (first potential VGL) to the high potential (second potential VGH). As a result, the pixel transistors Tr of the (n+2)th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) and the pixel transistors Tr of the (n+3)th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) are simultaneously turned on.

[0124] In addition, in Figure 8 During one horizontal period in the second half of the two-level period when the output signal SRout(p) output from the shift register circuit 421_p becomes the high potential (second potential VGH), the gate signals GATE<n+2> and GATE<n+3> simultaneously change from the high potential (second potential VGH) to the low potential (first potential VGL). The pixel transistors Tr of the (n+2)th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) and the pixel transistors Tr of the (n+3)th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction) are simultaneously turned off.

[0125] As a result, compared with Figure 7 the first example shown, a higher frame frequency can be achieved. Specifically, in Figure 8 the driving method of the second example shown, the frame frequency can be set to approximately twice that of Figure 7 the first example shown.

[0126] Figure 9 is a diagram showing an example of the schematic configuration of a display device of a comparative example. In Figure 9 the configuration of the display device 1a of the comparative example shown, the pixel configuration and the gate line SCL <n>The connection method is the same as that of Figure 1 the display device 1 shown in the embodiment.

[0127] In Figure 9 the configuration of the display device 1a in the comparative example shown, relative to Figure 1 the configuration of the display device 1 shown in the embodiment, the signal line DTL <m>The connection methods are different. Specifically, in the configuration of the display device 1a of the comparative example shown in Figure 9 the signal line DTL in <m>Connected to the pixel Pix arranged in the m-th column of each row. Thus, via the signal line DTL <m>, supply a pixel signal SIG to a pixel Pix arranged in the m-th column of each row <m>。

[0128] In Figure 9 In the configuration of the display device 1a of the comparative example shown, when the above-described second driving example is applied, the same pixel signal SIG is supplied to pixels Pix that display different colors <m>. Specifically, for example, a common pixel signal SIG is supplied to both the first pixel PixR at the first row and first column and the third pixel PixB at the first row and second column. Therefore, in the configuration of the display device 1a in the comparative example shown in Figure 9 , the above-described second driving example cannot be applied.

[0129] In contrast, in the configuration of the display device 1 in the embodiment shown in Figure 1 , as described above, the signal line DTL <m>Connects to the pixel Pix arranged in the (m - 1)-th column of the odd-numbered rows and the pixel Pix arranged in the m-th column of the even-numbered rows. Thus, as described above, via the signal line DTL <m>Supply a common pixel signal SIG to a pixel Pix arranged in the (m - 1)th column of an odd-numbered row and a pixel Pix arranged in the mth column of an even-numbered row <m>。

[0130] In Figure 1 In the configuration of the display device 1 of the embodiment shown, the display color of the pixel Pix arranged in the (m - 1)-th column of the odd rows is the same as the display color of the pixel Pix arranged in the m-th column of the even rows. Therefore, the above-described second driving example can be applied. Specifically, in Figure 1 In the configuration of the display device 1 of the embodiment shown, when the above-described second driving example is applied, for example, a common pixel signal SIG is supplied to both the first pixel PixR at the first row and first column and the first pixel PixR at the second row and second column.

[0131] It should be noted that the display device 1 is not limited to a liquid crystal display device. For example, it can be an organic EL display that uses an organic light emitting diode (OLED: Organic Light Emitting Diode) as a display element. In addition, the display device 1 can be an inorganic EL display that uses an inorganic light emitting diode (micro LED) as a display element. In addition, the display device 1 can be an electrophoretic display (EPD: Electrophoretic Display), and further a transparent display that causes a transmissive display surface to display an image.

[0132] In addition, the display colors of the first pixel PixR, the second pixel PixG, and the third pixel PixB are not limited to red (R), green (G), and blue (B). For example, the display colors of the first pixel PixR, the second pixel PixG, and the third pixel PixB can be cyan (C), magenta (M), and yellow (Y).

[0133] The preferred embodiments of the present disclosure have been described above, but the present disclosure is not limited to such embodiments. The content disclosed in the embodiments is merely an example, and various changes can be made without departing from the gist of the present disclosure. Appropriate changes made without departing from the gist of the present disclosure also naturally belong to the technical scope of the present disclosure.< / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / n> < / n> < / m> < / n> < / m> < / m> < / n> < / m> < / n> < / m> < / m> < / n> < / m> < / n>

Claims

1. A display device, characterized in that, Comprising: A plurality of pixels arranged in a matrix in a first direction of a display area and a second direction intersecting the first direction; A plurality of gate lines extending in the first direction and arranged in the second direction; A plurality of signal lines extending in the second direction and arranged in the first direction; And A driving circuit that supplies pixel signals to the pixels via the signal lines and drives the pixels via the gate lines. When the total number of pixels arranged in ascending order from one end to the other end of the first direction from the first column to the m-th column is set to M, and the total number of pixels arranged in ascending order from one end to the other end of the second direction from the first row to the n-th row is set to N, the total number of the gate lines is N, and the total number of the signal lines is M + 1, where m is a natural number and n is a natural number. The n-th gate line is connected to the pixels arranged in the n-th row of each column. The m-th signal line is connected to the pixels arranged in the (m - 1)-th column of odd rows and the pixels arranged in the m-th column of even rows.

2. The display device according to claim 1, wherein: The pixels of the n-th row and m-th column and the pixels of the n-th row and (m + 1)-th column display different colors respectively. The pixels of the n-th row and m-th column and the pixels of the (n + 1)-th row and m-th column display different colors respectively. The pixels of the n-th row and m-th column and the pixels of the (n + 1)-th row and (m + 1)-th column display the same color.

3. The display device according to claim 2, wherein: The plurality of pixels include: A first pixel that displays a first color; A second pixel that displays a second color different from the first color; and A third pixel that displays a third color different from the first color and the second color.

4. The display device according to claim 3, wherein: In the first direction, they are arranged in ascending order as the first pixel, the second pixel, and the third pixel. In the second direction, they are arranged in descending order as the first pixel, the second pixel, and the third pixel.

5. The display device according to claim 4, wherein: The first color is red. The second color is green. The third color is blue.

6. The display device according to claim 1, wherein: The driving circuit drives the pixels arranged in ascending order in the second direction in sequence.

7. The display device according to claim 1, wherein: The driving circuit simultaneously drives the pixels of odd rows and even rows that are arranged adjacent to each other in ascending order in the second direction.

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