Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and is used for reducing coupling between different signal lines. The display panel comprises a substrate; a pixel circuit; a data line extending along the first direction and electrically connected with the pixel circuit; the first signal line extends in the second direction and is electrically connected with the pixel circuit, the first signal line comprises a first line segment and a second line segment, and the second line segment is overlapped with the data line in the direction perpendicular to the plane where the substrate is located; wherein the data line, the first line segment and the second line segment are arranged in different layers, and the distance between the metal layer where the data line is located and the metal layer where the second line segment is located in the direction perpendicular to the substrate is larger than the distance between the metal layer where the data line is located and the metal layer where the first line segment is located in the direction perpendicular to the substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] A display panel includes a pixel circuit and various signal lines electrically connected to the pixel circuit. Among them, the coupling effect between the signal lines has a great influence on signal transmission. For example, the horizontal signal lines and the vertical signal lines in the display panel overlap to generate a coupling capacitance, resulting in interference between the signals on the two types of signal lines, and further affecting the display uniformity of the display panel. Summary of the Invention

[0003] Embodiments of the present invention provide a display panel and a display device for reducing the coupling between different signal lines.

[0004] In a first aspect, embodiments of the present invention provide a display panel, including: A substrate; A pixel circuit; Data lines extending along a first direction and electrically connected to the pixel circuit; A first signal line extending along a second direction and electrically connected to the pixel circuit, the first signal line including a first segment and a second segment, and in a direction perpendicular to the plane of the substrate, the second segment overlaps with the data line; Wherein, the data line, the first segment, and the second segment are arranged in different layers, and the distance between the metal layer where the data line is located and the metal layer where the second segment is located in a direction perpendicular to the substrate is greater than the distance between the metal layer where the data line is located and the metal layer where the first segment is located in a direction perpendicular to the substrate.

[0005] In a second aspect, based on the same inventive concept, embodiments of the present invention further provide a display device including the above display panel.

[0006] The technical solution provided by the embodiments of the present invention has the following beneficial effects: The first signal line extends horizontally and overlaps with the vertically extending data line. In the technical solution provided by the embodiments of the present invention, a wire replacement process is performed on the first signal line at the position where it overlaps with the data line, so that the segment of the first signal line that overlaps with the data line is longitudinally farther away from the data line. Specifically, in the first signal line, compared with the first segment that does not overlap with the data line, by arranging the second segment that overlaps with the data line in a metal layer that is longitudinally farther away from the data line, the coupling capacitance between the second segment and the data line can be reduced, and further, the mutual interference between the signals of the first signal line and the data line can be reduced, the signal stability can be improved, and thus the display uniformity of the display panel can be effectively improved. Description of the Drawings

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0008] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present invention; Figure 2 A schematic diagram of the film layer positions of a data line and a first signal line provided by an embodiment of the present invention; Figure 3 A schematic cross-sectional film layer structure diagram of a display panel provided by an embodiment of the present invention; Figure 4 Another schematic cross-sectional film layer structure diagram of a display panel provided by an embodiment of the present invention; Figure 5 Another schematic cross-sectional film layer structure diagram of a display panel provided by an embodiment of the present invention; Figure 6 A schematic structural diagram of a second line segment provided by an embodiment of the present invention; Figure 7 Another schematic structural diagram of a second line segment provided by an embodiment of the present invention; Figure 8 Another schematic structural diagram of a second line segment provided by an embodiment of the present invention; Figure 9 A schematic circuit structure diagram of a pixel circuit provided by an embodiment of the present invention; Figure 10 A schematic film layer structure diagram of a display panel provided by an embodiment of the present invention; Figure 11 Another schematic film layer structure diagram of a display panel provided by an embodiment of the present invention; Figure 12 For Figure 11 A cross-sectional view along the A1 - A2 direction; Figure 13 Another schematic film layer structure diagram of a display panel provided by an embodiment of the present invention; Figure 14 Another schematic film layer structure diagram of a display panel provided by an embodiment of the present invention; Figure 15 A schematic structural diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0009] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0010] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0011] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "the" and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0012] It should be understood that the term " / and" used herein is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0013] The embodiments of the present invention provide a display panel, as Figure 1 and Figure 2 shown, Figure 1 is a schematic structural diagram of the display panel provided by the embodiments of the present invention, Figure 2 is a schematic diagram of the film layer positions of the data line and the first signal line provided by the embodiments of the present invention. The display panel includes a substrate 1, a pixel circuit 2, a data line Data, and a first signal line 3.

[0014] Among them, the data line Data extends along the first direction x and is electrically connected to the pixel circuit 2. The first signal line 3 extends along the second direction y and is electrically connected to the pixel circuit 2. The first signal line 3 includes a first line segment 4 and a second line segment 5. In the direction perpendicular to the plane of the substrate 1, the second line segment 5 overlaps with the data line Data. Further, the first line segment 4 does not overlap with the data line Data.

[0015] Among them, the data line Data, the first line segment 4, and the second line segment 5 are arranged in different layers. The distance k1 between the metal layer where the data line Data is located and the metal layer where the second line segment 5 is located in the direction perpendicular to the substrate 1 is greater than the distance k2 between the metal layer where the data line Data is located and the metal layer where the first line segment 4 is located in the direction perpendicular to the substrate 1. That is, the longitudinal distance between the metal layer where the data line Data is located and the metal layer where the second line segment 5 is located is greater than the longitudinal distance between the metal layer where the data line Data is located and the metal layer where the first line segment 4 is located.

[0016] The first signal line 3 extends horizontally and overlaps with the vertically extending data line Data. In the technical solution provided by the embodiment of the present invention, the first signal line 3 is rewired at the position where it overlaps with the data line Data, so that the segment of the first signal line 3 overlapping with the data line Data is vertically farther apart from the data line Data. Specifically, in the first signal line 3, compared with the first segment 4 that does not overlap with the data line Data, by setting the second segment 5 overlapping with the data line Data in a metal layer that is vertically farther apart from the data line Data, the coupling capacitance between the second segment 5 and the data line Data can be reduced, thereby reducing the mutual interference between the signals of the first signal line 3 and the data line Data, improving signal stability, and effectively improving the display uniformity of the display panel.

[0017] Regarding the first signal line 3, in the embodiment of the present invention, the first signal line 3 can be used to transmit a constant voltage signal. Furthermore, some longitudinal traces connected thereto can be set to form a grid-like structure. This grid-like structure can make the overall load of the traces lower. Therefore, when rewiring the second segment 5 in the first signal line 3, the impedance limit for the selected film layer of the second segment 5 will be smaller. For example, the second segment 5 can select a metal layer that is farther from the data line Data but has a slightly larger impedance for wiring. Thus, while reducing the coupling between the second segment 5 and the data line Data and reducing the influence of data signal jumps on the signal on the first signal line 3, the overall load of the traces where the first signal line 3 is located will not be too large. The technical solution provided by the embodiment of the present invention is more applicable to large and medium-sized display panels. Such display panels are larger in size and have a lower PPI, and there is sufficient wiring space to set the above-mentioned longitudinal traces, so that the first signal line 3 can better balance low coupling and low load.

[0018] In a feasible implementation manner, referring to Figures 3 - 5 , the pixel circuit 2 includes a plurality of transistors 6. The active layers of at least some of the transistors 6 are electrically connected to the connection metal 8 through the first vias 7, and the connection metal 8 is located in the first metal layer sd1.

[0019] Among them, the data line Data is located in the second metal layer sd2, and the second metal layer sd2 is located on the side of the first metal layer sd1 away from the substrate 1. The first segment 4 is located in the first metal layer sd1, and the metal layer where the second segment 5 is located is on the side of the first metal layer sd1 close to the substrate 1.

[0020] In the film layer structure of the display panel, the metal layer where the connection metal 8 is located (the first metal layer sd1) and the metal layer above the connection metal 8 (the second metal layer sd2) are also called source-drain metal layers, and there is at least a planarization layer 9 between adjacent source-drain metal layers.

[0021] When the data line Data is located in the second metal layer sd2, the second line segment 5 is disposed in a certain metal layer below the first metal layer sd1. There is at least a planarization layer 9 and an inorganic insulating layer 10 between the data line Data and the second line segment 5. Since the planarization layer 9 is an organic film layer with a relatively large thickness, the planarization layer 9 can be used to increase the vertical distance between the data line Data and the second line segment 5 to a greater extent, thereby reducing the coupling between the data line Data and the first signal line 3 to a greater extent. In other words, in the embodiment of the present invention, at the overlapping position of the first signal line 3 and the data line Data, the first signal line 3 is switched from the first metal layer sd1 to a certain metal layer below the first metal layer sd1 to reduce the coupling at the overlapping position.

[0022] In addition, currently, the source-drain metal layer usually adopts a structure such as titanium-aluminum-titanium, which exhibits low impedance characteristics. In the above structure, the first line segment 4 and the data line Data are respectively located in two source-drain metal layers. The low impedance characteristics of the source-drain metal layer can also be used to make the first signal line 3 and the data line Data have a lower load, optimize the signal transmission in the first signal line 3 and the data line Data, and improve adverse problems such as signal voltage drop and delay. Further, the source-drain metal layer where the data line Data is located is farther from the substrate 1, that is, the film layer position of the data line Data is more upward, and the data line Data is farther from other traces, which can also reduce the coupling between the data line Data and other traces.

[0023] Further, as Figure 3 shown, Figure 3 is a schematic cross-sectional film layer structure diagram of a display panel provided by an embodiment of the present invention. The transistor 6 includes a first transistor 11. The active layer of the first transistor 11 includes an oxide semiconductor material, that is, the first transistor 11 is an oxide transistor, for example, an indium gallium zinc oxide (IGZO) transistor.

[0024] The first transistor 11 includes a first gate g1. In the first transistor 11, the first gate g1 is located on the side of the active layer away from the substrate 1, and the first gate g1 is located in the third metal layer mg. Among them, referring to Figure 3 , the first transistor 11 can be a top-bottom double-gate structure. In addition to the first gate g1, the first transistor 11 further includes a second gate g2. The second gate g2 is located on the side of the active layer close to the substrate 1. The first gate g1 is a top gate, and the second gate g2 is a bottom gate. Alternatively, the first transistor 11 can also be a single-gate structure. At this time, the first transistor 11 only includes the first gate g1.

[0025] In a structure, the second line segment 5 is located in the third metal layer mg, that is, the second line segment 5 is arranged on the same layer as the first gate g1 of the first transistor 11.

[0026] When the display panel includes the first transistor 11, choosing to arrange the second line segment 5 on the same layer as the first gate g1 of the first transistor 11 can reduce the coupling between the second line segment 5 and the data line Data while not requiring an additional metal layer for the second line segment 5.

[0027] Or, as Figure 4 shown, Figure 4 FIG. is a schematic cross-sectional film layer structure diagram of another display panel provided by an embodiment of the present invention. The transistor 6 includes a second transistor 12. The active layer of the second transistor 12 includes a silicon semiconductor material, that is, the second transistor 12 is a silicon transistor, such as a low temperature poly silicon (LTPS) transistor. The gate of the second transistor 12 is located in the fourth metal layer m1.

[0028] In a structure, the second line segment 5 is located in the fourth metal layer m1, that is, the second line segment 5 is arranged on the same layer as the gate of the second transistor 12.

[0029] In the film layer structure of the display panel, the metal layer where the gate of the silicon transistor is located is very close to the substrate 1, and its film layer position is very low. Arranging the second line segment 5 on the same layer as the gate of the second transistor 12 can make the second line segment 5 farther away from the second metal layer sd2 where the data line Data is located, thereby reducing the coupling between the second line segment 5 and the data line Data to a greater extent.

[0030] Or again, as Figure 5 shown, Figure 5 FIG. is a schematic cross-sectional film layer structure diagram of yet another display panel provided by an embodiment of the present invention. The transistor 6 includes a second transistor 12. The active layer of the second transistor 12 includes a silicon semiconductor material, and the gate of the second transistor 12 is located in the fourth metal layer m1.

[0031] The pixel circuit 2 further includes a storage capacitor Cst. The first electrode plate c1 of the storage capacitor Cst is located in the fourth metal layer m1, and the second electrode plate c2 of the storage capacitor Cst is located in the fifth metal layer mc. The fifth metal layer mc is located on the side of the fourth metal layer m1 away from the substrate 1.

[0032] In a structure, the second line segment 5 is located in the fifth metal layer mc.

[0033] In the film layer structure of the display panel, the position of the metal layer where the second electrode plate c2 of the storage capacitor Cst is located is also relatively low. By setting the second line segment 5 to be on the same layer as the second electrode plate c2, the coupling between the second line segment 5 and the data line Data can also be reduced to a large extent.

[0034] In addition, it should be noted that the display panel further includes a first semiconductor layer al1 and a second semiconductor layer al2. The first semiconductor layer al1 includes the active layer of the second transistor 12, and the second semiconductor layer al2 includes the active layer of the first transistor 11. Along the direction away from the substrate 1, the first semiconductor layer al1, the fourth metal layer m1, the fifth metal layer mc, the second semiconductor layer al2, the third metal layer mg, the first metal layer sd1, and the second metal layer sd2 are arranged in sequence.

[0035] In a feasible implementation manner, in combination with Figure 2 and Figure 6 , Figure 6 FIG. is a schematic structural diagram of a second line segment provided by an embodiment of the present invention. The first line segment 4 is electrically connected to the second line segment 5 through a second via 13. The distance d between the positive projection of the second via 13 in the plane of the substrate 1 and the positive projection of the data line Data in the plane of the substrate 1 is greater than or equal to 0.6 μm.

[0036] By setting the distance between the second via 13 and the data line Data to be greater than or equal to 0.6 μm, it can be ensured that there is enough line length in the second line segment 5 to overlap with the data line Data. Even if the positions of the data line Data and / or the second line segment 5 deviate due to process accuracy or other reasons, it can still be ensured that the data line Data overlaps with the second line segment 5, thereby ensuring that the first signal line 3 and the data line Data have a small coupling.

[0037] In a feasible implementation manner, as shown in Figure 7 , Figure 7 FIG. is another schematic structural diagram of the second line segment 5 provided by an embodiment of the present invention. The second line segment 5 includes a first sub - part 14 and a second sub - part 15. In the direction perpendicular to the plane of the substrate 1, the first sub - part 14 overlaps with the data line Data, and the second sub - part 15 does not overlap with the data line Data.

[0038] Wherein, the width h1 of the first sub - part 14 in the first direction x is smaller than the width h2 of the first line segment 4 in the first direction x.

[0039] It should be noted that, referring to Figure 7, the first line segment 4 includes a first connection portion 41 and a first regular line segment portion 42. In the direction perpendicular to the plane of the substrate 1, the first connection portion 41 overlaps with the second via 13, and the first regular line segment portion 42 does not overlap with the second via 13. To improve the connection stability, the width of the first connection portion 41 in the first direction x is generally greater than the width of the first regular line segment portion 42 in the first direction x. In the embodiments of the present invention, the width of the first line segment 4 in the first direction x refers to the width of the first regular line segment portion 42 of the first line segment 4 in the first direction x.

[0040] By providing a first sub-portion 14 and a second sub-portion 15 in the second line segment 5, the first sub-portion 14 with a smaller line width can be utilized to further reduce the overlapping area between the second line segment 5 and the data line Data, thereby further reducing the coupling capacitance between the second line segment 5 and the data line Data. At the same time, it also avoids the second sub-portion 15 being too narrow and affecting the load of the second line segment 5.

[0041] In a feasible implementation manner, as Figure 8 shown, Figure 8 FIG. is a schematic diagram of yet another structure of the second line segment provided by the embodiments of the present invention. The second line segment 5 includes a first sub-portion 14 and a second sub-portion 15. In the direction perpendicular to the plane of the substrate 1, the first sub-portion 14 overlaps with the data line Data, and the second sub-portion 15 does not overlap with the data line Data.

[0042] Among them, the width h3 of the second sub-portion 15 in the first direction x is greater than the width h2 of the first line segment 4 in the first direction x.

[0043] It should be noted that referring to Figure 8 , the first line segment 4 includes a first connection portion 41 and a first regular line segment portion 42. In the direction perpendicular to the plane of the substrate 1, the first connection portion 41 overlaps with the second via 13, and the first regular line segment portion 42 does not overlap with the second via 13. To improve the connection stability, the width of the first connection portion 41 in the first direction x is generally greater than the width of the first regular line segment portion 42 in the first direction x. In the embodiments of the present invention, the width of the first line segment 4 in the first direction x refers to the width of the first regular line segment portion 42 of the first line segment 4 in the first direction x.

[0044] Similarly, the second sub-portion 15 includes a second connection portion 151 and a second regular line segment portion 152. In the direction perpendicular to the plane of the substrate 1, the second connection portion 151 overlaps with the second via 13, and the second regular line segment portion 152 does not overlap with the second via 13. In the embodiments of the present invention, the width of the second sub-portion 15 in the first direction x refers to the width of the second regular line segment portion 152 of the second sub-portion 15 in the first direction x.

[0045] By setting the width of the second sub - part 15 to be greater than the width of the first line segment 4, the weakening effect of the larger line width of the second sub - part 15 on the load can be used to compensate for the increase in the load caused by the line change of the second line segment 5, thus optimizing the load of the first signal line 3.

[0046] Further, when the width h3 of the second sub - part 15 in the first direction x is greater than the width h2 of the first line segment 4 in the first direction x, the width h1 of the first sub - part 14 in the first direction x can be less than the width of the first line segment 4 in the first direction x, or can be equal to the width of the first sub - part 14 in the first direction x.

[0047] In a feasible implementation, referring to Figure 7 and Figure 8 , to ensure that the overlapping area between the second line segment 5 and the data line Data is small, the width h1 of the part of the second line segment 5 that overlaps with the data line Data in the first direction x can be less than or equal to 3 μm, that is, the width of the above - mentioned first sub - part 14 is less than or equal to 3 μm.

[0048] In a feasible implementation, as Figure 9 and Figure 10 shown, Figure 9 is a schematic circuit structure diagram of the pixel circuit 2 provided by an embodiment of the present invention. Figure 10 is a schematic film layer structure diagram of the display panel provided by an embodiment of the present invention. The first signal line 3 transmits a constant voltage signal.

[0049] The display panel further includes a second signal line 16. The second signal line 16 extends along the first direction x and is electrically connected to the first signal line 3. The second signal line 16 is arranged on the same layer as the data line Data.

[0050] When the first signal line 3 transmits a constant voltage signal, by designing the second signal line 16 to form a grid - like structure that intersects it horizontally and vertically, the overall routing load of this constant voltage line can be made lower. Furthermore, when a line change design is carried out on the second line segment 5 in the first signal line 3, the impedance limitation on the selected film layer of the second line segment 5 will be smaller. For example, the second line segment 5 can select a metal layer that is farther away from the data line Data but has a slightly larger impedance for wiring. Thus, while reducing the coupling between the second line segment 5 and the data line Data and reducing the influence of data signal jumps on the signal on the first signal line 3, the load of the overall routing where the first signal line 3 is located will not be too large.

[0051] Taking the data line Data being located in the second metal layer sd2 as an example, when the width and length of the second line segment 5 are fixed, when the second line segment 5 is located in the first metal layer sd1, the resistance of the second line segment 5 is 0.142800 Ω, and the parasitic capacitance between the second line segment 5 and the data line Data is 0.42 fF. When the second line segment 5 is located in the third metal layer mg, the resistance of the second line segment 5 is 1.123478 Ω, and the parasitic capacitance between the second line segment 5 and the data line Data is 0.245 fF. It can be seen that after the wire change design of the second line segment 5, the coupling with the data line Data is significantly reduced, which has a positive optimization effect on improving signal crosstalk. Although the resistance of the second line segment 5 slightly increases, due to the grid structure of the first signal line 3 and the second signal line 16, the small increase in the local resistance of the second line segment 5 has little impact on the overall wiring load.

[0052] Furthermore, the second signal line 16 and the data line Data are on the same layer, which can reduce the number of film layers occupied by various signal lines in the display panel and simplify the panel structure. Moreover, when the second signal line 16 and the data line Data are located in the second metal layer sd2, the low-impedance characteristics of the source-drain metal layer can be used to further reduce the load of the second signal line 16.

[0053] In addition, it should be noted that in one structure, referring to Figure 10 , in the direction perpendicular to the plane of the substrate 1, the second signal line 16 and the second line segment 5 may not overlap, or, as shown in Figure 11 and Figure 12 , Figure 11 is another schematic diagram of the film layer structure of the display panel provided by the embodiment of the present invention. Figure 12 is Figure 11 a cross-sectional view along the A1 - A2 direction. The second signal line 16 and the second line segment 5 may also overlap. At this time, the second via 13 between the first line segment 4 and the second line segment 5 overlaps with the second signal line 16.

[0054] In a feasible implementation manner, referring to Figure 9 and Figure 10 , the pixel circuit 2 includes a driving transistor T0 and a first light-emitting control transistor T1. Among them, the first light-emitting control transistor T1 is electrically connected between the first power supply line pvdd1 and the first pole of the driving transistor T0.

[0055] In one structure, the first signal line 3 includes the first power supply line pvdd1.

[0056] The driving current converted by the driving transistor T0 is directly related to the power supply voltage and the data voltage. When the first signal line 3 includes the first power supply line pvdd1, the coupling between the first power supply line pvdd1 and the data line Data is small, and the interference to the power supply signal when the data voltage jumps is small. Furthermore, the stability of the power supply signal can be improved, so as to effectively improve the stability of the driving current converted by the driving transistor T0.

[0057] Furthermore, the second signal line 16 may correspondingly include a second power supply line pvdd2. The second power supply line pvdd2 extends along the second direction y and is electrically connected to the first power supply line pvdd1. The second power supply line pvdd2 and the first power supply line pvdd1 cross to form a grid-like structure.

[0058] In a feasible implementation manner, in combination with Figure 9 , such as Figure 13 and Figure 14 shown, Figure 13 is another schematic diagram of the film layer structure of the display panel provided by the embodiment of the present invention. Figure 14 is another schematic diagram of the film layer structure of the display panel provided by the embodiment of the present invention. The pixel circuit 2 includes a driving transistor T0 and a first reset transistor T2. Among them, the first reset transistor T2 is electrically connected between the first reset line ref1 and the gate of the driving transistor T0.

[0059] In one structure, the first signal line 3 includes the first reset line ref1.

[0060] The reset voltage provided by the first reset line ref1 is used to reset the gate of the driving transistor T0. The gate reset state of the driving transistor T0 directly affects the working performance of the driving transistor T0, and further affects the accuracy of the driving current converted by the driving transistor T0. When the first signal line 3 includes the first reset line ref1, the coupling between the first reset line ref1 and the data line Data is small, and the interference to the reset signal when the data voltage jumps is also small. In this way, the stability of the reset signal can be improved, and further the reset consistency of the driving transistor T0 in different sub-pixels can be effectively improved, and the display uniformity can be optimized.

[0061] And / or, the pixel circuit 2 includes a second reset transistor T3. The second reset transistor T3 is electrically connected between the second reset line ref2 and the light-emitting element 17.

[0062] In one structure, the first signal line 3 includes the second reset line ref2.

[0063] The reset voltage provided by the second reset line ref2 is used to reset the anode of the light-emitting element 17. When the first signal line 3 includes the second reset line ref2, the coupling between the second reset line ref2 and the data line Data is small, and the interference to the reset signal during the data voltage jump is small. In this way, the stability of the reset signal can be improved, and further, the reset consistency of the light-emitting elements 17 in different sub-pixels can be effectively improved, and the display uniformity can be optimized.

[0064] Further, referring to Figure 14 , the second signal line 16 includes a third reset line ref3 and / or a fourth reset line ref4.

[0065] Among them, the third reset line ref3 extends along the second direction y and is electrically connected to the first reset line ref1, and the third reset line ref3 and the first reset line ref1 cross to form a grid-like structure.

[0066] The fourth reset line ref4 extends along the second direction y and is electrically connected to the second reset line ref2. The fourth reset line ref4 and the second reset line ref2 cross to form a grid-like structure.

[0067] In a feasible implementation manner, referring to Figure 9 , the pixel circuit 2 includes a driving transistor T0, a first reset transistor T2, and a threshold compensation transistor T4. Among them, the first reset transistor T2 is electrically connected between the first reset line ref1 and the gate of the driving transistor T0, and the threshold compensation transistor T4 is electrically connected between the second pole and the gate of the driving transistor T0.

[0068] Among them, the active layer of the first reset transistor T2 includes an oxide semiconductor material, and / or the active layer of the threshold compensation transistor T4 includes an oxide semiconductor material. That is, the first transistor 11 includes the first reset transistor T2 and / or the threshold compensation transistor T4. Exemplarily, both the first reset transistor T2 and the threshold compensation transistor T4 are IGZO transistors.

[0069] Due to the low defect state density and low mobility in the bandgap, oxide transistors have the good characteristic of low leakage current. The first reset transistor T2 and the threshold compensation transistor T4 are directly connected to the gate of the driving transistor T0. Setting the two as oxide transistors can effectively improve the node leakage problem of the driving transistor T0, and further optimize the low-frequency display of the display panel and reduce power consumption, etc.

[0070] In addition, it should be noted that the technical solution provided by the embodiments of the present invention can be applied to large and medium-sized display panels such as in-vehicle displays. In traditional large and medium-sized display panels, the transistors in the pixel circuit 2 are all silicon transistors. In the embodiments of the present invention, at least some of the transistors are oxide transistors, and the performance of the large and medium-sized display panel is optimized by utilizing the characteristic of low leakage current of the oxide transistors, so that it has better performance in low-frequency display and plays a greater advantage.

[0071] A schematic description of a structure of the pixel circuit 2 is given below. With reference to Figure 9 , Figure 10 and Figure 13 , the pixel circuit 2 may specifically include: Drive transistor T0.

[0072] A first reset transistor T2, whose gate is electrically connected to the first scan line s1n, the first pole is electrically connected to the first reset line ref1, and the second pole is electrically connected to the gate of the drive transistor T0. Among them, the first scan line s1n can be a double-layer structure, with one layer located in the fifth metal layer mc and the other layer located in the third metal layer mg.

[0073] Data writing transistor T5, whose gate is electrically connected to the second scan line sp1, the first pole is electrically connected to the data line Data, and the second pole is electrically connected to the first pole of the drive transistor T0. Among them, the second scan line sp1 can be located in the fourth metal layer m1.

[0074] Threshold compensation transistor T4, whose gate is electrically connected to the third scan line s2n, the first pole is electrically connected to the second pole of the drive transistor T0, and the second pole is electrically connected to the gate of the drive transistor T0. Among them, the third scan line s2n can be a double-layer structure, with one layer located in the fifth metal layer mc and the other layer located in the third metal layer mg Second reset transistor T3, whose gate is electrically connected to the fourth scan line sp2, the first pole is electrically connected to the second reset line ref2, and the second pole is electrically connected to the light-emitting element 17. Among them, the fourth scan line sp2 can be located in the fourth metal layer m1, and the fourth scan line sp2 and the second scan line sp1 can transmit the same signal or different signals.

[0075] First light-emitting control transistor T1, whose gate is electrically connected to the light-emitting control signal line Emit, the first pole is electrically connected to the first power supply line pvdd1, and the second pole is electrically connected to the first pole of the drive transistor T0. Among them, the light-emitting control signal line Emit can be located in the fourth metal layer m1.

[0076] Second light-emitting control transistor T6, whose gate is electrically connected to the light-emitting control signal line Emit, the first pole is electrically connected to the second pole of the drive transistor T0, and the second pole is electrically connected to the light-emitting element 17.

[0077] A storage capacitor Cst is electrically connected between a first power supply line pvdd1 and the gate of a driving transistor T0.

[0078] Among them, the active layers of the first reset transistor T2 and the threshold compensation transistor T4 may include an oxide semiconductor material. The active layers of the driving transistor T0, the data writing transistor T5, the second reset transistor T3, the first light emission control transistor T1, and the second light emission control transistor T6 may include a silicon semiconductor material.

[0079] That is, the aforementioned first transistor 11 includes the first reset transistor T2 and the threshold compensation transistor T4, and the second transistor 12 includes the driving transistor T0, the data writing transistor T5, the second reset transistor T3, the first light emission control transistor T1, and the second light emission control transistor T6.

[0080] Based on the same inventive concept, an embodiment of the present invention further provides a display device, as Figure 15 shown, Figure 15 is a schematic structural diagram of the display device provided by the embodiment of the present invention. The display device includes the above-mentioned display panel 100. Of course, Figure 15 the display device shown is only for illustrative purposes. The display device may be any electronic device with a display function, such as an in-vehicle display screen, a mobile phone, a tablet computer, a laptop computer, an e-book, or a television.

[0081] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of protection of the present invention.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, Comprising: A substrate; A pixel circuit; A data line extending in a first direction and electrically connected to the pixel circuit; A first signal line extending in a second direction and electrically connected to the pixel circuit, the first signal line including a first segment and a second segment, and in a direction perpendicular to the plane of the substrate, the second segment overlaps with the data line; Wherein, the data line, the first segment and the second segment are arranged in different layers, and the distance between the metal layer where the data line is located and the metal layer where the second segment is located in the direction perpendicular to the substrate is greater than the distance between the metal layer where the data line is located and the metal layer where the first segment is located in the direction perpendicular to the substrate.

2. The display panel according to claim 1, wherein The pixel circuit includes a plurality of transistors, and the active layers of at least some of the transistors are electrically connected to a connection metal through a first via, and the connection metal is located in a first metal layer; The data line is located in a second metal layer, and the second metal layer is located on a side of the first metal layer away from the substrate; The first segment is located in the first metal layer, and the metal layer where the second segment is located is located on a side of the first metal layer close to the substrate.

3. The display panel according to claim 2, wherein The transistor includes a first transistor, the active layer of the first transistor includes an oxide semiconductor material, the first transistor includes a first gate, and in the first transistor, the first gate is located on a side of the active layer away from the substrate, and the first gate is located in a third metal layer; Wherein, the second segment is located in the third metal layer.

4. The display panel according to claim 2, wherein The transistor includes a second transistor, the active layer of the second transistor includes a silicon semiconductor material, and the gate of the second transistor is located in a fourth metal layer; Wherein, the second segment is located in the fourth metal layer.

5. The display panel according to claim 2, wherein The transistor includes a second transistor, the active layer of the second transistor includes a silicon semiconductor material, and the gate of the second transistor is located in a fourth metal layer; The pixel circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is located in the fourth metal layer, a second electrode plate of the storage capacitor is located in a fifth metal layer, and the fifth metal layer is located on a side of the fourth metal layer away from the substrate; Wherein, the second segment is located in the fifth metal layer.

6. The display panel according to claim 1, wherein The first segment and the second segment are electrically connected through a second via, and the distance between the orthographic projection of the second via in the plane of the substrate and the orthographic projection of the data line in the plane of the substrate is greater than or equal to 0.6 μm.

7. The display panel according to claim 1, wherein The second segment includes a first sub - portion and a second sub - portion, and in a direction perpendicular to the plane of the substrate, the first sub - portion overlaps with the data line, and the second sub - portion does not overlap with the data line; The width of the first sub - portion in the first direction is less than the width of the first line segment in the first direction.

8. The display panel according to claim 1, wherein The second line segment includes a first sub - portion and a second sub - portion. In a direction perpendicular to the plane of the substrate, the first sub - portion overlaps with the data line, and the second sub - portion does not overlap with the data line; The width of the second sub - portion in the first direction is greater than the width of the first line segment in the first direction.

9. The display panel according to claim 1, wherein The width of the portion of the second line segment that overlaps with the data line in the first direction is less than or equal to 3 μm.

10. The display panel according to claim 1, wherein The first signal line transmits a constant voltage signal; The display panel further includes a second signal line, which extends along the first direction and is electrically connected to the first signal line, and the second signal line is disposed on the same layer as the data line.

11. The display panel according to claim 1, wherein The pixel circuit includes a driving transistor and a first light - emitting control transistor, and the first light - emitting control transistor is electrically connected between the first power supply line and the first pole of the driving transistor; The first signal line includes the first power supply line.

12. The display panel according to claim 1, wherein The pixel circuit includes a driving transistor and a first reset transistor, and the first reset transistor is electrically connected between the first reset line and the gate of the driving transistor, and the first signal line includes the first reset line; and / or, the pixel circuit includes a second reset transistor, and the second reset transistor is electrically connected between the second reset line and the light - emitting element, and the first signal line includes the second reset line.

13. The display panel according to claim 1, wherein The pixel circuit includes a driving transistor, a first reset transistor, and a threshold compensation transistor. Among them, the first reset transistor is electrically connected between the first reset line and the gate of the driving transistor, and the threshold compensation transistor is electrically connected between the second pole and the gate of the driving transistor; The active layer of the first reset transistor includes an oxide semiconductor material, and / or, the active layer of the threshold compensation transistor includes an oxide semiconductor material.

14. A display device, characterized in that, Comprising the display panel according to any one of claims 1 to 13.

Images