Display panel, display device and driving control method

Abstract

The invention relates to the technical field of display, and discloses a display panel, a display device and a driving control method.The display panel comprises a plurality of sub-pixels, a plurality of data lines, a plurality of data input lines and a plurality of gate control circuits, any one of the data lines is connected with the sub-pixels with the same color, and the data input lines are connected with the gate control circuits; one data input line is connected with a plurality of data lines through one gating control circuit, the colors of the sub-pixels corresponding to the data lines connected with any gating control circuit are the same, and the gating control circuits are configured to enable the data input lines to be communicated with the data lines connected with the data input lines respectively; therefore, the jump voltage among a plurality of data voltages provided by the source electrode driving circuit for the same data line is reduced, the power consumption of the source electrode driving circuit is effectively reduced, and the service life of the display panel is prolonged.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and provides a display panel, a display device, and a driving control method. Background Art

[0002] In related technologies, during the use of a display panel (such as an OLED, a mini LED, a Micro LED, etc.), the power consumption of the display screen, the power consumption of signal transmission, the power consumption of rendering pictures, etc. are all relatively high. Especially for a source chip that provides data voltages for each sub-pixel respectively, as the display picture becomes richer and richer, when the source chip provides data voltages for multiple sub-pixels on each data line, the data voltage jumps of adjacent sub-pixels, especially sub-pixels of different colors, are relatively large, resulting in a large power consumption of the source chip. The above power consumption makes it impossible to guarantee the standby time of the display panel. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display panel, a display device, and a driving control method, which reduce the jump voltage between multiple data voltages provided by a source driving circuit for the same data line, effectively reduce the power consumption of the source driving circuit, and improve the usage duration of the display panel.

[0004] The specific technical solutions provided by the present disclosure are as follows:

[0005] In a first aspect, embodiments of the present disclosure provide a display panel, including:

[0006] Multiple sub-pixels;

[0007] Multiple data lines, and any one of the multiple data lines is connected to multiple sub-pixels of the same color;

[0008] Multiple data input lines;

[0009] Multiple gating control circuits, one data input line is connected to multiple data lines through one gating control circuit, and the sub-pixels corresponding to the data lines connected by any one gating control circuit have the same color. The gating control circuit is configured to connect the data input line to the multiple data lines connected thereto respectively.

[0010] In some possible implementation manners, it further includes multiple gating control lines connected to the gating control circuits, and the multiple gating control lines are correspondingly arranged with the multiple data lines connected to the gating control circuits;

[0011] The gating control circuit is further configured to: in response to a gating control signal on the gating control line, connect the corresponding data line to the data input line.

[0012] In some possible embodiments, the strobe control circuit includes: a plurality of switching transistors, which are correspondingly arranged with a plurality of strobe control lines;

[0013] The control terminal of any one of the switching transistors is connected to the corresponding strobe control line, the first terminal of any one of the switching transistors is connected to the corresponding data line, and the second terminals of the plurality of switching transistors are all connected to the data input line.

[0014] In some possible embodiments, the sub-pixels in the odd rows of a column of sub-pixels and the sub-pixels in the even rows of a column of sub-pixels are respectively connected to different data lines.

[0015] In some possible embodiments, the plurality of sub-pixels include a first sub-pixel column and a second sub-pixel column alternately arranged in a first direction. The first sub-pixel column includes a first color sub-pixel and a second color sub-pixel alternately arranged in a second direction, and the second sub-pixel column includes a third color sub-pixel arranged in the second direction;

[0016] Two data lines are correspondingly arranged for the first sub-pixel column. The two data lines include a first data line and a second data line. The first data line is connected to the first color sub-pixel in the first sub-pixel column, and the second data line is connected to the second color sub-pixel in the first sub-pixel column;

[0017] Two data lines are correspondingly arranged for the second sub-pixel column. The two data lines include a third data line and a fourth data line. The third data line is connected to the third color sub-pixels in the odd rows of the second sub-pixel column, and the fourth data line is connected to the third color sub-pixels in the even rows of the second sub-pixel column.

[0018] In some possible embodiments, the strobe control line connected by the strobe control circuit corresponding to the first data line and the strobe control line connected by the strobe control circuit corresponding to the third data line are the same strobe control line;

[0019] The strobe control line connected by the strobe control circuit corresponding to the second data line and the strobe control line connected by the strobe control circuit corresponding to the fourth data line are the same strobe control line.

[0020] In some possible embodiments, the plurality of sub-pixels include a third sub-pixel column, a fourth sub-pixel column and a fifth sub-pixel column alternately arranged in a first direction. The third sub-pixel column includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel alternately arranged in a second direction. The fourth sub-pixel column includes a second color sub-pixel, a third color sub-pixel and a first color sub-pixel alternately arranged in a second direction. The fifth sub-pixel column includes a third color sub-pixel, a first color sub-pixel and a second color sub-pixel alternately arranged in a second direction;

[0021] The third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column are each correspondingly provided with six data lines, and the six data lines include: a fifth data line, a sixth data line, a seventh data line, an eighth data line, a ninth data line, and a tenth data line;

[0022] The fifth data line is connected to the first-color sub-pixels of the odd rows in the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column;

[0023] The sixth data line is connected to the second-color sub-pixels of the odd rows in the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column;

[0024] The seventh data line is connected to the third-color sub-pixels of the odd rows in the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column;

[0025] The eighth data line is connected to the first-color sub-pixels of the even rows in the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column;

[0026] The ninth data line is connected to the second-color sub-pixels of the even rows in the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column;

[0027] The tenth data line is connected to the third-color sub-pixels of the even rows in the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column.

[0028] In some possible implementation manners, the gate control lines connected to the gate control circuits corresponding to the fifth data line, the gate control lines connected to the gate control circuits corresponding to the sixth data line, and the gate control lines connected to the gate control circuits corresponding to the seventh data line are the same gate control line;

[0029] The gate control lines connected to the gate control circuits corresponding to the eighth data line, the gate control lines connected to the gate control circuits corresponding to the ninth data line, and the gate control lines connected to the gate control circuits corresponding to the tenth data line are the same gate control line.

[0030] In a second aspect, an embodiment of the present disclosure further provides a display device, including the display panel of any one of the above.

[0031] In some possible implementation manners, it further includes a source driver circuit;

[0032] The source driver circuit is connected to the gate control lines and is configured to provide gate control signals to the gate control lines.

[0033] In some possible implementation manners, one data input line is correspondingly connected to a connection terminal of the source driver circuit.

[0034] In a third aspect, an embodiment of the present disclosure further provides a driving control method for the display panel of any one of the above, including:

[0035] Each data input line is used to receive data voltages from different connection terminals of the source driver circuit respectively;

[0036] Any one of the gating control circuits is used to provide the multiple data voltages received from the data input lines to the corresponding connected data lines respectively.

[0037] In some possible implementation manners, it further includes:

[0038] The cut-off moment of the effective duration of the scanning signal of the scanning signal terminal corresponding to the sub-pixels in the nth row is not earlier than the effective start moment of the gating control signals corresponding to all the sub-pixels in the (n + 1)th row.

[0039] The beneficial effects of the present disclosure are as follows:

[0040] In summary, in the embodiments of the present disclosure, a display panel, a display device, and a driving control method are provided. The display panel includes: a plurality of sub-pixels, a plurality of data lines, a plurality of data input lines, and a plurality of gating control circuits. Any one of the plurality of data lines is connected to a plurality of sub-pixels with the same color. One data input line is connected to a plurality of data lines through one gating control circuit. The sub-pixels corresponding to the data lines connected by any one of the gating control circuits have the same color. The gating control circuit is configured to connect the data input line to the plurality of data lines connected thereto respectively, thereby reducing the jump voltage between the multiple data voltages provided by the source driver circuit for the same data line. Especially during the display process of a pure color screen, the power consumption of the source driver circuit is effectively reduced, and the service life of the display panel is improved.

[0041] Other features and advantages of the present disclosure will be described in subsequent specifications, and, in part, will become obvious from the specifications, or will be understood by implementing the present disclosure. The objectives and other advantages of the present disclosure can be achieved and obtained by the structures specifically pointed out in the written specifications, claims, and drawings. Description of the Drawings

[0042] The drawings described herein are used to provide a further understanding of the present disclosure, and constitute a part of the present disclosure. The schematic embodiments of the present disclosure and their descriptions are used to explain the present disclosure, and do not constitute an improper limitation to the present disclosure. In the drawings:

[0043] Figure 1 It is a schematic diagram of the first display panel in the embodiments of the present disclosure;

[0044] Figure 2 It is a schematic diagram of the second display panel in the embodiments of the present disclosure;

[0045] Figure 3 It is a schematic diagram of the third display panel in the embodiments of the present disclosure;

[0046] Figure 4 Schematic connection diagram of a gating control circuit in an embodiment of the present disclosure;

[0047] Figure 5 Schematic connection diagram of the first gating control circuit and each sub-pixel in a display panel in an embodiment of the present disclosure;

[0048] Figure 6 Schematic connection diagram of the second gating control circuit and each sub-pixel in a display panel in an embodiment of the present disclosure;

[0049] Figure 7 Schematic connection diagram of a gating control circuit in an embodiment of the present disclosure;

[0050] Figure 8 Schematic architecture diagram of the first display panel in an embodiment of the present disclosure;

[0051] Figure 9 Schematic architecture diagram of the second display panel in an embodiment of the present disclosure;

[0052] Figure 10 Schematic architecture diagram of the third display panel in an embodiment of the present disclosure;

[0053] Figure 11 Schematic timing diagram of the first display panel in an embodiment of the present disclosure;

[0054] Figure 12 Schematic timing diagram of the second display panel in an embodiment of the present disclosure;

[0055] Figure 13 Schematic connection diagram of a display device in an embodiment of the present disclosure;

[0056] Figure 14 Schematic connection diagram of another display device in an embodiment of the present disclosure;

[0057] Figure 15 Flowchart of a method for driving and controlling a display panel in an embodiment of the present disclosure. Detailed implementation manners

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments described in this disclosure document, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the technical solutions of the present disclosure.

[0059] In the description, claims, and above-mentioned drawings of the present invention, terms such as "first" and "second" are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data used can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.

[0060] In the related art, during the use of a display panel (such as OLED, mini LED, Micro LED, etc.), the power consumption of the display screen, the power consumption of signal transmission, the power consumption of rendering pictures, etc. are all relatively high. Especially for the source chip that provides data voltages for each sub-pixel respectively, as the display screen becomes more and more rich, during the process of the source chip providing data voltages for multiple sub-pixels on each data line, the data voltage jumps of adjacent sub-pixels, especially different-color sub-pixels, are relatively large, resulting in a large power consumption of the source chip. The above power consumption makes it impossible to guarantee the standby duration of the display panel.

[0061] Exemplarily, during the process of a data line providing data voltages for multiple sub-pixels of different colors, the voltage differences between data voltages of different colors (such as red and green or red and blue, etc.) are usually relatively large. In this way, the source chip needs to switch between multiple data voltages of different voltage values, resulting in a relatively large power consumption of the source chip.

[0062] The following will describe the embodiments of the present disclosure in detail with reference to the drawings.

[0063] A display panel proposed in an embodiment of the present application includes: a plurality of sub-pixels, a plurality of data lines, a plurality of data input lines, and a plurality of gating control circuits.

[0064] The display panel in the embodiment of the present application includes a plurality of sub-pixels, and the plurality of sub-pixels are arranged in an array in the display panel.

[0065] Exemplarily, referring to Figure 1 As shown, a pixel unit in the display panel includes sub-pixel R, first sub-pixel G, sub-pixel B, and second sub-pixel G. The above sub-pixel R, first sub-pixel G, sub-pixel B, and second sub-pixel G are sequentially and repeatedly arranged in the row direction in units of pixel units. It should be added that the above sub-pixel R represents a sub-pixel with a red color, the above sub-pixel B represents a sub-pixel with a blue color, and the above first sub-pixel G and second sub-pixel G represent sub-pixels with a green color located in different columns.

[0066] Exemplarily, referring to Figure 2As shown, a pixel unit in the display panel includes sub-pixel B, sub-pixel G, sub-pixel R, and sub-pixel G. The above-mentioned sub-pixel B, sub-pixel G, sub-pixel R, and sub-pixel G are sequentially and repeatedly arranged in the row direction in units of pixel units.

[0067] Exemplarily, refer to Figure 3 As shown, a pixel unit in the display panel includes sub-pixel R, sub-pixel G, and sub-pixel B. The above-mentioned sub-pixel R, sub-pixel G, and sub-pixel B are sequentially and repeatedly arranged in the row direction in units of pixel units.

[0068] The above display panel further includes a plurality of data lines, and any one of the plurality of data lines is connected to a plurality of sub-pixels of the same color.

[0069] Different from the related art, the data lines in the embodiments of the present application are not connected to a column of sub-pixels in a one-to-one correspondence. In the embodiments of the present application, a column of sub-pixels is connected to a plurality of data lines. The sub-pixels of the same color in a column of sub-pixels are connected to the same data line. When there are multiple colors of sub-pixels included in a column of sub-pixels, there are also multiple corresponding data lines. In this way, each data line can be connected to a plurality of sub-pixels of the same color, and different data lines are respectively connected to a plurality of sub-pixels of different colors.

[0070] Exemplarily, refer to Figure 1 As shown, the sub-pixel R in the odd rows of the first column is connected to the data line DA1, the sub-pixel B in the even rows of the first column is connected to the data line DA2, the sub-pixel G in the odd rows of the second column is connected to the data line DA3, the sub-pixel G in the even rows of the second column is connected to the data line DA4, the sub-pixel B in the odd rows of the third column is connected to the data line DA5, the sub-pixel R in the even rows of the third column is connected to the data line DA6, the sub-pixel G in the odd rows of the fourth column is connected to the data line DA7, and the sub-pixel G in the even rows of the fourth column is connected to the data line DA8.

[0071] Exemplarily, refer to Figure 2 As shown, the sub-pixel B in the odd rows of the first column is connected to the data line DA1, the sub-pixel R in the even rows of the first column is connected to the data line DA2, the sub-pixel G in the odd rows of the second column is connected to the data line DA3, the sub-pixel G in the even rows of the second column is connected to the data line DA4, the sub-pixel R in the odd rows of the third column is connected to the data line DA5, the sub-pixel B in the even rows of the third column is connected to the data line DA6, the sub-pixel G in the odd rows of the fourth column is connected to the data line DA7, and the sub-pixel G in the even rows of the fourth column is connected to the data line DA8.

[0072] Exemplarily, refer to Figure 3As shown, the sub-pixel R in the odd rows of the first column and the sub-pixel R in the odd rows of the second column are both connected to the data line DA1. The sub-pixel G in the even rows of the first column and the sub-pixel G in the even rows of the second column are both connected to the data line DA5. The sub-pixel G in the odd rows of the second column and the sub-pixel G in the odd rows of the third column are both connected to the data line DA2. The sub-pixel B in the even rows of the second column and the sub-pixel B in the even rows of the third column are both connected to the data line DA6. The sub-pixel B in the odd rows of the third column and the sub-pixel B in the odd rows of the first column are both connected to the data line DA3. The sub-pixel R in the even rows of the third column and the sub-pixel R in the even rows of the first column are both connected to the data line DA4.

[0073] The above display panel further includes a plurality of data input lines. The data input lines in the embodiments of the present application are mainly used to receive data voltages. During the implementation process, the data voltages generated by the source driver circuit are first provided to the data input lines, and the data voltages in the above data input lines are respectively provided to the corresponding connected plurality of data lines when the gating control circuit is turned on.

[0074] In the above display panel, a data input line is connected to a plurality of data lines through a gating control circuit. The colors of the sub-pixels corresponding to the data lines connected by any gating control circuit are the same, and the gating control circuit is configured to connect the data input line to the plurality of data lines connected thereto.

[0075] The multiple gating control circuits provided in the embodiments of the present application are mainly used to connect each data input line and each data line. That is, when the gating control circuit is turned on, the data voltage received by the data input line is provided to the corresponding data line through the gating control circuit.

[0076] It should be noted that in the embodiments of the present application, the quantitative relationship between the data input line and the data line is one-to-many. Exemplarily, for a gating control circuit, the number of data input lines connected thereto is one, and the number of data lines connected thereto is the same as the number of colors of the sub-pixels included in the pixel unit in the display panel. That is, the number of colors of the sub-pixels corresponding to the data lines connected by a gating control circuit is the same as the number of colors of the sub-pixels included in a pixel unit.

[0077] Exemplarily, referring to Figure 1 and Figure 2 As shown, when a pixel unit in the display panel includes a sub-pixel R, a first sub-pixel G, a sub-pixel B, and a second sub-pixel G, the number of data input lines connected by a gating control circuit is 1, and the minimum number of data lines connected by a gating control circuit is 4 (usually a multiple of 4).

[0078] Exemplarily, referring to Figure 3As shown, when a pixel unit in the display panel includes sub-pixel R, sub-pixel G, and sub-pixel B, the number of data input lines connected to a gating control circuit is 1, and the minimum number of data lines connected to a gating control circuit is 3 (usually a multiple of 3). The number of colors of the sub-pixels corresponding to the data lines connected to the above-mentioned gating control circuit is 3. It should be added that the arrangement order of the above-mentioned sub-pixel R, sub-pixel G, and sub-pixel B in the display panel is not specifically limited.

[0079] Referring to Figure 4 、 Figure 5 and Figure 6 As shown, the above-mentioned display panel further includes a plurality of gating control lines connected to the gating control circuit, and the plurality of gating control lines are correspondingly arranged with the plurality of data lines connected to the gating control circuit.

[0080] The gating control circuit is further configured to: in response to the gating control signal on the gating control line, connect the corresponding data line to the data input line.

[0081] In the embodiment of the present application, the gating control line is connected to the gating control circuit. The gating control line is used to send the gating control signal to the gating control circuit, so that the gating control circuit is turned on under the action of the gating control signal, and then the data input line is connected to the corresponding data line.

[0082] It should be noted that the number of the above-mentioned gating control lines is correspondingly set with the number of data lines, that is, the number of gating control lines is the same as the number of data lines. In this way, each gating control signal can accurately control the gating control circuit corresponding to the data line to be turned on, connect the data input line to the corresponding data line, and further provide a data voltage for the corresponding data line.

[0083] Exemplarily, referring to Figure 4 As shown, gating control line 1, gating control line 2, gating control line 3, data input line 1, data line 1, data line 2, and data line 3 are all connected to the gating control circuit. Assume that gating control line 1 corresponds to data line 1, gating control line 2 corresponds to data line 2, and gating control line 3 corresponds to data line 3. Then, after gating control line 1 provides the gating control signal 1 to the gating control circuit, the gating control circuit is turned on under the action of the gating control signal 1, and data input line 1 and data line 1 are connected; after gating control line 2 provides the gating control signal 2 to the gating control circuit, the gating control circuit is turned on under the action of the gating control signal 2, and data input line 1 and data line 2 are connected; after gating control line 3 provides the gating control signal 3 to the gating control circuit, the gating control circuit is turned on under the action of the gating control signal 3, and data input line 1 and data line 3 are connected.

[0084] Similarly, referring to Figure 6As shown, the select control line 1 corresponds to the data input line 1, the data lines DA1 and DA6; the select control line 2 corresponds to the data input line 3, the data lines DA2 and DA5; the select control line 3 corresponds to the data input line 2, the data lines DA3 and DA7; the select control line 4 corresponds to the data input line 2, the data lines DA4 and DA8.

[0085] Referring to Figure 7 As shown, the above select control circuit includes: a plurality of switching transistors, and the plurality of switching transistors are correspondingly arranged with a plurality of select control lines.

[0086] The control terminal of any one of the switching transistors is connected to the corresponding select control line, the first terminal of any one of the switching transistors is connected to the corresponding data line, and the second terminals of the plurality of switching transistors are all connected to the data input line.

[0087] In the embodiment of the present application, the select control circuit includes a plurality of switching transistors. The number of the above switching transistors is equal to the number of select control lines, that is, the number of switching transistors is equal to the number of data lines. Whether the data input line is connected to the data line is determined by whether the switching transistor is turned on or off.

[0088] For each switching transistor, the control terminal of the switching transistor is connected to the select control line, the first terminal of the switching transistor is connected to the data line, and the second terminals of the switching transistors are all connected to the data input line.

[0089] Exemplarily, referring to Figure 7 As shown, the select control circuit includes a switching transistor M1. The control terminal of the switching transistor M1 is connected to the first select control line. The first terminal of the switching transistor M1 is connected to the data line 1. The second terminal of the switching transistor M1 is connected to the data input line 1. The select control circuit further includes a switching transistor M2. The control terminal of the switching transistor M2 is connected to the second select control line. The first terminal of the switching transistor M2 is connected to the data line 2. The second terminal of the switching transistor M2 is connected to the data input line 1. It should be noted that the above data line 1 and the data line 2 are the data lines respectively connected to the sub-pixels with the same color, that is, the data input line 1 provides data voltages for the data line 1 and the data line 2 through the switching transistor M1 and the switching transistor M2 respectively.

[0090] After introducing the connection relationship between the data input line, the select control circuit and the data line, the following will be introduced in combination with the specific connection relationship of each sub-pixel in the display panel.

[0091] The sub-pixels in the odd rows and the sub-pixels in the even rows in a column of sub-pixels are respectively connected to different data lines.

[0092] Considering that the sub-pixels in the odd rows and the sub-pixels in the even rows of a column of sub-pixels in the display panel are usually sub-pixels of different colors, in the embodiments of the present application, the sub-pixels in the odd rows of a column of sub-pixels are connected to one data line, and the sub-pixels in the even rows of a column of sub-pixels are connected to another data line, so that different data lines provide data voltages for sub-pixels of different colors.

[0093] When the sub-pixels in the odd rows and the sub-pixels in the even rows of a column of sub-pixels are sub-pixels of the same color, the sub-pixels in the odd rows of a column of sub-pixels can also be connected to one data line, and the sub-pixels in the even rows of a column of sub-pixels can be connected to another data line, that is, a column of sub-pixels of the same color are respectively provided with data voltages by different data lines.

[0094] The following will specifically introduce in combination with the situation of the sub-pixels in the display panel:

[0095] In the first embodiment, referring to Figure 8 and Figure 9 as shown, a plurality of sub-pixels include a first sub-pixel column and a second sub-pixel column alternately arranged in a first direction. The first sub-pixel column includes a first color sub-pixel and a second color sub-pixel alternately arranged in a second direction, and the second sub-pixel column includes a third color sub-pixel arranged in the second direction.

[0096] Referring to Figure 8 as shown, a plurality of sub-pixels include a first sub-pixel column and a second sub-pixel column alternately arranged in a first direction (exemplarily, the column direction). Taking the sub-pixels in the first column in Figure 8 as the above-mentioned first sub-pixel column and the sub-pixels in the second column in Figure 8 as the above-mentioned second sub-pixel column for illustration. The first sub-pixel column includes a first color sub-pixel (i.e., the sub-pixel R in Figure 8 ) and a second color sub-pixel (i.e., the sub-pixel B in Figure 8 ) alternately arranged in a second direction (i.e., the row direction), and the second sub-pixel column includes a third color sub-pixel (i.e., the sub-pixel G in Figure 8 ) arranged in the second direction (i.e., the row direction).

[0097] Referring to Figure 9 as shown, a plurality of sub-pixels include a first sub-pixel column and a second sub-pixel column alternately arranged in a first direction (exemplarily, the column direction). Taking the sub-pixels in the first column in Figure 9 as the above-mentioned first sub-pixel column and the sub-pixels in the second column in Figure 9 as the above-mentioned second sub-pixel column for illustration. The first column of sub-pixels includes a first color sub-pixel (i.e., the sub-pixel B in Figure 9 ) and a second color sub-pixel (i.e., the sub-pixel in Figure 9The first sub-pixel column includes third color sub-pixels (i.e., sub-pixels R in it), and the second sub-pixel column includes third color sub-pixels (i.e., sub-pixels G in it) arranged along the second direction (i.e., the row direction). Figure 9 in it).

[0098] Two data lines are correspondingly set for the first sub-pixel column. The two data lines include a first data line and a second data line. The first data line is connected to the first color sub-pixels in the first sub-pixel column, and the second data line is connected to the second color sub-pixels in the first sub-pixel column.

[0099] Considering that the number of colors of the sub-pixels included in the first sub-pixel column is two, in the embodiments of the present application, two data lines are correspondingly set for the first sub-pixel column, namely the first data line and the second data line. Refer to Figure 8 as shown, the first data line is connected to the first color sub-pixels (i.e., sub-pixels R) in the first sub-pixel column, and the second data line is connected to the second color sub-pixels (i.e., sub-pixels B) in the first sub-pixel column.

[0100] Similarly, refer to Figure 9 as shown, the first data line is connected to the first color sub-pixels (i.e., sub-pixels B) in the first sub-pixel column, and the second data line is connected to the second color sub-pixels (i.e., sub-pixels R) in the first sub-pixel column.

[0101] Two data lines are correspondingly set for the second sub-pixel column. The two data lines include a third data line and a fourth data line. The third data line is connected to the third color sub-pixels in the odd rows of the second sub-pixel column, and the fourth data line is connected to the third color sub-pixels in the even rows of the second sub-pixel column.

[0102] In order to unify the connection method with the first sub-pixel column, that is, to ensure that the number of sub-pixels connected to each data line is equal, in the embodiments of the present application, two data lines are also correspondingly set for the second sub-pixel column, namely the third data line and the fourth data line. Refer to Figure 8 as shown, the third data line is connected to the third color sub-pixels (i.e., sub-pixels G in the odd rows) in the odd rows of the second sub-pixel column, and the fourth data line is connected to the third color sub-pixels (i.e., sub-pixels G in the even rows) in the even rows of the second sub-pixel column.

[0103] Similarly, refer to Figure 9 as shown, the third data line is connected to the third color sub-pixels (i.e., sub-pixels G in the odd rows) in the odd rows of the second sub-pixel column, and the fourth data line is connected to the third color sub-pixels (i.e., sub-pixels G in the even rows) in the even rows of the second sub-pixel column.

[0104] Refer to Figure 8 and Figure 9 as shown, the strobe control line connected to the strobe control circuit corresponding to the first data line and the strobe control line connected to the strobe control circuit corresponding to the third data line are the same strobe control line.

[0105] The strobe control line connected to the strobe control circuit corresponding to the second data line and the strobe control line connected to the strobe control circuit corresponding to the fourth data line are the same strobe control line.

[0106] In order to save the connection terminals of the source driver circuit, the number of data input lines in the embodiments of the present application is less than the number of data lines. For a strobe control circuit, the number of connection terminals connected to the source driver circuit, that is, the number of data input lines, is the same as the number of colors of the sub-pixels included in a pixel unit of the display panel. In this way, the same data input line can provide data voltages for different data lines of the same color respectively, that is, the above purpose is achieved through the switching transistors connected to different data lines, thereby being able to save the power consumption of the source driver circuit to the greatest extent.

[0107] In the embodiments of the present application, the strobe of different data lines can be further realized through time-sharing control of odd rows and even rows. Refer to Figure 8 and Figure 9 As shown, the strobe control line connected to the strobe control circuit corresponding to the first data line (i.e., the data line corresponding to the odd rows in the first sub-pixel column) and the strobe control line connected to the strobe control circuit corresponding to the third data line (i.e., the data line corresponding to the odd rows in the second sub-pixel column) are the same strobe control line, that is, the strobe control of the data line corresponding to the odd rows in the first sub-pixel column and the data line corresponding to the odd rows in the second sub-pixel column is realized through the above same strobe control line.

[0108] The strobe control line connected to the strobe control circuit corresponding to the second data line and the strobe control line connected to the strobe control circuit corresponding to the fourth data line are the same strobe control line.

[0109] Similarly, refer to Figure 8 and Figure 9 As shown, the strobe control line connected to the strobe control circuit corresponding to the second data line (i.e., the data line corresponding to the even rows in the first sub-pixel column) and the strobe control line connected to the strobe control circuit corresponding to the fourth data line (i.e., the data line corresponding to the even rows in the second sub-pixel column) are the same strobe control line, that is, the strobe control of the data line corresponding to the even rows in the first sub-pixel column and the data line corresponding to the even rows in the second sub-pixel column is realized through the above same strobe control line.

[0110] In the second embodiment, refer to Figure 10As shown, a plurality of sub-pixels include a third sub-pixel column, a fourth sub-pixel column, and a fifth sub-pixel column alternately arranged in a first direction. The third sub-pixel column includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel alternately arranged in a second direction. The fourth sub-pixel column includes a second color sub-pixel, a third color sub-pixel, and a first color sub-pixel alternately arranged in the second direction. The fifth sub-pixel column includes a third color sub-pixel, a first color sub-pixel, and a second color sub-pixel alternately arranged in the second direction.

[0111] Refer to Figure 10 As shown, a plurality of sub-pixels include a third sub-pixel column, a fourth sub-pixel column, and a fifth sub-pixel column alternately arranged in a first direction (exemplarily, the column direction), taking the sub-pixels in the first column in Figure 10 as the above-mentioned third sub-pixel column, taking the sub-pixels in the second column in Figure 10 as the above-mentioned fourth sub-pixel column, and taking the sub-pixels in the third column in Figure 10 as the above-mentioned fifth sub-pixel column for illustration.

[0112] Refer to Figure 10 As shown, the third sub-pixel column includes a first color sub-pixel (i.e., the sub-pixel R in Figure 10 ), a second color sub-pixel (i.e., the sub-pixel G in Figure 10 ), and a third color sub-pixel (i.e., the sub-pixel B in Figure 10 ) alternately arranged in a second direction (i.e., the row direction). The fourth sub-pixel column includes a second color sub-pixel (i.e., the sub-pixel G in Figure 10 ), a third color sub-pixel (i.e., the sub-pixel B in Figure 10 ), and a first color sub-pixel (i.e., the sub-pixel R in Figure 10 ) alternately arranged in the second direction. The fifth sub-pixel column includes a third color sub-pixel (i.e., the sub-pixel B in Figure 10 ), a first color sub-pixel (i.e., the sub-pixel R in Figure 10 ), and a second color sub-pixel (i.e., the sub-pixel G in Figure 10 ) alternately arranged in the second direction.

[0113] Six data lines are correspondingly arranged for the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column. The six data lines include: a fifth data line, a sixth data line, a seventh data line, an eighth data line, a ninth data line, and a tenth data line.

[0114] The fifth data line is connected to the first color sub-pixels in the odd rows of the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column.

[0115] The sixth data line is connected to the second color sub-pixels in the odd rows of the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column.

[0116] The seventh data line is connected to the third color sub-pixels of the odd rows in the third, fourth, and fifth sub-pixel columns.

[0117] The eighth data line is connected to the first color sub-pixels of the even rows in the third, fourth, and fifth sub-pixel columns.

[0118] The ninth data line is connected to the second color sub-pixels of the even rows in the third, fourth, and fifth sub-pixel columns.

[0119] The tenth data line is connected to the third color sub-pixels of the even rows in the third, fourth, and fifth sub-pixel columns.

[0120] Similarly, in order to achieve the purpose that the sub-pixels with the same color in the same column of sub-pixels are connected to the same data line, and the sub-pixels with different colors are connected to different data lines, in Figure 10 the pixel architecture shown, that is, if the three-color sub-pixels in the third, fourth, and fifth sub-pixel columns are arranged separately by odd and even rows, there are a total of 6 cases. Correspondingly, Figure 10 six data lines are correspondingly set for the third, fourth, and fifth sub-pixel columns, namely the fifth data line, the sixth data line, the seventh data line, the eighth data line, the ninth data line, and the tenth data line.

[0121] In order to distinguish the sub-pixel colors and the odd and even rows, in the embodiment of the present application, the fifth data line is connected to the first color sub-pixels of the odd rows in the third, fourth, and fifth sub-pixel columns. Refer to Figure 10 shown, the first color sub-pixels of the odd rows in the third sub-pixel column (exemplarily, Figure 10 the sub-pixel R in the first row of the first column in Figure 10 the sub-pixel R in the seventh row of the first column in Figure 10 the sub-pixel R in the third row of the second column in Figure 10 the sub-pixel R in the ninth row of the second column in Figure 10 the sub-pixel R in the fifth row of the third column in Figure 10 the sub-pixel R in the eleventh row of the third column in

[0122] Similarly, refer to Figure 10 shown, the second color sub-pixels of the odd rows in the third sub-pixel column (exemplarily, Figure 10 the sub-pixel G in the fifth row of the first column in Figure 10 the sub-pixel G in the eleventh row of the first column in Figure 10The sub-pixel G in the first row of the second column, Figure 10 the sub-pixel G in the seventh row of the second column) and the second-color sub-pixels in the odd rows of the fifth sub-pixel column (exemplarily, Figure 10 the sub-pixel G in the third row of the third column, Figure 10 the sub-pixel G in the ninth row of the third column) are all connected to the sixth data line.

[0123] Similarly, referring to Figure 10 as shown, the third-color sub-pixels in the odd rows of the third sub-pixel column (exemplarily, Figure 10 the sub-pixel B in the third row of the first column, Figure 10 the sub-pixel B in the ninth row of the first column), the third-color sub-pixels in the odd rows of the fourth sub-pixel column (exemplarily, Figure 10 the sub-pixel B in the fifth row of the second column, Figure 10 the sub-pixel B in the eleventh row of the second column) and the third-color sub-pixels in the odd rows of the fifth sub-pixel column (exemplarily, Figure 10 the sub-pixel B in the first row of the third column, Figure 10 the sub-pixel B in the seventh row of the third column) are all connected to the seventh data line.

[0124] Similarly, referring to Figure 10 as shown, the first-color sub-pixels in the even rows of the third sub-pixel column (exemplarily, Figure 10 the sub-pixel R in the fourth row of the first column, Figure 10 the sub-pixel R in the tenth row of the first column), the first-color sub-pixels in the even rows of the fourth sub-pixel column (exemplarily, Figure 10 the sub-pixel R in the sixth row of the second column, Figure 10 the sub-pixel R in the twelfth row of the second column) and the first-color sub-pixels in the even rows of the fifth sub-pixel column (exemplarily, Figure 10 the sub-pixel R in the second row of the third column, Figure 10 the sub-pixel R in the eighth row of the third column) are all connected to the eighth data line.

[0125] Similarly, referring to Figure 10 as shown, the second-color sub-pixels in the even rows of the third sub-pixel column (exemplarily, Figure 10 the sub-pixel G in the second row of the first column, Figure 10 the sub-pixel G in the eighth row of the first column), the second-color sub-pixels in the even rows of the fourth sub-pixel column (exemplarily, Figure 10 the sub-pixel G in the fourth row of the second column, Figure 10 the sub-pixel G in the tenth row of the second column) and the second-color sub-pixels in the even rows of the fifth sub-pixel column (exemplarily, Figure 10 the sub-pixel G in the sixth row of the third column, Figure 10 the sub-pixel G in the twelfth row of the third column) are all connected to the ninth data line.

[0126] Similarly, referring to Figure 10 as shown, the third color sub-pixels in the even rows of the third sub-pixel column (exemplarily, Figure 10 sub-pixel B in the sixth row of the first column in Figure 10 sub-pixel B in the twelfth row of the first column in), the third color sub-pixels in the even rows of the fourth sub-pixel column (exemplarily, Figure 10 sub-pixel B in the second row of the second column in Figure 10 sub-pixel B in the eighth row of the second column in) and the third color sub-pixels in the even rows of the fifth sub-pixel column (exemplarily, Figure 10 sub-pixel B in the fourth row of the third column in Figure 10 sub-pixel B in the tenth row of the third column in) are all connected to the tenth data line.

[0127] Referring to Figure 10 as shown, the strobe control lines connected to the strobe control circuits corresponding to the fifth data line, the strobe control lines connected to the strobe control circuits corresponding to the sixth data line, and the strobe control lines connected to the strobe control circuits corresponding to the seventh data line are the same strobe control line.

[0128] The strobe control lines connected to the strobe control circuits corresponding to the eighth data line, the strobe control lines connected to the strobe control circuits corresponding to the ninth data line, and the strobe control lines connected to the strobe control circuits corresponding to the tenth data line are the same strobe control line.

[0129] In the embodiments of the present application, in order to implement the control of the data lines corresponding to the odd rows, even rows, and sub-pixels of different colors, the above-mentioned fifth data line, sixth data line, and seventh data line can be correspondingly connected to the same strobe control line. Similarly, the eighth data line, ninth data line, and tenth data line can also be correspondingly connected to the same strobe control line, and then the strobe control signals (specifically, different switching transistors) on the same strobe control line are used to implement the strobe control of different data lines and the corresponding data input lines.

[0130] Referring to Figure 10As shown, the gate control lines connected to the gate control circuits corresponding to the fifth data line (i.e., the data line to which the first-color sub-pixels in the odd rows of the third, fourth, and fifth sub-pixel columns are correspondingly connected), the gate control lines connected to the gate control circuits corresponding to the sixth data line (i.e., the data line to which the second-color sub-pixels in the odd rows of the third, fourth, and fifth sub-pixel columns are correspondingly connected), and the gate control lines connected to the gate control circuits corresponding to the seventh data line (i.e., the data line to which the third-color sub-pixels in the odd rows of the third, fourth, and fifth sub-pixel columns are correspondingly connected) are the same gate control line. That is, through the above-mentioned same gate control line, the gating control of the data line to which the first-color sub-pixels in the odd rows of the third, fourth, and fifth sub-pixel columns are correspondingly connected, the data line to which the second-color sub-pixels in the odd rows of the third, fourth, and fifth sub-pixel columns are correspondingly connected, and the data line to which the third-color sub-pixels in the odd rows of the third, fourth, and fifth sub-pixel columns are correspondingly connected is respectively realized.

[0131] The following combines Figure 8 with the timing Figure 11 to describe in detail the working process of the gate control circuit in the embodiments of the present application.

[0132] Among them, 0 represents a low level, and 1 represents a high level. Combining Figure 8 it can be known that when the switching transistor is a P-type transistor, the above-mentioned low level 0 is the effective level.

[0133] First of all, it should be noted that the following description is based on the Figure 8 4 gate control circuits included. Among them, the gate control circuit 1 is connected to the data input line 1. The gate control circuit 1 includes a switching transistor M1, a switching transistor M2, a switching transistor M3, and a switching transistor M4. The control end of the above-mentioned switching transistor M1 is connected to the gate control line MUX1. The first end of the switching transistor M1 is connected to the data line M1. The second end of the switching transistor M1 is connected to the data input line 1. The control end of the above-mentioned switching transistor M2 is connected to the gate control line MUX2. The first end of the switching transistor M2 is connected to the data line M2. The second end of the switching transistor M2 is connected to the data input line 2. The control end of the above-mentioned switching transistor M3 is connected to the gate control line MUX3. The first end of the switching transistor M3 is connected to the data line M3. The second end of the switching transistor M3 is connected to the data input line 3. The control end of the above-mentioned switching transistor M4 is connected to the gate control line MUX4. The first end of the switching transistor M4 is connected to the data line M4. The second end of the switching transistor M4 is connected to the data input line 4.

[0134] The strobe control circuit 2 is connected to the data input line 2. The strobe control circuit 2 includes a switching transistor m1, a switching transistor m2, a switching transistor m3, and a switching transistor m4. The control terminal of the switching transistor m1 is connected to the strobe control line MUX1. The first terminal of the switching transistor m1 is connected to the data line m1. The second terminal of the switching transistor m1 is connected to the data input line 2. The control terminal of the switching transistor m2 is connected to the strobe control line MUX2. The first terminal of the switching transistor m2 is connected to the data line m2. The second terminal of the switching transistor m2 is connected to the data input line 2. The control terminal of the switching transistor m3 is connected to the strobe control line MUX3. The first terminal of the switching transistor m3 is connected to the data line m3. The second terminal of the switching transistor m3 is connected to the data input line 3. The control terminal of the switching transistor m4 is connected to the strobe control line MUX4. The first terminal of the switching transistor m4 is connected to the data line m4. The second terminal of the switching transistor m4 is connected to the data input line 4.

[0135] The strobe control circuit 3 is connected to the data input line 3. The strobe control circuit 3 includes a switching transistor T3, a switching transistor T1, a switching transistor T4, and a switching transistor T2. The control terminal of the switching transistor T1 is connected to the strobe control line MUX1. The first terminal of the switching transistor T1 is connected to the data line T1. The second terminal of the switching transistor T1 is connected to the data input line 3. The control terminal of the switching transistor T2 is connected to the strobe control line MUX2. The first terminal of the switching transistor T2 is connected to the data line T2. The second terminal of the switching transistor T2 is connected to the data input line 3. The control terminal of the switching transistor T3 is connected to the strobe control line MUX3. The first terminal of the switching transistor T3 is connected to the data line T3. The second terminal of the switching transistor T3 is connected to the data input line 3. The control terminal of the switching transistor T4 is connected to the strobe control line MUX4. The first terminal of the switching transistor T4 is connected to the data line T4. The second terminal of the switching transistor T4 is connected to the data input line 4.

[0136] The strobe control circuit 4 is connected to the data input line 4. The strobe control circuit 4 includes a switching transistor t1, a switching transistor t2, a switching transistor t3, and a switching transistor t4. The control terminal of the switching transistor t1 is connected to the strobe control line MUX1. The first end of the switching transistor t1 is connected to the data line t1. The second end of the switching transistor t1 is connected to the data input line 4. The control terminal of the switching transistor t2 is connected to the strobe control line MUX2. The first end of the switching transistor t2 is connected to the data line t2. The second end of the switching transistor t2 is connected to the data input line 4. The control terminal of the switching transistor t3 is connected to the strobe control line MUX3. The first end of the switching transistor t3 is connected to the data line t3. The second end of the switching transistor t3 is connected to the data input line 4. The control terminal of the switching transistor t4 is connected to the strobe control line MUX4. The first end of the switching transistor t4 is connected to the data line t4. The second end of the switching transistor t4 is connected to the data input line 4.

[0137] Timing Row1 stage: MUX1 = 0, MUX2 = 0, MUX3 = 1, MUX4 = 1

[0138] In this timing stage, the strobe control signal MUX1 is valid. The switching transistors M1, m1, T1, and t1 connected to the strobe control line MUX1 are all turned on. The data input line 1 is connected to the data line M1 through the turned-on switching transistor M1. The data voltage 1 in the data input line 1 is supplied to the data line M1. The data input line 2 is connected to the data line m1 through the turned-on switching transistor m1. The data voltage 2 in the data input line 2 is supplied to the data line m1. The data input line 3 is connected to the data line T1 through the turned-on switching transistor T1. The data voltage 3 in the data input line 3 is supplied to the data line T1. The data input line 4 is connected to the data line t1 through the turned-on switching transistor t1. The data voltage 4 in the data input line 4 is supplied to the data line t1.

[0139] The strobe control signal MUX2 is valid. The switching transistors m2, M2, T2, and t2 connected to the strobe control line MUX2 are turned on. The data voltage 2 in the data input line 2 is supplied to the data line m2 through the turned-on switching transistor m2. The data voltage 1 in the data input line 1 is supplied to the data line M2 through the turned-on switching transistor M2. The data voltage 3 in the data input line 3 is supplied to the data line T2 through the turned-on switching transistor T2. The data voltage 4 in the data input line 4 is supplied to the data line t2 through the turned-on switching transistor t2.

[0140] The strobe control signal MUX3 is invalid. The switching transistors connected to the strobe control line MUX3 are turned off.

[0141] The strobe control signal MUX4 is invalid. The switching transistors connected to the strobe control line MUX4 are turned off.

[0142] Timing Row2 stage: MUX1 = 1, MUX2 = 1, MUX3 = 0, MUX4 = 0

[0143] In this timing, the strobe control signal MUX1 is invalid, and the switching transistor connected to the strobe control line MUX1 is turned off.

[0144] The strobe control signal MUX2 is invalid, and the switching transistor connected to the strobe control line MUX2 is turned off.

[0145] The strobe control signal MUX3 is valid, and the switching transistors T3, m3, M3, and t3 connected to the strobe control line MUX3 are turned on. The data voltage 3 in the data input line 3 is provided to the data line T3 through the turned-on switching transistor T3, the data voltage 2 in the data input line 2 is provided to the data line m3 through the turned-on switching transistor m3, the data voltage 1 in the data input line 1 is provided to the data line M3 through the turned-on switching transistor M3, and the data voltage 4 in the data input line 4 is provided to the data line t3 through the turned-on switching transistor t3.

[0146] The strobe control signal MUX4 is valid, and the switching transistors m4, T4, M4, and t4 connected to the strobe control line MUX4 are turned on. The data voltage 2 in the data input line 2 is provided to the data line m4 through the turned-on switching transistor m4, the data voltage 3 in the data input line 3 is provided to the data line T4 through the turned-on switching transistor T4, the data voltage 1 in the data input line 1 is provided to the data line M4 through the turned-on switching transistor M4, and the data voltage 4 in the data input line 4 is provided to the data line t4 through the turned-on switching transistor t4.

[0147] Timing Row3 stage: MUX1 = 0, MUX2 = 0, MUX3 = 1, MUX4 = 1

[0148] In this timing stage, the strobe control signal MUX1 is valid, and the switching transistors M1, m1, T1, and t1 connected to the strobe control line MUX1 are all turned on. The data input line 1 is connected to the data line M1 through the turned-on switching transistor M1, and the data voltage 1 in the data input line 1 is provided to the data line M1. The data input line 2 is connected to the data line m1 through the turned-on switching transistor m1, and the data voltage 2 in the data input line 2 is provided to the data line m1. The data input line 3 is connected to the data line T1 through the turned-on switching transistor T1, and the data voltage 3 in the data input line 3 is provided to the data line T1. The data input line 4 is connected to the data line t1 through the turned-on switching transistor t1, and the data voltage 4 in the data input line 4 is provided to the data line t1.

[0149] The strobe control signal MUX2 is valid, and the switch transistors m2, M2, T2, and t2 connected to the corresponding strobe control lines MUX2 are turned on. The data voltage 2 in data input line 2 is supplied to data line m2 through the turned-on switch transistor m2, the data voltage 1 in data input line 1 is supplied to data line M2 through the turned-on switch transistor M2, the data voltage 3 in data input line 3 is supplied to data line T2 through the turned-on switch transistor T2, and the data voltage 4 in data input line 4 is supplied to data line t2 through the turned-on switch transistor t2.

[0150] The strobe control signal MUX3 is invalid, and the switch transistors connected to the corresponding strobe control line MUX3 are turned off.

[0151] The strobe control signal MUX4 is invalid, and the switch transistors connected to the corresponding strobe control line MUX4 are turned off.

[0152] Timing Row4 stage: MUX1 = 1, MUX2 = 1, MUX3 = 0, MUX4 = 0

[0153] In this timing, the strobe control signal MUX1 is invalid, and the switch transistors connected to the corresponding strobe control line MUX1 are turned off.

[0154] The strobe control signal MUX2 is invalid, and the switch transistors connected to the corresponding strobe control line MUX2 are turned off.

[0155] The strobe control signal MUX3 is valid, and the switch transistors T3, m3, M3, and t3 connected to the corresponding strobe control line MUX3 are turned on. The data voltage 3 in data input line 3 is supplied to data line T3 through the turned-on switch transistor T3, the data voltage 2 in data input line 2 is supplied to data line m3 through the turned-on switch transistor m3, the data voltage 1 in data input line 1 is supplied to data line M3 through the turned-on switch transistor M3, and the data voltage 4 in data input line 4 is supplied to data line t3 through the turned-on switch transistor t3.

[0156] The strobe control signal MUX4 is valid, and the switch transistors m4, T4, M4, and t4 connected to the corresponding strobe control line MUX4 are turned on. The data voltage 2 in data input line 2 is supplied to data line m4 through the turned-on switch transistor m4, the data voltage 3 in data input line 3 is supplied to data line T4 through the turned-on switch transistor T4, the data voltage 1 in data input line 1 is supplied to data line M4 through the turned-on switch transistor M4, and the data voltage 4 in data input line 4 is supplied to data line t4 through the turned-on switch transistor t4.

[0157] Timing Row5 stage: MUX1 = 0, MUX2 = 0, MUX3 = 1, MUX4 = 1

[0158] In this timing phase, the strobe control signal MUX1 is valid, and the switch transistors M1, m1, T1, and t1 connected to the corresponding strobe control lines MUX1 are all turned on. The data input line 1 is connected to the data line M1 through the turned-on switch transistor M1, and the data voltage 1 in the data input line 1 is provided to the data line M1. The data input line 2 is connected to the data line m1 through the turned-on switch transistor m1, and the data voltage 2 in the data input line 2 is provided to the data line m1. The data input line 3 is connected to the data line T1 through the turned-on switch transistor T1, and the data voltage 3 in the data input line 3 is provided to the data line T1. The data input line 4 is connected to the data line t1 through the turned-on switch transistor t1, and the data voltage 4 in the data input line 4 is provided to the data line t1.

[0159] The strobe control signal MUX2 is valid, and the switch transistors m2, M2, T2, and t2 connected to the corresponding strobe control lines MUX2 are turned on. The data voltage 2 in the data input line 2 is provided to the data line m2 through the turned-on switch transistor m2. The data voltage 1 in the data input line 1 is provided to the data line M2 through the turned-on switch transistor M2. The data voltage 3 in the data input line 3 is provided to the data line T2 through the turned-on switch transistor T2. The data voltage 4 in the data input line 4 is provided to the data line t2 through the turned-on switch transistor t2.

[0160] The strobe control signal MUX3 is invalid, and the switch transistors connected to the corresponding strobe control line MUX3 are turned off.

[0161] The strobe control signal MUX4 is invalid, and the switch transistors connected to the corresponding strobe control line MUX4 are turned off.

[0162] Timing Row6 phase: MUX1 = 1, MUX2 = 1, MUX3 = 0, MUX4 = 0

[0163] In this timing, the strobe control signal MUX1 is invalid, and the switch transistors connected to the corresponding strobe control line MUX1 are turned off.

[0164] The strobe control signal MUX2 is invalid, and the switch transistors connected to the corresponding strobe control line MUX2 are turned off.

[0165] The strobe control signal MUX3 is valid, and the switch transistors T3, m3, M3, and t3 connected to the corresponding strobe control line MUX3 are turned on. The data voltage 3 in the data input line 3 is provided to the data line T3 through the turned-on switch transistor T3. The data voltage 2 in the data input line 2 is provided to the data line m3 through the turned-on switch transistor m3. The data voltage 1 in the data input line 1 is provided to the data line M3 through the turned-on switch transistor M3. The data voltage 4 in the data input line 4 is provided to the data line t3 through the turned-on switch transistor t3.

[0166] The strobe control signal MUX4 is valid, and the switch transistors m4, T4, M4, and t4 connected to the corresponding strobe control line MUX4 are turned on. The data voltage 2 in data input line 2 is supplied to data line m4 through the turned-on switch transistor m4, the data voltage 3 in data input line 3 is supplied to data line T4 through the turned-on switch transistor T4, the data voltage 1 in data input line 1 is supplied to data line M4 through the turned-on switch transistor M4, and the data voltage 4 in data input line 4 is supplied to data line t4 through the turned-on switch transistor t4.

[0167] Timing Row7 stage: MUX1 = 0, MUX2 = 0, MUX3 = 1, MUX4 = 1

[0168] In this timing stage, the strobe control signal MUX1 is valid, and the switch transistors M1, m1, T1, and t1 connected to the corresponding strobe control line MUX1 are all turned on. Data input line 1 is connected to data line M1 through the turned-on switch transistor M1, and the data voltage 1 in data input line 1 is supplied to data line M1. Data input line 2 is connected to data line m1 through the turned-on switch transistor m1, and the data voltage 2 in data input line 2 is supplied to data line m1. Data input line 3 is connected to data line T1 through the turned-on switch transistor T1, and the data voltage 3 in data input line 3 is supplied to data line T1. Data input line 4 is connected to data line t1 through the turned-on switch transistor t1, and the data voltage 4 in data input line 4 is supplied to data line t1.

[0169] The strobe control signal MUX2 is valid, and the switch transistors m2, M2, T2, and t2 connected to the corresponding strobe control line MUX2 are turned on. The data voltage 2 in data input line 2 is supplied to data line m2 through the turned-on switch transistor m2, the data voltage 1 in data input line 1 is supplied to data line M2 through the turned-on switch transistor M2, the data voltage 3 in data input line 3 is supplied to data line T2 through the turned-on switch transistor T2, and the data voltage 4 in data input line 4 is supplied to data line t2 through the turned-on switch transistor t2.

[0170] The strobe control signal MUX3 is invalid, and the switch transistors connected to the corresponding strobe control line MUX3 are turned off.

[0171] The strobe control signal MUX4 is invalid, and the switch transistors connected to the corresponding strobe control line MUX4 are turned off.

[0172] Timing Row8 stage: MUX1 = 1, MUX2 = 1, MUX3 = 0, MUX4 = 0

[0173] In this timing, the strobe control signal MUX1 is invalid, and the switch transistors connected to the corresponding strobe control line MUX1 are turned off.

[0174] The strobe control signal MUX2 is invalid, and the switching transistors corresponding to the strobe control line MUX2 are turned off.

[0175] The strobe control signal MUX3 is valid, and the switching transistors T3, m3, M3, and t3 corresponding to the strobe control line MUX3 are turned on. The data voltage 3 in data input line 3 is supplied to data line T3 through the turned-on switching transistor T3, the data voltage 2 in data input line 2 is supplied to data line m3 through the turned-on switching transistor m3, the data voltage 1 in data input line 1 is supplied to data line M3 through the turned-on switching transistor M3, and the data voltage 4 in data input line 4 is supplied to data line t3 through the turned-on switching transistor t3.

[0176] The strobe control signal MUX4 is valid, and the switching transistors m4, T4, M4, and t4 corresponding to the strobe control line MUX4 are turned on. The data voltage 2 in data input line 2 is supplied to data line m4 through the turned-on switching transistor m4, the data voltage 3 in data input line 3 is supplied to data line T4 through the turned-on switching transistor T4, the data voltage 1 in data input line 1 is supplied to data line M4 through the turned-on switching transistor M4, and the data voltage 4 in data input line 4 is supplied to data line t4 through the turned-on switching transistor t4.

[0177] The following combines Figure 8 and the timing Figure 12 to describe in detail the working process of the display panel in the embodiments of the present application.

[0178] Among them, 0 represents a low level and 1 represents a high level. Combining Figure 8 it can be known that when the switching transistor is a P-type transistor, the above low level 0 is the effective level.

[0179] Timing T1 stage: MUX1 = 0, MUX2 = 0, MUX3 = 1, MUX4 = 1, Gout1 = 1 to 0, Gout2 = 1, Gout3 = 1

[0180] In this timing stage, the strobe control signal MUX1 is valid, and the switching transistor M1 corresponding to the strobe control line MUX1 is turned on. The data input line 1 is connected to the data line M1 through the turned-on switching transistor M1, and the data voltage 1 in the data input line 1 is supplied to the data line M1. When the scan signal Gout1 of the gate of the first row of pixel circuits is valid, Figure 8 the sub-pixel R in the first row corresponding to the data line M1 is filled with the above data voltage 1. The data input line 2 is connected to the data line m1 through the turned-on switching transistor m1, and the data voltage 2 in the data input line 2 is supplied to the data line m1. When the scan signal Gout1 of the gate of the first row of pixel circuits is valid, Figure 8The sub-pixels in the first row corresponding to the data line m1, i.e., the sub-pixels G, are filled with the above-mentioned data voltage 2. The data input line 3 is connected to the data line T1 through the turned-on switching transistor T1, and the data voltage 3 in the data input line 3 is supplied to the data line T1. When the scan signal Gout1 of the gate of the first row of pixel circuits is valid, Figure 8 The sub-pixels in the first row corresponding to the data line T1, i.e., the sub-pixels B, are filled with the above-mentioned data voltage 3. The data input line 4 is connected to the data line t1 through the turned-on switching transistor t1, and the data voltage 4 in the data input line 4 is supplied to the data line t1. When the scan signal Gout1 of the gate of the first row of pixel circuits is valid, Figure 8 The sub-pixels in the first row corresponding to the data line t1, i.e., the sub-pixels G, are filled with the above-mentioned data voltage 4.

[0181] The gating control signal MUX2 is valid, and the switching transistors m2, M2, T2, and t2 corresponding to the gating control line MUX2 are turned on. The data voltage 2 in the data input line 2 is supplied to the data line m2 through the turned-on switching transistor m2. When the scan signal Gout1 of the gate of the first row of pixel circuits is valid, Figure 8 The sub-pixels in the first row corresponding to the data line m2, i.e., the sub-pixels G, are filled with the above-mentioned data voltage 2. The data voltage 1 in the data input line 1 is supplied to the data line M2 through the turned-on switching transistor M2. When the scan signal Gout1 of the gate of the first row of pixel circuits is valid, Figure 8 The sub-pixels in the first row corresponding to the data line M2, i.e., the sub-pixels R, are filled with the above-mentioned data voltage 1. The data voltage 3 in the data input line 3 is supplied to the data line T2 through the turned-on switching transistor T2. When the scan signal Gout1 of the gate of the first row of pixel circuits is valid, Figure 8 The sub-pixels in the first row corresponding to the data line T2, i.e., the sub-pixels B, are filled with the above-mentioned data voltage 3. The data voltage 4 in the data input line 4 is supplied to the data line t2 through the turned-on switching transistor t2. When the scan signal Gout1 of the gate of the first row of pixel circuits is valid, Figure 8 The sub-pixels in the first row corresponding to the data line t2, i.e., the sub-pixels G, are filled with the above-mentioned data voltage 4.

[0182] The gating control signal MUX3 is invalid, and the switching transistors corresponding to the gating control line MUX3 are turned off.

[0183] The gating control signal MUX4 is invalid, and the switching transistors corresponding to the gating control line MUX4 are turned off.

[0184] Timing T2 stage: MUX1 = 0, MUX2 = 1, MUX3 = 0, MUX4 = 0, Gout1 = 0, Gout2 = 1 to 0, Gout3 = 1

[0185] In this timing sequence, the strobe control signal MUX1 is invalid, and the switching transistors corresponding to the strobe control line MUX1 are turned off.

[0186] The strobe control signal MUX2 is invalid, and the switching transistors corresponding to the strobe control line MUX2 are turned off.

[0187] It should be noted here that when the scan signal Gout1 of the gate of the first row of pixel circuits is valid, the data voltage continues to be charged into the relevant sub-pixels in the above-mentioned timing T1 stage, thus ensuring the charging duration of the data voltage and making the charging of the data voltage more sufficient.

[0188] The strobe control signal MUX3 is valid, and the switching transistors T3, m3, M3, and t3 corresponding to the strobe control line MUX3 are turned on. The data voltage 3 in the data input line 3 is supplied to the data line T3 through the turned-on switching transistor T3. When the scan signal Gout2 of the gate of the second row of pixel circuits is valid, Figure 8 the data voltage 3 is charged into the sub-pixel B of the second row corresponding to the data line T3, that is, the sub-pixel B. The data voltage 2 in the data input line 2 is supplied to the data line m3 through the turned-on switching transistor m3. When the scan signal Gout2 of the gate of the second row of pixel circuits is valid, Figure 8 the data voltage 2 is charged into the sub-pixel G of the second row corresponding to the data line m3, that is, the sub-pixel G. The data voltage 1 in the data input line 1 is supplied to the data line M3 through the turned-on switching transistor M3. When the scan signal Gout2 of the gate of the second row of pixel circuits is valid, Figure 8 the data voltage 1 is charged into the sub-pixel R of the second row corresponding to the data line M3, that is, the sub-pixel R. The data voltage 4 in the data input line 4 is supplied to the data line t3 through the turned-on switching transistor t3. When the scan signal Gout2 of the gate of the second row of pixel circuits is valid, Figure 8 the data voltage 4 is charged into the sub-pixel G of the second row corresponding to the data line t3, that is, the sub-pixel G.

[0189] The strobe control signal MUX4 is valid, and the switching transistors m4, T4, M4, and t4 corresponding to the strobe control line MUX4 are turned on. The data voltage 2 in the data input line 2 is supplied to the data line m4 through the turned-on switching transistor M13. When the scan signal Gout2 of the gate of the second row of pixel circuits is valid, Figure 8 the data voltage 2 is charged into the sub-pixel G of the second row corresponding to the data line m4, that is, the sub-pixel G. The data voltage 3 in the data input line 3 is supplied to the data line T4 through the turned-on switching transistor T4. When the scan signal Gout2 of the gate of the second row of pixel circuits is valid, Figure 8The sub-pixels in the second row corresponding to the data line T4, that is, the sub-pixel B, are filled with the above data voltage 3. The data voltage 1 in the data input line 1 is supplied to the data line M4 through the turned-on switching transistor M4. When the scan signal Gout2 of the gate of the second row of pixel circuits is valid, Figure 8 The sub-pixels in the second row corresponding to the data line M4, that is, the sub-pixel B, are filled with the above data voltage 1. The data voltage 4 in the data input line 4 is supplied to the data line t4 through the turned-on switching transistor t4. When the scan signal Gout2 of the gate of the second row of pixel circuits is valid, Figure 8 The sub-pixels in the second row corresponding to the data line t4, that is, the sub-pixel G, are filled with the above data voltage 4.

[0190] Timing T3 stage: MUX1 = 0, MUX2 = 0, MUX3 = 1, MUX4 = 1, Gout1 = 1, Gout2 = 0, Gout3 = 1 to 0

[0191] First of all, it should be noted that when the scan signal Gout1 of the gate of the first row of pixel circuits is invalid, the relevant sub-pixels in the above timing T2 stage will not continue to be filled with the data voltage. When the scan signal Gout2 of the gate of the second row of pixel circuits is valid, the relevant sub-pixels in the above timing T2 stage will continue to be filled with the data voltage under the action of the scan signal Gout2, thus ensuring the charging duration of the data voltage and making the charging of the data voltage more sufficient.

[0192] In this timing stage, the selection control signal MUX1 is valid, and the switching transistor M1 corresponding to the selection control line MUX1 is turned on. The data input line 1 is connected to the data line M1 through the turned-on switching transistor M1, and the data voltage 1 in the data input line 1 is supplied to the data line M1. When the scan signal Gout3 of the gate of the third row of pixel circuits is valid, Figure 8 The sub-pixels in the third row corresponding to the data line M1, that is, the sub-pixel R, are filled with the above data voltage 1. The data input line 2 is connected to the data line m1 through the turned-on switching transistor m1, and the data voltage 2 in the data input line 2 is supplied to the data line m1. When the scan signal Gout3 of the gate of the third row of pixel circuits is valid, Figure 8 The sub-pixels in the third row corresponding to the data line m1, that is, the sub-pixel G, are filled with the above data voltage 2. The data input line 3 is connected to the data line T1 through the turned-on switching transistor T1, and the data voltage 3 in the data input line 3 is supplied to the data line T1. When the scan signal Gout3 of the gate of the third row of pixel circuits is valid, Figure 8The sub-pixel in the third row corresponding to the data line T1, i.e., sub-pixel B, is filled with the above data voltage 3. The data input line 4 is connected to the data line t1 through the turned-on switching transistor t1, and the data voltage 4 in the data input line 4 is supplied to the data line t1. When the scan signal Gout3 of the gate of the third row pixel circuit is valid, Figure 8 The sub-pixel in the third row corresponding to the data line t1, i.e., sub-pixel G, is filled with the above data voltage 4.

[0193] The gating control signal MUX2 is valid, and the switching transistors m2, M2, T2, and t2 corresponding to the gating control line MUX2 are turned on. The data voltage 2 in the data input line 2 is supplied to the data line m2 through the turned-on switching transistor m2. When the scan signal Gout3 of the gate of the third row pixel circuit is valid, Figure 8 The sub-pixel in the third row corresponding to the data line m2, i.e., sub-pixel G, is filled with the above data voltage 2. The data voltage 1 in the data input line 1 is supplied to the data line M2 through the turned-on switching transistor M2. When the scan signal Gout3 of the gate of the third row pixel circuit is valid, Figure 8 The sub-pixel in the third row corresponding to the data line M2, i.e., sub-pixel R, is filled with the above data voltage 1. The data voltage 3 in the data input line 3 is supplied to the data line T2 through the turned-on switching transistor T2. When the scan signal Gout3 of the gate of the third row pixel circuit is valid, Figure 8 The sub-pixel in the third row corresponding to the data line T2, i.e., sub-pixel B, is filled with the above data voltage 3. The data voltage 4 in the data input line 4 is supplied to the data line t2 through the turned-on switching transistor t2. When the scan signal Gout3 of the gate of the third row pixel circuit is valid, Figure 8 The sub-pixel in the third row corresponding to the data line t2, i.e., sub-pixel G, is filled with the above data voltage 4.

[0194] The gating control signal MUX3 is invalid, and the switching transistors corresponding to the gating control line MUX3 are turned off.

[0195] The gating control signal MUX4 is invalid, and the switching transistors corresponding to the gating control line MUX4 are turned off.

[0196] Timing T4 stage: MUX1 = 1, MUX2 = 1, MUX3 = 0, MUX4 = 0, Gout1 = 1, Gout2 = 1, Gout3 = 0

[0197] First of all, it should be noted that when the scan signal Gout3 of the gate of the third row pixel circuit is valid, the relevant sub-pixels in the above timing T3 stage will continue to be filled with the data voltage under the action of the scan signal Gout3, thus ensuring the duration of the data voltage filling and making the filling of the data voltage more sufficient.

[0198] In this timing sequence, the strobe control signal MUX1 is invalid, and the switching transistors corresponding to the strobe control line MUX1 are turned off.

[0199] The strobe control signal MUX2 is invalid, and the switching transistors corresponding to the strobe control line MUX2 are turned off.

[0200] The strobe control signal MUX3 is valid, and the switching transistors T3, m3, M3, and t3 corresponding to the strobe control line MUX3 are turned on. The data voltage 3 in data input line 3 is supplied to data line T3 through the turned-on switching transistor T3. The data voltage 2 in data input line 2 is supplied to data line m3 through the turned-on switching transistor m3. The data voltage 1 in data input line 1 is supplied to data line M3 through the turned-on switching transistor M3. The data voltage 4 in data input line 4 is supplied to data line t3 through the turned-on switching transistor t3. The relevant data lines mentioned above will continue to be charged with data voltage under the action of other scan signals.

[0201] The strobe control signal MUX4 is valid, and the switching transistors m4, T4, M4, and t4 corresponding to the strobe control line MUX4 are turned on. The data voltage 2 in data input line 2 is supplied to data line m4 through the turned-on switching transistor m4. The data voltage 3 in data input line 3 is supplied to data line T4 through the turned-on switching transistor T4. The data voltage 1 in data input line 1 is supplied to data line M4 through the turned-on switching transistor M4. The data voltage 4 in data input line 4 is supplied to data line t4 through the turned-on switching transistor t4. The relevant data lines mentioned above will continue to be charged with data voltage under the action of other scan signals.

[0202] Timing T5 stage: MUX1 = 0, MUX2 = 0, MUX3 = 1, MUX4 = 1, Gout1 = 1, Gout2 = 1, Gout3 = 1

[0203] In this timing stage, the strobe control signal MUX1 is valid, and the switching transistor M1 corresponding to the strobe control line MUX1 is turned on. Data input line 1 is connected to data line M1 through the turned-on switching transistor M1, and the data voltage 1 in data input line 1 is supplied to data line M1. Data input line 2 is connected to data line m1 through the turned-on switching transistor m1, and the data voltage 2 in data input line 2 is supplied to data line m1. Data input line 3 is connected to data line T1 through the turned-on switching transistor T1, and the data voltage 3 in data input line 3 is supplied to data line T1. Data input line 4 is connected to data line t1 through the turned-on switching transistor t1, and the data voltage 4 in data input line 4 is supplied to data line t1. The relevant data lines mentioned above will continue to be charged with data voltage under the action of other scan signals.

[0204] The gating control signal MUX2 is valid, and the switching transistors m2, M2, T2, and t2 connected to the corresponding gating control lines are turned on. The data voltage 2 in the data input line 2 is supplied to the data line m2 through the turned-on switching transistor m2, the data voltage 1 in the data input line 1 is supplied to the data line M2 through the turned-on switching transistor M2, the data voltage 3 in the data input line 3 is supplied to the data line T2 through the turned-on switching transistor T2, and the data voltage 4 in the data input line 4 is supplied to the data line t2 through the turned-on switching transistor t2. The relevant data lines mentioned above will continue to be charged with data voltage under the action of other scanning signals.

[0205] The gating control signal MUX3 is invalid, and the switching transistors connected to the corresponding gating control line MUX3 are turned off.

[0206] The gating control signal MUX4 is invalid, and the switching transistors connected to the corresponding gating control line MUX4 are turned off.

[0207] In the timing T6 stage: MUX1 = 1, MUX2 = 1, MUX3 = 0, MUX4 = 0, Gout1 = 1, Gout2 = 1, Gout3 = 1

[0208] This timing is similar to the timing T4 stage and will not be elaborated here.

[0209] In the timing T7 stage: MUX1 = 0, MUX2 = 0, MUX3 = 1, MUX4 = 1, Gout1 = 1, Gout2 = 1, Gout3 = 1

[0210] This timing is similar to the timing T5 stage and will not be elaborated here.

[0211] In the timing T8 stage: MUX1 = 1, MUX2 = 1, MUX3 = 0, MUX4 = 0, Gout1 = 1, Gout2 = 1, Gout3 = 1

[0212] This timing is similar to the timing T6 stage and will not be elaborated here.

[0213] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, including the display panel of any one of the above.

[0214] Refer to Figure 13 As shown, the above display device further includes a source driver circuit.

[0215] The source driver circuit is connected to the gating control line and is configured to provide a gating control signal to the gating control line.

[0216] In an embodiment of the present application, on the one hand, the source driver circuit is used to generate data voltage. It should be noted that in a frame of display image, the number of data voltages generated by the source driver circuit is adapted to the number of sub-pixels in the display panel.

[0217] Refer to Figure 13 As shown, after the source driver circuit generates multiple data voltages, each data voltage is first provided to the corresponding connected data input line. Then, when the strobe control signal controls the strobe control circuit to conduct, the data voltage in the data input line is provided to multiple data lines connected to the data input line through the above-conducted strobe control circuit. In cooperation with the scan signal provided by the gate line, the data lines provide the data voltages to each sub-pixel respectively to realize the display of the display screen.

[0218] It should be added that since the pixel structure in the embodiment of the present application can be Figure 8 , Figure 9 or Figure 10 any one of them, the colors of the sub-pixels connected to the same data line are the same. However, under different pixel structures, the arrangement positions of the above-mentioned sub-pixels in the display panel are not specifically limited.

[0219] Compared with the related art, since the colors of the sub-pixels connected to the same data line are the same, in this way, during the process of the source driver circuit generating consecutive multiple data voltages, since the voltage values between the multiple data voltages are relatively close, in this way, the power consumption of the source driver circuit is effectively reduced, thereby increasing the service life of the display panel.

[0220] In the embodiment of the present application, on the other hand, the source driver circuit is used to generate the strobe control signal. It should be noted that the number of the above-mentioned strobe control signals is the same as the number of strobe control lines. Refer to Figure 13 As shown, the source driver circuit is connected to the strobe control line. During the implementation process, the source driver circuit provides the strobe control signal to the strobe control line, and this strobe control signal can be used to control the connection or disconnection between the data input line and the data line.

[0221] Refer to Figure 14 As shown, one data input line in the above display device is correspondingly connected to a connection terminal of the source driver circuit.

[0222] In the embodiment of the present application, the source driver circuit includes multiple connection terminals, and each connection terminal is connected to a data input line. Exemplarily, the connection terminal and the data input line are electrically connected by welding. After the source driver circuit generates the data voltage, the above data voltage is output from the source driver circuit through the connection terminal, and then provided to the data line in the display panel through the data input line.

[0223] Compared with the related art solution in which the number of connection terminals corresponds one-to-one to the data lines in the display panel, in the embodiment of the present application, the number of connection terminals corresponds one-to-one to the data input lines, and the number of data input lines is connected to multiple data lines. Exemplarily, refer toFigure 8 and Figure 9 As shown, a data input line is connected to four data lines. Exemplarily, refer to Figure 10 As shown, a data input line is connected to three data lines. Therefore, the number of connection terminals used in the embodiments of the present application is reduced, effectively saving the port consumption of the source driver circuit.

[0224] In the embodiments of the present invention, the display device may be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art and will not be elaborated here, nor should they be considered as a limitation to the present invention.

[0225] Based on the same inventive concept, a driving control method for a display panel is provided in the embodiments of the present disclosure. Refer to Figure 15 As shown, it includes:

[0226] Step 201: Each data input line is used to receive data voltages from different connection terminals of the source driver circuit respectively.

[0227] During the implementation process, after the source driver circuit generates multiple data voltages, the above-mentioned multiple data voltages are respectively output through different connection terminals of the source driver circuit. Since the output end of the connection terminal is electrically connected to the data input line, the above-mentioned multiple data voltages are further provided to each data input line through the connection terminal. In this way, the data voltages are provided from the source driver circuit to the data input lines.

[0228] Step 202: Any one of the gating control circuits is used to provide the multiple data voltages received from the data input line to the corresponding connected data lines respectively.

[0229] During the implementation process, for each gating control circuit, the input end of the gating control circuit is connected to the data input line, and the output end of the gating control circuit is connected to the data line. However, whether the input end and the output end of the above-mentioned gating control circuit are conducting depends on whether the gating control circuit is conducting. That is, when the gating control circuit is conducting under the action of the gating control signal, the input end and the output end are conducting, the data input line and the data line are connected, and the data voltage is provided to the corresponding connected data line through the data input line; when the gating control circuit is cut off under the action of the gating control signal, the input end and the output end are open-circuited, the data input line and the data line are not connected, and the data voltage cannot be provided to the corresponding connected data line.

[0230] In addition, the above driving control method further includes:

[0231] The end time of the effective duration of the scan signal of the scan signal terminal corresponding to the sub-pixels in the n-th row is not earlier than the effective start time of the strobe control signals corresponding to all the sub-pixels in the (n + 1)-th row.

[0232] In the embodiments of the present application, in order to ensure the sufficient writing of the data voltages of the sub-pixels in each row, during the implementation process, when the scan signal of the scan signal terminal corresponding to the sub-pixels in the n-th row (exemplarily, a certain sub-pixel in an odd row) is in the effective duration, the data voltage is written into the data line corresponding to the sub-pixels in the n-th row. When the scan signal of the scan signal terminal corresponding to the sub-pixels in the (n + 1)-th row (exemplarily, a certain sub-pixel in an even row connected to the same data line) is in the effective duration, the data voltage is written into the data line corresponding to the sub-pixels in the (n + 1)-th row. After the effective start times of the strobe control signals corresponding to all the sub-pixels in the n-th row and the (n + 1)-th row, the data voltages are respectively provided to all the sub-pixels in the n-th row and the (n + 1)-th row.

[0233] In summary, in the embodiments of the present disclosure, a display panel, a display device, and a driving control method are provided. The display panel includes: The present disclosure relates to the field of display technologies, and discloses a display panel, a display device, and a driving control method. The display panel includes: a plurality of sub-pixels, a plurality of data lines, a plurality of data input lines, and a plurality of strobe control circuits. Any one of the plurality of data lines is connected to a plurality of sub-pixels with the same color. One data input line is connected to a plurality of data lines through a strobe control circuit. The sub-pixels corresponding to the data lines connected by any strobe control circuit have the same color. The strobe control circuit is configured to connect the data input line to the plurality of data lines connected thereto respectively, thereby reducing the jump voltage between the plurality of data voltages provided by the source driver circuit for the same data line. Especially during the display process of a pure color screen, the power consumption of the source driver circuit is effectively reduced, and the service life of the display panel is improved.

[0234] Those skilled in the art should understand that the embodiments of the present disclosure can be provided as a method, a system, or a computer program product system. Therefore, the present disclosure can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present disclosure can take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0235] This disclosure is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to the disclosure. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded processors, or other programmable data processing devices to produce a machine, such that the instructions executed by the processors of the computer or other programmable data processing devices produce means for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0236] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufacture including instruction means that implement the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0237] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0238] Obviously, those skilled in the art can make various changes and modifications to this disclosure without departing from the spirit and scope of this disclosure. Thus, if these modifications and variations of this disclosure fall within the scope of the claims of this disclosure and their equivalent technologies, this disclosure is also intended to include these changes and modifications.

Claims

1. A display panel, wherein, Comprising: Multiple sub-pixels; Multiple data lines, any one of the multiple data lines being connected to multiple sub-pixels of the same color; Multiple data input lines; Multiple gating control circuits, one data input line being connected to multiple data lines through one gating control circuit, the sub-pixels corresponding to the data lines connected by any one gating control circuit having the same color, and the gating control circuit being configured to connect the data input line to the multiple data lines connected thereto respectively.

2. The display panel according to claim 1, wherein, Also included are multiple gating control lines connected to the gating control circuits, the multiple gating control lines being correspondingly arranged with the multiple data lines connected to the gating control circuits; The gating control circuit is further configured to: in response to a gating control signal on the gating control line, connect the corresponding data line to the data input line.

3. The display panel according to claim 2, wherein, The gating control circuit includes: multiple switching transistors, the multiple switching transistors being correspondingly arranged with the multiple gating control lines; The control terminal of any one switching transistor is connected to the corresponding gating control line, the first terminal of any one switching transistor is connected to the corresponding data line, and the second terminals of the multiple switching transistors are all connected to the data input line.

4. The display panel according to claim 1, wherein, The sub-pixels in the odd rows of the column of sub-pixels and the sub-pixels in the even rows of the column of sub-pixels are respectively connected to different data lines.

5. The display panel according to claim 1, wherein, The multiple sub-pixels include a first sub-pixel column and a second sub-pixel column alternately arranged in a first direction, the first sub-pixel column including first color sub-pixels and second color sub-pixels alternately arranged in a second direction, and the second sub-pixel column including third color sub-pixels arranged in the second direction; Two data lines are correspondingly arranged for the first sub-pixel column, the two data lines including a first data line and a second data line, the first data line being connected to the first color sub-pixels in the first sub-pixel column, and the second data line being connected to the second color sub-pixels in the first sub-pixel column; Two data lines are correspondingly arranged for the second sub-pixel column, the two data lines including a third data line and a fourth data line, the third data line being connected to the third color sub-pixels in the odd rows of the second sub-pixel column, and the fourth data line being connected to the third color sub-pixels in the even rows of the second sub-pixel column.

6. The display panel according to claim 5, wherein, The gating control line connected to the gating control circuit corresponding to the first data line and the gating control line connected to the gating control circuit corresponding to the third data line are the same gating control line; The gating control line connected to the gating control circuit corresponding to the second data line and the gating control line connected to the gating control circuit corresponding to the fourth data line are the same gating control line.

7. The display panel according to claim 1, wherein, The multiple sub-pixels include a third sub-pixel column, a fourth sub-pixel column, and a fifth sub-pixel column that are alternately arranged in a first direction. The third sub-pixel column includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel that are alternately arranged in a second direction. The fourth sub-pixel column includes a second color sub-pixel, a third color sub-pixel, and a first color sub-pixel that are alternately arranged in a second direction. The fifth sub-pixel column includes a third color sub-pixel, a first color sub-pixel, and a second color sub-pixel that are alternately arranged in a second direction; Six data lines are correspondingly arranged for each of the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column. The six data lines include: a fifth data line, a sixth data line, a seventh data line, an eighth data line, a ninth data line, and a tenth data line; The fifth data line is connected to the first color sub-pixels in the odd rows of the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column; The sixth data line is connected to the second color sub-pixels in the odd rows of the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column; The seventh data line is connected to the third color sub-pixels in the odd rows of the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column; The eighth data line is connected to the first color sub-pixels in the even rows of the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column; The ninth data line is connected to the second color sub-pixels in the even rows of the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column; The tenth data line is connected to the third color sub-pixels in the even rows of the third sub-pixel column, the fourth sub-pixel column, and the fifth sub-pixel column.

8. The display panel according to claim 7, wherein, The gate control lines connected to the gate control circuits corresponding to the fifth data line, the gate control lines connected to the gate control circuits corresponding to the sixth data line, and the gate control lines connected to the gate control circuits corresponding to the seventh data line are the same gate control line; The gate control lines connected to the gate control circuits corresponding to the eighth data line, the gate control lines connected to the gate control circuits corresponding to the ninth data line, and the gate control lines connected to the gate control circuits corresponding to the tenth data line are the same gate control line.

9. A display device, wherein, Comprising: The display panel according to any one of claims 1 to 8.

10. The display device according to claim 9, wherein, Further comprising a source driver circuit; The source driver circuit is connected to the gate control line and is configured to provide the gate control signal to the gate control line.

11. The display device according to claim 10, wherein, One of the data input lines is correspondingly connected to a connection terminal of the source driver circuit.

12. A driving control method applied to the display panel according to any one of claims 1 to 8, wherein, Comprising: Each of the data input lines is used to respectively receive data voltages from different connection terminals of the source driver circuit; Any one of the gate control circuits is used to respectively provide the multiple data voltages received from the data input line to the correspondingly connected data lines.

13. The drive control method according to claim 12, wherein, Further comprising: The end moment of the effective duration of the scan signal of the scan signal terminal corresponding to the sub-pixels in the nth row is not earlier than the effective start moment of the gate control signals corresponding to all the sub-pixels in the (n + 1)th row.

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