EMMC parallel video transmission method and system

Abstract

The invention relates to the technical field of network transmission, in particular to an EMMC parallel video transmission method and system, and the method comprises the steps: obtaining a video file, and carrying out the preprocessing of the video file; splitting the preprocessed video file into frame-by-frame pictures and storing the frame-by-frame pictures in an EMMC (Embedded Multi Media Card); in response to a video playing request, scheduling and reading the correspondingly stored images from the EMMC through the DDR; verifying whether each frame of image read from the EMMC by the DDR is complete or not; and in response to the verification success request, synchronously transmitting the image to the VR screen for frame-by-frame rendering playing. The technical problem that high-definition and smooth video transmission is difficult to realize under the condition that traditional VR screen lighting equipment does not depend on an external host is effectively solved.

Description

Technical Field

[0001] This application relates to the field of network transmission technologies, and in particular, to a video transmission method and system for EMMC parallelism. Background Art

[0002] With the rapid development of virtual reality (VR) technology, VR display devices have been widely used in fields such as game entertainment, education and training, and industrial simulation. To enhance the immersive experience, VR dot matrix display devices have put forward higher requirements for the clarity and smoothness of the displayed images. Especially when playing high-resolution and high-frame-rate video content, there are relatively high technical requirements for image transmission and processing capabilities.

[0003] In terms of image transmission of existing VR dot matrix display devices, image data is usually directly processed and displayed through a driver board, which can meet the requirements of static display. However, in actual applications, high-definition video content often needs to be played to present a more realistic visual effect. At this time, if a traditional desktop computer is used as the video source for transmission, although the requirements for high-resolution and high-frame-rate playback can be met, it will significantly increase the device volume and cost, and bring problems such as complex control and poor flexibility.

[0004] Therefore, in the above background, when implementing high-resolution and high-frame-rate video playback in the existing driver board, there is generally a problem that the transmission rate is difficult to meet the requirements. Especially under the condition of not relying on a host device, limited by the support capabilities of the existing driver board in terms of video processing path and storage bandwidth, it is difficult to achieve stable playback of high-definition video streams. Therefore, how to achieve efficient and stable video transmission and playback in VR dot matrix display devices without relying on an external host has become a difficult problem faced currently. Summary of the Invention

[0005] This application provides a video transmission method and system for EMMC parallelism, effectively solving the technical problem that traditional VR dot matrix display devices are difficult to achieve high-definition and smooth video transmission without relying on an external host. This application provides the following technical solutions:

[0006] In the first aspect, this application provides a video transmission method for EMMC parallelism, and the method includes:

[0007] Obtain a video file and perform preprocessing on the video file;

[0008] Split the preprocessed video file into frame-by-frame pictures and store them in the EMMC;

[0009] In response to a video playback request, schedule and read the corresponding stored images from the EMMC through the DDR;

[0010] Verify whether each frame of the image read from the EMMC by the DDR is complete and error-free;

[0011] In response to a request for successful verification, the image is synchronously transmitted to the VR screen for frame-by-frame rendering and playback.

[0012] In a specific feasible implementation, the obtaining the video file and preprocessing the video file includes:

[0013] Check whether the obtained video file meets the general encoding format;

[0014] Parse the video file through multimedia decoding technology, and perform filtering, noise reduction, and color balance processing on the video;

[0015] Mark the key frames in the video stream and correct the timestamps.

[0016] In a specific feasible implementation, the splitting the preprocessed video file into frame-by-frame pictures and storing them in the EMMC includes:

[0017] The preprocessed video data is discretely processed on the time axis according to its frame rate parameter, and each frame of image data is extracted;

[0018] Each frame of image generates a static picture in an uncompressed or lightly compressed manner and is saved as an image file with a unified resolution and bit depth format;

[0019] Perform serialization processing on the image naming and establish a mapping index table.

[0020] In a specific feasible implementation, the splitting the preprocessed video file into frame-by-frame pictures and storing them in the EMMC further includes:

[0021] Use the following formula to calculate the total number of frames N involved in the splitting process of the target video f :

[0022]

[0023] where N f is the maximum number of frames that can be split from the video file under the given EMMC capacity condition, C is the total capacity of the EMMC, R is the horizontal resolution of the video image, D is the vertical resolution of the video image, B is the number of bytes occupied by each pixel, is the floor operator.

[0024] In a specific feasible implementation, the scheduling and reading the corresponding stored images from the EMMC through the DDR includes:

[0025] Determine the current playback timestamp and frame rate, and calculate the image frame number to be read currently based on these parameters;

[0026] DDR schedules the corresponding image data from the EMMC storage according to the frame number and loads it into the memory.

[0027] In a specific feasible implementation, verifying whether each frame of image read by the DDR from the EMMC is complete and error-free includes:

[0028] Introduce a new image differential integrity function:

[0029]

[0030] where, Δ intergrity (i) represents the integrity differential evaluation value of the i-th frame of image, represent the hash values of the i-th frame of image during storage and reading respectively, F k (·) represents the k-th frequency domain feature extraction function, are the weight coefficients of each frequency domain feature, δ(i) represents the spatial error function of the i-th frame of image, and σ is a regulation parameter.

[0031] In a specific feasible implementation, verifying whether each frame of image read by the DDR from the EMMC is complete and error-free further includes:

[0032] Calculate a total integrity index Φ intergrity through the Δ total values of all frames:

[0033]

[0034] If the calculated Φ total value is lower than the preset security threshold, a retry mechanism will be triggered to request re-reading of the lost or damaged image data.

[0035] In a second aspect, the present application provides a video transmission system with EMMC parallelism, adopting the following technical solutions:

[0036] A video transmission system with EMMC parallelism includes:

[0037] A video acquisition module, used to acquire a video file and preprocess the video file;

[0038] A video splitting module, used to split the preprocessed video file into frame-by-frame pictures and store them in the EMMC;

[0039] An image reading module, configured to schedule and read the corresponding stored images from the EMMC through the DDR in response to a video playback request;

[0040] An image verification module, configured to verify whether each frame of the image read from the EMMC by the DDR is complete and error-free;

[0041] A video playback module, configured to synchronously transmit the image to the VR screen for frame-by-frame rendering and playback in response to a successfully verified request.

[0042] In a third aspect, the present application provides an electronic device, the device includes a processor and a memory; a program is stored in the memory, and the program is loaded and executed by the processor to implement an EMMC parallel video transmission method as described in the first aspect.

[0043] In a fourth aspect, the present application provides a computer-readable storage medium, a program is stored in the storage medium, and the program is used to implement an EMMC parallel video transmission method as described in the first aspect when executed by a processor.

[0044] In summary, the beneficial effects of the present application at least include:

[0045] (1) Through the frame-level splitting and frame sequence number indexing establishment mechanism, the preprocessed video file is disassembled into frame-by-frame images in a unified format, and combined with the frame number estimation formula, the dynamic evaluation and optimal utilization of the EMMC capacity resources are realized. At the same time, multiple EMMC modules are used for parallel writing and reading, and strategies such as page alignment, continuous address allocation, and average load scheduling are supplemented, significantly improving the data writing rate and reading concurrency, thereby effectively supporting the real-time transmission and smooth playback of high-resolution videos, and enhancing the system's performance in large-scale video processing tasks.

[0046] (2) Aiming at the data misalignment or image damage problems that may be caused in parallel transmission, the present application proposes an image integrity difference evaluation function based on the fusion of frequency domain and spatial features. This function not only compares the hash value differences during storage and reading, but also fuses the weighted differences of the image frequency components and the spatial pixel deviations to evaluate the image integrity from multiple dimensions. Compared with traditional hash verification or pixel comparison methods, this integrity function can more accurately identify potential distortion problems in the structure, details, or edges of the image, thereby effectively improving the data security and image quality guarantee capabilities of the system.

[0047] By preprocessing the video file, format standardization and data segmentation are achieved; then the preprocessed video is split into static images frame by frame, named serially in a unified format, and after calculating the total number of frames according to a preset formula, it is evenly distributed and written into multiple EMMCs, thus breaking through the limitations of the bandwidth and capacity of a single memory; then, when responding to a video playback request, the image data stored in the EMMC is read in parallel through the DDR cache, and then the integrity of the read data is verified through an innovative multi-dimensional integrity verification method that combines frequency domain features and spatial errors to ensure that there is no loss or disorder in the video data during transmission, and finally high-resolution and high-frame-rate image data is provided for the VR display screen to achieve stable and efficient video playback. This solution effectively solves the technical problem that traditional VR screen devices are difficult to achieve high-definition and smooth video transmission due to limited storage bandwidth and processing power of the driving board without relying on an external host, while taking into account the issues of device cost, volume, and control flexibility.

[0048] The above description is only an overview of the technical solution of this application. In order to understand the technical means of this application more clearly and be able to implement it according to the content of the specification, the following takes the preferred embodiments of this application and describes them in detail in conjunction with the drawings as follows. Brief Description of the Drawings

[0049] Figure 1 It is a schematic flowchart of the EMMC parallel video transmission method in an embodiment of this application.

[0050] Figure 2 It is a block diagram of the structure of the EMMC parallel video transmission system in an embodiment of this application.

[0051] Figure 3 It is a block diagram of the electronic device for EMMC parallel video transmission in an embodiment of this application. Detailed Description of the Embodiments

[0052] The following further describes the specific embodiments of this application in detail in conjunction with the drawings and embodiments. The following embodiments are used to illustrate this application, but are not used to limit the scope of this application.

[0053] Optionally, this application takes the EMMC parallel video transmission method provided in each embodiment as an example for an electronic device. The electronic device is a terminal or a server. The terminal can be a mobile phone, a computer, a tablet computer, etc. The type of the electronic device is not limited in this embodiment.

[0054] Refer to Figure 1 , which is a schematic flowchart of the EMMC parallel video transmission method provided in an embodiment of this application. The method at least includes the following steps:

[0055] Step S101: Obtain a video file and preprocess the video file.

[0056] In step S101, it is first necessary to obtain a video file and preprocess the video file. Its main objective is to provide a set of original data with a unified format, stable structure, and easy-to-parse for subsequent video frame decomposition. Therefore, in implementation, the source, encoding format, and key parameters of the video file must be carefully confirmed and processed.

[0057] In implementation, first check whether the obtained video file meets common encoding formats such as H.264, H.265, etc., to ensure high compatibility and stability of the file. Next, parse the video file through existing multimedia decoding technologies, separate the video stream and audio stream, and use image processing algorithms to extract key information such as the frame rate, resolution, color depth, and compression ratio of the video. At the same time, perform filtering, noise reduction, and color balance processing on the video to eliminate noise and distortion phenomena that may be introduced during compression or transmission, so as to ensure that the data format and size of each frame of image are consistent. In addition, the preprocessing also includes re-encoding or re-encapsulating the video file to generate a standardized data format that is convenient for subsequent frame splitting. At the same time, according to the total duration of the video file and the expected playback requirements, divide the video data into multiple data segments and perform necessary data caching processing to prevent buffer overflow or reading delay problems caused by excessive data volume. At the same time, it is also required to mark the key frames in the video stream and correct the timestamps to ensure accurate execution in the subsequent frame-by-frame splitting according to the predetermined time sequence.

[0058] Generally speaking, by carefully preprocessing the video file in step S101, it can not only effectively unify the data format and quality of video frames, but also lay a solid data foundation for subsequent splitting the video file into frame-by-frame pictures and storing them in the EMMC, while improving the stability and efficiency of the overall system in the process of high-speed data reading and real-time display.

[0059] Step S102: Split the preprocessed video file into frame-by-frame pictures and store them in the EMMC.

[0060] In step S102, perform a frame-level disassembly operation on the preprocessed video file, and efficiently write the disassembled frame-by-frame image data into an EMMC (embedded multimedia storage) device to achieve subsequent high-speed video playback capabilities. The splitting of video frames not only needs to ensure the integrity of each frame of image, but also fully consider the write bandwidth, capacity limit of the EMMC, and the organizational structure of the picture data, so as to achieve efficient distribution and fast readability of the image data during storage.

[0061] Specifically, the preprocessed video data will be discretized on the time axis according to its frame rate parameter, and each frame of image data will be extracted. Each frame of image will generate a static picture in an uncompressed or lightly compressed manner and be saved as an image file with a unified resolution and bit depth format. During the splitting process, to ensure the real-time performance and addressability of the split picture data during subsequent EMMC parallel reading and writing, it is also necessary to serialize the image naming, for example, rename it to frame_0001, frame_0002, etc. according to the frame number, and establish a mapping index table, so as to achieve fast positioning and scheduling of frame images during playback.

[0062] To more systematically plan the number of split frame images and reasonably allocate EMMC resources, the following formula is introduced to calculate the total number of frames N involved in the splitting process of the target video f :

[0063]

[0064] where N f is the maximum number of frames that can be split from the video file under the given EMMC capacity condition, C is the total capacity of the EMMC, in GB; R is the horizontal resolution of the video image, D is the vertical resolution of the video image, and B is the number of bytes occupied by each pixel, depending on the color depth, is the floor operator, used to ensure that the number of frames is an integer value. The above formula derives the number of frames that can be accommodated under the current EMMC specification based on the volume of the image data itself.

[0065] The advantage of the above formula is that it can not only dynamically reflect the upper limit of the frame capacity under different EMMC specifications, but also provide a quantitative basis for video splitting and subsequent parallel writing strategies. Furthermore, in a multi-EMMC parallel architecture, the number of frames can also be proportionally allocated to each storage module, thereby optimizing data balance and writing speed. In addition, by dynamically adjusting the compression ratio or color depth parameter of the image, the result of this formula can be further refined to achieve a flexible balance between the number of images and image quality.

[0066] During the specific storage process, the write operation of the image data is based on the block device structure of the EMMC. Each frame of image is divided into several equal-length data segments and buffered and written according to the page alignment strategy (such as 4KB alignment). In addition, to improve access efficiency, a continuous logical address space can be pre-allocated before EMMC writing, combined with the file system or bare data structure, to avoid bandwidth waste caused by fragmented storage. In the scenario of multiple EMMCs in parallel, the system can evenly distribute the image frames to multiple EMMC channels according to the frame sequence number to achieve concurrent writing and load balancing.

[0067] It should be noted that the number of EMMCs can be jointly determined according to the total number of frames of the target video, the storage capacity of a single EMMC, and the desired parallel write bandwidth. When a single EMMC cannot meet the capacity requirements or write speed requirements of all frame images, the capacity can be expanded and the bandwidth can be increased by increasing the number of EMMCs, thereby ensuring the efficient storage of video data and the smoothness of subsequent playback.

[0068] In summary, step S102 not only covers the complete process of splitting video frame-by-frame images, but also provides theoretical support and practical guidance for resource evaluation, system optimization, and playback control by introducing a frame number estimation formula, effectively improving the adaptability and scalability of the system to high-resolution video transmission tasks.

[0069] Step S103, in response to a video playback request, schedules and reads the corresponding stored images from the EMMC through the DDR.

[0070] In step S103, according to the video playback request, a read operation is started to schedule and extract the pre-stored frame-by-frame image data from the EMMC. At this time, the goal is to efficiently transfer the image data from the storage medium to the DDR memory to prepare for subsequent video playback.

[0071] Specifically, first determine the current playback timestamp and frame rate, and calculate the current image frame number to be read based on these parameters. Then, the DDR schedules the corresponding image data from the EMMC storage according to the frame number and loads it into the memory. To ensure the real-time and stability of the read operation, the data of subsequent frames may be pre-loaded into the DDR cache in advance to avoid delays or stuttering. During the read process, through an effective scheduling mechanism, ensure the order and integrity of the data, and avoid frame loss or out-of-order during the read process. After the data transfer is completed, the image frames will be stored in the DDR memory for subsequent operations to verify and further process. It should be noted that the read bandwidth and latency of the EMMC will directly affect the data scheduling efficiency. Therefore, when designing, multiple EMMC storage modules will be considered for parallel reading to improve the data read speed.

[0072] Step S104, verify whether each frame of the image read from the EMMC by the DDR is complete and error-free.

[0073] In step S104, it is necessary to verify whether each frame of the image read from the EMMC is complete and error-free to ensure that no loss or damage occurs during the transmission of the entire video file during the read process. This verification process is crucial, especially in high-resolution and high-frame-rate video playback scenarios. The loss or error of any frame of the image may cause a significant decrease in video playback quality and even directly affect the stability of the system.

[0074] In implementation, since the storage process involves multiple EMMCs writing, reading in parallel, and possible buffer synchronization issues, simply through conventional hash comparison or simple pixel difference comparison cannot fully handle all potential data corruption situations. Therefore, this application designs a multi-dimensional integrity verification method based on image features. To solve the inconsistency and latency problems brought by multiple EMMC parallel writes and more accurately detect the integrity of image data, a new image differential integrity function is introduced. This function not only considers the direct comparison of hash values or pixels, but also combines the spatial features and frequency features of the image, so as to more comprehensively evaluate the integrity of each frame of the image. The function is as follows:

[0075]

[0076] Among them, Δ intergrity (i) represents the integrity differential evaluation value of the i-th frame of the image. The closer the value is to 0, the more complete the frame of the image is; the closer the value is to 1, the greater the image difference and the higher the possibility of data corruption. respectively represent the hash values when the i-th frame of the image is stored and read. F k (·) represents the k-th frequency domain feature extraction function, which converts the image data from the spatial domain to the frequency domain. is the weight coefficient of each frequency domain feature, used to measure the influence of this frequency component on integrity. Different frequency components have different degrees of influence on the image quality. Therefore, different weights need to be assigned to the frequency domain features of each frame of the image. δ(i) represents the spatial error function of the i-th frame of the image, indicating the spatial deviation between image pixels. This deviation will be introduced during the image reading process and may cause distortion or alignment problems at the image edges. σ is a tuning parameter used to balance the influence of spatial error on image integrity.

[0077] It should be noted that is the hash value calculated through the MD5 hash algorithm, and F k (·) is the existing discrete Fourier transform algorithm, used to convert the image from the spatial domain to the frequency domain. The converted frequency domain features can reveal the structural information of the image under different frequency components. By comparing the frequency domain features when stored and read, the possible subtle damages or distortions in the image can be captured more carefully. δ(i) is the mean square error method, used to measure the pixel-level differences in the image.

[0078] In the design of the above formula, traditional image integrity verification only relies on hash value comparison or pixel differences, but these methods often ignore the high-level features of images. By introducing frequency domain features, more accurate comparison can be carried out in terms of image details, textures, and overall structures, improving the reliability of verification. In high-concurrency EMMC reading scenarios, due to caching, read-write order, and synchronization issues, partial damage or displacement of some images may occur, and traditional hash or simple pixel comparison methods are difficult to capture these problems. By introducing a method that combines spatial error and frequency domain features, we can more comprehensively evaluate the integrity of images and improve the verification accuracy.

[0079] Finally, the integrity verification of the overall video can be obtained by calculating the Δ intergrity value of all frames to get a total integrity index Φ total :

[0080]

[0081] If the calculated Φ total value is lower than the preset safety threshold, a retry mechanism will be triggered to request the re-reading of lost or damaged image data to ensure that the quality of the finally played video is not affected.

[0082] Step S105: In response to a successful verification request, the image is synchronously transmitted to the VR screen for frame-by-frame rendering and playback.

[0083] In step S105, after completing the verification of the integrity of each frame of the image, the image data that has been confirmed to be correct in the DDR buffer is synchronously transmitted to the terminal device, that is, the VR display screen for frame-by-frame rendering and playback.

[0084] To sum up, through the preprocessing of video files, format standardization and data segmentation are realized; then the preprocessed video is split into static images frame by frame, named serially in a unified format, and after calculating the total number of frames according to the preset formula, it is evenly distributed and written into multiple EMMCs, thus breaking through the limitations of the bandwidth and capacity of a single memory; then, when responding to a video playback request, the image data stored in the EMMC is read in parallel through the DDR cache, and then the integrity of the read data is verified through an innovative multi-dimensional integrity verification method that combines frequency domain features and spatial error to ensure that there is no loss or disorder in the video data during transmission, and finally high-resolution and high-frame-rate image data is provided for the VR display screen to achieve stable and efficient video playback. This solution effectively solves the technical problem that traditional VR dot-matrix devices are difficult to achieve high-definition and smooth video transmission due to the limited storage bandwidth and processing power of the driver board without relying on an external host, while also taking into account the issues of device cost, volume, and control flexibility.

[0085] Figure 2 It is a block diagram of an EMMC parallel video transmission system provided by an embodiment of the present application. The system at least includes the following modules:

[0086] A video acquisition module, configured to acquire a video file and preprocess the video file;

[0087] A video splitting module, configured to split the preprocessed video file into frame-by-frame pictures and store them in the EMMC;

[0088] An image reading module, configured to schedule and read the corresponding stored images from the EMMC through the DDR in response to a video playback request;

[0089] An image verification module, configured to verify whether each frame of the image read from the EMMC by the DDR is complete and error-free;

[0090] A video playback module, configured to synchronously transmit the image to the VR screen for frame-by-frame rendering and playback in response to a successful verification request.

[0091] For related details, refer to the above method embodiment.

[0092] Figure 3 It is a block diagram of an electronic device provided by an embodiment of the present application. The device at least includes a processor 401 and a memory 402.

[0093] The processor 401 may include one or more processing cores, such as: a 4-core processor, an 8-core processor, etc. The processor 401 may be implemented in at least one of the following hardware forms: DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 401 may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 401 may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 401 may further include an AI (Artificial Intelligence) processor, and the AI processor is used to process computational operations related to machine learning.

[0094] The memory 402 may include one or more computer-readable storage media, which may be non-transitory. The memory 402 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In some embodiments, the non-transitory computer-readable storage media in the memory 402 is used to store at least one instruction for being executed by the processor 401 to implement the EMMC parallel video transmission method provided in the method embodiments of this application.

[0095] In some embodiments, the electronic device may optionally further include: a peripheral device interface and at least one peripheral device. The processor 401, the memory 402, and the peripheral device interface may be connected through a bus or signal lines. Each peripheral device may be connected to the peripheral device interface through a bus, signal lines, or a circuit board. Schematically, the peripheral devices include but are not limited to: a radio frequency circuit, a touch display screen, an audio circuit, and a power supply, etc.

[0096] Certainly, the electronic device may also include fewer or more components, and this embodiment does not limit this.

[0097] Optionally, this application also provides a computer-readable storage medium, in which a program is stored, and the program is loaded and executed by a processor to implement the EMMC parallel video transmission method in the above method embodiments.

[0098] Optionally, this application also provides a computer product, which includes a computer-readable storage medium, in which a program is stored, and the program is loaded and executed by a processor to implement the EMMC parallel video transmission method in the above method embodiments.

[0099] The technical features of the above embodiments may be combined arbitrarily. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0100] The above embodiments only represent several implementation manners of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several deformations and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of the patent of this application should be subject to the appended claims.

Claims

1. An EMMC parallel video transmission method, characterized in that, The method includes: Obtain a video file and preprocess the video file; Split the preprocessed video file into frame-by-frame pictures and store them in the EMMC; In response to a video playback request, schedule and read the corresponding stored images from the EMMC through the DDR; Verify whether each frame of image read from the EMMC by the DDR is complete and error-free; In response to a successful verification request, the images are synchronously transmitted to the VR screen for frame-by-frame rendering and playback.

2. The EMMC parallel video transmission method according to claim 1, wherein The obtaining a video file and preprocessing the video file includes: Check whether the obtained video file meets the general coding format; Parse the video file through multimedia decoding technology, and perform filtering, noise reduction, and color balance processing on the video; Mark the key frames in the video stream and correct the timestamps.

3. The EMMC parallel video transmission method according to claim 1, characterized in that, The splitting the preprocessed video file into frame-by-frame pictures and storing them in the EMMC includes: Discretize the preprocessed video data on the time axis according to its frame rate parameter, and extract each frame of image data; Generate static pictures for each frame of image in an uncompressed or lightly compressed manner, and save them as image files with a unified resolution and bit depth format; Perform serialization processing on the image naming and establish a mapping index table.

4. The EMMC parallel video transmission method according to claim 1, wherein The splitting the preprocessed video file into frame-by-frame pictures and storing them in the EMMC further includes: Calculate the total number of frames N involved in the splitting process of the target video using the following formula f : Among them, N f is the maximum number of frames that a video file can be split into under the given EMMC capacity condition, C is the total capacity of the EMMC, R is the horizontal resolution of the video image, D is the vertical resolution of the video image, B is the number of bytes occupied by each pixel, is the floor operator.

5. The EMMC parallel video transmission method according to claim 1, wherein The scheduling and reading the corresponding stored images from the EMMC through the DDR includes: Determine the current playback timestamp and frame rate, and calculate the current image frame number to be read according to these parameters; The DDR schedules the corresponding image data from the EMMC storage according to the frame number and loads it into the memory.

6. The EMMC parallel video transmission method according to claim 1, characterized in that The verifying whether each frame of image read from the EMMC by the DDR is complete and error-free includes: Introduce a new image differential integrity function: Among them, Δ intergrity (i) represents the integrity differentiation evaluation value of the i-th frame image, respectively represent the hash values of the i-th frame image during storage and reading, F k (·) represents the k-th frequency domain feature extraction function, are the weight coefficients of each frequency domain feature, δ(i) represents the spatial error function of the i-th frame image, and σ is a regulation parameter.

7. The EMMC parallel video transmission method according to claim 6, wherein The verifying whether each frame of image read from the EMMC by the DDR is complete and error-free further includes: Δ through all frames intergrity values are used to calculate a total integrity index Φ total : If the calculated Φ total value is below the preset safety threshold, a retry mechanism will be triggered to request the rereading of the lost or corrupted image data.

8. An EMMC parallel video transmission system, characterized in that, Includes: A video acquisition module for obtaining a video file and preprocessing the video file; A video splitting module for splitting the preprocessed video file into frame-by-frame pictures and storing them in the EMMC; An image reading module for scheduling and reading the corresponding stored images from the EMMC through the DDR in response to a video playback request; An image verification module for verifying whether each frame of image read from the EMMC by the DDR is complete and error-free; A video playback module for synchronously transmitting the images to the VR screen for frame-by-frame rendering and playback in response to a successful verification request.

9. An electronic device, characterized in that, The device includes a processor and a memory; a program is stored in the memory, and the program is loaded and executed by the processor to implement an EMMC parallel video transmission method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, A program is stored in the storage medium, and when the program is executed by the processor, it is used to implement an EMMC parallel video transmission method as described in any one of claims 1 to 7.

Images