EMMC parallel video transmission method and system

Abstract

The application relates to the technical field of network transmission, in particular to an EMMC parallel video transmission method and system, which comprises the following steps: acquiring a video file and preprocessing the video file; splitting the preprocessed video file into frame-by-frame pictures and storing the frame-by-frame pictures in an EMMC; in response to a video playing request, scheduling and reading corresponding stored pictures from the EMMC through DDR; verifying whether each frame of picture read from the EMMC by the DDR is complete and correct; and in response to a successful verification request, synchronously transmitting the picture to a VR screen for frame-by-frame rendering and playing. The technical problem that a traditional VR point screen device is difficult to realize high-definition and smooth video transmission without relying on an external host is effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of network transmission, and particularly relates to an EMMC parallel video transmission method and system. BACKGROUND

[0002] With the rapid development of virtual reality (VR) technology, VR display devices have been widely applied in the fields of game entertainment, education and training, industrial simulation, etc. In order to improve the immersive experience, the VR point screen device puts forward higher requirements on the definition and smoothness of the displayed image, especially when playing high-resolution and high-frame-rate video content, the image transmission and processing capacity have higher technical requirements.

[0003] The existing VR point screen device usually directly processes and displays image data through a drive board during picture transmission, which can meet the needs of static display. However, in actual application, it is often necessary to play high-definition video content to present a more realistic visual effect. At this time, if a traditional desktop computer is used as a video source for transmission, although it can meet the requirements of high-resolution and high-frame-rate playback, it will significantly increase the device size and cost, and bring problems such as complex control and poor flexibility.

[0004] Therefore, under the above background, the existing technology generally has the problem that the transmission rate cannot meet the requirements when implementing high-resolution and high-frame-rate video playback in the drive board. Especially without the help of a host device, limited by the support capability of the existing drive board in the video processing path and storage bandwidth, it is difficult to realize stable playback of high-definition video stream. Therefore, how to realize efficient and stable video transmission and playback in the VR point screen device without relying on an external host has become a difficult problem currently faced. SUMMARY

[0005] The present application provides an EMMC parallel video transmission method and system, which effectively solves the technical problem that the traditional VR point screen device cannot realize high-definition and smooth video transmission without relying on an external host. The present application provides the following technical solutions:

[0006] In a first aspect, the present application provides an EMMC parallel video transmission method, which comprises:

[0007] acquiring a video file and preprocessing the video file;

[0008] splitting the preprocessed video file into frame-by-frame pictures and storing them in an EMMC;

[0009] in response to a request for video playback, scheduling and reading the corresponding stored images from the EMMC through a DDR;

[0010] verify whether each frame of image read out from the EMMC by the DDR is complete and correct;

[0011] In response to the request of successful verification, the image is synchronously transmitted to the VR screen for frame-by-frame rendering and playing.

[0012] In one specific implementation, the acquiring and preprocessing of the video file includes:

[0013] checking whether the acquired video file meets the general encoding format;

[0014] analyzing the video file by multimedia decoding technology, filtering, noise reduction and color balance processing of the video;

[0015] labeling the key frame in the video stream and correcting the timestamp.

[0016] In one specific implementation, the splitting of the preprocessed video file into frame-by-frame pictures and storing in the EMMC includes:

[0017] discrete processing of the preprocessed video data on the time axis according to the frame rate parameter thereof, and extracting each frame of image data;

[0018] generating a static picture in an uncompressed or lightly compressed manner for each frame of image, and saving as an image file in a unified resolution and bit depth format;

[0019] serializing the naming of the image and establishing a mapping index table.

[0020] In one specific implementation, the splitting of the preprocessed video file into frame-by-frame pictures and storing in the EMMC further includes:

[0021] The total number of frames N involved in the splitting process of the target video is calculated using the following formula f :

[0022]

[0023] wherein N f is the maximum number of frames that can be split from the video file under the given EMMC capacity condition, C is the total capacity of the EMMC, R is the horizontal resolution of the video image, D is the vertical resolution of the video image, B is the number of bytes occupied by each pixel, is a floor operator.

[0024] In one specific implementation, the scheduling and reading of the corresponding stored image from the EMMC by the DDR includes:

[0025] determining the current playing timestamp and frame rate, and calculating the image frame number to be read according to the parameters;

[0026] The DDR schedules the corresponding image data from the EMMC according to the frame number and loads it into the memory.

[0027] In a specific implementation, the verification of whether each frame of image read from the EMMC by the DDR is complete and correct includes:

[0028] A new image differential integrity function is introduced:

[0029]

[0030] where Δ intergrity (i) represents the differential integrity evaluation value of the i-th frame of image, respectively represent the hash values of the i-th frame of image at storage time and reading time, F k (·) represents the k-th frequency domain feature extraction function, is the weight coefficient of each frequency domain feature, δ(i) represents the spatial error function of the i-th frame of image, and σ is a regulation parameter.

[0031] In a specific implementation, the verification of whether each frame of image read from the EMMC by the DDR is complete and correct further includes:

[0032] A total integrity index Φ intergrity is calculated by using the Δ total values of all frames.

[0033]

[0034] If the calculated Φ total value is lower than a preset safety threshold, a retry mechanism is triggered to require re-reading of the lost or damaged image data.

[0035] In a second aspect, the present application provides an EMMC parallel video transmission system, which adopts the following technical scheme:

[0036] An EMMC parallel video transmission system includes:

[0037] A video acquisition module is configured to acquire a video file and pre-process the video file.

[0038] A video splitting module is configured to split the pre-processed video file into frame-by-frame pictures and store the pictures in an EMMC.

[0039] an image reading module, configured to read the corresponding stored images from the EMMC through the DDR in response to a request for video playback;

[0040] an image verification module, configured to verify whether each frame of image read from the EMMC by the DDR is complete and correct;

[0041] a video playback module, configured to transmit the images to the VR screen for frame-by-frame rendering and playback in response to a request for successful verification.

[0042] In a third aspect, the present application provides an electronic device, which comprises a processor and a memory; the memory stores a program, which is loaded and executed by the processor to implement the EMMC parallel video transmission method according to the first aspect.

[0043] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a program, which is executed by a processor to implement the EMMC parallel video transmission method according to the first aspect.

[0044] In summary, the beneficial effects of the present application include at least:

[0045] (1) By frame-level splitting and frame sequence number index establishment mechanism, the preprocessed video file is disassembled into uniform format frame-by-frame images, and combined with the frame number estimation formula, the dynamic evaluation and optimized utilization of EMMC capacity resources are realized. At the same time, multiple EMMC modules are used for parallel writing and reading, supplemented by page alignment, continuous address allocation and average load scheduling strategies, which significantly improves the data writing rate and reading concurrency, thereby effectively supporting real-time transmission and non-jitter playback of high-resolution videos, and enhancing the performance of the system under large-scale video processing tasks.

[0046] (2) In view of the data misplacement or image damage problem that may be caused in parallel transmission, the present application proposes an image integrity difference evaluation function based on frequency domain and spatial feature fusion. This function not only compares the hash value difference in the storage and reading process, but also fuses the weighted difference of image frequency components and spatial pixel deviation, to evaluate the image integrity from multiple dimensions. Compared with traditional hash check or pixel comparison methods, this integrity function can more accurately identify potential distortion problems of images in structure, details or edges, thereby effectively improving the data security and image quality assurance capability of the system.

[0047] By preprocessing the video file, the format standardization and data segmentation are realized; then the preprocessed video is split into static images by frame, and after being named in a unified format and sequence and the total frame number being calculated according to a preset formula, the static images are evenly distributed and written into multiple EMMC, so as to break through the limitation of single memory bandwidth and capacity; then, when responding to a video playing request, the image data stored in the EMMC is read in parallel through the DDR cache, and then a multi-dimensional integrity checking method innovatively combining frequency domain features and spatial errors is used to verify the integrity of the read data, so as to ensure that the video data is not lost or disordered in the transmission process, and finally high-resolution and high-frame-rate image data is provided for the VR display screen, so that stable and efficient video playing is realized. The scheme effectively solves the technical problem that the traditional VR point screen device is difficult to realize high-definition and smooth video transmission due to the limitation of the storage bandwidth and processing capacity of the drive board without relying on an external host, and at the same time, the problems of device cost, size and control flexibility are considered.

[0048] The above description is only a summary of the technical scheme of the present application. In order to more clearly understand the technical means of the present application and can be implemented according to the content of the description, the following will be described in detail with the preferred embodiments of the present application and with the help of the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 is a flowchart of the EMMC parallel video transmission method in the embodiments of the present application.

[0050] Figure 2 is a structural block diagram of the EMMC parallel video transmission system in the embodiments of the present application.

[0051] Figure 3 is a block diagram of the electronic device for EMMC parallel video transmission in the embodiments of the present application. DETAILED DESCRIPTION

[0052] The specific embodiments of the present application will be further described in detail below in combination with the drawings and embodiments. The following embodiments are used to illustrate the present application, but not to limit the scope of the present application.

[0053] Alternatively, the EMMC parallel video transmission method provided by the embodiments of the present application is used as an example to illustrate the electronic device, which is a terminal or a server. The terminal can be a mobile phone, a computer, a tablet computer, etc. The type of the electronic device is not limited in the present embodiment.

[0054] Referring to Figure 1 is a flowchart of the EMMC parallel video transmission method provided by an embodiment of the present application. The method includes at least the following steps:

[0055] Step S101, acquire a video file and pre-process the video file.

[0056] In step S101, first, the video file needs to be acquired and pre-processed, and the main goal is to provide a set of original data with uniform format, stable structure and easy to parse for subsequent video frame decomposition, so in the implementation the source, encoding format and key parameters of the video file must be confirmed and processed in detail.

[0057] In the implementation, first check whether the acquired video file meets the general encoding format, such as H.264, H.265, etc., to ensure that the file has high compatibility and stability. Next, the video file is parsed by existing multimedia decoding technology, the video stream and audio stream are separated, and the frame rate, resolution, color depth and compression ratio of the video are extracted by using image processing algorithm, and at the same time the video is filtered, noise reduced and color balanced to eliminate the noise and distortion that may be introduced in the compression or transmission process, so as to ensure that the data format and size of each frame image remain consistent. In addition, the pre-processing also includes re-encoding or re-encapsulating the video file to generate a standardized data format for subsequent frame splitting, and dividing the video data into multiple data segments according to the total length of the video file and the expected playback requirements, and performing necessary data buffering processing to prevent buffer overflow or reading delay problems caused by too large data volume; at the same time, the key frames in the video stream are marked and the time stamp is corrected, so as to ensure that the subsequent frame-by-frame splitting can be accurately executed according to the predetermined time sequence.

[0058] Overall, through the detailed pre-processing of the video file in step S101, not only the data format and quality of the video frame can be effectively unified, but also a solid data foundation is laid for the subsequent splitting of the video file into frame-by-frame pictures and stored in the EMMC, and the stability and efficiency of the whole system in the process of high-speed data reading and real-time display are improved.

[0059] Step S102, split the pre-processed video file into frame-by-frame pictures and store them in the EMMC.

[0060] In step S102, the frame-level splitting operation is performed on the pre-processed video file, and the frame-by-frame image data obtained by splitting is efficiently written into the EMMC (embedded multimedia storage) device to realize the subsequent high-speed video playback capability. The splitting of the video frame not only ensures the integrity of each frame image, but also fully considers the writing bandwidth, capacity limitation of the EMMC and the organization structure of the picture data, so as to realize the efficient distribution and fast readability of the image data in the storage process.

[0061] Specifically, the pre-processed video data will be discretely processed in the time axis according to its frame rate parameter, and each frame of image data will be extracted. Each frame of image will be generated as a static picture in an uncompressed or lightly compressed manner, and saved as an image file in a unified resolution and bit depth format. In the splitting process, in order to ensure the real-time performance and addressability of the split picture data in the subsequent EMMC parallel read / write process, the image naming also needs to be sequentially processed, for example, renamed as frame_0001, frame_0002, etc. according to the frame number, and a mapping index table is established, so that the frame image can be quickly located and scheduled during playback.

[0062] In order to more systematically plan the number of split frames of image and reasonably allocate EMMC resources, the following formula is introduced to calculate the total number of frames N involved in the splitting process of the target video f :

[0063]

[0064] wherein N f is the maximum number of frames that can be split from the video file under the given EMMC capacity condition, C is the total capacity of the EMMC, in GB; R is the horizontal resolution of the video image, D is the vertical resolution of the video image, B is the number of bytes occupied by each pixel, which depends on the color depth, is the floor operator, which is used to ensure that the frame number is an integer value. The above formula is based on the volume of the image data itself to derive the number of frames that can be accommodated under the current EMMC specification.

[0065] The advantage of the above formula is that it not only dynamically reflects the upper limit of the frame capacity under different EMMC specifications, but also provides a quantitative basis for video splitting and subsequent parallel writing strategies. Further, in a multi-EMMC parallel architecture, the number of frames can also be allocated to each storage module in proportion, thereby optimizing data balance and writing speed. In addition, by dynamically adjusting the compression ratio or color depth parameters of the image, the result of the formula can be further refined to improve the flexible balance between the number of images or the quality of the images.

[0066] In the specific storage process, the writing operation of image data is based on the block device structure of EMMC, each frame of image is divided into several equal-length data segments, and is written after being buffered according to the page alignment strategy (such as 4KB alignment). In addition, in order to improve the access efficiency, a continuous logical address space can be pre-allocated before EMMC writing, combined with the file system or the bare data structure, to avoid the bandwidth waste caused by fragmented storage. In the multi-EMMC parallel scenario, the system can distribute the image frames according to the frame number and write them into multiple EMMC channels, realizing concurrent writing and load balancing.

[0067] It should be noted that the number of EMMCs can be determined according to the total number of frames of the target video, the storage capacity of a single EMMC, and the desired parallel write bandwidth. When a single EMMC cannot meet the capacity requirements or write speed requirements of all frame images, capacity expansion and bandwidth improvement can be achieved by increasing the number of EMMCs, thereby ensuring efficient storage of video data and smoothness of subsequent playback.

[0068] In summary, step S102 not only covers the complete splitting process of video frame-by-frame images, but also provides theoretical support and practical guidance for resource evaluation, system tuning, and playback control by introducing a frame number estimation formula, effectively improving the adaptability and scalability of the system for high-resolution video transmission tasks.

[0069] Step S103, in response to the request for video playback, schedules and reads the corresponding stored images from the EMMC through the DDR.

[0070] In step S103, according to the request for video playback, the reading operation is started, and the pre-stored frame-by-frame image data is scheduled and extracted from the EMMC. At this time, the goal is to efficiently transfer the image data from the storage medium to the DDR memory, preparing for subsequent video playback.

[0071] Specifically, first, determine the timestamp and frame rate of the current playback, and calculate the image frame number that needs to be read according to these parameters. Then, the DDR schedules the corresponding image data from the EMMC storage according to the frame number and loads it into the memory. In order to ensure the real-time and stability of the reading operation, the data of the subsequent frames may be preloaded into the DDR cache to avoid delay or lag phenomenon. During the reading process, through effective scheduling mechanism, the order and integrity of the data are ensured to avoid frame loss or sequence disorder. After the data transmission is completed, the image frames are stored in the DDR memory, waiting for subsequent operations to verify and further process. It should be noted that the reading bandwidth and delay of the EMMC will directly affect the data scheduling efficiency, so in the design, multiple EMMC storage modules are considered for parallel reading to improve the data reading speed.

[0072] Step S104, verify whether each frame of image read from the EMMC is complete and correct.

[0073] In step S104, it is necessary to verify whether each frame of image read from the EMMC is complete and correct, to ensure that the transmission of the entire video file does not have any loss or damage during the reading process. This verification process is crucial, especially in high-resolution, high-frame-rate video playback scenarios, any loss or error of a frame of image can cause a significant decrease in video playback quality, and even directly affect the stability of the system.

[0074] In implementation, due to the storage process involves multiple EMMC parallel writing, reading and possible buffer synchronization problems, only by the conventional hash comparison or simply pixel difference comparison can not fully handle all potential data damage. Therefore, the present application designs a multi-dimensional integrity check method based on image features, in order to solve the inconsistency and delay problems caused by multiple EMMC parallel writing, and more accurately detect the integrity of image data, a new image differentiation integrity function is introduced, which not only considers the hash value or the direct comparison of pixels, but also combines the spatial features and frequency features of the image, so as to more comprehensively evaluate the integrity of each frame of image. The function is as follows:

[0075]

[0076] Where Δ intergrity (i) represents the integrity differentiation evaluation value of the i-th frame of image. The value is closer to 0, indicating that the frame of image is more complete; the value is closer to 1, indicating that the image difference is larger, and the possibility of data damage is higher. respectively represent the hash values of the i-th frame of image when stored and read. F k (·) represents the k-th frequency domain feature extraction function, which converts the image data from the spatial domain to the frequency domain. is the weight coefficient of each frequency domain feature, used to measure the influence of the frequency component on the integrity. Different frequency components have different influences on image quality, so different weights need to be assigned to the frequency domain features of each frame of image. δ(i) represents the spatial error function of the i-th frame of image, indicating the spatial deviation between image pixels. This deviation will be introduced during image reading, which may cause image edge distortion or alignment problems. σ is a tuning parameter used to balance the influence of spatial error on image integrity.

[0077] It should be noted that, is the hash value calculated by the MD5 hash algorithm, F k (·) is the existing discrete Fourier transform algorithm, which is used to convert the image from the spatial domain to the frequency domain. The frequency domain features after conversion can reveal the structural information of the image under different frequency components, and by comparing the frequency domain features when stored and read, the subtle damage or distortion that may exist in the image can be captured in more detail. δ(i) is the mean square error method, which is used to measure the pixel-level difference in the image.

[0078] In the design of the above formula, the traditional image integrity check only relies on hash value comparison or pixel difference, but these methods often ignore the high-level features of the image. By introducing frequency domain features, more accurate comparison can be made in terms of image details, texture and overall structure, improving the reliability of the verification. In the high-concurrency EMMC reading scene, due to cache, read-write sequence, synchronization problems, it may cause partial damage or displacement of some images, and the traditional hash or simple pixel comparison method is difficult to capture these problems. By introducing the method of combining spatial error and frequency domain features, we can more comprehensively evaluate the integrity of the image and improve the verification accuracy.

[0079] Finally, the integrity verification of the whole video can be obtained by calculating the total integrity index Φ intergrity of all frames Δ total :

[0080]

[0081] If the calculated Φ total value is lower than the preset safety threshold, the retry mechanism will be triggered to re-read the lost or damaged image data to ensure that the quality of the final played video is not affected.

[0082] Step S105, in response to the request for successful verification, the image is synchronously transmitted to the VR screen for frame-by-frame rendering and playing.

[0083] In step S105, after completing the verification of the integrity of each frame of image, the image data confirmed to be correct in the DDR buffer is synchronously transmitted to the terminal device, i.e. the VR display screen, for frame-by-frame rendering and playing.

[0084] In summary, by preprocessing the video file, format standardization and data segmentation are achieved; then the preprocessed video is split into static images by frame, and after being named in a unified format, serialized and having the total number of frames calculated according to a preset formula, it is evenly distributed and written into multiple EMMC, thereby breaking through the limitation of single memory bandwidth and capacity; then, when responding to a video playing request, the image data stored in the EMMC is read in parallel through the DDR cache, and then a multi-dimensional integrity check method innovatively combining frequency domain features and spatial error is used to verify the integrity of the read data, ensuring that the video data is not lost or disordered during transmission, and finally providing high-resolution, high-frame-rate image data for the VR display screen, realizing stable and efficient video playing. This scheme effectively solves the technical problem that the traditional VR point screen device is difficult to realize high-definition and smooth video transmission due to the limitation of the storage bandwidth and processing capacity of the drive board without relying on an external host, while taking into account the problems of device cost, size and control flexibility.

[0085] Figure 2 is a structural block diagram of an EMMC parallel video transmission system provided by an embodiment of the present application, which at least includes the following modules:

[0086] a video acquisition module, configured to acquire a video file and pre-process the video file;

[0087] a video splitting module, configured to split the pre-processed video file into frame-by-frame pictures and store the pictures in an EMMC;

[0088] an image reading module, configured to read the corresponding stored pictures from the EMMC through a DDR in response to a request for video playing;

[0089] an image verification module, configured to verify whether each frame of picture read from the EMMC by the DDR is complete and correct;

[0090] a video playing module, configured to transmit the pictures to a VR screen for frame-by-frame rendering and playing in response to a request for successful verification.

[0091] For related details, refer to the above method embodiments.

[0092] Figure 3 is a block diagram of an electronic device provided by an embodiment of the present application. The device at least includes a processor 401 and a memory 402.

[0093] The processor 401 can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 401 can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 401 can also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 401 can be integrated with a GPU (Graphics Processing Unit) that is responsible for rendering and drawing the content to be displayed by the display screen. In some embodiments, the processor 401 can also include an AI (Artificial Intelligence) processor for processing machine learning-related computing operations.

[0094] The memory 402 can include one or more computer-readable storage media. The computer-readable storage media can be non-transitory. The memory 402 can also include high-speed random access memory and can include non-volatile memory, such as one or more magnetic disk storage devices, optical storage devices, flash memory devices, or other non-volatile solid-state storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 402 stores at least one instruction for execution by the processor 401 to implement the method of parallel video transmission of EMMC according to the method embodiments of the present application.

[0095] In some embodiments, the electronic device can also optionally include a peripheral device interface and at least one peripheral device. The processor 401, the memory 402, and the peripheral device interface can be connected by a bus or a signal line. Each peripheral device can be connected to the peripheral device interface by a bus, a signal line, or a circuit board. Illustratively, the peripheral device includes, but is not limited to, a radio frequency circuit, a touch display screen, an audio circuit, and a power supply, etc.

[0096] Of course, the electronic device can also include fewer or more components, and the present embodiment is not limited in this regard.

[0097] Optionally, the present application also provides a computer-readable storage medium, which stores a program, and the program is loaded and executed by a processor to implement the method of parallel video transmission of EMMC according to the method embodiments described above.

[0098] Optionally, the present application also provides a computer product, which includes a computer-readable storage medium, and the computer-readable storage medium stores a program, and the program is loaded and executed by a processor to implement the method of parallel video transmission of EMMC according to the method embodiments described above.

[0099] The technical features of the above embodiments can be combined in any manner. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0100] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method for EMMC parallel video transmission, characterized in that, The method comprises: acquiring a video file and preprocessing the video file; splitting the preprocessed video file into frame-by-frame pictures and storing them in multiple EMMCs in parallel; in response to a request for video playback, scheduling and reading the corresponding stored images from the multiple EMMCs in parallel through DDR; verifying whether each frame of image read from the EMMC by the DDR is complete and correct; the verification whether each frame of image read from the EMMC by the DDR is complete and correct comprises: a new image differentiation integrity function is introduced: wherein, denotes the frame image, , denotes the frame image, denotes the frame image, is a weight coefficient of each frequency domain feature, denotes the frame image, is an adjustment parameter; A total integrity index is computed from the values of all frames :​ wherein, is the maximum number of frames that the video file can be split into under the given EMMC capacity condition, if the calculated value is lower than a preset safety threshold, a retry mechanism is triggered, requiring the image data that is lost or damaged to be re-read. in response to a request for successful verification, the image is synchronously transmitted to a VR screen for frame-by-frame rendering and playback.

2. The method of claim 1, wherein, The acquiring of the video file and the preprocessing of the video file comprise: checking whether the acquired video file meets a general encoding format; analyzing the video file through multimedia decoding technology, filtering, noise reduction and color balance processing of the video; labeling key frames in the video stream and correcting timestamps.

3. The method of claim 1, wherein, The splitting of the preprocessed video file into frame-by-frame pictures and storing them in the EMMC comprise: discrete processing of the preprocessed video data on a time axis according to its frame rate parameters to extract each frame of image data; generating a static picture in an uncompressed or lightly compressed manner for each frame of image and saving it as an image file in a uniform resolution and bit depth format; serializing the naming of the image and establishing a mapping index table.

4. The method of claim 1, wherein, The splitting of the preprocessed video file into frame-by-frame pictures and storing them in the EMMC further comprise: The total number of frames involved in the splitting process for the target video is calculated using the following formula : wherein, is the maximum number of frames that can be split by the video file under the given EMMC capacity, is the total capacity of the EMMC, is the horizontal resolution of the video image, is the vertical resolution of the video image, is the number of bytes per pixel, is the floor operator.

5. The method of claim 1, wherein, The scheduling and reading of the corresponding stored images from the EMMC through the DDR comprise: determining the current playback timestamp and frame rate, and calculating the image frame number to be read according to these parameters; scheduling the corresponding image data from the EMMC storage according to the frame number and loading it into the memory through the DDR.

6. An EMMC parallel video transmission system, characterized by, It comprises: a video acquisition module for acquiring a video file and preprocessing the video file; a video splitting module for splitting the preprocessed video file into frame-by-frame pictures and storing them in multiple EMMCs in parallel; an image reading module for scheduling and reading the corresponding stored images from the multiple EMMCs in parallel through DDR in response to a request for video playback; an image verification module for verifying whether each frame of image read from the EMMC by the DDR is complete and correct; The verification whether each frame of image read from the EMMC by the DDR is complete and correct comprises: a new image differentiation integrity function is introduced: wherein, denotes the integrity differentiated evaluation value of the frame image, , denote the hash values of the frame image at the time of storage and reading, respectively, denotes the frequency domain feature extraction function, is the weight coefficient of each frequency domain feature, denotes the spatial error function of the frame image, is the adjustment parameter; A total integrity index is computed from the values of all frames :​ wherein, is the maximum number of frames that the video file can be split into under the given EMMC capacity condition, if the calculated value is lower than a preset safety threshold, a retry mechanism is triggered, requiring the image data that is lost or damaged to be re-read. a video playback module for synchronously transmitting the image to a VR screen for frame-by-frame rendering and playback in response to a request for successful verification.

7. An electronic device, comprising: The device comprises a processor and a memory; the memory stores a program which is loaded and executed by the processor to implement an EMMC parallel video transmission method according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The storage medium stores a program which is executed by the processor to implement an EMMC parallel video transmission method according to any one of claims 1 to 5.

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