Display device

Abstract

The invention relates to a display device. The display device includes: a first insulating layer disposed on a substrate; a first transistor including a first active layer disposed on the first insulating layer and having a first mobility, and a first gate electrode overlapping the first active layer in plan view; a first gate insulating layer disposed on the first insulating layer and the first active layer; a second gate insulating layer disposed on the first gate insulating layer; and a second transistor including a second active layer disposed between the first gate insulating layer and the second gate insulating layer at a position spaced apart from the first active layer and having a second mobility greater than the first mobility, and a second gate electrode overlapping the second active layer in plan view. The first gate insulating layer includes a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer, and a hydrogen concentration of the first oxide layer is higher than a hydrogen concentration of the second oxide layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2024 - 0004774, filed with the Korean Intellectual Property Office (KIPO) on January 11, 2024, the entire contents of which are incorporated herein by reference. Technical field

[0003] Embodiments of the present disclosure relate to a display device. Background art

[0004] With the development of the information society, various demands for display devices are continuously increasing. Accordingly, various types of display devices, including light - emitting display devices, are being developed. A light - emitting display device may include pixels including transistors and light - emitting elements. Summary of the invention

[0005] Aspects of the present disclosure provide a display device that can improve the operating characteristics of pixels.

[0006] However, the aspects of the present disclosure are not limited to the aspects stated herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to an embodiment of the present disclosure, a display device may include: a first insulating layer disposed on a substrate; a first transistor including a first active layer disposed on the first insulating layer and having a first mobility and a first gate electrode overlapping the first active layer in a plan view; a first gate insulating layer disposed on the first insulating layer and the first active layer; a second gate insulating layer disposed on the first gate insulating layer; and a second transistor including a second active layer disposed between the first gate insulating layer and the second gate insulating layer at a position spaced apart from the first active layer and having a second mobility greater than the first mobility and a second gate electrode overlapping the second active layer in a plan view. The first gate insulating layer may include a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer, and the hydrogen concentration of the first oxide layer may be higher than the hydrogen concentration of the second oxide layer.

[0008] In an embodiment, the first active layer may include a first oxide semiconductor, and the second active layer may include a second oxide semiconductor different from the first oxide semiconductor.

[0009] In an embodiment, the first oxide semiconductor may include indium gallium zinc oxide (IGZO).

[0010] In an embodiment, the second oxide semiconductor may include indium tin gallium zinc oxide (ITGZO) or indium gallium oxide (IGO).

[0011] In an embodiment, the first oxide layer and the second oxide layer may include silicon oxide.

[0012] In an embodiment, the nitride layer may include silicon nitride.

[0013] In an embodiment, the first gate insulating layer may include: a first portion disposed on the first active layer; and a second portion disposed between the first insulating layer and the second active layer.

[0014] In an embodiment, the first gate insulating layer may be partially disposed on a part of the first active layer and a part of the first insulating layer.

[0015] In an embodiment, the second gate insulating layer may include: a first portion disposed on the first portion of the first gate insulating layer; and a second portion disposed on the second active layer.

[0016] In an embodiment, the second gate insulating layer may be partially disposed on a part of the first active layer and a part of the second active layer.

[0017] In an embodiment, the first gate electrode and the second gate electrode may be disposed on the second gate insulating layer.

[0018] In an embodiment, the second gate insulating layer may include silicon oxide.

[0019] In an embodiment, the substrate may include a display area, and the first transistor and the second transistor are disposed in the display area.

[0020] In an embodiment, the display device may further include: a pixel disposed in the display area and including the first transistor and the second transistor.

[0021] In an embodiment, the first transistor may be a driving transistor of the pixel.

[0022] In an embodiment, the pixel may further include a light-emitting element electrically connected to the first transistor.

[0023] In an embodiment, the display device may further include: a bottom electrode disposed between the substrate and the first insulating layer and overlapping the first active layer in a plan view.

[0024] In an embodiment, the second transistor may be a switching transistor of the pixel.

[0025] In an embodiment, the display device may further include: a second insulating layer disposed on the first insulating layer and covering the first active layer, the first gate insulating layer, the second active layer, the second gate insulating layer, the first gate electrode, and the second gate electrode.

[0026] In an embodiment, the display device may further include at least one of the following: a first source electrode disposed on the second insulating layer and electrically connected to the source region of the first active layer; a first drain electrode disposed on the second insulating layer and electrically connected to the drain region of the first active layer; a second source electrode disposed on the second insulating layer and electrically connected to the source region of the second active layer; and a second drain electrode disposed on the second insulating layer and electrically connected to the drain region of the second active layer.

[0027] According to an embodiment of the present disclosure, the display device may include a first gate insulating layer disposed on the first active layer of the first transistor in the pixel and below the second active layer of the second transistor in the pixel. The first gate insulating layer may be formed of three or more layers including a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer. The first oxide layer and the second oxide layer may respectively have a hydrogen concentration suitable for improving and / or stabilizing the characteristics of the first transistor and the second transistor, and may have different hydrogen concentrations.

[0028] According to an embodiment, the characteristics of the first transistor and the second transistor may be improved simultaneously to satisfy the operating characteristics required for the first transistor and the second transistor of the pixel. Accordingly, the operating characteristics of the pixel including the first transistor and the second transistor and the display device including the pixel may be improved, and the reliability of the pixel and the display device may be ensured.

[0029] However, the effects according to the embodiments of the present disclosure are not limited to the effects exemplified above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by referring to the following detailed description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is a plan view showing a display device according to an embodiment of the present disclosure.

[0032] Figure 2 is for showing Figure 1 a plan view of the display panel.

[0033] Figure 3 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment of the present disclosure.

[0034] Figure 4 is a schematic cross-sectional view showing a display panel according to an embodiment of the present disclosure.

[0035] Figure 5 is for showing in detail Figure 4 a schematic cross-sectional view of region A1.

[0036] Figure 6 Schematic cross-sectional view showing in detail Figure 4 area A2 of Detailed implementation

[0037] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings which show embodiments of the present disclosure. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0038] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or directly coupled to the other element or layer or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connection" can refer to physical connection, electrical connection and / or fluid connection with or without intervening elements. And when an element is referred to as "in contact with" or "contacting" another element, etc., the element can be "electrically in contact with" or "physically in contact with" the other element; or "indirectly in contact with" or "directly in contact with" the other element. The same reference numerals throughout the specification indicate the same components.

[0039] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0040] The features of each of the various different embodiments of the present disclosure can be partially or fully combined with each other, and can interact with each other in different ways technically, and the respective embodiments can be implemented independently of each other or can be implemented together in an associated manner.

[0041] In the specification and claims, for the purpose of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B". In the specification and claims, for the purpose of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctive sense or a disjunctive sense, and can be understood to be equivalent to "and / or".

[0042] As used herein, "about" or "approximate" includes the recited value and means within an acceptable deviation range of a particular value as determined by one of ordinary skill in the art in view of the measurements discussed and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the recited value.

[0043] Unless otherwise defined or implied herein, all terms used (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in a commonly used dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0044] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 FIG. is a plan view showing a display device 100 according to an embodiment of the present disclosure. Figure 2 To show Figure 1 a plan view of the display panel 110 of

[0046] Referring to Figure 1 and Figure 2 , the display device 100 can be used to display moving images or still images. The display device 100 can be used as a display screen of a portable electronic device (such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, and a ultra-mobile personal computer (UMPC)), as well as a display screen of various products (such as a television, a notebook computer, a monitor, a billboard, and an Internet of Things (IoT) device). The above are only examples, and the display device 100 can also be used in other electronic devices.

[0047] According to an embodiment of the present disclosure, the display device 100 can be a light-emitting display device, such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, and an ultra-small light-emitting display device including an ultra-small light-emitting diode (such as a micro light-emitting diode or a nano light-emitting diode (micro LED or nano LED)). However, it should be understood that the present disclosure is not limited thereto. For example, the display device 100 can be other types of display devices in addition to the light-emitting display device. In the following description, a light-emitting display device (e.g., an organic light-emitting display device) is disclosed as an embodiment of the display device 100.

[0048] The display device 100 may include a display panel 110 including pixels PX, and a first driver 120 and a second driver 130 that supply driving signals to the pixels PX. The display device 100 may further include additional elements. For example, the display device 100 may further include a power supply unit for supplying a power voltage to the pixels PX, the first driver 120, and the second driver 130, and a timing controller for controlling operations of the first driver 120, the second driver 130, etc.

[0049] The display panel 110 may include a display area DA and a non-display area NDA. The display area DA may include pixels PX to display an image. For example, the display area DA may include a pixel area in which the pixels PX are disposed. The non-display area NDA may be an area other than the display area DA where an image is not displayed. According to an embodiment of the present disclosure, the non-display area NDA may be disposed adjacent to the display area DA (e.g., surrounding the display area DA).

[0050] In Figure 1 and Figure 2 , a first direction D1, a second direction D2, and a third direction D3 are defined. According to an embodiment of the present disclosure, the first direction D1 may be a horizontal direction of the display panel 110, and the second direction D2 may be a vertical direction of the display panel 110. The third direction D3 may be a thickness direction of the display panel 110.

[0051] According to an embodiment of the present disclosure, the display panel 110 may have a rectangular shape in a plan view. Although in Figure 1 and Figure 2 the display panel 110 has a horizontal length greater than a vertical length, the shape of the display panel 110 is not limited thereto. For example, the display panel 110 may have a shape in which the vertical length is greater than the horizontal length, or may have a square shape, etc. The display panel 110 may include sharp corners or rounded corners.

[0052] The shape of the display panel 110 in a plan view is not limited to the above-mentioned rectangular shape, but may adopt other shapes. For example, the display panel 110 may have a polygonal shape, a circular shape, an elliptical shape, or other shapes other than a rectangle.

[0053] The display panel 110 may be a substantially non-deformable rigid display panel, or may be a flexible display panel that is deformable (i.e., at least partially foldable, bendable, or rollable). The display panel 110 may be provided to the display device 100 without being bent or partially bent.

[0054] The display panel 110 may include a substrate SUB and pixels PX disposed on the substrate SUB. The pixels PX may be disposed in the display area DA on the substrate SUB.

[0055] The substrate SUB can be used to fabricate or provide a base member of the display panel 110 and can form a base surface of the display panel 110. The substrate SUB can include a display area DA and a non-display area NDA surrounding the display area DA.

[0056] According to an embodiment, the display area DA can have various shapes. For example, the display area DA can have a rectangular shape, a non-rectangular polygon shape, a circular shape, an oval shape, an irregular shape, or other shapes in a plan view. According to an embodiment of the present disclosure, the display area DA can have a shape corresponding to the shape of the display panel 110.

[0057] A plurality of pixels PX can be arranged in the display area DA. For example, the display area DA can include a pixel area in which the pixels PX are disposed.

[0058] According to an embodiment of the present disclosure, the display device 100 can be a light-emitting display device, and each pixel PX can include a light-emitting element located in respective emission areas and a pixel circuit connected to the light-emitting element. In the following description of the embodiment, the term "connected" can cover electrical connection and / or physical connection. Each pixel circuit can include transistors (e.g., a driving transistor that generates a driving current corresponding to a data signal and at least one switching transistor) and at least one capacitor (e.g., a storage capacitor).

[0059] The non-display area NDA can include a pad area PA in which pads PD are disposed. According to an embodiment of the present disclosure, the non-display area NDA can further include a driving circuit area located on at least one side of the display area DA. At least one driver, pads PD, and / or lines can be provided in the non-display area NDA.

[0060] At least one driver or a part of the driver for driving the pixels PX can be provided in the driving circuit area. For example, circuit elements forming the first driver 120 (e.g., a driving transistor and a driving capacitor forming a stage circuit of the first driver 120) can be provided in the driving circuit area on the substrate SUB. According to an embodiment of the present disclosure, the circuit elements of the first driver 120 can be formed together with the pixels PX in the display panel 110. According to an embodiment of the present disclosure, the driving transistor provided to the first driver 120 can be a transistor of a type and / or structure that is substantially the same as or similar to the type and / or structure of the transistor provided to the pixels PX, and can be formed together with the transistors of the pixels PX. For example, each driving transistor can have a structure that is substantially the same as or similar to the structure of the driving transistor or the switching transistor of the pixels PX.

[0061] The pad PD can be disposed in the pad region PA. At least one circuit board 140 can be disposed and / or bonded on the pad region PA. According to an embodiment of the present disclosure, a plurality of circuit boards 140 connected to different pads PD can be disposed on the pad region PA. The pad PD can include a signal pad and a power pad for transmitting a driving signal and a power voltage required to drive the pixel PX and / or the first driver 120 to the display panel 110.

[0062] The first driver 120 and the second driver 130 can generate driving signals for controlling the operation timing and brightness of the pixel PX, and can supply the driving signals to the pixel PX. For example, the first driver 120 can be a gate driver including a scan driver, and can be connected to the pixel PX through respective gate lines. The first driver 120 can supply a gate signal (for example, a gate signal including a scan signal for controlling the operation timing of the pixel PX) to the pixel PX. The second driver 130 can be a data driver including a source driver circuit, and can be connected to the pixel PX through respective data lines. The second driver 130 can supply respective data signals to the pixel PX.

[0063] According to an embodiment of the present disclosure, at least one of the first driver 120 and the second driver 130 or a part of at least one of the first driver 120 and the second driver 130 can be incorporated into the display panel 110. For example, the first driver 120 or a part of the first driver 120 can be disposed on the substrate SUB of the display panel 110, and can be disposed and / or formed in the non-display area NDA.

[0064] Although in Figure 1 the embodiment shown, the first driver 120 is formed on one side of the display area DA (for example, in the non-display area NDA on the right side of the display area DA), the present disclosure is not limited thereto. In another embodiment, the first driver 120 can be only located on the other side of the display area DA (for example, in the non-display area NDA on the left side of the display area DA), or located on both sides of the display area DA (for example, in the non-display areas NDA on the left and right sides of the display area DA). In another embodiment, a part of the first driver 120 can be located in the non-display area NDA, while another part of the first driver 120 can be located in a non-emitting area in the display area DA (for example, an area between the emitting areas of the pixels PX).

[0065] According to an embodiment of the present disclosure, the other one of the first driver 120 and the second driver 130 or a part of the other one of the first driver 120 and the second driver 130 may be disposed or formed outside the display panel 110 and may be electrically connected to the display panel 110. For example, the second driver 130 may be implemented with a plurality of integrated circuit chips and may be disposed on a circuit board 140 that is electrically connected to the pixels PX of the display panel 110. The first driver 120 may be implemented with at least one integrated circuit chip and may be mounted in the non-display area NDA of the display panel 110.

[0066] The circuit board 140 may be connected to the display panel 110 through pads PD. According to an embodiment of the present disclosure, the circuit board 140 may be, but is not limited to, a flexible printed circuit board (FPCB), a rigid printed circuit board (RPCB), or a flexible film (such as chip on film (COF)). According to an embodiment of the present disclosure, the circuit board 140 may be connected to the timing controller and / or the power supply unit through another circuit board or a connector.

[0067] Figure 3 FIG. is a schematic diagram of an equivalent circuit of a pixel PX according to an embodiment of the present disclosure. For example, Figure 3 FIG. schematically shows a pixel PX of a light-emitting display device including a light-emitting element ED. The type and / or structure of the pixels PX that may be included in the display device 100 (see Figure 1 ) may vary according to embodiments.

[0068] Reference Figure 3 shows that the pixel PX may include a light-emitting element ED and a pixel circuit PC connected to the light-emitting element ED. The light-emitting element ED may be a light source of the pixel PX and may be, but is not limited to, an organic light-emitting diode. The pixel circuit PC may control the emission timing and brightness of the light-emitting element ED.

[0069] The pixel circuit PC may supply a driving current Id to the light-emitting element ED in response to driving signals supplied from the first driver 120 (see Figure 1 ) and the second driver 130 (see Figure 1 ). For example, the pixel circuit PC may supply a driving current Id to the light-emitting element ED in response to a gate signal GS supplied from the first driver 120 (see Figure 1 ) through each gate line GL and a data signal DATA supplied from the second driver 130 (see Figure 1 ) through the data line DL.

[0070] The pixel PX can be connected to a first gate line GWL that transmits a first gate signal GW (e.g., a scan signal), a second gate line GIL that transmits a second gate signal GIN, a third gate line GRL that transmits a third gate signal GR, an emission control line ECL that transmits an emission control signal EM, and a data line DL that transmits a data signal DATA. The pixel PX can be connected to a first voltage line VDL that transmits a first pixel voltage ELVDD (also referred to as "first pixel power supply voltage" or "driving voltage") and a second voltage line VSL that transmits a second pixel voltage ELVSS (also referred to as "second pixel power supply voltage" or "common voltage"). According to an embodiment of the present disclosure, the pixel PX can be further connected to an initialization voltage line VIL that transmits an initialization voltage VINT (also referred to as "third pixel power supply voltage") and a reference voltage line VRL that transmits a reference voltage VREF (also referred to as "fourth pixel power supply voltage").

[0071] The pixel circuit PC can include a transistor T and at least one capacitor C. For example, the pixel circuit PC can include a driving transistor DT, one or more switching transistors ST, and first and second capacitors C1 and C2. According to an embodiment of the present disclosure, the pixel circuit PC can include four switching transistors ST, such as a first switching transistor ST1, a second switching transistor ST2, a third switching transistor ST3, and a fourth switching transistor ST4.

[0072] The driving transistor DT can control the magnitude of a driving current Id supplied to the light-emitting element ED according to a gate-source voltage. One or more switching transistors ST can be turned on or off according to their respective gate-source voltages. Depending on the type of each transistor T (e.g., p-type or n-type transistor) and / or operating conditions, the first electrode of each transistor T can be a drain electrode (or drain region) or a source electrode (or source region), and its second electrode can be an electrode different from the first electrode. For example, when the first electrode is a drain electrode, the second electrode can be a source electrode.

[0073] Although Figure 3 it is illustrated that all the transistors T are n-type transistors, the type of the transistor T is not limited thereto. In another embodiment, at least one transistor T can be formed as a p-type transistor.

[0074] According to an embodiment of the present disclosure, the transistors can be located in respective pixel regions and can be oxide transistors (also referred to as "oxide semiconductor transistors") including an oxide semiconductor. For example, the active layer of each of the driving transistor DT and the first to fourth switching transistors ST1 to ST4 can include an oxide semiconductor. However, it should be understood that the present disclosure is not limited thereto. For example, at least one transistor T can be formed of a semiconductor material other than an oxide semiconductor (e.g., amorphous silicon or polycrystalline silicon).

[0075] According to an embodiment of the present disclosure, the transistor T in each pixel PX and the transistors T provided on the display panel 110 may all be oxide transistors including an oxide semiconductor. The oxide semiconductor has a high carrier mobility and a low leakage current, and accordingly, even when the oxide transistor is driven for a long time, a large voltage drop does not occur. For example, the pixel PX including the oxide transistor may be driven at a low frequency because even when driven at a low frequency, the change in the brightness and / or color of the image due to the voltage drop is negligible. When the transistor T is formed of an oxide semiconductor, the leakage current of the pixel PX can be suppressed or prevented, and power consumption can be saved.

[0076] The oxide semiconductor may be sensitive to light, and thus the amount of current may be changed by external light. According to an embodiment of the present disclosure, a light blocking pattern or a light blocking electrode (e.g., a bottom electrode BE or a back gate electrode) may be provided under the active layer included in at least one transistor T to block external light. Accordingly, the operating characteristics of the transistor T can be stabilized.

[0077] The driving transistor DT may include a gate electrode connected to the first node N1, a first electrode (e.g., a drain electrode) connected to the second node N2, and a second electrode (e.g., a source electrode) connected to the third node N3. The first electrode of the driving transistor DT may be connected to the first voltage line VDL through the fourth switching transistor ST4, and the second electrode may be connected to the light emitting element ED. The driving transistor DT may control the magnitude (e.g., the amount of current) of the driving current Id flowing to the light emitting element ED in response to the data signal DATA transmitted to the first node N1.

[0078] According to an embodiment of the present disclosure, the driving transistor DT may further include a bottom electrode (or a light blocking layer) BE connected to the third node N3. The bottom electrode BE of the driving transistor DT may be connected to the third node N3 such that the driving transistor DT is implemented as a transistor having a double gate structure (e.g., a double gate transistor having a source-sync structure), thereby improving the operating characteristics of the driving transistor DT. The bottom electrode BE of the driving transistor DT may be provided under the active layer of the driving transistor DT to block external light.

[0079] The first switching transistor ST1 may include a gate electrode connected to the first gate line GWL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1. The first switching transistor ST1 may be turned on by the first gate signal GW (e.g., the first gate signal GW of the gate conduction voltage) transmitted through the first gate line GWL to connect the data line DL to the first node N1. Accordingly, the data signal DATA transmitted through the data line DL may be transmitted to the first node N1.

[0080] The second switching transistor ST2 may include a gate electrode connected to the third gate line GRL, a first electrode connected to the reference voltage line VRL, and a second electrode connected to the first node N1. The second switching transistor ST2 may be turned on by a third gate signal GR transmitted through the third gate line GRL, and may transmit a reference voltage VREF transmitted through the reference voltage line VRL to the first node N1.

[0081] The third switching transistor ST3 may include a gate electrode connected to the second gate line GIL, a first electrode connected to the third node N3, and a second electrode connected to the initialization voltage line VIL. The third switching transistor ST3 may be turned on by a second gate signal GIN transmitted through the second gate line GIL, and may transmit an initialization voltage VINT transmitted through the initialization voltage line VIL to the third node N3.

[0082] The fourth switching transistor ST4 may include a gate electrode connected to the emission control line ECL, a first electrode connected to the first voltage line VDL, and a second electrode (or the first electrode of the driving transistor DT) connected to the second node. The fourth switching transistor ST4 may be turned on by an emission control signal EM (e.g., an emission control signal EM of a gate turn-on voltage) transmitted through the emission control line ECL to control the emission timing of the pixel PX.

[0083] Each switching transistor ST may or may not include a bottom electrode (or a light blocking layer) BE under the active layer. According to an embodiment of the present disclosure, at least one switching transistor ST may include the bottom electrode BE, and the bottom electrode BE of at least one switching transistor ST may be connected to the gate electrode of the switching transistor ST. By connecting the bottom electrode BE of the switching transistor ST to the gate electrode, the turn-off characteristics and switching speed of the switching transistor ST may be improved, an additional voltage tolerance range may be obtained, leakage current may be reduced, and voltage stability may be improved. According to another embodiment, the bottom electrode BE may not be provided under the active layer of the switching transistor ST.

[0084] The first capacitor C1 may be connected between the first node N1 and the third node N3. The first capacitor C1 may be a storage capacitor of the pixel PX, and may store a voltage (e.g., a data voltage) corresponding to the data signal DATA.

[0085] The second capacitor C2 may be connected between the first voltage line VDL and the third node N3. According to an embodiment of the present disclosure, the capacitance of the second capacitor C2 may be smaller than the capacitance of the first capacitor C1.

[0086] The light-emitting element ED can be connected between the third node N3 and the second voltage line VSL. For example, the light-emitting element ED can include a first electrode (e.g., an anode electrode) connected to the third node N3, a second electrode (e.g., a cathode electrode) facing the first electrode and connected to the second voltage line VSL, and an emission layer inserted between the first electrode and the second electrode. According to an embodiment of the present disclosure, the first electrode of the light-emitting element ED can be an independent electrode separately provided in each pixel PX, while the second electrode of the light-emitting element ED can be a common electrode shared by a plurality of pixels PX. The light-emitting element ED can emit light having a brightness corresponding to the driving current Id supplied from the pixel circuit PC.

[0087] Figure 4 FIG. is a schematic cross-sectional view showing a display panel 110 according to an embodiment of the present disclosure. For example, Figure 4 Schematically shows a part of the display area DA of the display panel 110. Figure 4 Schematically shows an embodiment of a light-emitting display panel including a light-emitting element ED (e.g., an organic light-emitting diode) as the display panel 110.

[0088] Reference Figure 4 , the display panel 110 can include a substrate (or "base layer") SUB, a panel circuit layer PCL, a light-emitting element layer LEL, and a packaging layer ENL. The panel circuit layer PCL, the light-emitting element layer LEL, and the packaging layer ENL can be provided on the substrate SUB and can overlap each other. For example, in the display area DA, the panel circuit layer PCL, the light-emitting element layer LEL, and the packaging layer ENL can be sequentially provided on the substrate SUB in the third direction D3. The positions of the panel circuit layer PCL, the light-emitting element layer LEL, and / or the packaging layer ENL can be changed according to embodiments.

[0089] According to an embodiment of the present disclosure, the display panel 110 can further include additional elements provided on and / or below the packaging layer ENL. For example, the display panel 110 can further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a protective layer (e.g., a protective film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and the protective layer can be provided on the packaging layer ENL or between the light-emitting element layer LEL and the packaging layer ENL.

[0090] The substrate SUB can be a base member for forming the display panel 110 and can be a rigid or flexible substrate (or film). According to an embodiment of the present disclosure, the substrate SUB can be a rigid substrate including an insulating material (such as glass) and is not bendable. In another embodiment, the substrate SUB can be a flexible substrate that includes polyimide or other insulating materials and allows deformation (such as bending, folding, or rolling up), and can be bendable or not bendable. The type and / or material of the substrate SUB can vary according to the embodiment.

[0091] The panel circuit layer PCL (e.g., pixel circuit layer or thin film transistor layer) can be disposed on the substrate SUB. The panel circuit layer PCL can include circuit elements that include transistors T and capacitors C (see Figure 1 ) of the pixel PX (see Figure 3 ) and lines (e.g., signal lines and voltage lines). According to an embodiment of the present disclosure, the panel circuit layer PCL can further include circuit elements of the first driver 120 (see Figure 1 ) (e.g., driving transistors and / or driving capacitors provided in the first driver 120 (see Figure 1 )) and / or additional conductive patterns (e.g., bridge patterns).

[0092] Figure 4 An embodiment is shown in which the first transistor T1 and the second transistor T2 provided in one pixel region PXA are circuit elements that can be provided in the panel circuit layer PCL. Figure 4 The first transistor T1 in Figure 1 can be the driving transistor DT of the pixel PX (see Figure 4 ). For example, Figure 3 the first transistor T1 can be the driving transistor DT of Figure 4 The second transistor T2 in Figure 1 can be the switching transistor ST of the pixel PX (see Figure 4 ). For example, Figure 3 the second transistor T2 can be one of the first switching transistor ST1 to the fourth switching transistor ST4 of

[0093] According to an embodiment of the present disclosure, the switching transistors ST provided in each pixel PX (see Figure 1 ) can be formed simultaneously using the same oxide semiconductor and can have substantially the same cross-sectional structure. According to an embodiment of the present disclosure, the driving transistors DT and the switching transistors ST provided to each pixel PX (see Figure 1 ) can be formed using different oxide semiconductors. For example, the active layer (e.g., the first active layer ACT1) of the driving transistor DT and the active layer (e.g., the second active layer ACT2) of the switching transistor ST can use different oxide semiconductors.

[0094] According to an embodiment of the present disclosure, the panel circuit layer PCL may include an isolation layer BR. For example, the isolation layer BR may be disposed on the substrate SUB, and circuit elements and lines may be disposed on the isolation layer BR.

[0095] The panel circuit layer PCL may include a plurality of conductive layers and at least one semiconductor layer disposed on the isolation layer BR. Among the conductive layers, electrodes, conductive patterns (e.g., bridge electrodes), and / or lines connected to the circuit elements may be disposed to form the circuit elements (e.g., transistors T and capacitors C (see Figure 3 )) of the panel circuit layer PCL. The active layer of the transistor T formed in the panel circuit layer PCL may be disposed in at least one semiconductor layer.

[0096] According to an embodiment, the panel circuit layer PCL may include a plurality of semiconductor layers. For example, the panel circuit layer PCL may include a first semiconductor layer SCL1 and a second semiconductor layer SCL2. The first semiconductor layer SCL1 includes a first active layer ACT1 of a first transistor T1 (e.g., a driving transistor DT) for each pixel PX (see Figure 1 ), and the second semiconductor layer SCL2 includes a second active layer ACT2 of a second transistor T2 (e.g., at least one switching transistor ST) for each pixel PX (see Figure 1 ).

[0097] According to an embodiment of the present disclosure, the panel circuit layer PCL may include a first conductive layer CDL1 (e.g., a bottom electrode BE), a first semiconductor layer SCL1 (e.g., a first oxide semiconductor layer), a second semiconductor layer SCL2 (e.g., a second oxide semiconductor layer), a second conductive layer CDL2 (e.g., a gate conductive layer), and a third conductive layer CDL3 (e.g., a source-drain conductive layer or a data conductive layer) sequentially disposed on the isolation layer BR (or the substrate SUB) in a third direction D3. An insulating layer and / or an insulating pattern may be disposed between the conductive layers and the semiconductor layers of the panel circuit layer PCL.

[0098] According to an embodiment of the present disclosure, the panel circuit layer PCL may further include at least one conductive layer disposed on the third conductive layer CDL3 and at least one insulating layer covering the at least one conductive layer. The at least one conductive layer may include bridge electrodes and / or at least one line, etc., that connect the light-emitting element ED to the pixel circuit PC (see Figure 1 ) of each pixel PX (see Figure 3 ).

[0099] The patterns (e.g., electrodes, conductive patterns, and / or lines of each conductive layer) included in each conductive layer of the panel circuit layer PCL may include at least one conductive material. For example, the patterns provided or included in each of the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), and magnesium (Mg), etc., their alloys, or other conductive materials. According to an embodiment of the present disclosure, the patterns included in the same conductive layer may be formed simultaneously using the same conductive material.

[0100] According to an embodiment of the present disclosure, the patterns provided in each conductive layer of the panel circuit layer PCL may have a single-layer or multi-layer structure. For example, the patterns provided or included in the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 respectively may have a single-layer or multi-layer structure. According to an embodiment of the present disclosure, the patterns included in the same conductive layer may have the same cross-sectional structure.

[0101] The panel circuit layer PCL may further include an insulating layer and / or insulating patterns provided on the substrate SUB. For example, the panel circuit layer PCL may include a barrier layer BR, a first insulating layer INS1 (e.g., a buffer layer), a first gate insulating layer GI1, a second gate insulating layer GI2, a second insulating layer INS2 (e.g., an interlayer dielectric layer), and a third insulating layer INS3 (e.g., a planarization layer) sequentially provided on the substrate SUB in the third direction D3.

[0102] According to an embodiment of the present disclosure, at least one insulating layer provided in the panel circuit layer PCL may be entirely provided in the display area DA. For example, the barrier layer BR, the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may be entirely provided in the display area DA.

[0103] Each of the first gate insulating layer GI1 and the second gate insulating layer GI2 may be only partially provided in each pixel area PXA and a part of the display area DA including the pixel area PXA, or may be entirely provided in the display area DA. According Figure 4 to an embodiment, the first gate insulating layer GI1 and the second gate insulating layer GI2 may be only partially provided in each pixel area PXA and a part of the display area DA including the pixel area PXA.

[0104] The isolation layer BR may be disposed between the substrate SUB and the first conductive layer CDL1. The isolation layer BR may include at least one inorganic layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials). The isolation layer BR may protect the pixel PX (see Figure 1 ) from moisture that penetrates through the substrate SUB (the substrate SUB may be vulnerable to moisture penetration). The material of the isolation layer BR may vary according to embodiments.

[0105] The first insulating layer INS1 may be disposed on the first conductive layer CDL1. For example, the first insulating layer INS1 may be disposed on the isolation layer BR (or the substrate SUB) and may cover the pattern of the first conductive layer CDL1. The first insulating layer INS1 may include at least one inorganic layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials).

[0106] The first gate insulating layer GI1 may be disposed on the first insulating layer INS1 and the first semiconductor layer SCL1. The first gate insulating layer GI1 may include at least one inorganic insulating layer including an inorganic insulating material. According to an embodiment of the present disclosure, the first gate insulating layer GI1 may include a plurality of oxide layers (e.g., silicon oxide layers) and at least one nitride layer (e.g., silicon nitride layer) disposed between the plurality of oxide layers.

[0107] According to an embodiment of the present disclosure, the first gate insulating layer GI1 may be disposed on a part of each of the first insulating layer INS1 and the first semiconductor layer SCL1. For example, the first gate insulating layer GI1 may include a first portion GI1a disposed on the first active layer ACT1 of the first semiconductor layer SCL1 and a second portion GI1b disposed on a part of the first insulating layer INS1. In a plan view, the first portion GI1a and the second portion GI1b of the first gate insulating layer GI1 may be an integral insulating layer (or insulating pattern) connected to each other or may be separate independent insulating layers (or insulating patterns) from each other.

[0108] According to an embodiment of the present disclosure, the first portion GI1a of the first gate insulating layer GI1 may be disposed only partially on a part of the first active layer ACT1. For example, the first portion GI1a of the first gate insulating layer GI1 may be disposed only on the part of the first active layer ACT1 including the first channel region CH1 (the channel region of the first active layer ACT1), and may expose at least a part of the other parts of the first active layer ACT1 including each of the first source region SR1 (the source region of the first active layer ACT1) and the first drain region DR1 (the drain region of the first active layer ACT1).

[0109] Since the first gate insulating layer GI1 exposes the first source region SR1 and the first drain region DR1, the first source region SR1 and the first drain region DR1 can be appropriately and / or easily conductive during the process of manufacturing the display panel 110. For example, during the etching of the first gate insulating layer GI1 such that at least a part of each of the first source region SR1 and the first drain region DR1 is exposed, oxygen vacancies may exist in the first source region SR1 and / or the first drain region DR1. Accordingly, the first source region SR1 and the first drain region DR1 can be appropriately and / or easily conductive in subsequent processes (such as the process of forming the second insulating layer INS2, etc.) without performing a separate doping process.

[0110] The second part GI1b of the first gate insulating layer GI1 may be only partially disposed on a part of the first insulating layer INS1. For example, in a plan view (e.g., in the third direction D3), the second part GI1b of the first gate insulating layer GI1 may be disposed on a part of the first insulating layer INS1 that overlaps with the second active layer ACT2. For example, the second part GI1b of the first gate insulating layer GI1 may be disposed between the first insulating layer INS1 and the second active layer ACT2.

[0111] The second gate insulating layer GI2 may be disposed on the first gate insulating layer GI1 and the second semiconductor layer SCL2. The second gate insulating layer GI2 may include at least one inorganic insulating layer including an inorganic insulating material. For example, the second gate insulating layer GI2 may include at least one oxide layer including silicon oxide (SiO x ) or other oxides.

[0112] According to an embodiment of the present disclosure, the second gate insulating layer GI2 may be disposed on a part of each of the first gate insulating layer GI1 and the second semiconductor layer SCL2. For example, the second gate insulating layer GI2 may include: a first part GI2a disposed on the first part GI1a of the first gate insulating layer GI1 on the first active layer ACT1; and a second part GI2b disposed on the second active layer ACT2 of the second semiconductor layer SCL2 on the first insulating layer INS1. In a plan view, the first part GI2a and the second part GI2b of the second gate insulating layer GI2 may be an integral insulating layer (or insulating pattern) connected to each other or may be separate independent insulating layers (or insulating patterns) from each other.

[0113] According to an embodiment of the present disclosure, the first part GI2a of the second gate insulating layer GI2 may be only partially disposed on a part of the first active layer ACT1. For example, the first part GI2a of the second gate insulating layer GI2 may be only disposed on the part of the first active layer ACT1 including the first channel region CH1, and may expose the other parts of the first active layer ACT1 including at least a part of each of the first source region SR1 and the first drain region DR1.

[0114] The second part GI2b of the second gate insulating layer GI2 may be disposed only partially on a part of the second active layer ACT2. For example, the second part GI2b of the second gate insulating layer GI2 may be disposed only on the part of the second active layer ACT2 including the second channel region CH2 (the channel region of the second active layer ACT2), and may expose other parts of the second active layer ACT2 including at least a part of each of the second source region SR2 (the source region of the second active layer ACT2) and the second drain region DR2 (the drain region of the second active layer ACT2).

[0115] Since the second gate insulating layer GI2 exposes the first source region SR1, the first drain region DR1, the second source region SR2, and the second drain region DR2, the first source region SR1, the first drain region DR1, the second source region SR2, and the second drain region DR2 may be properly and / or easily conductive during the process of manufacturing the display panel 110. For example, oxygen vacancies may exist in the first source region SR1, the first drain region DR1, the second source region SR2, and / or the second drain region DR2 during etching of the second gate insulating layer GI2 and the like. Accordingly, the first source region SR1, the first drain region DR1, the second source region SR2, and the second drain region DR2 may be properly and / or easily conductive in subsequent processes without performing a separate doping process.

[0116] The second insulating layer INS2 may be disposed on the first insulating layer INS1, the first semiconductor layer SCL1, the first gate insulating layer GI1, the second semiconductor layer SCL2, the second gate insulating layer GI2, and the second conductive layer CDL2. For example, the second insulating layer INS2 may be disposed on the first insulating layer INS1 and cover the first semiconductor layer SCL1, the first gate insulating layer GI1, the second semiconductor layer SCL2, the second gate insulating layer GI2, and the second conductive layer CDL2. The second insulating layer INS2 may include at least one inorganic insulating layer including an inorganic insulating material.

[0117] The third insulating layer INS3 may be disposed on the third conductive layer CDL3. For example, the third insulating layer INS3 may be disposed on the second insulating layer INS2 and cover the pattern of the third conductive layer CDL3. The third insulating layer INS3 may include at least one organic insulating layer including an organic insulating material (for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating materials). The third insulating layer INS3 may or may not include an inorganic insulating layer. The surface (for example, the upper surface) of the third insulating layer INS3 may be substantially flat.

[0118] The first transistor T1 may include a first active layer ACT1 and a first gate electrode GE1 overlapping the first active layer ACT1 in a plan view. According to an embodiment of the present disclosure, the first gate electrode GE1 may be disposed on a part of the first active layer ACT1. For example, the first gate electrode GE1 may be a top gate electrode.

[0119] According to an embodiment of the present disclosure, the first transistor T1 may further include at least one of a first source electrode SE1 and a first drain electrode DE1. For example, the first transistor T1 may further include a first source electrode SE1 connected to a first source region SR1 and a first drain electrode DE1 connected to a first drain region DR1. In another embodiment, the first transistor T1 may not include separate source and / or drain electrodes, and the first source region SR1 and / or the first drain region DR1 may be connected to other circuit elements, lines, and / or conductive patterns to function as the first source electrode SE1 and / or the first drain electrode DE1 of the first transistor T1.

[0120] According to an embodiment of the present disclosure, the first transistor T1 may further include a bottom electrode (or light-blocking layer) BE disposed under the first active layer ACT1. According to an embodiment of the present disclosure, the bottom electrode BE may be connected to an electrode of the first transistor T1 (e.g., the first source electrode SE1) and may be used as a back gate electrode (or bottom gate electrode) to adjust the characteristics of the first transistor T1. For example, the bottom electrode BE may be electrically connected to the first source electrode SE1 through at least one contact hole penetrating the first insulating layer INS1 and the second insulating layer INS2. By disposing the bottom electrode BE under the first active layer ACT1, external light can be blocked from entering the first channel region CH1.

[0121] According to an embodiment of the present disclosure, the first transistor T1 may be an oxide transistor. For example, the first transistor T1 may be an n-type oxide transistor.

[0122] The bottom electrode BE may be provided or included in a first conductive layer CDL1 disposed on an isolation layer BR (or substrate SUB). For example, the bottom electrode BE may be disposed between the isolation layer BR (or substrate SUB) and the first insulating layer INS1.

[0123] In a plan view, the bottom electrode BE may overlap the first active layer ACT1 and the first gate electrode GE1. For example, the bottom electrode BE may be disposed under the first active layer ACT1 and overlap at least a part of the first active layer ACT1 including the first channel region CH1, and may face the first gate electrode GE1 with the first active layer ACT1 interposed between the first gate electrode GE1 and the bottom electrode BE.

[0124] The first active layer ACT1 may be provided or included in the first semiconductor layer SCL1. For example, the first active layer ACT1 may be disposed on the first insulating layer INS1 and may be covered by a first portion GI1a of the first gate insulating layer GI1 and the second insulating layer INS2.

[0125] The first active layer ACT1 may include a first channel region CH1 and a first source region SR1 and a first drain region DR1 spaced apart from each other, wherein the first channel region CH1 is inserted between the first source region SR1 and the first drain region DR1. For example, the first source region SR1 and the first drain region DR1 may be located on both sides of the first channel region CH1, respectively. The first source region SR1 and the first drain region DR1 may have a carrier concentration (e.g., electron concentration) higher than that of the first channel region CH1.

[0126] In a plan view, the first active layer ACT1 may overlap with the bottom electrode BE and the first gate electrode GE1. For example, a part of the first active layer ACT1 including the first channel region CH1 may overlap with the bottom electrode BE and the first gate electrode GE1 in the third direction D3.

[0127] According to an embodiment of the present disclosure, the first active layer ACT1 may include an oxide semiconductor. For example, the first active layer ACT1 may include an oxide semiconductor containing at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf), or other oxide semiconductors. According to an embodiment of the present disclosure, the first active layer ACT1 may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO or In2O3), titanium oxide (TiO or TiO2), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), and indium tin gallium zinc oxide (ITGZO).

[0128] According to an embodiment of the present disclosure, the first active layer ACT1 may have a first mobility (e.g., a first electron mobility) suitable for using the first transistor T1 as a driving transistor DT of the pixel PX (see Figure 1 ). For example, the first active layer ACT1 may include a first oxide semiconductor having the first mobility, and the first oxide semiconductor having the first mobility ensures an appropriate driving voltage range without significantly causing deviations or changes in characteristics such as the threshold voltage. For example, compared with the second active layer ACT2 of the second transistor T2 used as a switching transistor ST of the pixel PX (see Figure 1 ), the first active layer ACT1 may be formed of a first oxide semiconductor having a relatively low mobility. According to an embodiment of the present disclosure, the first oxide semiconductor may include, but is not limited to, indium gallium zinc oxide (IGZO).

[0129] The first part GI1a of the first gate insulating layer GI1 and the first part GI2a of the second gate insulating layer GI2 may be disposed on the first active layer ACT1. For example, the first part GI1a of the first gate insulating layer GI1 and the first part GI2a of the second gate insulating layer GI2 may be sequentially disposed on a part of the first active layer ACT1 including the first channel region CH1.

[0130] The first gate electrode GE1 may be disposed on the first gate insulating layer GI1 and the second gate insulating layer GI2. For example, the first gate electrode GE1 may be disposed on the second gate insulating layer GI2 in the first transistor region where the first transistor T1 is disposed. The first gate electrode GE1 may be provided or included in the second conductive layer CDL2. The second conductive layer CDL2 may be disposed on the second gate insulating layer GI2 and may be covered by the second insulating layer INS2.

[0131] The first gate electrode GE1 may be disposed on the first active layer ACT1. For example, the first gate electrode GE1 may be disposed on the first part GI1a of the first gate insulating layer GI1 and the first part GI2a of the second gate insulating layer GI2 covering the first channel region CH1. The first gate electrode GE1 and the first active layer ACT1 may be separated from each other, and the first part GI1a of the first gate insulating layer GI1 and the first part GI2a of the second gate insulating layer GI2 are inserted between the first gate electrode GE1 and the first active layer ACT1.

[0132] The first source electrode SE1 and the first drain electrode DE1 may be provided or included in the third conductive layer CDL3. The third conductive layer CDL3 may be disposed on the second insulating layer INS2 covering the second conductive layer CDL2 etc. and may be covered by the third insulating layer INS3.

[0133] The first source electrode SE1 may be connected to a part of the first active layer ACT1. For example, the first source electrode SE1 may be electrically connected to the first source region SR1 through at least one contact hole penetrating the second insulating layer INS2. According to an embodiment of the present disclosure, the first source electrode SE1 may also be electrically connected to the bottom electrode BE through at least one contact hole penetrating the first insulating layer INS1 and the second insulating layer INS2.

[0134] The first drain electrode DE1 may be connected to another part of the first active layer ACT1. For example, the first drain electrode DE1 may be electrically connected to the first drain region DR1 through at least one contact hole penetrating the second insulating layer INS2.

[0135] The first transistor T1 of each pixel PX (see Figure 1 ) may be electrically connected to each pixel PX (see Figure 1) light-emitting element ED. For example, the first transistor T1 provided in each pixel region PXA may be electrically connected to the first electrode ET1 of the light-emitting element ED in each pixel region PXA provided in the light-emitting element layer LEL.

[0136] The second transistor T2 may include a second active layer ACT2 and a second gate electrode GE2 overlapping the second active layer ACT2 in a plan view. According to an embodiment of the present disclosure, the second gate electrode GE2 may be provided on a part of the second active layer ACT2. For example, the second gate electrode GE2 may be a top gate electrode.

[0137] According to an embodiment of the present disclosure, the second transistor T2 may further include at least one of a second source electrode SE2 and a second drain electrode DE2. For example, the second transistor T2 may further include a second source electrode SE2 connected to the second source region SR2 of the second active layer ACT2 and a second drain electrode DE2 connected to the second drain region DR2 of the second active layer ACT2. In another embodiment, the second transistor T2 may not include separate source and / or drain electrodes, and the second source region SR2 and / or the second drain region DR2 may be connected to other circuit elements, lines, and / or conductive patterns to function as the second source electrode SE2 and / or the second drain electrode DE2 of the second transistor T2. The second transistor T2 may or may not include a bottom electrode BE provided under the second active layer ACT2.

[0138] According to an embodiment of the present disclosure, the second transistor T2 may be an oxide transistor. For example, the second transistor T2 may be an n-type oxide transistor.

[0139] The second active layer ACT2 may be provided or included in the second semiconductor layer SCL2. For example, the second active layer ACT2 may be provided on the second part GI1b of the first gate insulating layer GI1 and may be covered by the second part GI2b of the second gate insulating layer GI2 and the second insulating layer INS2.

[0140] The second active layer ACT2 may be provided between the first gate insulating layer GI1 and the second gate insulating layer GI2 at a position spaced apart from the first active layer ACT1. For example, the first active layer ACT1 and the second active layer ACT2 may be separated and / or spaced apart from each other in a plan view defined by a first direction D1 and a second direction D2, and may not overlap each other in a third direction D3.

[0141] The second active layer ACT2 may include a second channel region CH2, and a second source region SR2 and a second drain region DR2 spaced apart from each other, with the second channel region CH2 inserted between the second source region SR2 and the second drain region DR2. For example, the second source region SR2 and the second drain region DR2 may be located on both sides of the second channel region CH2, respectively. The second source region SR2 and the second drain region DR2 may have a carrier concentration (e.g., electron concentration) higher than that of the second channel region CH2.

[0142] In a plan view, the second active layer ACT2 may overlap with the second gate electrode GE2. For example, a part of the second active layer ACT2 including the second channel region CH2 may overlap with the second gate electrode GE2 in the third direction D3.

[0143] According to an embodiment of the present disclosure, the second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include an oxide semiconductor including at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), hafnium (Hf), etc. According to an embodiment of the present disclosure, the second active layer ACT2 may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO or In2O3), titanium oxide (TiO or TiO2), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), and indium tin gallium zinc oxide (ITGZO), etc.

[0144] According to an embodiment of the present disclosure, the second active layer ACT2 may have a second mobility (e.g., second electron mobility) suitable for using the second transistor T2 as a switching transistor ST of a pixel PX (see Figure 1 )). For example, the second active layer ACT2 may include a second oxide semiconductor having a second mobility higher than the first mobility of the first active layer ACT1 to ensure fast switching operation.

[0145] According to an embodiment of the present disclosure, the second active layer ACT2 may include a second oxide semiconductor different from the first oxide semiconductor of the first active layer ACT1. For example, compared to being used as a pixel PX (see Figure 1) The first active layer ACT1 of the first transistor T1 of the driving transistor DT may be formed of a first oxide semiconductor, and the second active layer ACT2 may be formed of a second oxide semiconductor having a relatively high mobility. According to an embodiment of the present disclosure, the second oxide semiconductor may include, but is not limited to, indium tin gallium zinc oxide (ITGZO) (e.g., high-mobility indium tin gallium zinc oxide (ITGZO)) or indium gallium oxide (IGO) (e.g., crystalline high-mobility indium gallium oxide (IGO)), which has a higher mobility than that of indium gallium zinc oxide (IGZO). For example, the second oxide semiconductor may include a high-mobility oxide semiconductor other than indium tin gallium zinc oxide (ITGZO) and indium gallium oxide (IGO) (e.g., an oxide semiconductor having a higher mobility than that of the first oxide semiconductor forming the first active layer ACT1).

[0146] A second portion GI2b of the second gate insulating layer GI2 may be disposed on the second active layer ACT2. For example, the second portion GI2b of the second gate insulating layer GI2 may be disposed on a portion of the second active layer ACT2 including the second channel region CH2.

[0147] The second gate electrode GE2 may be disposed on the second gate insulating layer GI2. For example, the second gate electrode GE2 may be disposed on the second gate insulating layer GI2 in a second transistor region where the second transistor T2 is disposed. According to an embodiment of the present disclosure, the first gate electrode GE1 and the second gate electrode GE2 may be disposed in the same conductive layer and may be formed simultaneously. For example, the second gate electrode GE2 may be provided or included in the second conductive layer CDL2.

[0148] The second gate electrode GE2 may be disposed on the second active layer ACT2. For example, the second gate electrode GE2 may be disposed on the second portion GI2b of the second gate insulating layer GI2 covering the second channel region CH2. The second gate electrode GE2 and the second active layer ACT2 may be separated from each other, and the second portion GI2b of the second gate insulating layer GI2 is inserted between the second gate electrode GE2 and the second active layer ACT2.

[0149] The second source electrode SE2 and the second drain electrode DE2 may be disposed on the second insulating layer INS2. According to an embodiment of the present disclosure, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and / or the second drain electrode DE2 may be provided in the same conductive layer and may be formed simultaneously. For example, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and / or the second drain electrode DE2 may be provided or included in the third conductive layer CDL3.

[0150] The second source electrode SE2 may be connected to a portion of the second active layer ACT2. For example, the second source electrode SE2 may be electrically connected to the second source region SR2 through at least one contact hole penetrating the second insulating layer INS2.

[0151] The second drain electrode DE2 may be connected to another part of the second active layer ACT2. For example, the second drain electrode DE2 may be electrically connected to the second drain region DR2 through at least one contact hole penetrating the second insulating layer INS2.

[0152] The third conductive layer CDL3 including the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and / or the second drain electrode DE2 may be covered by the third insulating layer INS3.

[0153] The light-emitting element layer LEL may be disposed on the panel circuit layer PCL. For example, the light-emitting element layer LEL may be disposed on the third insulating layer INS3 and may be at least located in the display area DA.

[0154] The light-emitting element layer LEL may include a light-emitting element ED for each pixel PX (see Figure 1 ). For example, the light-emitting element layer LEL may include a pixel defining layer PDL (also referred to as a "bank") that separates the emission regions of each pixel PX (see Figure 1 ) and a light-emitting element ED located in each emission region. According to an embodiment of the present disclosure, the light-emitting element layer LEL may further include a spacer SPC disposed on a part of the pixel defining layer PDL.

[0155] Each light-emitting element ED may include a first electrode ET1 located in each emission region, and an emission layer EML and a second electrode ET2 sequentially disposed on the first electrode ET1. The first electrode ET1 of the light-emitting element ED may be connected to at least one transistor (e.g., the first transistor T1) included in the corresponding pixel PX (see Figure 1 ).

[0156] The first electrode ET1 of the light-emitting element ED may be a single-layer or multi-layer electrode including at least one conductive material. According to an embodiment of the present disclosure, the display panel 110 may be a top-emission display panel, and the first electrode ET1 may include a reflective electrode layer having a high reflectivity.

[0157] The emission layer EML of each light-emitting element ED may include a polymer material or a low-molecular material. The light emitted from the emission layer EML may contribute to displaying an image.

[0158] Although Figure 4 the display panel 110 is shown in which the emission layer EML of the light-emitting element ED is independently formed in each pixel region PXA, the present disclosure is not limited thereto. For example, the display panel 110 may include light-emitting elements in a series structure, and the light-emitting elements in the series structure include an emission layer EML formed as a common film throughout the display area DA.

[0159] The second electrode ET2 of the light-emitting element ED may include a conductive material. According to an embodiment of the present disclosure, the second electrode ET2 may be a common layer formed throughout the display area DA and covering the emission layer EML and the pixel defining layer PDL. According to an embodiment of the present disclosure, the display panel 110 may be a top-emission display panel, and the second electrode ET2 may include a transparent or semi-transparent electrode layer.

[0160] The pixel defining layer PDL may have openings corresponding to respective emission regions and may surround the emission regions in a plan view. For example, the pixel defining layer PDL may cover the edge of the first electrode ET1 of the light-emitting element ED and may include an opening exposing the remaining portion of the first electrode ET1. The region where the exposed portion of the first electrode ET1 and the emission layer EML overlap each other may be the emission region of each pixel PX (see Figure 1 ). According to an embodiment of the present disclosure, the pixel defining layer PDL may include at least one organic insulating layer including an organic insulating material.

[0161] The spacer SPC may be provided on a part of the pixel defining layer PDL. The spacer SPC may include at least one organic insulating layer including an organic insulating material. The spacer SPC and the pixel defining layer PDL may include the same material or different materials. The pixel defining layer PDL and the spacer SPC may be sequentially formed through respective mask processes, or may be simultaneously formed and / or integrally formed using a halftone mask.

[0162] The encapsulation layer ENL may be provided on the light-emitting element layer LEL. The encapsulation layer ENL may cover the light-emitting element layer LEL in the display area DA and may extend to the non-display area NDA to contact the panel circuit layer PCL. The encapsulation layer ENL may block oxygen or moisture from penetrating into the light-emitting element layer LEL and may mitigate electrical shock and / or physical shock on the panel circuit layer PCL and the light-emitting element layer LEL.

[0163] According to an embodiment of the present disclosure, the encapsulation layer ENL may include a first encapsulation layer ENL1, a second encapsulation layer ENL2, and a third encapsulation layer ENL3 sequentially provided on the light-emitting element layer LEL. Each of the first encapsulation layer ENL1 and the third encapsulation layer ENL3 may be an inorganic encapsulation layer including an inorganic material. The second encapsulation layer ENL2 may be an organic encapsulation layer including an organic material.

[0164] Figure 5 To show in detail Figure 4 A schematic cross-sectional view of the region A1. Figure 6 To show in detail Figure 4 A schematic cross-sectional view of the region A2. For example, Figure 5 and Figure 6 To show in detail Figure 4 An enlarged view of the first gate insulating layer GI1.

[0165] Combined with Figure 4 Refer to Figure 5 and Figure 6 Figure 6

[0166] According to an embodiment of the present disclosure, the first gate insulating layer GI1 may be three-layer, and the three layers include a first oxide layer OL1, a nitride layer NL on the first oxide layer OL1, and a second oxide layer OL2 on the nitride layer NL. According to another embodiment, the first gate insulating layer GI1 may be composed of four or more layers, and the four or more layers further include at least one additional insulating layer in addition to the first oxide layer OL1, the nitride layer NL, and the second oxide layer OL2.

[0167] The first oxide layer OL1 and the second oxide layer OL2 may be oxide-based insulating layers including oxides having different hydrogen concentrations. According to an embodiment of the present disclosure, among the first oxide layer OL1 and the second oxide layer OL2, the first oxide layer OL1 adjacent to the first active layer ACT1 having a first mobility (for example, the oxide layer in the lower layer of the first gate insulating layer GI1) may have a higher hydrogen concentration than the second oxide layer OL2 adjacent to the second active layer ACT2 having a second mobility (for example, the oxide layer in the upper layer of the first gate insulating layer GI1). For example, the hydrogen concentration of the first oxide layer OL1 may be higher than that of the second oxide layer OL2. According to another embodiment, where the first active layer ACT1 is located at a position higher than the first gate insulating layer GI1 and the second active layer ACT2 having a second mobility greater than the first mobility of the first active layer ACT1 is located at a position lower than the first gate insulating layer GI1, the hydrogen concentration of the oxide layer in the upper layer of the first gate insulating layer GI1 may be higher than that of the oxide layer in the lower layer of the first gate insulating layer GI1.

[0168] According to an embodiment of the present disclosure, each of the first oxide layer OL1 and the second oxide layer OL2 may be a silicon oxide layer including silicon oxide (SiO x )). For example, the first oxide layer OL1 may be a high-hydrogen silicon oxide layer having a first hydrogen concentration, and the second oxide layer OL2 may be a low-hydrogen silicon oxide layer having a second hydrogen concentration lower than the first hydrogen concentration.

[0169] For example, in the case of measuring the hydrogen concentration of the first gate insulating layer GI1 by secondary ion mass spectrometry (SIMS), the hydrogen concentration measured at the position where the first oxide layer OL1 is formed may be higher than the hydrogen concentration measured at the position where the second oxide layer OL2 is formed. According to an embodiment of the present disclosure, the hydrogen concentration of the first oxide layer OL1 may be about 2.5 times or more of the hydrogen concentration of the second oxide layer OL2, but the present disclosure is not limited thereto. For example, the hydrogen concentration of the first oxide layer OL1 may be about 3 times or more of the hydrogen concentration of the second oxide layer OL2.

[0170] By forming the first oxide layer OL1 to include an oxide layer having a high hydrogen concentration (e.g., a high silicon hydroxide layer), the carrier concentration (e.g., electron concentration) of the first active layer ACT1 can be increased. Accordingly, traps in the first active layer ACT1 can be reduced, and the reliability of the first transistor T1 (e.g., positive bias temperature stress (PBTS) characteristics) can be improved.

[0171] According to an embodiment of the present disclosure, the characteristics of the first transistor T1 can be stabilized by controlling the film formation conditions of the first oxide layer OL1. For example, by forming the first oxide layer OL1 by low-power deposition, an initial threshold voltage deviation of the first transistor T1 due to plasma damage to the first active layer ACT1 can be prevented or suppressed. For example, by forming the first oxide layer OL1 by high-temperature deposition, defects in the first oxide layer OL1 can be reduced and the reliability of the first transistor T1 can be improved.

[0172] On the other hand, by forming the second oxide layer OL2 to include an oxide layer having a low hydrogen concentration (e.g., a low silicon hydroxide layer), the supply of hydrogen to the second active layer ACT2 can be controlled or restricted. Accordingly, characteristic deviations and / or characteristic changes (such as deviations and variations in threshold voltage) of the second transistor T2 can be prevented or suppressed, and the characteristics of the second transistor T2 can be improved. For example, by restricting the supply of hydrogen to the second active layer ACT2 by the second oxide layer OL2, the operating characteristics of the second transistor T2 can become balanced and / or stable.

[0173] The nitride layer NL may include an insulating material suitable for serving as a barrier to prevent the diffusion of moisture or hydrogen between the first oxide layer OL1 and the second oxide layer OL2. For example, the nitride layer NL may be formed as a porous film and can capture and remove moisture introduced from the vicinity. Accordingly, the reliability of the first transistor T1 and the second transistor T2 and circuit elements, conductive patterns, and / or lines formed in the panel circuit layer PCL can be improved.

[0174] According to an embodiment of the present disclosure, the nitride layer NL may include silicon nitride (SiN x) of silicon nitride layer, which can effectively block moisture or hydrogen. It should be noted that the material of the nitride layer NL is not limited to this. In addition to silicon nitride (SiN x ), it may also include other materials that can appropriately block moisture or hydrogen.

[0175] According to the above embodiment, the first transistor T1 operating as the driving transistor DT of the pixel PX (see Figure 1 ) and the second transistor T2 operating as the switching transistor ST of the pixel PX (see Figure 1 ) can be formed of different types of oxide semiconductors having different characteristics. For example, a first oxide semiconductor with a first mobility (e.g., indium gallium zinc oxide (IGZO)) can form the first active layer ACT1 of the first transistor T1, and a second oxide semiconductor with a second mobility higher than the first mobility (e.g., indium tin gallium zinc oxide (ITGZO) or indium gallium oxide (IGO)) can form the second active layer ACT2 of the second transistor T2. In this way, the characteristics of the first transistor T1 and the second transistor T2 can be improved to meet the required operating characteristics of each of the first transistor T1 and the second transistor T2. For example, the characteristics of the first transistor T1 and the second transistor T2 can be distinguished and / or optimized to meet the required operating characteristics of each of the first transistor T1 and the second transistor T2.

[0176] According to an embodiment, the first gate insulating layer GI1 disposed on the first active layer ACT1 and below the second active layer ACT2 can be formed to include three or more insulating layers of a first oxide layer OL1, a nitride layer NL, and a second oxide layer OL2. The first oxide layer OL1 adjacent to the first active layer ACT1 can be formed as a high hydroxide layer (e.g., a high silicon hydroxide layer) that can supply hydrogen to the first active layer ACT1, and the second oxide layer OL2 adjacent to the second active layer ACT2 can be formed as a low hydroxide layer (e.g., a low silicon hydroxide layer) that can limit the inflow of hydrogen into the second active layer ACT2. The nitride layer NL inserted between the first oxide layer OL1 and the second oxide layer OL2 can be formed of a material (e.g., silicon nitride) that can effectively block moisture, hydrogen, etc. In this way, the characteristics of the first transistor T1 and the second transistor T2 can be improved and / or optimized simultaneously, and the operation characteristics of the pixel PX (see Figure 1 ) including the first transistor T1 and the second transistor T2 and the display device 100 (see Figure 1 ) including the pixel PX (see Figure 1 ) can be improved.

[0177] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and variations. Therefore, the above embodiments of the present disclosure can be implemented alone or in combination with each other.

[0178] Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of this disclosure, but to describe the technical spirit of this disclosure, and the scope of the technical spirit of this disclosure is not limited to these embodiments. The protection scope of this disclosure shall be interpreted by the claims, and it shall be interpreted that all technical spirits within the equivalent scope are included within the scope of this disclosure.

Claims

1. A display device, comprising: A first insulating layer disposed on a substrate; A first transistor, comprising a first active layer disposed on the first insulating layer and having a first mobility, and a first gate electrode overlapping with the first active layer in a plan view; A first gate insulating layer disposed on the first insulating layer and the first active layer; A second gate insulating layer disposed on the first gate insulating layer; And A second transistor, comprising a second active layer disposed between the first gate insulating layer and the second gate insulating layer at a position spaced apart from the first active layer and having a second mobility greater than the first mobility, and a second gate electrode overlapping with the second active layer in a plan view, wherein The first gate insulating layer includes a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer, and The hydrogen concentration of the first oxide layer is higher than that of the second oxide layer.

2. The display device according to claim 1, wherein The first active layer includes a first oxide semiconductor, and The second active layer includes a second oxide semiconductor different from the first oxide semiconductor.

3. The display device according to claim 2, wherein the first oxide semiconductor includes indium gallium zinc oxide.

4. The display device according to claim 2, wherein the second oxide semiconductor includes indium tin gallium zinc oxide or indium gallium oxide.

5. The display device according to claim 1, wherein the first oxide layer and the second oxide layer include silicon oxide.

6. The display device according to claim 1, wherein the nitride layer includes silicon nitride.

7. The display device according to claim 1, wherein the first gate insulating layer includes: A first portion disposed on the first active layer; And A second portion disposed between the first insulating layer and the second active layer.

8. The display device according to claim 7, wherein the first gate insulating layer is partially disposed on a part of the first active layer and a part of the first insulating layer.

9. The display device according to claim 7, wherein the second gate insulating layer includes: A first portion disposed on the first portion of the first gate insulating layer; And A second portion disposed on the second active layer.

10. The display device according to claim 1, wherein the second gate insulating layer is partially disposed on a part of the first active layer and a part of the second active layer.

11. The display device according to claim 10, wherein the first gate electrode and the second gate electrode are disposed on the second gate insulating layer.

12. The display device according to claim 1, wherein the second gate insulating layer includes silicon oxide.

13. The display device according to claim 1, wherein The substrate includes a display area, and The first transistor and the second transistor are disposed in the display area.

14. The display device according to claim 13, further comprising: A pixel disposed in the display area and including the first transistor and the second transistor.

15. The display device according to claim 14, wherein the first transistor is a driving transistor of the pixel.

16. The display device according to claim 15, wherein the pixel further includes a light-emitting element electrically connected to the first transistor.

17. The display device according to claim 15, further comprising: A bottom electrode disposed between the substrate and the first insulating layer and overlapping the first active layer in a plan view.

18. The display device according to claim 14, wherein the second transistor is a switching transistor of the pixel.

19. The display device according to claim 1, further comprising: A second insulating layer disposed on the first insulating layer and covering the first active layer, the first gate insulating layer, the second active layer, the second gate insulating layer, the first gate electrode, and the second gate electrode.

20. The display device according to claim 19, further comprising at least one of the following: A first source electrode disposed on the second insulating layer and electrically connected to a source region of the first active layer; A first drain electrode disposed on the second insulating layer and electrically connected to a drain region of the first active layer; A second source electrode disposed on the second insulating layer and electrically connected to a source region of the second active layer; and A second drain electrode disposed on the second insulating layer and electrically connected to a drain region of the second active layer.

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