Display device

Abstract

A display device according to an embodiment is provided. The display device includes a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a common voltage line disposed in the display area and connected to an external common voltage line; a dam disposed between the substrate and the common voltage line, and including an opening; and a plurality of pixels disposed in the display area and including a first electrode, a light emitting layer, and a second electrode, the common voltage line being a multilayer structure including a first layer, a second layer, and a third layer, the first layer including a planar portion disposed at an opening of the dam and a non-planar portion disposed to overlap the dam.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2024-0003493, filed with the Korean Intellectual Property Office on January 9, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] A display device is a device that displays an image. Recently, light-emitting diode displays have received attention as self-emitting display devices.

[0004] The light-emitting display device has a self-emitting characteristic and, unlike a liquid crystal display device, does not require a separate light source, so that the thickness and weight can be reduced.

[0005] In addition, the light-emitting display device exhibits high-quality characteristics such as low power consumption, high brightness, and high response speed.

[0006] Generally, a light-emitting display device may include a substrate, a plurality of thin film transistors disposed on the substrate, a plurality of insulating layers disposed between wirings constituting the thin film transistors, and a light-emitting device connected to the thin film transistors.

[0007] The light-emitting device may include a first electrode, a light-emitting layer, and a second electrode, and the second electrode may be disposed in a plate shape throughout the display device. Summary of the Invention

[0008] An embodiment aims to provide a display device that improves the contact characteristics between an electrode and a wiring and prevents a voltage drop.

[0009] A display device according to an embodiment includes: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a common voltage line disposed in the display area and connected to the external common voltage line; a dam disposed between the substrate and the common voltage line and including an opening; and a plurality of pixels disposed in the display area and including a first electrode, a light-emitting layer, and a second electrode. The common voltage line is a multilayer structure including a first layer, a second layer, and a third layer. The first layer includes a planar portion disposed at the opening of the dam and a non-planar portion disposed to overlap the dam.

[0010] The second electrode may be in direct contact with the top surface of the first layer and the side surface of the second layer.

[0011] The planar portion of the first layer may be disposed closer to the substrate than the non-planar portion.

[0012] The thickness of the dam may be 3000 Å to 5000 Å.

[0013] The second layer may have a shape that widens toward the center of the second layer.

[0014] The width of the widest part of the second layer may be 1.1 to 1.5 times the width of the part of the second layer where the second layer and the first layer are in contact.

[0015] The angle formed between the side surface of the second layer and the top surface of the substrate may be 20 degrees or greater and 50 degrees or less.

[0016] The thickness of the second layer may be 6000 Å to 10000 Å.

[0017] The non-planar part of the first layer and the side surface of the second layer may be spaced apart from each other.

[0018] The spacing region between the non-planar part of the first layer and the side surface of the second layer may have a length of 200 nm to 300 nm.

[0019] The second electrode may be disposed in the spacing region between the non-planar part of the first layer and the side surface of the second layer.

[0020] The third layer may include a planar part and a non-planar part, and the planar part of the third layer may be disposed closer to the substrate than the non-planar part of the third layer.

[0021] The planar part of the third layer may be in contact with the second layer.

[0022] The thickness of the second layer may be greater than the sum of the thicknesses of the first layer and the third layer.

[0023] The thickness of the second layer may be greater than the thickness of the first layer, and the thickness of the first layer may be greater than the thickness of the third layer.

[0024] The first layer may have a thickness of 500 Å to 1000 Å, the second layer may have a thickness of 6000 Å to 10000 Å, and the third layer may have a thickness of 100 Å to 500 Å.

[0025] The display device according to an embodiment includes: a substrate including a display region and a non-display region; an external common voltage line disposed in the non-display region; a common voltage line disposed in the display region and connected to the external common voltage line; a dam disposed between the substrate and the common voltage line and including an opening; and a plurality of pixels disposed in the display region and including a first electrode, a light-emitting layer, and a second electrode. The common voltage line is a multilayer structure including a first layer, a second layer, and a third layer. The second electrode is in direct contact with the top surface of the first layer and the side surface of the second layer.

[0026] The first layer may include a planar portion and a non-planar portion. The planar portion of the first layer is disposed closer to the substrate than the non-planar portion, and a spacer region may be disposed between the non-planar portion of the first layer and the side surface of the second layer.

[0027] The length of the spacer region may be from 200 nm to 300 nm.

[0028] The width of the portion of the second layer where the second layer contacts the first layer may be narrower than the width of the center of the second layer.

[0029] According to an embodiment, a display device is provided that improves the contact characteristics between electrodes and wirings and prevents voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A display device according to the present embodiment is briefly illustrated.

[0031] Figure 2 A cross-section of a common voltage line according to the present embodiment is illustrated.

[0032] Figure 3 A common voltage line according to an embodiment is illustrated.

[0033] Figure 4 、 Figure 5 、 Figure 6 and Figure 7 A manufacturing process of a common voltage line according to the present embodiment is illustrated.

[0034] Figure 8 A cross-section of a pixel of a display device according to the present embodiment is briefly illustrated.

[0035] Figure 9 is a plan view of a display device according to the present embodiment.

[0036] Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 and Figure 18 The display device is illustrated for each layer Figure 9 of. DETAILED DESCRIPTION

[0037] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the inventive concept.

[0038] The inventive concept may be implemented in many different forms and is not limited to the embodiments described herein.

[0039] To clearly explain the inventive concept, components irrelevant to the description are omitted, and the same or similar components are assigned the same reference numerals throughout the specification.

[0040] In addition, the dimensions and thicknesses of each component shown in the drawings are arbitrarily shown for ease of explanation, and thus the inventive concept is not necessarily limited to what is shown.

[0041] In the drawings, the thicknesses are exaggerated to clearly show the respective layers and regions.

[0042] In the drawings, for ease of explanation, the thicknesses of some layers and regions are exaggerated.

[0043] Furthermore, when a part of a layer, film, region, or plate is referred to as being "on" or "above" another part, this includes not only the case where the part of the layer, film, region, or plate is "directly on" the other part, but also the case where there is another part therebetween.

[0044] In contrast, when an element is referred to as being "directly on" another element, there is no intervening element.

[0045] In addition, "on" or "above" a reference member means being disposed above or below the reference member, and does not necessarily mean being disposed "above" or "on" it in the direction opposite to gravity.

[0046] In addition, throughout the specification, when a component is referred to as "including" a certain element, unless otherwise specifically stated to the contrary, this means that the component may also include other elements, rather than excluding other elements.

[0047] In addition, throughout the specification, when referring to "in a plane", this means when viewing the target part from above, and when referring to "in a cross-section", this means when vertically cutting the cross-section of the target part and viewing it from the side.

[0048] Figure 1 A display device according to the present embodiment is briefly shown.

[0049] Referring to Figure 1 , the display device according to the embodiment may include a display area DPA and a non-display area NDA.

[0050] A plurality of pixels PX1, PX2, PX3 may be provided in the display area DPA.

[0051] For ease of explanation, in Figure 1 , only some pixels are briefly shown.

[0052] Each pixel PX may include a transistor and a light-emitting device connected thereto.

[0053] The light-emitting device may include a first electrode, a light-emitting layer, and a second electrode.

[0054] For ease of explanation, Figure 1 the second electrode 270 is shown in

[0055] The specific structure of the pixel PX including the light-emitting device in the display area DPA will be described separately later in Figure 8 this document.

[0056] The external common voltage line 7410 may be disposed in the non-display area NDA.

[0057] The external common voltage line 7410 may be formed to surround the display area DPA.

[0058] The external common voltage lines 7410 may be spaced apart from each other and not connected to one side surface of the display area DPA.

[0059] The external common voltage line 7410 may transmit the common voltage ELVSS to the second electrode 270 of the pixel PX.

[0060] The common voltage line 740 connected to the external common voltage line 7410 may be disposed in the display area DPA.

[0061] The common voltage line 740 may be disposed along the first direction DR1 and connect the external common voltage lines 7410 to each other.

[0062] The common voltage line 740 may be disposed in the same layer as the source electrode and the drain electrode in the display area DPA.

[0063] When the external common voltage line 7410 is connected to the common voltage line 740 in this way, the problem of voltage drop during the transmission of the common voltage ELVSS can be solved.

[0064] That is, when the external common voltage line 7410 is disposed to surround the edge of the display area DPA, voltage drop may occur while transmitting the common voltage ELVSS along the external common voltage line 7410.

[0065] However, when the external common voltage line 7410 is connected to the common voltage line 740 disposed in the display area DPA, the voltage transmission path is shortened, thereby preventing the reduction of the common voltage ELVSS.

[0066] The common voltage ELVSS is transmitted to the second electrode 270.

[0067] Although not shown in Figure 1 this document, the display device may further include a driving voltage line for transmitting a driving voltage.

[0068] The external driving voltage line can be disposed in the non-display area NDA, and the driving voltage line disposed in the display area DPA can be connected to the external driving voltage line disposed in the non-display area NDA.

[0069] The driving voltage can be transmitted to each pixel PX of the display device through these driving voltage lines.

[0070] Referring to Figure 1 , the second electrode 270 can be provided.

[0071] The second electrode 270 can be provided in both the display area DPA and the non-display area NDA.

[0072] The second electrode 270 can receive the common voltage ELVSS by contacting the external common voltage line 7410 in the non-display area NDA.

[0073] In Figure 1 , the external common voltage line 7410 and the second electrode 270 can be in contact with each other in the area where they overlap, and the common voltage ELVSS can be transmitted to the second electrode 270.

[0074] In addition, the second electrode 270 can receive the common voltage ELVSS by contacting the common voltage line 740 in the display area DPA.

[0075] Since the second electrode 270 receives the common voltage ELVSS from both the display area DPA and the non-display area NDA, the voltage drop can be minimized during the voltage transmission process, and the common voltage ELVSS can be well transmitted to the second electrode 270.

[0076] Although Figure 1 only shows a part of the common voltage line 740, the common voltage line 740 can be provided in various numbers according to the embodiment.

[0077] As Figure 1 shown, the common voltage line 740 can be in contact with the second electrode 270 in only some pixels PX, or the common voltage line 740 can be in contact with the second electrode 270 in each pixel PX.

[0078] However, since space is required in the display device for the common voltage line 740 and the second electrode 270 to contact each other, the common voltage line 740 can be in contact with the second electrode 270 in only some pixels PX.

[0079] Hereinafter, the structure of the common voltage line 740 disposed in the display area DPA will be described in detail with reference to the drawings.

[0080] Figure 2 A cross-section of the common voltage line according to the present embodiment is shown.

[0081] In Figure 2 Figure 2 , for ease of explanation, only the structures of the base 110, the dam 900, the light-emitting layer 360, and the second electrode 270 are shown.

[0082] The specific stacked structure will be described later.

[0083] As Figure 2 Figure 2 shows, the common voltage line 740 may have a three-layer structure including a first layer 741, a second layer 742, and a third layer 743.

[0084] At this time, as Figure 2 Figure 2 shows, the second layer 742 may be disposed between the first layer 741 and the third layer 743.

[0085] The first layer 741 is disposed along the opening of the dam 900 and the side surface of the dam 900, and may include a planar portion 741A and a non-planar portion 741B.

[0086] The non-planar portion 741B may be disposed at the edge of the first layer 741, and the planar portion 741A may be disposed at the center of the first layer 741.

[0087] As Figure 2 Figure 2 shows, the planar portion 741A (sometimes referred to as the flat portion 741A) of the first layer 741 is formed at the opening of the dam 900, and the non-planar portion 741B of the first layer 741 is formed on the dam 900.

[0088] Since the dam 900 has a curved surface, the non-planar portion 741B of the first layer 741 disposed on the dam 900 may also be formed as a curved surface.

[0089] That is, the shape of the non-planar portion 741B of the first layer 741 may vary according to the shape of the side surface of the dam 900.

[0090] As Figure 2 Figure 2 shows, the planar portion 741A of the first layer 741 may be disposed closer to the base 110 than the non-planar portion 741B.

[0091] In Figure 2 Figure 2 , the thickness T1 of the dam 900 in the third direction DR3 may be 3000 Å to 5000 Å.

[0092] The height difference between the planar portion 741A and the non-planar portion 741B of the first layer 741 may also be 3000 Å to 5000 Å.

[0093] The third layer 743 may include a planar portion 743A and a non-planar portion 743B.

[0094] As Figure 2As shown, the planar portion 743A can be the portion in direct contact with the second layer 742, and the non-planar portion 743B can be the portion not in direct contact with the second layer 742.

[0095] The planar portion 743A of the third layer 743 can be disposed at the center of the third layer 743, and the non-planar portion 743B can be disposed at the edge of the third layer 743.

[0096] As Figure 2 shown, the planar portion 743A of the third layer 743 can be disposed closer to the substrate 110 than the non-planar portion 743B.

[0097] The second layer 742 can be disposed between the first layer 741 and the third layer 743.

[0098] The second layer 742 can have a structure in which the width in the second direction DR2 increases toward the center.

[0099] That is, as Figure 2 shown, the center width H2 of the second layer 742 can be greater than the width H1 of the lower surface and the width H3 of the upper surface.

[0100] At this time, the width H1 of the lower surface and the width H3 of the upper surface can be the same or different.

[0101] As Figure 2 shown, the center width H2 of the second layer 742 can be 1.1 to 1.5 times the width H1 of the lower surface (i.e., the portion where the second layer 742 and the first layer 741 are in contact).

[0102] If it is less than 1.1 times, it may not be possible to form a sufficient slope, and if it is greater than 1.5 times, the structural stability may be reduced.

[0103] In addition, as Figure 2 shown, the second layer 742 can be spaced apart from the first layer 741 in the second direction DR2.

[0104] That is, the width H1 of the lower surface of the second layer 742 can be narrower than the width F1 of the flat portion 741A of the first layer 741.

[0105] As will be explained later, since the first layer 741 and the second layer 742 are spaced apart (that is, the non-planar portion 741B of the first layer 741 and the side surface of the second layer 742 are spaced apart from each other) and the contact between the second electrode 270 and the common voltage line 740 can even be made on the top surface of the first layer 741, the entire contact area is increased, and stable contact can be achieved.

[0106] At this time, the spacing region D1 between the first layer 741 and the second layer 742 (i.e., between the non-planar portion 741B of the first layer 741 and the side surface of the second layer 742) may have a length of 200 nm to 300 nm.

[0107] As described above, this is the spacing region for the contact between the second electrode 270 and the common voltage line 740 on the top surface of the first layer 741.

[0108] If the spacing region D1 has a length less than 200 nm, there may not be enough space for the contact between the first layer 741 and the second electrode 270. If the spacing region D1 has a length greater than 300 nm, the light-emitting layer 360 is formed without interruption such that the second electrode 270 and the common voltage line 740 do not contact each other.

[0109] In addition, as Figure 2 shown, the side surface of the second layer 742 may form an inclined surface.

[0110] This is because the width of the second layer 742 becomes wider toward the center of the second layer 742 and an inclined surface is formed on the side surface of the second layer 742.

[0111] At this time, the angle θ1 formed between the side surface of the second layer 742 and the flat portion 741A of the first layer 741 (or the top surface of the substrate 110) may be 20 degrees or greater and 50 degrees or less.

[0112] Generally, the angle for depositing the light-emitting layer 360 is 50 to 60 degrees. Therefore, the angle θ1 formed between the side surface of the second layer 742 and the flat portion 741A of the first layer 741 is 50 degrees or less.

[0113] When the angle θ1 formed by the side surface of the second layer 742 and the flat portion 741A of the first layer 741 is 50 degrees or less, the light-emitting layer 360 is formed as disconnected in this region, and the contact between the second electrode 270 and the common voltage line 740 can be made in this region.

[0114] However, if the angle θ1 formed by the flat portion 741A of the first layer 741 and the side surface of the second layer 742 is less than 20 degrees, the deposition of the second electrode 270 may be difficult, which is not desirable.

[0115] In this embodiment, among the first layer 741, the second layer 742, and the third layer 743, the second layer 742 may be the thickest and the third layer 743 may be the thinnest.

[0116] For example, the thickness T3 of the first layer 741 may be 500 Å to 1000 Å.

[0117] In addition, the thickness T4 of the third layer 743 may be from 100 Å to 500 Å.

[0118] The thickness T2 of the second layer 742 may be from 6000 Å to 10000 Å.

[0119] The thickness T2 of the second layer 742 may be greater than the sum of the thickness T3 of the first layer 741 and the thickness T4 of the third layer.

[0120] If the thickness T3 of the first layer 741 is less than 500 Å, the non-planar portion 741B will not have sufficient durability and may bend or fold. If it is greater than 1000 Å, the first layer 741 will become thick, and the non-planar portion 741B of the first layer 741 may not be able to maintain its shape.

[0121] Similarly, if the thickness T4 of the third layer 743 is less than 100 Å, the non-planar portion 743A will not have sufficient durability and may bend or fold. And if it is greater than 500 Å, the third layer 743 will become thick, and the non-planar portion 743B of the third layer 743 may not be able to maintain its shape and may be stretched.

[0122] Since the third layer 743 is disposed above the first layer 741, the thickness of the third layer 743 is appropriately less than the thickness of the first layer 741.

[0123] In this embodiment, the thickness T2 of the second layer 742 may be greater than the thickness T1 of the dam 900.

[0124] This is the condition for forming the shape of the common voltage line 740 as shown in Figure 2 during the manufacturing process. If the thickness T2 of the second layer 742 is less than the thickness T1 of the dam 900, the undercut structure and the spacer structure will not be formed.

[0125] That is to say, if the thickness of the second layer 742 is less than 6000 Å, it may be difficult to form the common voltage line 740 having the shape as shown in Figure 2 If the thickness of the second layer 742 is greater than 10000 Å, the thickness of the common voltage line 740 will become too large, which is not desirable.

[0126] In this embodiment, the first layer 741, the second layer 742, and the third layer 743 may each include one or more of Al, Cu, Ti, and their alloys.

[0127] The second layer 742 may include a material different from that of the first layer 741 and the third layer 743.

[0128] The second layer 742 may include a material that is easier to etch than the first layer 741 and the third layer 743.

[0129] The first layer 741 and the third layer 743 may include different materials or the same material.

[0130] For example, the first layer 741 and the third layer 743 may include Ti, and the second layer 742 may include Al.

[0131] However, this is only an example, and the inventive concept is not limited thereto.

[0132] That is, as Figure 2 shown, the common voltage line 740 according to the present embodiment has a structure in which the first layer 741 and the third layer 743 include a planar portion and a non-planar portion. In addition, the second layer 742 has a structure in which an undercut is formed with respect to the first layer 741 and the third layer 743, a structure in which the width of the second layer 742 increases toward the center, and a structure in which a gap space exists between the second layer 742 and the first layer 741.

[0133] With this structure, the contact area between the common voltage line 740 and the second electrode 270 can be increased to maintain stable contact.

[0134] As Figure 2 shown, the second electrode 270 contacts the upper surface of the first layer 741 of the common voltage line 740 and the spaced-apart region where the first layer 741 and the second layer 742 are spaced apart.

[0135] In addition, the second electrode 270 contacts the common voltage line 740 on the side surface of the second layer 742.

[0136] At this time, as Figure 2 shown, based on the thickest portion of the second layer 742, the second electrode 270 may contact the common voltage line 740 on the lower portion of the second layer 742.

[0137] As Figure 2 shown, the light-emitting layer 360 is disposed on the side surface of the second layer 742 above the thickest portion of the second layer 742 disposed at the center, which results in a reduction in the contact between the second layer 742 and the second electrode 270.

[0138] Figure 3 Shows a common voltage line according to an embodiment.

[0139] Referring to Figure 3 , the common voltage line 740 according to the present embodiment includes a first layer 741, a second layer 742, and a third layer 743.

[0140] Figure 3 The embodiment of

[0141] However, Figure 3The embodiment of Figure 2 has a slightly different structure because it does not include the structure in which the first layer 741 and the third layer 743 include planar and non-planar portions, the structure in which the central portion of the second layer 742 protrudes, and the structure in which the spacer region is provided between the first layer 741 and the second layer 742.

[0142] Referring to Figure 3 , in the embodiment of Figure 3 , the contact area between the common voltage line 740 and the second electrode 270 is very small.

[0143] That is, as shown by the circle in Figure 3 , the second electrode 270 contacts the common voltage line 740 only on a part of the side surface of the second layer 742 of the common voltage line 740. When the contact area is narrow, the contact resistance increases, which is not desirable.

[0144] However, in the case of the display device according to the present embodiment, the common voltage line 740 has the shape shown in Figure 2 such that the second electrode 270 contacts the upper surface of the first layer 741, and the upper surface and the side surface of the second layer 742 provided in the spacer region between the first layer 741 and the second layer 742 are extended.

[0145] Therefore, the contact resistance can be reduced and stable contact can be achieved.

[0146] The manufacturing method of the common voltage line 740 according to the present embodiment will be described below with reference to Figures 4 to 7 .

[0147] Figures 4 to 7 shows the manufacturing process of the common voltage line according to the embodiment of Figure 2 .

[0148] Referring to Figure 4 , a dam 900 is formed on the substrate 110, and a common voltage line 740 including a first layer 741, a second layer 742, and a third layer 743 is formed on the dam 900.

[0149] For ease of explanation, Figures 4 to 7 shows the dam 900 directly provided on the substrate 110, but the embodiment includes a transistor provided on the substrate 110 and an insulating layer covering the transistor, and the dam 900 can be formed on the top of the insulating layer.

[0150] The dam 900 may include an inorganic material.

[0151] For example, the dam 900 may include one or more of SiO2, SiN x and SiON.

[0152] In other embodiments, the dam 900 may be a composite material including an organic material and an inorganic material.

[0153] The thickness T1 of the dam 900 may be from 3000 Å to 5000 Å.

[0154] As Figure 4 shown, the dam 900 may include an opening 910.

[0155] The side surface of the dam 900 adjacent to the opening 910 may be curved.

[0156] The first layer 741, the second layer 742, and the third layer 743 may be formed on the dam 900 and in the opening 910 of the dam 900.

[0157] The thickness T3 of the first layer 741 may be from 500 Å to 1000 Å.

[0158] In addition, the thickness T4 of the third layer 743 may be from 100 Å to 500 Å.

[0159] The thickness T2 of the second layer 742 may be from 6000 Å to 10000 Å.

[0160] The first layer 741, the second layer 742, and the third layer 743 may each include one or more of Al, Cu, Ti, and their alloys.

[0161] The second layer 742 may include a material different from that of the first layer 741 and the third layer 743.

[0162] For example, the first layer 741 and the third layer 743 may include Ti, and the second layer 742 may include Al.

[0163] As Figure 4 shown, the first layer 741 is disposed above both the dam 900 and the opening 910 of the dam 900.

[0164] Therefore, according to the height of the dam 900, a step difference is formed in the first layer 741.

[0165] As described above, the first layer 741 disposed at the opening 910 of the dam 900 may constitute a planar portion, and the first layer 741 disposed above the dam 900 may constitute a non-planar portion.

[0166] Similarly, due to the level difference between the first layer 741 disposed below and the second layer 742, the third layer 743 also has a step difference, and the third layer 743 includes a planar portion and a non-planar portion.

[0167] In the first layer 741 and the third layer 743, the non-planar portion may be disposed farther from the substrate 110 than the planar portion.

[0168] Refer to Figure 5 and etch the first layer 741, the second layer 742, and the third layer 743.

[0169] The etching at this time can be carried out by dry etching.

[0170] In this etching, the edges of the first layer 741, the second layer 742, and the third layer 743 can be set on the same line, wherein the etching of the first layer 741, the second layer 742, and the third layer 743 can be such that the first layer 741 covers the curved side surface of the dam 900.

[0171] That is to say, in this step, the curved side surface of the dam 900 can not be exposed during the etching.

[0172] Refer to Figure 6 and selectively etch the second layer 742.

[0173] That is to say, in the Figure 5 etching, the first layer 741, the second layer 742, and the third layer 743 are etched equally, and in the Figure 6 etching, the second layer 742 is selectively etched.

[0174] The etching in this step can be wet etching.

[0175] Through this etching, as shown in Figure 6 , an undercut structure of the second layer 742 and an interval region between the second layer 742 and the first layer 741 are formed.

[0176] That is to say, as shown in Figure 6 , the width H1 of the second layer 742 in the second direction DR2 is narrower than the width F1 of the flat portion 741A of the first layer 741.

[0177] Therefore, an interval region is formed between the second layer 742 and the first layer 741.

[0178] In addition, the central width H2 of the second layer 742 can be greater than the width H1 of the lower surface and the width H3 of the upper surface.

[0179] That is to say, the second layer 742 can have a structure in which the central part is the widest.

[0180] The shape of the second layer 742 of the common voltage line 740 formed in the Figure 6 etching process can be formed by adjusting the wet etching time.

[0181] That is to say, the shape of the second layer 742 of the common voltage line 740 according to this embodiment can be formed by adjusting the wet etching time without any additional process.

[0182] Reference Figure 7 , forming a light emitting layer 360 and a second electrode 270.

[0183] At this time, the angle at which the light emitting layer 360 is deposited and the angle at which the second electrode 270 is formed may be different.

[0184] like Figure 7 As shown in FIG. 5 , the angle θ2 at which the light emitting layer 360 is deposited may be different from the angle θ3 at which the second electrode 270 is deposited.

[0185] That is, the angle θ3 at which the second electrode 270 is deposited may be smaller than the angle θ2 at which the light emitting layer 360 is deposited.

[0186] Therefore, if Figure 7 As shown in , the light emitting layer 360 may not be formed in the space between the first layer 741 and the second layer 742 .

[0187] Furthermore, the light emitting layer 360 may be formed over the thickest central portion of the second layer 742 .

[0188] The second electrode 270 may be formed at a different angle from the light emitting layer 360 , so that the second electrode 270 may be formed in a spaced region between the first layer 741 and the second layer 742 .

[0189] Therefore, if Figure 7 As shown in , the second electrode 270 may be in direct contact with the upper surface of the first layer 741 .

[0190] In addition, the second electrode 270 is formed on the side of the second layer 742 where the light emitting layer 360 is not formed, so that the second layer 742 and the second electrode 270 can be in direct contact.

[0191] Therefore, if Figure 7 As shown in , the common voltage line 740 according to the present embodiment may contact the second electrode 270 over a large area, and the contact between the second electrode 270 and the common voltage line 740 may be stably established.

[0192] Therefore, since the second electrode 270 receives the common voltage from the display area DPA and the non-display area NDA, a voltage drop is minimized in a voltage transfer process and the common voltage is well transferred to the second electrode 270 .

[0193] A pixel of a display device including the common voltage line 740 according to the present embodiment will be described below.

[0194] Figure 8 A cross section of a pixel of the display device according to the present embodiment is briefly shown.

[0195] Reference Figure 8 , a substrate SUB is provided.

[0196] The substrate SUB may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0197] The substrate SUB may be a rigid substrate or a flexible substrate capable of being bent, folded, curled, etc.

[0198] The substrate SUB may have a single-layer or multi-layer structure.

[0199] The substrate SUB may be alternately laminated with at least one matrix layer and at least one inorganic layer, and the at least one matrix layer includes polymer resins laminated in sequence.

[0200] The light blocking layer BML may be provided on the substrate SUB.

[0201] The light blocking layer BML may include aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu) and metal oxides, and may have a single-layer or multi-layer structure including these.

[0202] The buffer layer BUF may be provided on the light blocking layer BML.

[0203] The buffer layer BUF may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), and amorphous silicon (Si).

[0204] The buffer layer BUF may include a first opening OP1 that overlaps with the light blocking layer BML and extends into the light blocking layer BML.

[0205] The source electrode SE may be connected to the light blocking layer BML at the first opening OP1.

[0206] The semiconductor layer ACT may include a channel region CA that overlaps with the gate electrode GE and source regions SA and drain regions DA provided on both sides of the channel region.

[0207] The gate insulating layer GI is provided on the semiconductor layer ACT.

[0208] The gate insulating layer GI may include silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y), and may have a single-layer or multi-layer structure including these.

[0209] The gate insulating layer GI may be provided to overlap with the channel region CA of the semiconductor layer ACT.

[0210] The gate conductive layer including the gate electrode GE may be provided on the gate insulating layer GI.

[0211] The gate conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and metal oxides, and may have a single-layer or multi-layer structure including these.

[0212] The gate electrode GE is formed in the same process as the gate insulating layer GI and may have the same planar shape.

[0213] However, this is only an example, and the planar shapes of the gate insulating layer GI and the gate electrode GE may be different.

[0214] The gate electrode GE may be provided to overlap with the semiconductor layer ACT and the substrate SUB in a direction perpendicular to the surface.

[0215] The interlayer insulating layer ILD may be provided on the semiconductor layer ACT and the gate electrode GE.

[0216] The interlayer insulating layer ILD may include silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiO x N y ), and may have a single-layer or multi-layer structure including these.

[0217] When the interlayer insulating layer ILD has a multi-layer structure including silicon nitride and silicon oxide, the layer including silicon nitride may be provided closer to the substrate SUB than the layer including silicon oxide.

[0218] The interlayer insulating layer ILD may have a first opening OP1 extending to and overlapping with the light blocking layer BML, a second opening OP2 extending to and overlapping with the source region SA of the semiconductor layer ACT, and a third opening OP3 extending to and overlapping with the drain region DA of the semiconductor layer ACT.

[0219] The data conductive layer including the source electrode SE, the drain electrode DE, and the common voltage line 740 may be provided on the interlayer insulating layer ILD.

[0220] The data conductive layer can be made of aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), as well as metal oxides, and can have a single-layer or multi-layer structure including these.

[0221] Referring Figure 8 , the common voltage line 740 can have a three-layer structure including a first layer 741, a second layer 742, and a third layer 743.

[0222] Since each layer of the common voltage line 740 is the same as previously described, the description of each layer of the common voltage line 740 is omitted.

[0223] Referring Figure 8 , the dam 900 is disposed on the interlayer insulating layer ILD.

[0224] At this time, the dam 900 can be disposed adjacent to the common voltage line 740.

[0225] As Figure 8 shown, the dam 900 includes an opening 910, and the common voltage line 740 can be disposed in the dam 900 and the opening 910 of the dam 900.

[0226] Since the dam 900 is the same as previously described, the description of the dam 900 is also omitted.

[0227] The source electrode SE can contact the light-blocking layer BML at the first opening OP1 and can contact the source region SA of the semiconductor layer ACT at the second opening OP2.

[0228] The drain electrode DE can contact the drain region DA of the semiconductor layer ACT at the third opening OP3.

[0229] The source electrode SE and the drain electrode DE can be formed by the same process as the common voltage line 740 and can have the same stacked structure.

[0230] That is to say, the source electrode SE and the drain electrode DE can have a three-layer structure including a first layer 741, a second layer 742, and a third layer 743.

[0231] However, since the formation of the source electrode SE and the drain electrode DE does not include the selective etching process of the second layer 742 of the common voltage line 740, the first layer 741, the second layer 742, and the third layer 743 of the source electrode SE and the drain electrode DE can have the same shape.

[0232] The insulating layer VIA can be disposed on the data conductive layer.

[0233] The insulating layer VIA may include common polymers such as polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, polyimides, silicone polymers, and the like.

[0234] The insulating layer VIA may include a fourth opening OP4 extending to and overlapping with the source electrode SE and a fifth opening OP5 overlapping with the common voltage line 740 and in which the common voltage line 740 is formed.

[0235] The first electrode 191 may be disposed on the insulating layer VIA.

[0236] The separator 350 may be disposed on the insulating layer VIA and the first electrode 191.

[0237] The separator 350 may have an opening 355 extending to and overlapping with the first electrode 191 and an opening 356 overlapping with the fifth opening OP5.

[0238] The light-emitting layer 360 may be disposed on the first electrode 191 and the separator 350.

[0239] The second electrode 270 may be disposed on the light-emitting layer 360.

[0240] The first electrode 191, the light-emitting layer 360, and the second electrode 270 may form a light-emitting device LED.

[0241] As Figure 8 shown by part B, the second electrode 270 and the common voltage line 740 are in contact at the fifth opening OP5, and the common voltage is transmitted to the second electrode 270.

[0242] The contact form between the second electrode 270 and the common voltage line 740 in part B is as Figure 2 shown.

[0243] A detailed description of the same components is omitted.

[0244] Hereinafter, the planar layout of the display device according to the embodiment will be described with reference to the drawings.

[0245] Figure 9 is a plan view of the display device according to the present embodiment.

[0246] Figures 10 to 18 The display device is shown for each layer Figure 9 .

[0247] Hereinafter, with reference to Figure 9 and Figures 10 to 18 the planar structure of the display device according to the present embodiment will be described.

[0248] Figure 9 The display device shown shows Figures 10 to 18 the structure.

[0249] Referring to Figure 9 and Figure 10 , a light-blocking layer BML and a semiconductor layer ACT are provided on a substrate.

[0250] As Figure 10 shown, the semiconductor layer ACT constitutes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7.

[0251] Although not shown, a buffer layer may be provided between the light-blocking layer BML and the semiconductor layer ACT.

[0252] Referring to Figure 9 and Figure 11 , a first insulating layer IL1 is provided on the semiconductor layer ACT.

[0253] The first insulating layer may include a plurality of openings OP.

[0254] Referring to Figure 9 and Figure 12 , a first gate conductive layer GAT1 is provided on the semiconductor layer ACT.

[0255] The first gate conductive layer GAT1 may include a plurality of signal lines arranged along a second direction DR2.

[0256] Specifically, the first gate conductive layer GAT1 may include a first initialization voltage line VINT1, a first scan line GI, a second scan line GW, an emission control line EM, a bypass control line GB, a second initialization voltage line VINT2, and a first storage electrode E1.

[0257] Referring to Figure 9 and Figure 13 , a second gate conductive layer GAT2 is provided on the first gate conductive layer GAT1.

[0258] Although not shown, a second insulating layer may be provided between the second gate conductive layer GAT2 and the first gate conductive layer GAT1 to insulate them from each other.

[0259] Referring to Figure 13 , the second gate conductive layer GAT2 includes a second storage electrode E2 and a third storage electrode E3.

[0260] The second storage electrode E2 may include an opening EOP.

[0261] The first storage electrode E1 of the first gate conductive layer GAT1 and the second storage electrode E2 of the second gate conductive layer GAT2 may form a storage capacitor.

[0262] In addition, a third storage electrode E3 of the second gate conductive layer GAT2 can form a capacitor with the first gate conductive layer GAT1.

[0263] Referring to Figure 9 and Figure 14 , a dam 900 is provided on the second gate conductive layer GAT2.

[0264] This can have the same structure as the dam 900 described above.

[0265] Figure 9 and Figure 14 show the dam 900 and the opening 910 of the dam 900.

[0266] That is, the opening 910 of the dam 900 can be formed in the region where the common voltage line 740 and the second electrode are in contact.

[0267] Referring to Figure 15 , a third insulating layer IL3 can be provided.

[0268] The third insulating layer IL3 can include a plurality of openings OP.

[0269] Referring to Figure 9 and Figure 16 , a data conductive layer DAT is provided.

[0270] The data conductive layer DAT can include a plurality of signal lines arranged along a first direction DR1. The signal lines can include data lines 171, drive voltage lines 172, and a common voltage line 740.

[0271] In Figure 16 , the region where contact occurs between the common voltage line 740 and the second electrode (i.e., the part where the cross-section of the common voltage line 740 of the above inventive concept is provided) is indicated by A.

[0272] Referring to Figure 9 and Figure 17 , a fourth insulating layer IL4 can be provided on the data conductive layer DAT.

[0273] The fourth insulating layer IL4 can have a structure corresponding to the previously described insulating layer VIA.

[0274] The fourth insulating layer IL4 can include a plurality of openings.

[0275] At this time, the openings can include a fourth opening OP4 and a fifth opening OP5 of the previously described insulating layer VIA.

[0276] That is, the fifth opening OP5 is arranged to overlap with the common voltage line 740, and then the common voltage line 740 and the second electrode are brought into contact.

[0277] Referring toFigure 18 , the first electrode 191 and the auxiliary electrode 193 are disposed on the fourth insulating layer IL4.

[0278] The first electrode 191 may be disposed corresponding to each light-emitting device LED, and the auxiliary electrode 193 may be disposed to overlap with the common voltage line 740.

[0279] However, the auxiliary electrode 193 may be omitted.

[0280] Although not shown hereinafter, the light-emitting layer may be disposed on the first electrode 191, and the second electrode may be disposed on the light-emitting layer.

[0281] As previously in Figures 2 to 8 described, the common voltage line 740 and the second electrode may be in the area indicated by Figure 16 A in contact.

[0282] However, the above planar structure is merely an example, and the inventive concept is not limited thereto.

[0283] The inventive concept may be applied to various planar pixel arrangements as long as the common voltage line 740 and the second electrode 270 are in contact with each other as shown in Figure 2 .

[0284] As described above, the common voltage line 740 according to the present embodiment has a structure in which the first layer 741 and the third layer 743 include a planar portion and a non-planar portion, a structure in which the second layer 742 has an undercut with respect to the first layer 741 and the third layer 743, a structure in which the width of the second layer 742 becomes larger toward the center, and a structure in which there is a gap region between the second layer 742 and the first layer 741. With this structure, the contact area between the common voltage line 740 and the second electrode 270 can be increased, so that the common voltage line 740 and the second electrode 270 can be stably in contact.

[0285] Although the embodiments have been described in detail above, the scope of the inventive concept is not limited thereto, and those skilled in the art can make various modifications and improvements using the basic concepts of the inventive concept defined in the claims.

Claims

1. A display device, the display device comprising: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a common voltage line disposed in the display area and connected to the external common voltage line; a dam disposed between the substrate and the common voltage line and including an opening; and a plurality of pixels disposed in the display area and including a first electrode, a light-emitting layer, and a second electrode, wherein the common voltage line has a multilayer structure including a first layer, a second layer, and a third layer, and the first layer includes a planar portion disposed at the opening of the dam and a non-planar portion disposed to overlap the dam.

2. The display device according to claim 1, wherein: the second electrode is in direct contact with the top surface of the first layer and the side surface of the second layer.

3. The display device according to claim 1, wherein: the planar portion of the first layer is disposed closer to the substrate than the non-planar portion.

4. The display device according to claim 1, wherein: the dam has a thickness of 3000 Å to 5000 Å.

5. The display device according to claim 1, wherein: the second layer has a shape that widens toward the center of the second layer.

6. The display device according to claim 1, wherein: the width of the widest portion of the second layer is 1.1 times to 1.5 times the width of the portion of the second layer where the second layer and the first layer contact.

7. The display device according to claim 1, wherein: the angle between the side surface of the second layer and the top surface of the substrate is 20 degrees or greater and 50 degrees or less.

8. The display device according to claim 1, wherein: the second layer has a thickness of 6000 Å to 10000 Å.

9. The display device according to claim 1, wherein: the non-planar portion of the first layer and the side surface of the second layer are spaced apart from each other.

10. The display device according to claim 9, wherein: the spaced-apart region between the non-planar portion of the first layer and the side surface of the second layer has a length of 200 nm to 300 nm.

11. The display device according to claim 9, wherein: the second electrode is disposed in the spaced-apart region between the non-planar portion of the first layer and the side surface of the second layer.

12. The display device according to claim 1, wherein: the third layer includes a planar portion and a non-planar portion, and the planar portion of the third layer is disposed closer to the substrate than the non-planar portion of the third layer.

13. The display device according to claim 12, wherein: the planar portion of the third layer is in contact with the second layer.

14. The display device according to claim 1, wherein: the thickness of the second layer is greater than the sum of the thicknesses of the first layer and the third layer.

15. The display device according to claim 1, wherein: the thickness of the second layer is greater than the thickness of the first layer, and the thickness of the first layer is greater than the thickness of the third layer.

16. The display device according to claim 1, wherein: The thickness of the first layer is from 500 Å to 1000 Å, the thickness of the second layer is from 6000 Å to 10000 Å, and the third layer has a thickness of 100 Å to 500 Å.

17. A display device, the display device comprising: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a common voltage line disposed in the display area and connected to the external common voltage line; a dam disposed between the substrate and the common voltage line and including an opening; and a plurality of pixels disposed in the display area and including a first electrode, a light-emitting layer, and a second electrode, wherein the common voltage line has a multi-layer structure including a first layer, a second layer, and a third layer, and the second electrode is in direct contact with the top surface of the first layer and the side surface of the second layer.

18. The display device according to claim 17, wherein: the first layer includes a planar portion and a non-planar portion, the planar portion of the first layer is disposed closer to the substrate than the non-planar portion, and a spacer region is disposed between the non-planar portion of the first layer and the side surface of the second layer.

19. The display device according to claim 18, wherein: the length of the spacer region is from 200 nm to 300 nm.

20. The display device according to claim 17, wherein: the width of the portion of the second layer where the second layer and the first layer are in contact with each other is narrower than the width of the center of the second layer.

Images