Display device

Abstract

Disclosed is a display device. The display device includes: a substrate; a pixel circuit layer on the substrate; an anode electrode on the pixel circuit layer; a pixel defining layer on a portion of the anode electrodes and the pixel circuit layer, and having a recessed shape between the anode electrodes in a direction facing the substrate, where the recessed shape is arranged along a periphery of each of the anode electrodes; a light emitting structure on the anode electrode and the pixel defining layer, and including a plurality of light generating layers; a cathode electrode on the light emitting structure; and a reflective layer overlapping the recessed shape and located between the light emitting structure and the pixel circuit layer.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2024-0003571, filed with the Korean Intellectual Property Office on January 9, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Aspects of some embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0003] As consumers' interest in information display has recently increased, research and development of display devices have been continuously conducted.

[0004] Specifically, since an organic light-emitting diode (OLED) is an active light-emitting display element having advantages such as not only a relatively wide viewing angle and excellent contrast, but also being able to be driven at a relatively low voltage, being light in weight and thin, and having a relatively fast response speed, the organic light-emitting diode (OLED) is attracting attention as a next-generation display element.

[0005] The above information disclosed in this background art section is only for enhancing the understanding of the background art, and thus the information discussed in this background art section does not necessarily constitute the prior art. Summary of the Invention

[0006] Aspects of some embodiments of the present disclosure include a display device having relatively improved reliability. For example, the display device may relatively improve the lateral leakage phenomenon occurring between adjacent sub-pixels by forming or disposing a reflective layer between adjacent sub-pixels in a pixel.

[0007] Aspects of some embodiments of the present disclosure include a method of manufacturing a display device having relatively improved reliability.

[0008] According to some embodiments of the present disclosure, a display device includes: a substrate; a pixel circuit layer on the substrate; an anode electrode on the pixel circuit layer; a pixel defining layer on a part of the anode electrode and the pixel circuit layer, and having a recessed shape disposed along the periphery of each of the anode electrodes in a direction facing the substrate; a light-emitting structure on the anode electrode and the pixel defining layer, and including a plurality of light-generating layers; a cathode electrode on the light-emitting structure; and a reflective layer superposed with the recessed shape and located between the light-emitting structure and the pixel circuit layer.

[0009] According to some embodiments, the reflective layer may be disposed along the periphery of each of the anode electrodes.

[0010] According to some embodiments, the reflective layer may include the same material as the anode electrode.

[0011] According to some embodiments, a sub-groove further recessed from the recessed shape may be between one of the anode electrodes and the reflective layer, and the sub-groove may be disposed along the periphery of the one anode electrode among the anode electrodes.

[0012] According to some embodiments, a first sub-groove further recessed from the recessed shape between one of the anode electrodes and the reflective layer, and a second sub-groove further recessed from the recessed shape between the other of the anode electrodes and the reflective layer may be disposed.

[0013] According to some embodiments, the light-emitting structure may include at least two light-emitting units stacked in sequence and at least one charge generation layer between the at least two light-emitting units. Each of the at least two light-emitting units may include a light-emitting layer, and the at least one charge generation layer may be interrupted in a region overlapping with the recessed shape.

[0014] According to some embodiments, the reflective layer may have a lower surface adjacent to the substrate and an upper surface opposite to the lower surface, and the upper surface of the reflective layer may have a recessed shape in a direction facing the substrate.

[0015] According to some embodiments, the lower surface of the reflective layer may have a recessed shape in a direction facing the substrate.

[0016] According to some embodiments, the reflective layer may include a matrix surface parallel to the substrate and an inclined surface extending from the matrix surface, and each of the inclined surfaces may be inclined at a predetermined angle with respect to the matrix surface.

[0017] According to some embodiments, each of the inclined surfaces may have an angle of 45 degrees or more with respect to the matrix surface.

[0018] According to some embodiments, the reflective layer may have a first width, and the matrix surface has a second width narrower than the first width.

[0019] According to some embodiments, the anode electrode may have a quadrilateral shape or a hexagonal shape in a plan view.

[0020] According to some embodiments of the present disclosure, in a method of manufacturing a display device, the method includes: forming an anode electrode on a substrate; forming a pixel defining layer on a part of the anode electrode and a pixel circuit layer, the pixel defining layer forming a recessed shape in a direction facing the substrate along the periphery of each of the anode electrodes between the anode electrodes; forming a reflective layer overlapping with the recessed shape; forming a light-emitting structure including a plurality of light generation layers on the anode electrode and the pixel defining layer; and forming a cathode electrode on the light-emitting structure, and the reflective layer is located between the light-emitting structure and the pixel circuit layer.

[0021] According to some embodiments, the method may further include: positioning a mask having an opening superposed on the reflective layer on the cathode electrode, and irradiating ultraviolet light through the opening.

[0022] According to some embodiments, the reflective layer may be disposed along the periphery of each of the anode electrodes.

[0023] According to some embodiments, the reflective layer may include the same material as the anode electrode.

[0024] According to some embodiments, the reflective layer may have a lower surface adjacent to the substrate and an upper surface opposite to the lower surface, and the upper surface of the reflective layer may have a concave shape in a direction facing the substrate.

[0025] According to some embodiments, the reflective layer may include a matrix surface parallel to the substrate and inclined surfaces extending from the matrix surface, and each of the inclined surfaces may be inclined at a predetermined angle with respect to the matrix surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of embodiments of the present disclosure will become more apparent by describing aspects of some embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which: Figure 1 is a block diagram showing aspects of a display device disclosed according to some embodiments; Figure 2 is a block diagram showing aspects of Figure 1 a sub-pixel according to some embodiments; Figure 3 is a plan view showing further details of Figure 1 a display panel according to some embodiments; Figure 4 is a perspective exploded view showing Figure 3 a part of the display panel; Figure 5 is a plan view showing further details of Figure 4 a pixel according to some embodiments; Figure 6 is a cross-sectional view taken along Figure 5 line I-I' of Figure 7 is a cross-sectional view showing aspects of a light-emitting structure included in any one of the first to third light-emitting elements included in Figure 6 according to some embodiments; Figure 8 is a cross-sectional view showing further details of a light-emitting structure included in any one of the first to third light-emitting elements included in Figure 6 according to some embodiments; Figure 9 is a view showingFigure 6 An enlarged view of part A; Figure 10 shows aspects of Figure 6 the reflective layer according to some embodiments; Figure 11 and Figure 12 shows further details of a pixel Figure 4 according to some embodiments; Figure 13 shows further details of a pixel Figure 4 according to some embodiments; Figure 14 is a cross-sectional view taken along line II-II' of Figure 13 ; Figure 15 is a flowchart showing aspects of a method of manufacturing a display device according to some embodiments; and Figures 16 to 19 is a cross-sectional view schematically showing a method of manufacturing a display device according to some embodiments. DETAILED DESCRIPTION

[0027] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. It should be noted that, in the following description, only parts necessary for understanding the operations according to the disclosure are described, and descriptions of other parts are omitted so as not to obscure the subject matter of the disclosure. Additionally, the disclosure may be embodied in other forms and is not limited to the embodiments described herein. However, the embodiments described herein are provided to describe in more detail to enable those skilled in the art to implement the technical spirit of the disclosure.

[0028] Throughout the specification, in the case where a part is "connected" to another part, this case includes not only the case where the part is "directly connected" to the other part, but also the case where the part is "indirectly connected" to the other part and another element is disposed between the part and the other part. The terms used herein are for describing specific embodiments and are not intended to limit the disclosure. Throughout the specification, in the case where a specific part "includes" a component, unless otherwise stated, this case means that the part may also include another component without excluding the other component. "At least any one of X, Y, and Z" and "at least any one selected from the group consisting of X, Y, and Z" may be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, and ZZ). Here, "and / or" includes all combinations of one or more of the corresponding configurations.

[0029] Here, terms such as first and second may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Thus, without departing from the scope disclosed herein, the first component may refer to the second component.

[0030] Spatial relative terms such as "below", "above", etc. may be used for descriptive purposes to describe the relationship between one element or feature and another (additional) element or feature as shown in the drawings. In addition to the directions depicted in the drawings, spatial relative terms are intended to include other directions during use, operation, and / or manufacturing. For example, when the device shown in the drawings is inverted, an element depicted as being "below" another element or feature is oriented in the direction of being "above" the other element or feature. Thus, in the present disclosure, the term "below" may include both upward and downward directions. Further, the device may face other directions (e.g., rotated 90 degrees or in other directions), and thus the spatial relative terms used herein are interpreted accordingly.

[0031] Various embodiments are described with reference to the drawings schematically showing ideal embodiments. Thus, it will be appreciated that the shape may vary, for example, according to tolerances and / or manufacturing techniques. Accordingly, the embodiments disclosed herein are not to be construed as limited to the specific shapes shown and should be construed as including, for example, variations in shape due to manufacturing. As described above, the shapes shown in the drawings may not represent the actual shape of the regions of the device, and the present embodiments are not limited thereto.

[0032] Figure 1 is a diagram showing aspects of a display device according to some embodiments.

[0033] Referring to Figure 1 , the display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0034] The display panel 110 may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through the first gate line GL1 to the m-th gate line GLm. The sub-pixels SP may be connected to the data driver 130 through the first data line DL1 to the n-th data line DLn.

[0035] Each of the sub-pixels SP may include at least one light-emitting element configured to generate light. Thus, each of the sub-pixels SP may generate light of a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more of the sub-pixels among the sub-pixels SP may construct a pixel PXL. For example, as Figure 1 shown, three sub-pixels SP may construct a pixel PXL.

[0036] The gate driver 120 can be connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 can output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. According to some embodiments, the gate control signal GCS can include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting the gate signal synchronously with the timing of the applied data signal, and the like.

[0037] According to some embodiments, the first emission control lines EL1 to the m-th emission control lines ELm connected to the sub-pixels SP in the row direction can be further provided. In this case, the gate driver 120 can include an emission control driver configured to control the first emission control lines EL1 to the m-th emission control lines ELm, and the emission control driver can operate under the control of the controller 150.

[0038] The gate driver 120 can be located on one side of the display panel 110. However, the embodiments according to the present disclosure are not limited thereto. For example, the gate driver 120 can be divided into two or more physically and / or logically divided drivers, and such drivers can be located on one side of the display panel 110 and on the other side of the display panel 110 opposite to the one side. As described above, the gate driver 120 can be arranged around the display panel 110 in various shapes according to embodiments.

[0039] The data driver 130 can be connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the n-th data line DLn. The data driver 130 can receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. According to some embodiments, the data control signal DCS can include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0040] The data driver 130 can apply a data signal having a gray voltage corresponding to the image data DATA to the first data line DL1 to the n-th data line DLn using a voltage from the voltage generator 140. When a gate signal is applied to each of the first gate line GL1 to the m-th gate line GLm, the data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLm. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Therefore, an image can be displayed on the display panel 110.

[0041] According to some embodiments, the gate driver 120 and the data driver 130 can include complementary metal oxide semiconductor (CMOS) circuit elements.

[0042] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a plurality of voltages and supply the generated voltages to components of the display device 100. For example, the voltage generator 140 may be configured to generate a plurality of voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0043] The voltage generator 140 may generate a first power voltage VDD and a second power voltage VSS, and the generated first power voltage VDD and second power voltage VSS may be supplied to the sub-pixel SP. The first power voltage VDD may have a relatively high voltage level, and the second power voltage VSS may have a voltage level lower than that of the first power voltage VDD. According to some embodiments, the first power voltage VDD or the second power voltage VSS may be provided by an external device of the display device 100.

[0044] In addition, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixel SP. For example, during a sensing operation for sensing the electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a reference voltage (e.g., a set or predetermined reference voltage) may be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 may generate such a reference voltage.

[0045] The controller 150 may control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0046] The controller 150 may convert the input image data IMG such that the input image data IMG is suitable for the display device 100 or the display panel 110, and output image data DATA. According to some embodiments, the controller 150 may output the image data DATA by aligning the input image data IMG such that the input image data IMG is suitable for the sub-pixels SP of the row unit.

[0047] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. As Figure 1As shown, the data driver 130, the voltage generator 140, and the controller 150 may be included in the driving integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be functionally divided components in a driving integrated circuit DIC. According to some embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component separate from the driving integrated circuit DIC.

[0048] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 may be configured to sense the temperature around the temperature sensor 160 and generate temperature data TEP indicating the sensed temperature. According to some embodiments, the temperature sensor 160 may be positioned adjacent to the display panel 110 and / or the driving integrated circuit DIC.

[0049] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. According to some embodiments, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control the data signal and the first power voltage VDD and the second power voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0050] Figure 2 is a block diagram showing Figure 1 an example of any one of the sub-pixels in. In Figure 2 In, among the sub-pixels SP of Figure 1 as an example, the sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown.

[0051] Referring to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0052] The light-emitting element LD may be connected between the first power voltage node VDDN and the second power voltage node VSSN. At this time, the first power voltage node VDDN may be a node for transmitting Figure 1 the first power voltage VDD, and the second power voltage node VSSN may be a node for transmitting Figure 1 the second power voltage VSS.

[0053] The anode electrode AE of the light-emitting element LD can be connected to the first power voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD can be connected to the second power voltage node VSSN. For example, the anode electrode AE of the light-emitting element LD can be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0054] The sub-pixel circuit SPC can be connected to Figure 1 the i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm of Figure 1 the i-th emission control line ELi among the first emission control line EL1 to the m-th emission control line ELm of Figure 1 and the j-th data line DLj among the first data line DL1 to the n-th data line DLn of. The sub-pixel circuit SPC can be configured to control the light-emitting element LD according to the signals received through such signal lines.

[0055] The sub-pixel circuit SPC can operate in response to the gate signal received through the i-th gate line GLi. The i-th gate line GLi can include one or more sub-gate lines. According to some embodiments, as Figure 2 shown in, the i-th gate line GLi can include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. As described above, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to the gate signals received through the corresponding sub-gate lines.

[0056] The sub-pixel circuit SPC can operate in response to the emission control signal received through the i-th emission control line ELi. According to some embodiments, the i-th emission control line ELi can include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC can operate in response to the emission control signals received through the corresponding sub-emission control lines.

[0057] The sub-pixel circuit SPC can receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 or the second sub-gate line SGL2. The sub-pixel circuit SPC can adjust the current flowing from the first power voltage node VDDN to the second power voltage node VSSN through the light-emitting element LD according to the stored voltage in response to the emission control signal received through the i-th emission control line ELi. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0058] Figure 3 is a plan view showing further details of a display panel according to some embodiments Figure 1 .

[0059] Referring Figure 3 , according to some embodiments, Figure 1 the display panel 110 may include a display area DA and a non-display area NDA. The display panel 110 may display an image through the display area DA. The non-display area NDA may be arranged around the display area DA (e.g., in the periphery of the display area DA or outside the coverage area of the display area DA).

[0060] The display panel 110 may include a substrate SUB, sub-pixels SP, and pads (also referred to as "bonding pads", "landing pads") PD.

[0061] When the display panel 110 is used as a display screen of a head-mounted display (HMD), virtual reality (VR) device, mixed reality (MR) device, or augmented reality (AR) device, etc., the display panel 110 may be positioned very close to the user's eyes. In this case, a relatively high integration degree of sub-pixels SP may be required. To increase the integration degree of sub-pixels SP, the substrate SUB may be set as a silicon substrate. The sub-pixels SP and / or the display panel 110 may be formed on the substrate SUB that is a silicon substrate. The display device 100 including the display panel 110 formed on the substrate SUB that is a silicon substrate (referring to Figure 1 ) may be referred to as an OLED on silicon (OLEDoS) display device.

[0062] The sub-pixels SP may be located in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments according to the present disclosure are not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag form along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a PENTILE ® form. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0063] Two or more of the plurality of sub-pixels SP may construct a pixel PXL.

[0064] Components for controlling the sub-pixels SP may be located in the non-display area NDA on the substrate SUB. For example, lines connected to the sub-pixels SP (such as Figure 1 the first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn) may be located in the non-display area NDA.

[0065] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 may be integrated in the non-display area NDA of the display panel 110. According to some embodiments, Figure 1 the gate driver 120 may be mounted on the display panel 110 and may be located in the non-display area NDA. According to some embodiments, the gate driver 120 may be implemented as an integrated circuit separated from the display panel 110. According to some embodiments, the temperature sensor 160 may be located in the non-display area NDA to sense the temperature of the display panel 110.

[0066] The pad PD may be located in the non-display area NDA on the substrate SUB. The pad PD may be electrically connected to the sub-pixel SP through a line. For example, the pad PD may be connected to the sub-pixel SP through the first data line DL1 to the nth data line DLn.

[0067] The pad PD may bond the display panel 110 to other components of the display device 100 (refer to Figure 1 )). According to some embodiments, the voltage and signals required for the operation of the components included in the display panel 110 may be provided from Figure 1 the driving integrated circuit DIC through the pad PD. For example, the first data line DL1 to the nth data line DLn may be connected to the driving integrated circuit DIC through the pad PD. For example, the first power voltage VDD and the second power voltage VSS may be received from the driving integrated circuit DIC through the pad PD. For example, when the gate driver 120 is mounted on the display panel 110, the gate control signal GCS may be transmitted from the driving integrated circuit DIC to the gate driver 120 through the pad PD.

[0068] According to some embodiments, the circuit board may be electrically connected to the pad PD using a conductive bonding member such as an anisotropic conductive film. At this time, the circuit board may be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. The driving integrated circuit DIC may be mounted on the circuit board to be electrically connected to the pad PD.

[0069] According to some embodiments, the display area DA may have various shapes. The display area DA may have a closed-loop shape including straight edges and / or curved edges. For example, the display area DA may have shapes such as a polygon, a circle, a semi-circle, and an ellipse.

[0070] According to some embodiments, the display panel 110 may have a flat display surface. According to some embodiments, the display surface of the display panel 110 may be at least partially rounded. According to some embodiments, the display panel 110 may be bendable, foldable, or rollable. In these cases, the display panel 110 and / or the substrate SUB may include materials having flexible characteristics.

[0071] Figure 4 is an exploded perspective view showing Figure 3 a part of the display panel. In Figure 4 for clarity and concise description, a part of the display panel 110 corresponding to Figure 3 two of the pixels PXL1 and PXL2 among the pixels PXL of

[0072] is schematically shown. The part of the display panel 110 corresponding to the remaining pixels may be configured similarly. Figure 3 and Figure 4 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel to a third sub-pixel SP1, SP2, and SP3. However, the embodiments are not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0073] In Figure 4 when viewed from a third direction DR3 intersecting the first direction DR1 and the second direction DR2, the first sub-pixel to the third sub-pixel SP1, SP2, and SP3 have a quadrilateral shape and have equal dimensions to each other. However, the embodiments according to the present disclosure are not limited thereto. The first sub-pixel to the third sub-pixel SP1, SP2, and SP3 may be modified to have various shapes.

[0074] The display panel 110 may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a packaging layer TFE, an optical function layer OFL, an outer coating OC, and a cover window CW.

[0075] According to some embodiments, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer, etc. According to some embodiments, the substrate SUB may include a glass substrate. In still other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0076] The pixel circuit layer PCL may be located on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and conductive patterns located between the insulating layers. The conductive patterns of the pixel circuit layer PCL may be used as at least a part of circuit elements, lines, etc. The conductive patterns may include copper, but are not limited thereto according to embodiments of the present disclosure.

[0077] The circuit elements may include sub-pixel circuits SPC (refer to Figure 2 ) for each of the first sub-pixel to the third sub-pixel SP1, SP2, and SP3. The sub-pixel circuit SPC may include transistors and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode stacked on the semiconductor portion. According to some embodiments, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. According to some embodiments, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3, and an insulating layer is disposed between the spaced-apart electrodes.

[0078] The lines of the pixel circuit layer PCL may include signal lines (e.g., gate lines, emission control lines, data lines, etc.) connected to each of the first sub-pixel to the third sub-pixel SP1, SP2, and SP3. The lines may also include lines connected to Figure 2 the first power voltage node VDDN. Additionally, the lines may also include lines connected to Figure 2 the second power voltage node VSSN.

[0079] The light-emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0080] The anode electrode AE may be located on the pixel circuit layer PCL. The anode electrode AE may be in contact with the circuit elements of the pixel circuit layer PCL. The anode electrode AE may include an opaque conductive material capable of reflecting light, but is not limited thereto according to embodiments of the present disclosure.

[0081] The pixel defining layer PDL may be located on the anode electrode AE. The pixel defining layer PDL may include openings OP exposing a part of each of the anode electrodes AE. The openings OP of the pixel defining layer PDL may be understood as emission regions corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively.

[0082] According to some embodiments, the pixel defining layer PDL may include an inorganic material. In this case, the pixel defining layer PDL may include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiO x ), and silicon nitride (SiN x ). According to some embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0083] The light emitting structure EMS may be located on the anode electrode AE exposed through the opening OP of the pixel defining layer PDL. The light emitting structure EMS may include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, a hole transport layer configured to transport holes, and the like.

[0084] According to some embodiments, the light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be entirely disposed or formed on the pixel defining layer PDL. In other words, the light emitting structure EMS may extend over the first sub-pixel SP1 to the third sub-pixel SP3. In this case, at least a part of the layers in the light emitting structure EMS may be disconnected or bent at the boundaries between the first sub-pixel SP1 to the third sub-pixel SP3. However, the embodiments according to the present disclosure are not limited thereto. For example, the portions of the light emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each of the portions may be located in the opening OP of the pixel defining layer PDL.

[0085] The cathode electrode CE may be located on the light emitting structure EMS. The cathode electrode CE may extend over the first sub-pixel SP1 to the third sub-pixel SP3. As described above, the cathode electrode CE may be provided as a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3.

[0086] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit the light emitted from the light emitting structure EMS. The cathode electrode CE may be formed of a metal material or a transparent conductive material to have a relatively thin thickness. According to some embodiments, the cathode electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc oxide tin, and gallium tin oxide. According to some embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited thereto.

[0087] It can be understood that any one of the anode electrodes AE, the portion of the light emitting structure EMS stacked with the any one of the anode electrodes AE, and the portion of the cathode electrode CE stacked with the any one of the anode electrodes AE construct a light emitting element LD (refer toFigure 2 ). In other words, each of the light-emitting elements of the first sub-pixel SP1 to the third sub-pixel SP3 may include an anode electrode AE, a portion of the light-emitting structure EMS that is stacked with the one anode electrode AE, and a portion of the cathode electrode CE that is stacked with the one anode electrode AE. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode electrode AE and electrons injected from the cathode electrode CE may be transferred to the light-emitting layer of the light-emitting structure EMS to form excitons, and when the excitons transition from the excited state to the ground state, light may be generated. The brightness of the light may be determined according to the amount of current flowing through the light-emitting layer. According to the structure of the light-emitting layer, the wavelength range of the generated light may be determined.

[0088] The encapsulation layer TFE may be located on the cathode electrode CE. The encapsulation layer TFE may cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent or reduce the penetration of contaminants such as oxygen, moisture, etc. into the light-emitting element layer LDL. According to some embodiments, the encapsulation layer TFE may include a structure in which one or more inorganic layers and one or more organic layers are alternately stacked. For example, the inorganic layer may include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ), etc. For example, the organic layer may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited thereto.

[0089] To relatively improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include a thin film containing aluminum oxide (AlO x ). The thin film including aluminum oxide may be positioned on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0090] The thin film including aluminum oxide may be formed by atomic layer deposition (ALD) method. However, the embodiments according to the present disclosure are not limited thereto. The encapsulation layer TFE may further include a thin film formed of at least one of various materials suitable for relatively improving the encapsulation efficiency.

[0091] The optical function layer OFL may be located on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0092] The color filter layer CFL may be located between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the light-emitting structure EMS and selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively, and each of the color filters CF may allow light of a wavelength range corresponding to the corresponding sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 may allow red light to pass through, the color filter corresponding to the second sub-pixel SP2 may allow green light to pass through, and the color filter corresponding to the third sub-pixel SP3 may allow blue light to pass through. At least a portion of the color filter CF may be omitted according to the light emitted from the light-emitting structure EMS of each sub-pixel.

[0093] The lens array LA may be located on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the lenses LS may relatively improve the light output efficiency by outputting the light emitted from the light-emitting structure EMS to an intended path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the outer coating OC. According to some embodiments, the lens LS may include an organic material. According to some embodiments, the lens LS may include an acrylic material. However, the material of the lens LS is not limited thereto.

[0094] According to some embodiments, at least a part of the color filter CF of the color filter layer CFL and at least a part of the lens LS of the lens array LA may be shifted in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2 compared to the opening OP of the pixel defining layer PDL. For example, in the central region of the display area DA, when viewed in the third direction DR3, the center of the color filter and the center of the lens may be aligned or superimposed with the center of the opening OP of the corresponding pixel defining layer PDL. For example, in the central region of the display area DA, the opening OP of the pixel defining layer PDL may be completely superimposed with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3 (e.g., in a plan view), the center of the color filter and the center of the lens may be shifted in the plane direction from the center of the opening OP of the corresponding pixel defining layer PDL. For example, in the region of the display area DA adjacent to the non-display area NDA, the opening OP of the pixel defining layer PDL may be partially superimposed with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. Therefore, at the center of the display area DA, the light emitted from the light emitting structure EMS can be effectively output in the normal direction of the display surface. At the periphery of the display area DA, the light emitted from the light emitting structure EMS can be effectively output in a direction inclined at an angle (e.g., a set or predetermined angle) with respect to the normal direction of the display surface.

[0095] The outer coating OC may be located on the lens array LA. The outer coating OC may cover the optical functional layer OFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The outer coating OC may include various materials suitable for protecting the layers below it from foreign substances such as dust or moisture. For example, the outer coating OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC may include an epoxy resin, but the embodiments are not limited thereto. The outer coating OC may have a refractive index lower than that of the lens array LA.

[0096] The cover window CW may be located on the outer coating OC. The cover window CW may be configured to protect the layers below it. The cover window CW may have a refractive index higher than that of the outer coating OC. The cover window CW may include glass, but the embodiments are not limited thereto. For example, the cover window CW may be an encapsulation glass configured to protect the components located below it. According to some embodiments, the cover window CW may be omitted.

[0097] Figure 5 is a plan view showing aspects of a Figure 4 pixel according to some embodiments. In Figure 5 order to describe clearly and concisely, Figure 4The first pixel PXL1 among the first pixel PXL1 and the second pixel PXL2. The remaining pixels can be constructed similarly to the first pixel PXL1.

[0098] Referring to Figure 4 and Figure 5 , the first pixel PXL1 and the second pixel PXL2 can include first to third sub-pixels SP1 to SP3 arranged in a first direction DR1.

[0099] The first sub-pixel SP1 can include a first anode electrode AE1. The second sub-pixel SP2 can include a second anode electrode AE2. The third sub-pixel SP3 can include a third anode electrode AE3.

[0100] The first pixel PXL1 can include a reflective layer RFL in a boundary region BDA (referring to Figure 6 ) between the first to third sub-pixels SP1 to SP3. The reflective layer RFL can be arranged along the periphery of the first anode electrode AE1 in the first sub-pixel SP1. The reflective layer RFL can be arranged along the periphery of the second anode electrode AE2 in the second sub-pixel SP2. The reflective layer RFL can be arranged along the periphery of the third anode electrode AE3 in the third sub-pixel SP3. Additionally, a part of the reflective layer RFL can be located between the first anode electrode AE1 and the second anode electrode AE2. Another part of the reflective layer RFL can be located between the second anode electrode AE2 and the third anode electrode AE3.

[0101] The first sub-pixel SP1 can include a first emission region EMA1 and a non-emission region NEA around the first emission region EMA1. The first emission region EMA1 can be positioned in the first anode electrode AE1, and at least a part of the first anode electrode AE1 can extend to the non-emission region NEA. The second sub-pixel SP2 can include a second emission region EMA2 and a non-emission region NEA around the second emission region EMA2. The second emission region EMA2 can be positioned in the second anode electrode AE2, and at least a part of the second anode electrode AE2 can extend to the non-emission region NEA. The third sub-pixel SP3 can include a third emission region EMA3 and a non-emission region NEA around the third emission region EMA3. The third emission region EMA3 can be positioned in the third anode electrode AE3, and at least a part of the third anode electrode AE3 can extend to the non-emission region NEA.

[0102] The first emission region EMA1 can be where light is emitted from a light-emitting structure EMS (referring to Figure 4The region where light is emitted from the portion corresponding to the first sub-pixel SP1. The second emission region EMA2 may be the region where light is emitted from the portion of the light-emitting structure EMS corresponding to the second sub-pixel SP2. The third emission region EMA3 may be the region where light is emitted from the portion of the light-emitting structure EMS corresponding to the third sub-pixel SP3. As referred to Figure 5 as described above, each emission region may be understood as an opening OP corresponding to each of the first sub-pixel SP1 to the third sub-pixel SP3 in the pixel defining layer PDL.

[0103] Figure 6 is a cross-sectional view taken along the line I-I' of Figure 5 .

[0104] Referring to Figure 6 , a substrate SUB and a pixel circuit layer PCL located on the substrate SUB may be provided.

[0105] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0106] The pixel circuit layer PCL may be located on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first sub-pixel SP1 to the third sub-pixel SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be any one of the transistors included in the sub-pixel circuit SPC of the first sub-pixel SP1 (refer to Figure 2 ), the transistor T_SP2 of the second sub-pixel SP2 may be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 may be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. In Figure 6 , for the sake of clear and concise description, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0107] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0108] The source region SRA and the drain region DRA may be located in the substrate SUB. A well WL formed by an ion implantation process may be located in the substrate SUB, and the source region SRA and the drain region DRA may be arranged to be spaced apart from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0109] The gate electrode GE may be stacked with the channel region between the source region SRA and the drain region DRA, and may be located in the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0110] The plurality of layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns located between the insulating layers, and such conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA through a drain connection portion DRC passing through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA through a source connection portion SRC passing through one or more insulating layers.

[0111] Since the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 are connected to different circuit elements and / or lines, the transistor T_SP1 of the first sub-pixel SP1 may be set to any one of the transistors of the first sub-pixel SP1.

[0112] Each of the transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 may be constructed similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0113] As described above, the substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first sub-pixel SP1 to the third sub-pixel SP3.

[0114] The via layer VIAL may be located on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL, and may have an overall flat surface. The via layer VIAL may be configured to planarize the steps on the pixel circuit layer PCL. The via layer VIAL may include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon carbonitride (SiCN), but is not limited thereto according to embodiments of the present disclosure.

[0115] The light-emitting element layer LDL may be located on the via layer VIAL. The light-emitting element layer LDL may include a first reflective electrode RE1 to a third reflective electrode RE3, a planarization layer PLNL, a first anode electrode AE1 to a third anode electrode AE3, a pixel defining layer PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0116] The first reflective electrode RE1 to the third reflective electrode RE3 may be respectively located in the first sub-pixel SP1 to the third sub-pixel SP3 on the via layer VIAL. Each of the first reflective electrode RE1 to the third reflective electrode RE3 may contact a circuit element located in the pixel circuit layer PCL through a via penetrating the via layer VIAL.

[0117] The first reflective electrode RE1 to the third reflective electrode RE3 may serve as a total reflection mirror (full mirror) that reflects light emitted from the light-emitting structure EMS toward the display surface (or the cover window CW). The first reflective electrode RE1 to the third reflective electrode RE3 may include a metal material suitable for reflecting light. The first reflective electrode RE1 to the third reflective electrode RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected from them, but the embodiments are not limited thereto.

[0118] According to some embodiments, a connection electrode may be located under each of the first reflective electrode RE1 to the third reflective electrode RE3. The connection electrode may relatively improve the electrical connection characteristics between the corresponding reflective electrode and the circuit element of the pixel circuit layer PCL. The connection electrode may have a multi-layer structure. The multi-layer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiments are not limited thereto. According to some embodiments, the corresponding reflective electrode may be positioned between multiple layers of the connection electrode.

[0119] The buffer pattern BFP may be located under at least one of the first reflective electrode RE1 to the third reflective electrode RE3. The buffer pattern BFP may include an inorganic material such as silicon carbonitride, but is not limited thereto according to the embodiments of the present disclosure. The height of the third direction DR3 of the corresponding reflective electrode may be adjusted by forming the buffer pattern BFP. For example, the buffer pattern BFP may be located between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0120] The first reflective electrode RE1 to the third reflective electrode RE3 may serve as a total reflection mirror, and the cathode electrode CE may serve as a half mirror (half mirror). The light emitted from the light-emitting layer of the light-emitting structure EMS may be amplified by at least partially reciprocating between the corresponding reflective electrode and the cathode electrode CE, and the amplified light may be output through the cathode electrode CE. As described above, the distance between each reflective electrode and the cathode electrode CE may be understood as a resonant distance for the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0121] The first sub-pixel SP1 can have a resonance distance shorter than that of another sub-pixel through the buffer pattern BFP. The resonance distance adjusted as described above can allow the light in a specific wavelength range (e.g., red) to be amplified effectively and efficiently. Therefore, the first sub-pixel SP1 can output the light in the corresponding wavelength range effectively and efficiently.

[0122] In Figure 6 it, the buffer pattern BFP is provided to the first sub-pixel SP1 and not provided to the second sub-pixel SP2 and the third sub-pixel SP3, but the embodiments are not limited thereto. The buffer pattern can also be provided to at least one of the second sub-pixel SP2 and the third sub-pixel SP3 to adjust the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the buffer pattern BFP can also be provided to the second sub-pixel SP2, and the resonance distance of the second sub-pixel SP2 can be adjusted. For example, the first sub-pixel SP1 to the third sub-pixel SP3 can correspond to red, green, and blue respectively, the distance between the first reflective electrode RE1 and the cathode electrode CE can be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE can be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0123] To flatten the steps between the first reflective electrode RE1 to the third reflective electrode RE3, a planarization layer PLNL can be located on the via layer VIAL and the first reflective electrode RE1 to the third reflective electrode RE3. The planarization layer PLNL can cover the first reflective electrode RE1 to the third reflective electrode RE3 and the via layer VIAL as a whole and can have a flat surface. According to some embodiments, the planarization layer PLNL can be omitted.

[0124] The first anode electrode AE1 to the third anode electrode AE3 respectively stacked with the first reflective electrode RE1 to the third reflective electrode RE3 can be arranged on the planarization layer PLNL. When viewed in the third direction DR3 (e.g., in a plan view), the first anode electrode AE1 to the third anode electrode AE3 can have a shape similar to that of Figure 5 the first emission regions EMA1 to the third emission regions EMA3. The first anode electrode AE1 to the third anode electrode AE3 can be respectively connected to the first reflective electrode RE1 to the third reflective electrode RE3. The first anode electrode AE1 can be connected to the first reflective electrode RE1 through a first via VIA1 passing through the planarization layer PLNL. The second anode electrode AE2 can be connected to the second reflective electrode RE2 through a second via VIA2 passing through the planarization layer PLNL. The third anode electrode AE3 can be connected to the third reflective electrode RE3 through a third via VIA3 passing through the planarization layer PLNL.

[0125] According to some embodiments, the first to third anode electrodes AE1 to AE3 may include at least one of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the materials of the first to third anode electrodes AE1 to AE3 are not limited thereto. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0126] According to some embodiments, an insulating layer may also be provided for adjusting the height of one or more of the first to third anode electrodes AE1 to AE3. The insulating layer may be located between one or more of the first to third anode electrodes AE1 to AE3 and the corresponding reflective electrode. In this case, the planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first to third sub-pixels SP1 to SP3 may correspond to red, green, and blue respectively, the distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE, and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE.

[0127] The pixel defining layer PDL may be located on a part of the first to third anode electrodes AE1 to AE3 and the planarization layer PLNL. The pixel defining layer PDL may include an opening OP exposing a part of each of the first to third anode electrodes AE1 to AE3. The opening OP of the pixel defining layer PDL may define the emission region of each of the first to third sub-pixels SP1 to SP3. As described above, the pixel defining layer PDL may be located in Figure 5 the non-emission area NEA, and may define Figure 5 the first to third emission areas EMA1 to EMA3.

[0128] The pixel defining layer PDL may have a recessed shape arranged to surround the first to third anode electrodes AE1 to AE3. Here, the recessed shape may be a trench TRCH. Hereinafter, the trench TRCH is used as an example to describe Figure 6 the recessed shape, but the recessed shape is not limited to the trench TRCH.

[0129] Referring to Figure 6, the trench TRCH may include a first trench TRCH1 and a second trench TRCH2. The first trench TRCH1 may be located in a boundary region BDA between the first sub-pixel SP1 and the second sub-pixel SP2. The second trench TRCH2 may be located in a boundary region BDA between the second sub-pixel SP2 and the third sub-pixel SP3. However, the embodiments are not limited thereto. For example, the pixel defining layer PDL may include two or more trenches in the boundary region BDA.

[0130] According to some embodiments, as Figure 6 shown, the first trench TRCH1 and the second trench TRCH2 may partially penetrate the pixel defining layer PDL. According to some embodiments, the first trench TRCH1 and the second trench TRCH2 may completely penetrate the pixel defining layer PDL. In this case, the first trench TRCH1 and the second trench TRCH2 may partially penetrate the planarization layer PLNL.

[0131] The first trench TRCH1 and the second trench TRCH2 may cause the formation of a discontinuous portion (discontinuity) in the light-emitting structure EMS in the boundary region BDA. The light-emitting structure EMS may have a discontinuous portion in a region overlapping with the first trench TRCH1 and the second trench TRCH2. Due to the discontinuity, a part of the layer of the light-emitting structure EMS may be electrically disconnected at the boundary region BDA.

[0132] According to some embodiments, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include at least one of silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the pixel defining layer PDL may include a first inorganic insulating layer to a third inorganic insulating layer stacked in sequence, and each of the first inorganic insulating layer to the third inorganic insulating layer may include silicon nitride, silicon oxide, and silicon nitride. However, the embodiments according to the present disclosure are not limited thereto. The first inorganic insulating layer to the third inorganic insulating layer may have a stepped cross-section in a region adjacent to the opening OP of the pixel defining layer PDL.

[0133] The reflective layer RFL may be located in the boundary region BDA between adjacent sub-pixels. In other words, the reflective layer RFL may be located in Figure 5 each of the boundary regions BDA between the sub-pixels SP of

[0134] The reflective layer RFL may be disposed in or on the pixel defining layer PDL. The pixel defining layer PDL may include the reflective layer RFL stacked with one or more trenches TRCH in the boundary region BDA. The pixel defining layer PDL may include a first reflective layer RFL1 stacked with the first trench TRCH1. The pixel defining layer PDL may include a second reflective layer RFL2 stacked with the second trench TRCH2.

[0135] In the manufacturing process, a mask MSK having openings M_OP1 and M_OP2 may be arranged. The openings M_OP1 and M_OP2 of the mask MSK may be stacked with the first reflective layer RFL1 and the second reflective layer RFL2. Subsequently, ultraviolet rays UV may be irradiated through the openings M_OP1 and M_OP2. The ultraviolet rays UV may cause the portions of the light emitting structure EMS stacked with the openings M_OP1 and M_OP2 to further have discontinuous portions. A part of the multiple layers stacked in the light emitting structure EMS may be disconnected or denatured by the ultraviolet rays UV. For example, at least one charge generation layer CGL (refer to Figure 7 ) included in the light emitting structure EMS may be disconnected in the region stacked with the first reflective layer RFL1 and the second reflective layer RFL2. At least one p-hole injection layer p-HIL (refer to Figure 7 ) included in the light emitting structure EMS may be disconnected in the region stacked with the first reflective layer RFL1 and the second reflective layer RFL2. In the disclosure, the charge generation layer CGL and the p-hole injection layer p-HIL are described as examples, but the disclosure is not limited thereto. For example, at least one layer among the first hole transport unit HTU1 and the second hole transport unit HTU2, the first electron transport unit ETU1 and the second electron transport unit ETU2, and the first light emitting layer EML1 and the second light emitting layer EML2 included in the light emitting structure EMS may be disconnected in the region stacked with the first reflective layer RFL1 and the second reflective layer RFL2. As another example, multiple layers included in the light emitting structure EMS may be disconnected in the region stacked with the first reflective layer RFL1 and the second reflective layer RFL2.

[0136] The reflective layer RFL may be set as a reflector that reflects the ultraviolet rays UV. According to some embodiments, the first reflective layer RFL1 and the second reflective layer RFL2 may be formed of the same material as the anode electrode. For example, the first reflective layer RFL1 and the second reflective layer RFL2 may have a shape that is recessed in a direction opposite to the third direction DR3. According to the shape of the reflective layer RFL, a part of the multiple layers stacked in the light emitting structure EMS may be disconnected using a small amount of ultraviolet rays UV. In addition, the region irradiated with the ultraviolet rays UV may be minimized.

[0137] According to some embodiments, the light-emitting structure EMS can be formed by processes such as vacuum deposition, inkjet printing, etc. In this case, in the first trench TRCH1 and the second trench TRCH2, the same material as the light-emitting structure EMS can be positioned on the bottom surface adjacent to the planarization layer PLNL.

[0138] The light-emitting structure EMS can be located on the anode electrode AE exposed through the opening OP of the pixel defining layer PDL. The light-emitting structure EMS can fill the opening OP of the pixel defining layer PDL and can be arranged to span entirely across the first sub-pixel SP1 to the third sub-pixel SP3. As described above, at least a part of the light-emitting structure EMS can be disconnected in the boundary region BDA by the first trench TRCH1 and the second trench TRCH2 and ultraviolet light UV.

[0139] Therefore, when operating the display panel 110, the current flowing out from each of the first sub-pixel SP1 to the third sub-pixel SP3 to the adjacent sub-pixels through the layers included in the light-emitting structure EMS can be reduced. Therefore, the first light-emitting element LD1 to the third light-emitting element LD3 can operate with relatively high reliability.

[0140] The cathode electrode CE can be located on the light-emitting structure EMS. The cathode electrode CE can be commonly provided to the first sub-pixel SP1 to the third sub-pixel SP3. The cathode electrode CE can be used as a semi-reflective mirror that partially transmits and partially reflects the light emitted from the light-emitting structure EMS.

[0141] The first anode electrode AE1, the portion of the light-emitting structure EMS that overlaps with the first anode electrode AE1, and the portion of the cathode electrode CE that overlaps with the first anode electrode AE1 can construct the first light-emitting element LD1. The second anode electrode AE2, the portion of the light-emitting structure EMS that overlaps with the second anode electrode AE2, and the portion of the cathode electrode CE that overlaps with the second anode electrode AE2 can construct the second light-emitting element LD2. The third anode electrode AE3, the portion of the light-emitting structure EMS that overlaps with the third anode electrode AE3, and the portion of the cathode electrode CE that overlaps with the third anode electrode AE3 can construct the third light-emitting element LD3.

[0142] The encapsulation layer TFE can be located on the cathode electrode CE. The encapsulation layer TFE can prevent or reduce the penetration of contaminants such as oxygen and / or moisture into the light-emitting element layer LDL.

[0143] The optical function layer OFL can be located on the encapsulation layer TFE. According to some embodiments, the optical function layer OFL can be attached to the encapsulation layer TFE through the adhesive layer APL. For example, the optical function layer OFL can be separately manufactured and attached to the encapsulation layer TFE through the adhesive layer APL. The adhesive layer APL can also perform the function of protecting the underlying layer including the encapsulation layer TFE.

[0144] The optical functional layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include a first color filter CF1 to a third color filter CF3 corresponding to a first sub-pixel SP1 to a third sub-pixel SP3, respectively. The first color filter CF1 to the third color filter CF3 may allow light of different wavelength ranges to pass through. For example, the first color filter CF1 to the third color filter CF3 may allow red, green, and blue light to pass through, respectively.

[0145] According to some embodiments, the first color filter CF1 to the third color filter CF3 may be partially overlapped in a boundary region BDA. According to some embodiments, the first color filter CF1 to the third color filter CF3 may be spaced apart from each other, and a black matrix may be disposed between the first color filter CF1 to the third color filter CF3.

[0146] The lens array LA may be located on the color filter layer CFL. The lens array LA may include a first lens LS1 to a third lens LS3 corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the first lens LS1 to the third lens LS3 may relatively improve the light output efficiency by outputting the light emitted from the first light-emitting element LD1 to the third light-emitting element LD3 to an intended path.

[0147] The outer coating OC and the cover window CW may be located on the lens array LA.

[0148] Figure 7 is a cross-sectional view showing an aspect of a light-emitting structure included in any one of the first light-emitting element to the third light-emitting element according to some embodiments. Figure 6 of the first light-emitting element to the third light-emitting element.

[0149] Referring to Figure 7 , the light-emitting structure EMS may have a series structure in which a first light-emitting unit EU1 and a second light-emitting unit EU2 are stacked. The light-emitting structure EMS may be substantially similarly configured in each of the first light-emitting element LD1 to the third light-emitting element LD3.

[0150] Each of the first light-emitting unit EU1 and the second light-emitting unit EU2 may include at least one light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be located between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be located between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0151] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer HIL and a hole transport layer HTL. Additionally, if necessary, each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may further include a hole buffer layer, an electron blocking layer, etc. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same or different structures from each other.

[0152] The first hole transport unit HTU1 may include a p-type hole injection layer p-HIL in which a known hole injection material is doped with a p-type dopant. For example, the p-type hole injection layer p-HIL may be located between the first anode electrode to the third anode electrodes AE1, AE2, and AE3 and the hole transport layer HTL. The p-type hole injection layer p-HIL may perform the function of smoothly injecting holes transported from each of the first anode electrode to the third anode electrodes AE1, AE2, and AE3. The p-type hole injection layer p-HIL may be separated for each sub-pixel, or may be integrally formed over the entire surface of the substrate SUB (refer to Figure 6 ) However, in Figure 7 , the p-type hole injection layer p-HIL is shown as a single layer within the hole injection layer HIL, but the embodiments are not limited thereto. For example, the hole injection layer HIL may be the p-type hole injection layer p-HIL.

[0153] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer EIL and an electron transport layer ETL. Additionally, if necessary, each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may further include an electron buffer layer, a hole blocking layer, etc. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same or different structures from each other.

[0154] A connection layer, which may be provided in the form of a charge generation layer CGL, may be located between the first light-emitting unit EU1 and the second light-emitting unit EU2 to connect the first light-emitting unit EU1 and the second light-emitting unit EU2 to each other. According to some embodiments, the charge generation layer CGL may include an n-type electron generation layer n-CGL for supplying charges to the first light-emitting unit EU1 and a p-type electron generation layer p-CGL for supplying holes to the second light-emitting unit EU2. For example, the n-type electron generation layer n-CGL may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. The p-type charge generation layer p-CGL may include a p-type dopant such as HAT-CN, TCNQ, or NDP-9. However, the embodiments are not limited thereto.

[0155] According to some embodiments, the first emission layer EML1 and the second emission layer EML2 may emit light of different colors. The light emitted from each of the first emission layer EML1 and the second emission layer EML2 may be mixed and regarded as white light. For example, the first emission layer EML1 may emit blue light, and the second emission layer EML2 may emit yellow light. According to some embodiments, the second emission layer EML2 may include a structure in which a first sub-emission layer configured to emit red light and a second sub-emission layer configured to emit green light are stacked. The red light and the green light may be mixed, and thus yellow light may be provided. In this case, an intermediate layer configured to perform a function of transporting holes and / or blocking electrons may be further located between the first sub-emission layer and the second sub-emission layer. According to some embodiments, the first emission layer EML1 and the second emission layer EML2 may emit light of the same color.

[0156] Figure 8 is a cross-sectional view showing an aspect of a light-emitting structure included in any one of a first light-emitting element to a third light-emitting element according to some embodiments. Figure 6

[0157] Referring to Figure 8 , the light-emitting structure EMS' may have a series structure in which a first light-emitting unit EU1' to a third light-emitting unit EU3' are stacked. The light-emitting structure EMS' may be substantially the same in each of the first light-emitting element LD1 to the third light-emitting element LD3 of Figure 6 .

[0158] Each of the first light-emitting unit EU1' to the third light-emitting unit EU3' may include an emission layer that emits light according to an applied current. The first light-emitting unit EU1' may include a first emission layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first emission layer EML1' may be located between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second emission layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second emission layer EML2' may be located between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third emission layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third emission layer EML3' may be located between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0159] Each of the first hole transport unit HTU1' to the third hole transport unit HTU3' may include a hole injection layer HIL (refer to Figure 7), and at least one of a hole transport layer HTL (refer to Figure 7 ), and may further include a hole buffer layer, an electron blocking layer, etc. if necessary. The first hole transport unit HTU1' to the third hole transport unit HTU3' may have the same or different structures from each other.

[0160] Each of the first electron transport unit ETU1' to the third electron transport unit ETU3' may include an electron injection layer EIL (refer to Figure 7 ), and at least one of an electron transport layer ETL (refer to Figure 7 ), and may further include an electron buffer layer, a hole blocking layer, etc. if necessary. The first electron transport unit ETU1' to the third electron transport unit ETU3' may have equal or different configurations from each other.

[0161] The first charge generation layer CGL1' may be located between the first light emitting unit EU1' and the second light emitting unit EU2'. The second charge generation layer CGL2' may be located between the second light emitting unit EU2' and the third light emitting unit EU3'.

[0162] According to some embodiments, the first light emitting layer EML1' to the third light emitting layer EML3' may generate light of different colors. The light emitted from each of the first light emitting layer EML1' to the third light emitting layer EML3' may be mixed and may be regarded as white light. For example, the first light emitting layer EML1' may generate blue light, the second light emitting layer EML2' may generate green light, and the third light emitting layer EML3' may generate red light.

[0163] According to some embodiments, two or more of the first light emitting layer EML1' to the third light emitting layer EML3' may generate light of the same color.

[0164] Unlike Figure 7 and Figure 8 shown in, Figure 6 the light emitting structure EMS of Figure 6As shown differently, the light-emitting units of the first sub-pixel SP1 to the third sub-pixel SP3 can be separated from each other, and each of the light-emitting units of the first sub-pixel SP1 to the third sub-pixel SP3 can be located in the opening OP of the pixel defining layer PDL. In this case, at least a part of the first color filter CF1 to the third color filter CF3 can be omitted.

[0165] Figure 9 is an enlarged view of part A showing Figure 6 of.

[0166] Referring to Figure 9 , the first reflective layer RFL1 can be located below the light-emitting structure EMS, specifically, in the central region of the pixel defining layer PDL. The first reflective layer RFL1 can be located between the first anode electrode AE1 of the first sub-pixel SP1 and the second anode electrode AE2 of the second sub-pixel SP2. Hereinafter, referring to Figure 9 to describe the first reflective layer RFL1, the second reflective layer RFL2 can be described substantially the same as the first reflective layer RFL1. Hereinafter, repeated descriptions are omitted.

[0167] The first reflective layer RFL1 can include a reflective material that reflects ultraviolet rays UV. The first reflective layer RFL1 can include the same material as the first anode electrode AE1 and the second anode electrode AE2. According to some embodiments, each of the first anode electrode AE1 and the second anode electrode AE2 can include a first metal layer MT1, a second metal layer MT2, and a third metal layer MT3 stacked in sequence. For example, the first metal layer MT1 can be formed on the planarization layer PLNL and can include a reflective material such as titanium (Ti). The second metal layer MT2 can be formed on the first metal layer MT1 and can include a reflective material such as an aluminum (Al) alloy. The third metal layer MT3 can be formed on the second metal layer MT2 and can include a material with a high work function (such as indium tin oxide (ITO)). However, this is an example, and the materials forming the first metal layer MT1 to the third metal layer MT3 are not limited thereto.

[0168] The first reflective layer RFL1 can be formed on the planarization layer PLNL or the pixel defining layer PDL. The first reflective layer RFL1 can include at least one of the first metal layer MT1, the second metal layer MT2, and the third metal layer MT3. Referring to Figure 9, the first reflective layer RFL1 may have a structure in which a first metal layer MT1 and a second metal layer MT2 are sequentially stacked. However, the structure of the first reflective layer RFL1 is not limited thereto. For example, the first reflective layer RFL1 may have a structure in which a first metal layer MT1 to a third metal layer MT3 are sequentially stacked. Additionally, the first reflective layer RFL1 may have a single-layer structure formed by the first metal layer MT1, the second metal layer MT2, or the third metal layer MT3.

[0169] The light-emitting structure EMS located on the first reflective layer RFL1 may include a first light-emitting unit EU1 and a second light-emitting unit EU2, and a charge generation layer CGL located between the first light-emitting unit EU1 and the second light-emitting unit EU2. Ultraviolet light UV may be irradiated onto the light-emitting structure EMS through openings M_OP1 and M_OP2 of a mask MSK (refer to Figure 6 ). Figure 6 ). The charge generation layer CGL and the p-hole injection layer p-HIL in the light-emitting structure EMS may be disconnected or denatured by the irradiated ultraviolet light UV. In Figure 9 , the charge generation layer CGL and the p-hole injection layer p-HIL are disconnected or denatured, but it is not limited thereto according to embodiments of the present disclosure. For example, other layers included in the light-emitting structure EMS may be disconnected or denatured by the irradiated ultraviolet light UV. Optionally, all of the multiple layers included in the light-emitting structure EMS may be disconnected or denatured by the irradiated ultraviolet light UV.

[0170] The first reflective layer RFL1 may reflect the ultraviolet light UV back to the light-emitting structure EMS, thereby increasing the exposure of the ultraviolet light UV to the light-emitting structure EMS. According to some embodiments, the first reflective layer RFL1 may have a lower surface S1 adjacent to a substrate SUB (refer to Figure 6 ), and an upper surface S2 opposite to the lower surface S1. The upper surface S2 of the first reflective layer RFL1 may have a shape in which a central portion is recessed in a direction facing the substrate SUB or the lower surface S1. Additionally, the lower surface S1 of the first reflective layer RFL1 may have a shape in which a central portion is recessed in a direction facing the substrate SUB. Due to the recessed shape of the first reflective layer RFL1, the diffuse reflection of the ultraviolet light UV may be increased. For example, the ultraviolet light UV irradiated through the openings M_OP1 and M_OP2 of the mask MSK may be reflected back to the light-emitting structure EMS by the upper surface S2 of the first reflective layer RFL1.

[0171] According to some embodiments, the upper surface S2 of the first reflective layer RFL1 may include a first inclined surface SS1 and a second inclined surface SS2, and a base surface BS connecting the first inclined surface SS1 and the second inclined surface SS2. The ultraviolet ray UV may travel in a direction opposite to the third direction DR3 and reach the second inclined surface SS2. The ultraviolet ray UV reaching the second inclined surface SS2 may be reflected toward the base surface BS through the second inclined surface SS2, the ultraviolet ray UV reaching the base surface BS may be reflected toward the first inclined surface SS1 through the base surface BS, and the ultraviolet ray UV reaching the first inclined surface SS1 may be output in the third direction DR3 through the first inclined surface SS1 (a). Additionally, the ultraviolet ray UV may travel in a direction opposite to the third direction DR3 and reach the base surface BS. The ultraviolet ray UV reaching the base surface BS may be reflected by the base surface BS in the third direction DR3 (b).

[0172] As described above, due to the concave shape of the first reflective layer RFL1, the diffuse reflection of the ultraviolet ray UV can be increased. Thus, the light-emitting structure EMS can be exposed not only to the irradiated ultraviolet ray UV but also to the ultraviolet ray UV reflected by the first reflective layer RFL1. As described above, the first reflective layer RFL1 can increase the disconnection effect with a small amount of ultraviolet ray UV. Additionally, the first reflective layer RFL1 can minimize the area irradiated by the ultraviolet ray UV.

[0173] Figure 10 is a magnified view showing an aspect of a Figure 6 reflective layer according to some embodiments.

[0174] Referring to Figure 10 , the first reflective layer RFL1 may include a base surface BS and inclined surfaces SS1 and SS2 extending from the base surface BS. The base surface BS and the inclined surfaces SS1 and SS2 may have a structure in which a first metal layer MT1 and a second metal layer MT2 are stacked. In Figure 10 , as an example, the first reflective layer RFL1 includes the first metal layer MT1 and the second metal layer MT2, but the present disclosure is not limited thereto, and the first reflective layer RFL1 may include a first metal layer MT1 to a third metal layer MT3. Hereinafter, the first reflective layer RFL1 is described with reference to Figure 10 , but this can be equally applied to the second reflective layer RFL2.

[0175] The first reflective layer RFL1 may include a base surface BS parallel to the substrate SUB (refer to Figure 6). The first reflective layer RFL1 may include a first inclined surface SS1 extending from the substrate surface BS in a first direction DR1. Additionally, the first reflective layer RFL1 may include a second inclined surface SS2 extending in a direction opposite to the first direction DR1.

[0176] Since the first reflective layer RFL1 includes the first inclined surface SS1 and the second inclined surface SS2, the first reflective layer RFL1 may have a first width WD1, and the substrate surface BS may have a second width WD2 that is narrower than the first width WD1. For example, the first width WD1 may be 110 nm, and the second width WD2 may be 38 nm. However, this is an example, and the dimensions of the first reflective layer RFL1 are not limited thereto.

[0177] The first inclined surface SS1 may be inclined with respect to the substrate surface BS at a first angle SOD1. The second inclined surface SS2 may be inclined with respect to the substrate surface BS at a second angle SOD2. The first angle SOD1 of the first inclined surface SS1 and the second angle SOD2 of the second inclined surface SS2 may be the same angle. For example, the first angle SOD1 and the second angle SOD2 may be 45 degrees or greater.

[0178] When the first inclined surface SS1 and the second inclined surface SS2 of the first reflective layer RFL1 are inclined with respect to the substrate surface BS, the probability that ultraviolet light UV is reflected by the first reflective layer RFL1 in a third direction DR3 and provided back to the light-emitting structure EMS may increase. Since the first reflective layer RFL1 includes the first inclined surface SS1 and the second inclined surface SS2, the area of the first reflective layer RFL1 can be reduced, and the reflection efficiency of the first reflective layer RFL1 for ultraviolet light UV can be increased.

[0179] Figure 11 and Figure 12 is a plan view showing Figure 4 any other embodiment of a pixel of

[0180] Referring to Figure 11 , the first pixel PXL1' may include a first sub-pixel SP1' to a third sub-pixel SP3'.

[0181] The first sub-pixel SP1' may include a first anode electrode AE1'. The second sub-pixel SP2' may include a second anode electrode AE2'. The third sub-pixel SP3' may include a third anode electrode AE3'.

[0182] The first pixel PXL1' may include a boundary region BDA (refer to Figure 6The reflective layer RFL' in ). The reflective layer RFL' can be arranged along the periphery of the first anode electrode AE1' in the first sub-pixel SP1'. The reflective layer RFL' can be arranged along the periphery of the second anode electrode AE2' in the second sub-pixel SP2'. The reflective layer RFL' can be arranged along the periphery of the third anode electrode AE3' in the third sub-pixel SP3'. Additionally, a part of the reflective layer RFL' can be located between the first anode electrode AE1' and the second anode electrode AE2'. Another part of the reflective layer RFL' can be located between the second anode electrode AE2' and the third anode electrode AE3'. Still another part of the reflective layer RFL' can be located between the first anode electrode AE1' and the third anode electrode AE3'.

[0183] The first sub-pixel SP1' can include a first emission area EMA1' and a non-emission area NEA' surrounding the first emission area EMA1'. The first emission area EMA1' can be positioned in the first anode electrode AE1', and at least a part of the first anode electrode AE1' can extend into the non-emission area NEA'. The second sub-pixel SP2' can include a second emission area EMA2' and a non-emission area NEA' surrounding the second emission area EMA2'. The second emission area EMA2' can be positioned in the second anode electrode AE2', and at least a part of the second anode electrode AE2' can extend into the non-emission area NEA'. The third sub-pixel SP3' can include a third emission area EMA3' and a non-emission area NEA' surrounding the third emission area EMA3'. The third emission area EMA3' can be positioned in the third anode electrode AE3', and at least a part of the third anode electrode AE3' can extend into the non-emission area NEA'.

[0184] The first sub-pixel SP1' and the second sub-pixel SP2' can be arranged in the second direction DR2. The third sub-pixel SP3' can be arranged in the first direction DR1 with respect to each of the first sub-pixel SP1' and the second sub-pixel SP2'.

[0185] The second sub-pixel SP2' may have an area larger than that of the first sub-pixel SP1'. The third sub-pixel SP3' may have an area larger than that of the second sub-pixel SP2'. Accordingly, the second anode electrode AE2' and the second emission region EMA2' may respectively have areas larger than those of the first anode electrode AE1' and the first emission region EMA1'. The third anode electrode AE3' and the third emission region EMA3' may respectively have areas larger than those of the second anode electrode AE2' and the second emission region EMA2'. However, the embodiments are not limited thereto. For example, the first sub-pixel SP1' and the second sub-pixel SP2' may have substantially the same area, and the third sub-pixel SP3' may have an area larger than each of the areas of the first sub-pixel SP1' and the second sub-pixel SP2'. As described above, the areas of the first sub-pixel SP1' to the third sub-pixel SP3' may be variously modified according to some embodiments.

[0186] Referring to Figure 12 , the first pixel PXL1'' may include a reflective layer RFL'' in a boundary region BDA (referring to Figure 6 ) between the first sub-pixel SP1'' to the third sub-pixel SP3''. The reflective layer RFL'' may be disposed along the periphery of the first anode electrode AE1'' in the first sub-pixel SP1''. The reflective layer RFL'' may be disposed along the periphery of the second anode electrode AE2'' in the second sub-pixel SP2''. The reflective layer RFL'' may be disposed along the periphery of the third anode electrode AE3'' in the third sub-pixel SP3''. In addition, a part of the reflective layer RFL'' may be located between the first anode electrode AE1'' and the second anode electrode AE2''. Another part of the reflective layer RFL'' may be located between the second anode electrode AE2'' and the third anode electrode AE3''. Still another part of the reflective layer RFL'' may be located between the first anode electrode AE1'' and the third anode electrode AE3''.

[0187] The first sub-pixel SP1'' may include a first emission area EMA1'' and a non-emission area NEA'' surrounding the first emission area EMA1''. The first emission area EMA1'' may be positioned in the first anode electrode AE1'', and at least a part of the first anode electrode AE1'' may extend into the non-emission area NEA''. The second sub-pixel SP2'' may include a second emission area EMA2'' and a non-emission area NEA'' surrounding the second emission area EMA2''. The second emission area EMA2'' may be positioned in the second anode electrode AE2'', and at least a part of the second anode electrode AE2'' may extend into the non-emission area NEA''. The third sub-pixel SP3'' may include a third emission area EMA3'' and a non-emission area NEA'' surrounding the third emission area EMA3''. The third emission area EMA3'' may be positioned in the third anode electrode AE3'', and at least a part of the third anode electrode AE3'' may extend into the non-emission area NEA''.

[0188] When viewed in the third direction DR3, the first sub-pixel SP1'' to the third sub-pixel SP3'' may have a polygonal shape. For example, the first sub-pixel SP1'' to the third sub-pixel SP3'' may have a hexagonal shape as shown in Figure 12 .

[0189] When viewed in the third direction DR3, the first anode electrode AE1'' to the third anode electrode AE3'' may have a polygonal shape. However, the embodiments are not limited thereto. For example, each of the first anode electrode AE1'' to the third anode electrode AE3'' may have a circular shape.

[0190] When viewed in the third direction DR3, the first emission area EMA1'' to the third emission area EMA3'' may have a polygonal shape. However, the embodiments are not limited thereto. For example, each of the first emission area EMA1'' to the third emission area EMA3'' may have a circular shape.

[0191] The first sub-pixel SP1'' and the second sub-pixel SP2'' may be arranged in the first direction DR1. The third sub-pixel SP3'' may be arranged in a direction that is inclined at an acute angle with respect to the second direction DR2 (or in a diagonal direction) with respect to the first sub-pixel SP1''.

[0192] It is shown that Figure 5 , Figure 11 and Figure 12The arrangement of sub-pixels shown, but not limited to this according to embodiments of the present disclosure. Each pixel may include two or more sub-pixels, and the sub-pixels may be arranged in various ways. Each of the sub-pixels may have various shapes, and each of the anode electrodes and emission regions in the sub-pixels may also have various shapes.

[0193] Figure 13 is a plan view showing aspects of a Figure 4 pixel according to some embodiments. Referring to Figure 13 , the first pixel PXL1''' may include a first sub-pixel SP1''' to a third sub-pixel SP3'''. Hereinafter, the first sub-pixel SP1''' to the third sub-pixel SP3''', the first anode electrode AE1''' to the third anode electrode AE3''', and the first emission regions EMA1''' to the third emission regions EMA3''' may be described Figure 5 , Figure 11 and Figure 12 similarly. Their repeated descriptions are omitted.

[0194] The first sub-pixel SP1''' may include a first anode electrode AE1'''. The second sub-pixel SP2''' may include a second anode electrode AE2'''. The third sub-pixel SP3''' may include a third anode electrode AE3'''.

[0195] The first pixel PXL1''' may include a reflective layer RFL''' and a sub-groove STRCH in a boundary region BDA (refer to Figure 6 ) between the first sub-pixel SP1''' to the third sub-pixel SP3'''. Specifically, the sub-groove STRCH may be a region further recessed from the recessed shape where the reflective layer RFL''' is located.

[0196] The sub-groove STRCH may be arranged along the periphery of the first anode electrode AE1''' in the first sub-pixel SP1'''. The sub-groove STRCH may be arranged along the periphery of the second anode electrode AE2''' in the second sub-pixel SP2'''. The sub-groove STRCH may be arranged along the periphery of the third anode electrode AE3''' in the third sub-pixel SP3'''.

[0197] The sub-groove STRCH may be located between the first anode electrode AE1''' and the reflective layer RFL'''. Additionally, a part of the sub-groove STRCH may be located between the first anode electrode AE1''' and the second anode electrode AE2'''. The sub-groove STRCH may be located between the second anode electrode AE2''' and the reflective layer RFL'''. Additionally, another part of the sub-groove STRCH may be located between the second anode electrode AE2''' and the third anode electrode AE3'''. The sub-groove STRCH may be located between the third anode electrode AE3''' and the reflective layer RFL'''.

[0198] As described above, due to the provision of the sub-groove STRCH, the probability that at least a part of the layers of the light-emitting structure EMS has a discontinuous part in the boundary region BDA can be further increased. Therefore, at least a part of the layers of the light-emitting structure EMS can be disconnected in the boundary region BDA with higher reliability.

[0199] Figure 14 is a cross-sectional view taken along Figure 13 the line II-II'.

[0200] Referring to Figure 14 , a substrate SUB, a pixel circuit layer PCL, a transistor T_SP1 of the first sub-pixel SP1''', a transistor T_SP2 of the second sub-pixel SP2''', a transistor T_SP3 of the third sub-pixel SP3''', a via layer VIAL, a planarization layer PLNL', first to third reflective electrodes RE1 to RE3, a buffer pattern BFP, a pixel definition layer PDL', anode electrodes AE1''' to AE3''', a first reflective layer RFL1 and a second reflective layer RFL2, a light-emitting structure EMS, a cathode electrode CE, a light-emitting element layer LDL, a packaging layer TFE, an adhesive layer APL, an optical function layer OFL, a color filter layer CFL, first to third color filters CF1 to CF3, first to third lenses LS1 to LS3, a lens array LA, an outer coating OC, and a cover window CW may be provided.

[0201] may be associated with Figure 6The embodiments are similarly described for the substrate SUB, pixel circuit layer PCL, transistor T_SP1 of the first sub-pixel SP1''', transistor T_SP2 of the second sub-pixel SP2''', transistor T_SP3 of the third sub-pixel SP3''', via layer VIAL, first reflective electrode RE1 to third reflective electrode RE3, buffer pattern BFP, anode electrodes AE1''' to AE3''', first reflective layer RFL1 and second reflective layer RFL2, light-emitting structure EMS, cathode electrode CE, encapsulation layer TFE, adhesive layer APL, optical functional layer OFL, color filter layer CFL, first color filter CF1 to third color filter CF3, first lens LS1 to third lens LS3, lens array LA, outer coating OC, and cover window CW. Some repetitive descriptions related to Figure 6 the embodiments may be omitted, and the key points different from the above embodiments are mainly described.

[0202] The pixel defining layer PDL' may have a concave shape in the boundary region BDA between the first sub-pixel SP1''' and the second sub-pixel SP2'''. Hereinafter, Figure 14 the concave shape in is described by taking a trench as an example, but the concave shape is not limited to a trench.

[0203] The pixel defining layer PDL' may include one or more sub-trenches STRCH that are further recessed from the first trench TRCH1. According to some embodiments, the pixel defining layer PDL' may include a first sub-trench STRCH1 located between the first anode electrode AE1''' and the first reflective layer RFL1. The pixel defining layer PDL' may include a second sub-trench STRCH2 located between the second anode electrode AE2''' and the first reflective layer RFL1. That is, the first sub-trench STRCH1 and the second sub-trench STRCH2 may be arranged to be spaced apart from each other, and the first reflective layer RFL1 is disposed between the first sub-trench STRCH1 and the second sub-trench STRCH2. The first sub-trench STRCH1 and the second sub-trench STRCH2 may have a structure that is recessed from the upper surface of the pixel defining layer PDL' into the interior of the planarization layer PLNL'.

[0204] The pixel defining layer PDL' may include one or more sub-trenches STRCH that are further recessed from the second trench TRCH2 in a boundary region BDA between the second sub-pixel SP2''' and the third sub-pixel SP3'''. According to some embodiments, the pixel defining layer PDL' may include a third sub-trench STRCH3 located between the second anode electrode AE2''' and the second reflective layer RFL2. The pixel defining layer PDL' may include a fourth sub-trench STRCH4 located between the third anode electrode AE3''' and the second reflective layer RFL2. That is, the third sub-trench STRCH3 and the fourth sub-trench STRCH4 may be arranged to be spaced apart from each other, and the second reflective layer RFL2 is disposed between the third sub-trench STRCH3 and the fourth sub-trench STRCH4. The third sub-trench STRCH3 and the fourth sub-trench STRCH4 may have a structure that is recessed from the upper surface of the pixel defining layer PDL' into the interior of the planarization layer PLNL'.

[0205] By additionally forming the first sub-trench STRCH1 to the fourth sub-trench STRCH4 around the first reflective layer RFL1 and the second reflective layer RFL2, the probability that at least a part of the layer of the light emitting structure EMS has a discontinuous part in the boundary region BDA can be further increased.

[0206] Figure 15 is a flowchart showing aspects of a method of manufacturing a display device according to some embodiments. Although various operations are shown in Figure 15 , the embodiments according to the present disclosure are not limited thereto. For example, according to some embodiments, without departing from the spirit and scope of the embodiments according to the present disclosure, the method of manufacturing a display device may include additional operations or fewer operations, or the order of operations may vary (unless otherwise stated or implied).

[0207] Figures 16 to 19 is a cross-sectional view schematically showing a method of manufacturing a display device according to some embodiments. It can be described similarly to the embodiments of Figures 1 to 14 The method of manufacturing the display device 100 (refer to Figure 15 ) can be described in detail. Figure 1 ).

[0208] Referring to Figure 15 , the method of manufacturing the display device 100 according to the disclosed embodiments may include forming an anode electrode (S1010), forming a pixel defining layer (S1020), forming a reflective layer (S1030), forming a light emitting structure (S1040), forming a cathode electrode (S1050), positioning a mask (S1060), and irradiating ultraviolet light (S1070).

[0209] The pixel circuit layer PCL, via layer VIAL, and planarization layer PLNL can be sequentially stacked on the substrate SUB.

[0210] Referring Figure 15 and Figure 16 , in S1010, the first anode electrode AE1 to the third anode electrode AE3 can be formed on the planarization layer PLNL to be spaced apart from each other in the first direction DR1.

[0211] In S1020, the pixel defining layer PDL can be positioned on a portion of the first anode electrode AE1 to the third anode electrode AE3 and the planarization layer PLNL. The pixel defining layer PDL can include openings OP1 to OP3 that expose a part of each of the first anode electrode AE1 to the third anode electrode AE3. The pixel defining layer PDL can include a first trench TRCH1 and a second trench TRCH2 arranged to surround the first anode electrode AE1 to the third anode electrode AE3.

[0212] Referring Figure 15 and Figure 17 , in S1030, the first reflective layer RFL1 and the second reflective layer RFL2 can be formed in or on the pixel defining layer PDL. According to some embodiments, the first reflective layer RFL1 and the second reflective layer RFL2 can be formed on the pixel defining layer PDL through an exposure process, a development process, an etching process, etc. The first reflective layer RFL1 and the second reflective layer RFL2 can be formed to overlap with the first trench TRCH1 and the second trench TRCH2, respectively. The first reflective layer RFL1 can be located between the first anode electrode AE1 of the first sub-pixel SP1 and the second anode electrode AE2 of the second sub-pixel SP2. The second reflective layer RFL2 can be located between the second anode electrode AE2 of the second sub-pixel SP2 and the third anode electrode AE3 of the third sub-pixel SP3.

[0213] The first reflective layer RFL1 and the second reflective layer RFL2 can include a reflective material that reflects ultraviolet light UV. The first reflective layer RFL1 and the second reflective layer RFL2 can include the same material as the first anode electrode AE1 and the second anode electrode AE2. Additionally, each of the first reflective layer RFL1 and the second reflective layer RFL2 can have a shape in which a central portion is recessed in a direction opposite to the third direction DR3 (or the direction facing the substrate SUB). The recessed shapes of the first reflective layer RFL1 and the second reflective layer RFL2 can increase the diffuse reflection of ultraviolet light UV. As referred to above Figure 10As described above, the first reflective layer RFL1 and the second reflective layer RFL2 can be formed to include a substrate surface BS parallel to the substrate SUB and a first inclined surface SS1 and a second inclined surface SS2 extending from the substrate surface BS. Here, each of the first inclined surface SS1 and the second inclined surface SS2 can have a shape inclined at an angle (e.g., a set or predetermined angle) with respect to the substrate surface BS.

[0214] Referring to Figure 15 and Figure 18 , in S1040, a light-emitting structure EMS including a plurality of light-generating layers can be formed on the first anode electrode AE1 to the third anode electrode AE3 and the pixel defining layer PDL.

[0215] The light-emitting structure EMS can include a low-molecular or high-molecular organic material. The light-emitting structure EMS can be formed by vapor deposition technology, printing technology, slit coating technology, etc., but is not limited thereto. The light-emitting structure EMS can be formed on a part of the first anode electrode AE1 to the third anode electrode AE3 and the pixel defining layer PDL. The light-emitting structure EMS can also be formed on the first reflective layer RFL1 and the second reflective layer RFL2.

[0216] Referring to Figure 15 and Figure 18 , in S1050, a cathode electrode CE can be formed on the light-emitting structure EMS. The cathode electrode CE can be a common electrode commonly formed in the first sub-pixel SP1 to the third sub-pixel SP3.

[0217] Referring to Figure 19 , an encapsulation layer TFE, an adhesive layer APL, an optical function layer OFL, a color filter layer CFL, a first color filter CF1 to a third color filter CF3, a first lens LS1 to a third lens LS3, a lens array LA, an outer coating OC, and a cover window CW can be provided on the cathode electrode CE.

[0218] Referring to Figure 15 and Figure 19 , in S1060, a mask MSK having a first opening M_OP1 and a second opening M_OP2 can be positioned on the cover window CW. The mask MSK can be positioned such that the first opening M_OP1 and the second opening M_OP2 respectively overlap with a first trench TRCH1 and a second trench TRCH2 between the first anode electrode AE1 to the third anode electrode AE3. Specifically, the mask MSK can be positioned such that the first opening M_OP1 and the second opening M_OP2 respectively overlap with the first reflective layer RFL1 and the second reflective layer RFL2.

[0219] Referring to Figure 15 and Figure 19, in S1060, ultraviolet light UV can be irradiated through the first opening M_OP1 and the second opening M_OP2 of the mask MSK. The ultraviolet light UV can be irradiated onto the light-emitting structure EMS through the first opening M_OP1 and the second opening M_OP2 of the mask MSK. Additionally, the ultraviolet light UV can be reflected back to the light-emitting structure EMS by the first reflective layer RFL1 and the second reflective layer RFL2. The light-emitting structure EMS can be exposed not only to the irradiated ultraviolet light UV but also to the ultraviolet light UV reflected by the first reflective layer RFL1 and the second reflective layer RFL2. Accordingly, at least a portion of the layers in the light-emitting structure EMS can be disconnected or bent on the first reflective layer RFL1 and the second reflective layer RFL2 by a small amount of ultraviolet light UV. For example, the disconnected layer in the light-emitting structure EMS can be the charge generation layer CGL and the p-hole injection layer p-HIL.

[0220] In the display device and the method of manufacturing the display device according to the disclosed embodiments, by arranging (or forming) the reflective layer to surround each of the anode electrodes, at least a portion of the layers constituting the light-emitting structure can be effectively disconnected by ultraviolet light UV. Accordingly, the lateral leakage phenomenon caused by commonly disposing the light-emitting structure in the sub-pixels can be effectively improved.

[0221] According to the disclosed embodiments, there is provided a display device having relatively improved reliability and a method of manufacturing the display device.

[0222] The effects according to the embodiments are not limited to those described above, and further various effects are included in the present specification.

[0223] Although specific embodiments and application examples are described herein, other embodiments and modifications can be derived from the above description. Accordingly, the spirit of the disclosure is not limited to such embodiments and extends to the scope of the following claims and their equivalents.

Claims

1. A display device, the display device comprising: a substrate; a pixel circuit layer on the substrate; anode electrodes on the pixel circuit layer; a pixel defining layer on a part of the anode electrodes and the pixel circuit layer, and having a recessed shape in a direction facing the substrate between the anode electrodes, wherein the recessed shape is disposed along the periphery of each of the anode electrodes; a light-emitting structure on the anode electrodes and the pixel defining layer, and comprising a plurality of light-generating layers; a cathode electrode on the light-emitting structure; and a reflective layer superimposed on the recessed shape and located between the light-emitting structure and the pixel circuit layer.

2. The display device according to claim 1, wherein, The reflective layer is disposed along the periphery of each of the anode electrodes.

3. The display device according to claim 1, wherein The reflective layer comprises the same material as the anode electrodes.

4. The display device according to claim 1, wherein, A sub-groove further recessed from the recessed shape is between one of the anode electrodes and the reflective layer, and the sub-groove is disposed along the periphery of the one anode electrode.

5. The display device according to claim 1, wherein, The light-emitting structure comprises at least two light-emitting units stacked in sequence and at least one charge generation layer between the at least two light-emitting units, each of the at least two light-emitting units comprises a light-emitting layer, and the at least one charge generation layer is interrupted in a region superimposed on the recessed shape.

6. The display device according to claim 1, wherein, The reflective layer has a lower surface adjacent to the substrate and an upper surface opposite to the lower surface, and the upper surface of the reflective layer has a recessed shape in the direction facing the substrate.

7. The display device according to claim 6, wherein, The lower surface of the reflective layer has a recessed shape in the direction facing the substrate.

8. The display device according to claim 1, wherein, The reflective layer comprises a matrix surface parallel to the substrate and inclined surfaces extending from the matrix surface, and each of the inclined surfaces is inclined at a predetermined angle with respect to the matrix surface.

9. The display device according to claim 8, wherein, Each of the inclined surfaces has an angle of 45 degrees or more with respect to the matrix surface.

10. The display device according to claim 8, wherein, The reflective layer has a first width, and the matrix surface has a second width narrower than the first width.

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