Display device and method of manufacturing same

Abstract

The invention relates to a display device and a manufacturing method thereof. The display device includes a substrate. The pixel circuit layer is arranged on the substrate. The pattern layer is disposed on the pixel circuit layer and includes a first region and a second region not including the first region. The first region is defined by the opening. The thin film encapsulation layer is disposed only in the first region over the pixel circuit layer, and includes a plurality of inorganic material layers having densities different from each other. The thin film encapsulation layer includes a first inorganic material layer disposed in the first region and having a first density. The second inorganic material layer is disposed on the first inorganic material layer and has a second density greater than the first density. The third inorganic material layer is disposed on the second inorganic material layer and has a third density less than the second density.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0003637, filed with the Korean Intellectual Property Office on January 9, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] One or more embodiments relate to a display device and a method of manufacturing the same, and more particularly, to a display device including a thin - film encapsulation layer formed only in a desired region and a method of manufacturing the display device. Background art

[0004] A display device is configured to receive information about an image and display the image to a viewer. The display device can be used as a display unit of a small electronic product (such as a mobile phone) and can also be used as a display unit of a larger electronic product (such as a television).

[0005] A display device includes a plurality of pixels that receive an electrical signal and emit light to display an image to a viewer. Each pixel includes a light - emitting element. As an example, an organic light - emitting display device includes an organic light - emitting diode as the light - emitting element. Generally, an organic light - emitting display device includes thin - film transistors and organic light - emitting diodes on a substrate. The organic light - emitting diodes emit light by themselves in response to an electrical signal from the thin - film transistors and do not require a backlight.

[0006] A display device may include a thin - film encapsulation layer formed on its entire surface. Since the thin - film encapsulation layer is formed on the entire surface of the display device, the thin - film encapsulation layer may not be formed only in a desired region. Summary of the invention

[0007] One or more embodiments include a display device including a thin - film encapsulation layer formed only in a desired region and a method of manufacturing the display device. However, such a technical objective is for example, and aspects of the embodiments of the present disclosure are not limited thereto.

[0008] Additional aspects will be set forth in part in the following description and in part will be obvious from the description, or may be learned by practice of the presented embodiments of the present disclosure.

[0009] According to an embodiment of the present disclosure, a display device includes a substrate. A pixel circuit layer is disposed on the substrate. A pattern layer is disposed on the pixel circuit layer and includes a first region and a second region excluding the first region. The first region is defined by an opening. A thin film encapsulation layer is disposed only in the first region, above the pixel circuit layer, and includes a plurality of inorganic material layers having different densities from each other. The thin film encapsulation layer includes a first inorganic material layer disposed in the first region and having a first density. A second inorganic material layer is disposed on the first inorganic material layer and has a second density greater than the first density. A third inorganic material layer is disposed on the second inorganic material layer and has a third density less than the second density.

[0010] In an embodiment, a lower surface of the second inorganic material layer may be in direct contact with an upper surface of the first inorganic material layer.

[0011] In an embodiment, an upper surface of the second inorganic material layer may be in direct contact with a lower surface of the third inorganic material layer.

[0012] In an embodiment, the display device may further include a light emitting diode disposed in the first region, between the pixel circuit layer and the first inorganic material layer.

[0013] In an embodiment, the display device may further include a capping layer disposed between the pixel circuit layer and the pattern layer.

[0014] In an embodiment, a thickness of the second inorganic material layer may be less than a thickness of the first inorganic material layer.

[0015] In an embodiment, a thickness of the second inorganic material layer may be less than a thickness of the third inorganic material layer.

[0016] In an embodiment, a thickness of the second inorganic material layer may be in a range of about 10% to about 20% of a thickness of the third inorganic material layer.

[0017] In an embodiment, the first density may be the lowest density among the first density to the third density.

[0018] In an embodiment, a first adsorption force between an upper surface of the pattern layer and the thin film encapsulation layer may be less than a second adsorption force between an upper surface of the capping layer and the thin film encapsulation layer.

[0019] In an embodiment, the pattern layer may include a metal oxide material.

[0020] In an embodiment, the pattern layer may include aluminum oxide.

[0021] According to an embodiment of the present disclosure, a method of manufacturing a display device includes: forming a pixel circuit layer on a substrate; forming a pattern layer on the pixel circuit layer; forming an opening in the pattern layer, the opening corresponding to a pattern of a preset shape; forming a first inorganic material layer covering the opening and having a first density; forming a second inorganic material layer on the first inorganic material layer and having a second density greater than the first density; and forming a third inorganic material layer on the second inorganic material layer and having a third density less than the second density.

[0022] In an embodiment, a lower surface of the second inorganic material layer may be in direct contact with an upper surface of the first inorganic material layer.

[0023] In an embodiment, an upper surface of the second inorganic material layer may be in direct contact with a lower surface of the third inorganic material layer.

[0024] A thickness of the second inorganic material layer may be less than a thickness of the first inorganic material layer.

[0025] In an embodiment, a thickness of the second inorganic material layer may be less than a thickness of the third inorganic material layer.

[0026] In an embodiment, a thickness of the second inorganic material layer may be in a range of about 10% to about 20% of a thickness of the third inorganic material layer.

[0027] In an embodiment, forming the pattern layer on the pixel circuit layer may include forming a capping layer on the pixel circuit layer and forming the pattern layer on the capping layer.

[0028] In an embodiment, the first inorganic material layer to the third inorganic material layer form a thin film encapsulation layer, and a first adsorption force between an upper surface of the pattern layer and the thin film encapsulation layer may be less than a second adsorption force between an upper surface of the capping layer and the thin film encapsulation layer.

[0029] According to an embodiment of the present disclosure, a display device includes a substrate, the substrate including a covering region and a non-covering region. The covering region is arranged in a pattern of a preset shape. A pixel circuit layer is disposed on the substrate. A light emitting diode is disposed on the pixel circuit layer. The pattern layer covers the pixel circuit layer in the non-covering region and has an opening in the covering region. The thin film encapsulation layer is disposed only in the opening of the pattern layer in the covering region. The thin film encapsulation layer is arranged in a pattern of a preset shape and encapsulates the light emitting diode. The thin film encapsulation layer includes a plurality of inorganic material layers having different densities from each other.

[0030] In an embodiment, the thin film encapsulation layer includes a first inorganic material layer. A second inorganic material layer is directly disposed on the first inorganic material layer and has a density greater than a density of the first inorganic material layer. A third inorganic material layer is disposed on the second inorganic material layer and has a density less than a density of the second inorganic material layer.

[0031] In an embodiment, the thickness of the second inorganic material layer is less than the thicknesses of the first inorganic material layer and the third inorganic material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a schematic plan view of a display panel of a display device according to an embodiment of the present disclosure;

[0034] Figure 2 and Figure 3 is a perspective view showing an example of a display device according to an embodiment of the present disclosure Figure 1 in a stretched state;

[0035] Figure 4 is an equivalent circuit diagram of an example of a pixel included in a display panel according to an embodiment of the present disclosure Figure 1 ;

[0036] Figure 5 is a schematic plan view of an example of region A according to an embodiment of the present disclosure Figure 1 ;

[0037] Figure 6 is a schematic cross-sectional view of an example of a display device taken along line I-I' according to an embodiment of the present disclosure Figure 5 ; Figure 1 ;

[0038] Figure 7 is a schematic cross-sectional view of a thin film encapsulation layer according to an embodiment of the present disclosure Figure 5 ;

[0039] Figure 8 is a schematic cross-sectional view of an example of a display device taken along line II-II' according to an embodiment of the present disclosure Figure 5 ; Figure 1 ;

[0040] Figures 9 to 13 is a cross-sectional view sequentially showing a manufacturing method of a display device according to an embodiment of the present disclosure; and

[0041] Figure 14 is a schematic cross-sectional view of an example of a part of a display device according to a comparative example. DETAILED DESCRIPTION

[0042] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the embodiments of the present disclosure may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by referring to the drawings to explain aspects of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the present disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variants thereof.

[0043] Since the present disclosure allows for various changes and many embodiments, certain non-limiting embodiments will be illustrated in the drawings and described in the written description. The effects and features of the present disclosure and the methods for achieving them will be clarified with reference to the embodiments described in detail below with reference to the drawings. However, the present disclosure need not be limited to the described embodiments and can be implemented in various forms.

[0044] Hereinafter, embodiments will be described with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout, and their repeated description will be omitted.

[0045] Although terms such as "first" and "second" may be used to describe various elements, such elements need not be limited by the above terms. The above terms are used to distinguish one element from another. In addition, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0046] As used herein, when various elements (such as layers, regions, and plates, etc.) are provided "on" another element, not only can the element be "directly" provided "on" the other element, but also another element can be provided between them. When various elements (such as layers, regions, and plates, etc.) are "directly" provided "on" another element, there may be no intervening element therebetween.

[0047] In addition, for ease of explanation, the dimensions of the elements in the drawings may be enlarged or reduced. By way of example, for ease of description, the dimensions (e.g., thickness) of each element shown in the drawings may be arbitrarily represented, and thus, the embodiments of the present disclosure need not be limited thereto.

[0048] It will be understood that as used herein, the terms "comprise", "comprising", "include" and / or "including" indicate the presence of the recited features or elements, but do not preclude the addition of one or more other features or elements.

[0049] In cases where some of these embodiments may be implemented differently, a particular process order may be performed in an order different from the described order. As an example, two processes described consecutively may be performed substantially simultaneously and may be performed in a reverse order.

[0050] In this specification, "A and / or B" means A or B, or A and B. In this specification, "at least one of A and B" means A or B, or A and B.

[0051] It will be understood that when a layer, region, or element is referred to as being "connected" to another layer, region, or element, it may be "directly connected" to the other layer, region, or element, or may be "indirectly connected" to the other layer, region, or element with another layer, region, or element therebetween. For example, it will be understood that when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it may be "directly electrically connected" to the other layer, region, or element, or may be "indirectly electrically connected" to the other layer, region, or element with another layer, region, or element inserted therebetween.

[0052] The x-direction, y-direction, and z-direction need not be limited to the directions corresponding to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the x-direction, y-direction, and z-direction may be perpendicular to each other, or may represent different orientations that cross each other but are not perpendicular to each other. The -x-direction, -y-direction, and -z-direction represent the directions opposite to the x-direction, y-direction, and z-direction, respectively.

[0053] Hereinafter, a display device according to an embodiment and a method of manufacturing the same will be described in detail.

[0054] Figure 1 is a schematic plan view of a display panel of a display device according to an embodiment.

[0055] As Figure 1 shown, a display device according to an embodiment may include a display panel 10. The display panel 10 may be applied to various different display devices. As an example, the display device may be various devices such as a smartphone, a tablet computer, a laptop computer, a television, or a billboard. The display device according to an embodiment includes thin film transistors and capacitors, etc., and the thin film transistors and capacitors, etc. may be implemented by a conductive layer and an insulating layer.

[0056] The display panel 10 includes a display area DA and a peripheral area PA (e.g., in the x-direction and / or y-direction) located outside the display area DA. In Figure 1 it is shown that the display area DA (e.g., in a plane defined in the x-direction and y-direction) has a rectangular shape. However, embodiments of the present disclosure need not be limited thereto. The display area DA may have various shapes, for example, a circular shape, an oval shape, other polygonal shapes, or the shape of a specific figure.

[0057] The display area DA is an area where an image is displayed, and a plurality of pixels PX may be arranged in the display area DA. Each pixel PX may include a light-emitting element (such as an organic light-emitting diode). In an embodiment, each pixel PX may be configured to emit, for example, red, green, or blue light. The pixel PX may be connected to a pixel circuit including a thin-film transistor and a storage capacitor, etc. The pixel circuit may be connected to a scan line SL, a data line DL, and a driving voltage line PWL. In an embodiment, the scan line SL is configured to transmit a scan signal, the data line DL intersects the scan line SL and is configured to transmit a data signal, and the driving voltage line PWL is configured to supply a driving voltage. The scan line SL may extend in the x direction (hereinafter, referred to as the second direction), and the data line DL and the driving voltage line PWL may extend in the y direction (hereinafter, referred to as the first direction).

[0058] The pixel PX may be configured to emit light corresponding to the luminance of an electrical signal from the pixel circuit electrically connected thereto. The display area DA may be configured to display a preset image by using the light emitted from the pixel PX. As a reference, as described above, the pixel PX may be defined as an emission area configured to emit light of one of red, green, and blue. However, embodiments of the present disclosure are not necessarily limited thereto, and the color of the pixel PX may vary.

[0059] The outer peripheral area PA is an area where no pixel PX is arranged, and may be an area configured not to display an image. In an embodiment, a power supply line or the like for driving the pixel PX may be arranged in the outer peripheral area PA. Additionally, pads may be arranged in the outer peripheral area PA. A printed circuit board including a driving circuit portion or an integrated circuit element (such as a driving integrated circuit (IC)) may be arranged to be electrically connected to the plurality of pads.

[0060] As a reference, since the display panel 10 includes the substrate 100, it can be understood that the substrate 100 includes the display area DA and the outer peripheral area PA. The substrate 100 will be described in detail below.

[0061] Additionally, the area A may represent a part of the display area DA. For ease of description, the area A will be mainly described below, and the structure of the display area DA may be understood as repeating the structure of the area A, or may be understood as a structure similar to the structure of the area A.

[0062] Additionally, a plurality of transistors may be arranged in the display area DA. Depending on the type of transistor (e.g., N-type or P-type) and / or operating conditions, the first terminal of each of the plurality of transistors may be a source electrode or a drain electrode, and the second terminal may be an electrode different from the first terminal. As an example, in an embodiment where the first terminal is a source electrode, the second terminal may be a drain electrode.

[0063] In an embodiment, the plurality of transistors may include a driving transistor, a data writing transistor, a compensating transistor, an initializing transistor, and an emission control transistor. The driving transistor may be connected between a driving voltage line PWL (see Figure 4 ) and an organic light-emitting diode OLED (see Figure 4 ), and the data writing transistor may be connected to a data line DL and the driving transistor, and may perform a switching operation of transmitting a data signal transmitted through the data line DL to the driving transistor.

[0064] In an embodiment, the compensating transistor may be configured to connect the driving transistor to the organic light-emitting diode OLED (see Figure 4 ) by being turned on according to a scan signal transmitted through a scan line SL to compensate for the threshold voltage of the driving transistor.

[0065] The initializing transistor may be configured to initialize the gate electrode of the driving transistor by being turned on according to a scan signal (the scan signal is transmitted through the scan line SL) and transmitting an initialization voltage to the gate electrode of the driving transistor. The scan line connected to the initializing transistor may be a separate scan line different from the scan line connected to the compensating transistor.

[0066] In an embodiment, the emission control transistor may be turned on according to an emission control signal transmitted through an emission control line, and as a result, a driving current may flow through the organic light-emitting diode OLED (see Figure 4 ).

[0067] The organic light-emitting diode OLED (see Figure 4 ) may include a pixel electrode (e.g., an anode) and a counter electrode (e.g., a cathode), and the counter electrode layer 170 (see Figure 6 ) may be configured to receive a second power supply voltage ELVSS (see Figure 4 ). The organic light-emitting diode OLED (see Figure 4 ) may be configured to display an image by receiving a driving current from the driving transistor and emitting light.

[0068] Hereinafter, although the organic light-emitting display device is described as an example of the display device according to the embodiment, the display device is not necessarily limited thereto. For example, in some embodiments of the present disclosure, the display device may be an inorganic light-emitting display device or a quantum dot light-emitting display device. As an example, the emission layer of the display element of the display device may include an organic material or an inorganic material. Additionally, the display device may include an emission layer and quantum dots provided on a path of light emitted from the emission layer.

[0069] Figure 2 and Figure 3 is a perspective view showing an example of the display device in a stretched state for showing Figure 1 .

[0070] As Figure 2 shown, in an embodiment, the display area DA and / or the outer peripheral area PA of the display panel 10 may be stretched in a first direction (e.g., the y-direction and / or the -y direction). As an example, the display panel 10 may be stretched in the y-direction and the -y direction. In some embodiments, different from the embodiment shown in Figure 2 , the display panel 10 may be stretched in the y-direction while being fixed on one side of the display panel 10.

[0071] As Figure 3 shown, in an embodiment, due to an external force applied by an external object or a part of a human body, the display panel 10 may be stretched in a plurality of directions (e.g., a first direction (e.g., the y-direction and / or the -y direction) and a second direction (e.g., the x-direction and / or the -x direction)). The display area DA and / or the outer peripheral area PA of the display panel 10 may be stretched in the ±x direction and the ±y direction.

[0072] Figure 4 Figure Figure 1 is an equivalent circuit diagram of an example of a pixel included in the display panel 10.

[0073] As Figure 4 shown, each pixel PX may include a pixel circuit PC and a light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC is connected to a scan line SL and a data line DL.

[0074] In an embodiment, the pixel circuit PC includes a driving thin film transistor Td, a switching thin film transistor Ts, and a storage capacitor Cst. The switching thin film transistor Ts is connected to the scan line SL and the data line DL, and is configured to transmit a data signal Dm to the driving thin film transistor Td according to a scan signal Sn. The data signal Dm is input through the data line DL, and the scan signal Sn is input through the scan line SL.

[0075] The storage capacitor Cst may be connected to the switching thin film transistor Ts and a driving voltage line PWL, and is configured to store a voltage corresponding to the difference between the voltage transmitted from the switching thin film transistor Ts and a first power supply voltage ELVDD supplied to the driving voltage line PWL.

[0076] In an embodiment, the second power supply voltage ELVSS may be a driving voltage having a level lower than that of the first power supply voltage ELVDD. The level of the driving voltage supplied to each pixel PX may be the difference between the first power supply voltage ELVDD and the second power supply voltage ELVSS.

[0077] The driving thin-film transistor Td can be connected to the driving voltage line PWL and the storage capacitor Cst, and is configured to control the driving current according to the voltage stored in the storage capacitor Cst. The driving current flows from the driving voltage line PWL to the light-emitting diode OLED. The light-emitting diode OLED can be configured to emit light with a preset brightness corresponding to the driving current.

[0078] Although the pixel circuit PC is described with reference Figure 4 to including two thin-film transistors and one storage capacitor, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, the pixel circuit PC may include two or more storage capacitors.

[0079] Figure 5 For Figure 1 an example of the region A of

[0080] As a reference, in Figure 5 the description, for the sake of simplicity of description, content that is the same as or repetitive of the above may be omitted.

[0081] As Figure 5 shown in Figure 5 , the covering region CA and the non-covering region NCA may be arranged in the region A. However,

[0082] the pattern including the covering region CA and the non-covering region NCA shown in Figure 6 may be merely an example, and embodiments of the present disclosure are not necessarily limited thereto. Figure 8

[0083] In an embodiment, the covering region CA may have a pattern with a preset shape. The light-emitting diode OLED (see Figure 4 ) etc. may be arranged in the covering region CA, and the thin-film encapsulation layer 300 may be configured to encapsulate the light-emitting diode OLED (see Figure 4 ) etc. arranged in the covering region CA. Hereinafter, the covering region CA according to the present disclosure may be referred to as the first region.

[0084] The covering region CA may be defined by an opening included in the pattern layer PL. In an embodiment, the covering region CA may be defined by the thin-film encapsulation layer 300 covering the opening included in the covering pattern layer PL. In a plan view, the covering region CA may be the thin-film encapsulation layer 300 covering the opening included in the covering pattern layer PL.

[0085] The non-covering region NCA may be arranged in the pixel circuit layer PCL (seeFigure 6 ) In the plan view, the non-covered area NCA can be covered by the pattern layer PL.

[0086] As an example, in an embodiment, the non-covered area NCA can be a stretchable area. In some embodiments, the components arranged in the non-covered area NCA can be configured to be stretchable due to an external force. Additionally, according to the property that the non-covered area NCA is stretchable due to an external force, the pattern layer PL arranged in the non-covered area NCA can have a stretchable structure or include a stretchable material.

[0087] The pattern layer PL and the thin film encapsulation layer 300 will be specifically described below.

[0088] Figure 6 For an example of a display device taken along the Figure 5 line I-I' according to an embodiment of the present disclosure. Figure 1 Schematic cross-sectional view.

[0089] Referring to Figure 1 and Figure 6 , as described above, the substrate 100 can include regions corresponding to the display area DA and the peripheral area PA (e.g., in the x direction and / or y direction) located outside the display area DA. In an embodiment, the substrate 100 can include various flexible or bendable materials. As an example, the substrate 100 can include glass, metal, or polymer resin. Additionally, the substrate 100 can include polymer resins (such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate). In an embodiment, the substrate 100 can have a multilayer structure including two layers (each layer including a polymer resin) and an isolation layer (including an inorganic material, e.g., silicon oxide, silicon nitride, and / or silicon oxynitride) located between the two layers. However, the embodiments of the present disclosure are not limited thereto, and various modifications can be made.

[0090] The buffer layer 101 can be disposed on the substrate 100 (e.g., directly disposed on the substrate 100 in the z direction). The buffer layer 101 can prevent the diffusion of impurity ions, prevent the penetration of moisture or external air, and act as a barrier layer and / or isolation layer for flattening the surface. In an embodiment, the buffer layer 101 can include silicon oxide, silicon nitride, and / or silicon oxynitride. Additionally, the buffer layer 101 can make the semiconductor layer 110 crystallize uniformly by adjusting the heating rate during the crystallization process for forming the semiconductor layer 110.

[0091] The semiconductor layer 110 may be disposed on the buffer layer 101 (e.g., directly on the buffer layer 101 in the z direction). In an embodiment, the semiconductor layer 110 may include polysilicon and include a channel region, a source region, and a drain region. The channel region is not doped with impurities, and the source region and the drain region are located on two opposite sides of the channel region and doped with impurities. Here, the impurities may vary according to the type of thin film transistor. For example, the impurities may be N-type impurities or P-type impurities.

[0092] The gate insulating layer 102 may be disposed on the semiconductor layer 110 (e.g., directly on the semiconductor layer 110). The gate insulating layer 102 may be a layer for ensuring insulation between the semiconductor layer 110 and the gate layer (such as the first gate layer 120a). In an embodiment, the gate insulating layer 102 may include an inorganic material (such as silicon oxide, silicon nitride, and / or silicon oxynitride) and may be disposed (e.g., in the z direction) between the semiconductor layer 110 and the gate layer (such as the first gate layer 120a). In an embodiment, the gate insulating layer 102 may have a shape corresponding to the entire surface of the substrate 100 and have a structure in which contact holes are formed in a preset portion thereof. As described above, in an embodiment, the insulating layer including an inorganic material may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). This also applies to the following embodiments and their modifications.

[0093] The first gate layer 120a may be disposed on the gate insulating layer 102 (e.g., directly on the gate insulating layer 102 in the z direction). In an embodiment, the first gate layer 120a may be disposed at a position vertically overlapping with the semiconductor layer 110 and may include at least one metal among molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu).

[0094] The first interlayer insulating layer 103a may be disposed on the first gate layer 120a (e.g., directly on the first gate layer 120a). The first interlayer insulating layer 103a may cover the first gate layer 120a. In an embodiment, the first interlayer insulating layer 103a may include an inorganic material. As an example, the first interlayer insulating layer 103a may include a metal oxide or a metal nitride, and specifically, the inorganic material may include silicon oxide (SiO x ), silicon nitride (SiN y ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x , which is ZnO and / or ZnO2). In an embodiment, the first interlayer insulating layer 103a may have SiO x / SiN y dual structure.

[0095] The second gate layer 120b may be disposed on the first interlayer insulating layer 103a (e.g., directly disposed on the first interlayer insulating layer 103a in the z direction). In an embodiment, the second gate layer 120b may be disposed at a position vertically overlapping with the first gate layer 120a, and may include at least one metal among molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu).

[0096] The second gate layer 120b may cooperate with the first gate layer 120a to form a storage capacitor Cst. The first gate layer 120a may be the first electrode of the storage capacitor Cst, and the second gate layer 120b may be the second electrode of the storage capacitor Cst.

[0097] When observed in a direction perpendicular to the substrate 100, the area of the second gate layer 120b may be larger than the area of the first gate layer 120a. Alternatively, when observed in a direction perpendicular to the substrate 100, the second gate layer 120b may cover the first gate layer 120a and have an area substantially similar to that of the first gate layer 120a.

[0098] The second interlayer insulating layer 103b may be disposed on the second gate layer 120b (e.g., directly disposed on the second gate layer 120b). The second interlayer insulating layer 103b may cover the second gate layer 120b. The second interlayer insulating layer 103b may include an inorganic material. As an example, in an embodiment, the second interlayer insulating layer 103b may include a metal oxide or a metal nitride, and specifically, the inorganic material may include silicon oxide (SiO x ), silicon nitride (SiN y ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x , which is ZnO or ZnO2). In an embodiment, the second interlayer insulating layer 103b may have a SiO x / SiN y or SiN x / SiO y dual structure.

[0099] The first conductive layer 130 may be disposed on the second interlayer insulating layer 103b (e.g., directly disposed on the second interlayer insulating layer 103b in the z direction). The first conductive layer 130 may be used as an electrode connected to the source / drain regions of the semiconductor layer 110 through contact holes included in the second interlayer insulating layer 103b, the first interlayer insulating layer 103a, and the gate insulating layer 102. In an embodiment, the first conductive layer 130 may include at least one metal among aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). As an example, the first conductive layer 130 may include a Ti layer, an Al layer, and / or a Cu layer.

[0100] The first organic insulating layer 104 may be disposed on the first conductive layer 130 (e.g., directly disposed on the first conductive layer 130). The first organic insulating layer 104 may cover the first conductive layer 130, have an approximately flat upper surface, and may be an organic insulating layer serving as a planarization layer. In an embodiment, the first organic insulating layer 104 may include an organic material, such as acrylic acid, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). The first organic insulating layer 104 may include a single layer or multiple layers. However, embodiments of the present disclosure are not necessarily limited thereto, and various modifications may be made.

[0101] The second conductive layer 140 may be disposed on the first organic insulating layer 104 (e.g., directly disposed on the first organic insulating layer 104 in the z direction). The second conductive layer 140 may be used as an electrode connected to the source / drain regions of the semiconductor layer 110 through contact holes included in the first organic insulating layer 104. In an embodiment, the second conductive layer 140 may include at least one metal among aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). As an example, the second conductive layer 140 may include a Ti layer, an Al layer, and / or a Cu layer.

[0102] The second organic insulating layer 105 may be disposed on the second conductive layer 140 (e.g., directly disposed on the second conductive layer 140). The second organic insulating layer 105 may cover the second conductive layer 140, have an approximately flat upper surface, and may be an organic insulating layer serving as a planarization layer. In an embodiment, the second organic insulating layer 105 may include an organic material, such as acrylic acid, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). The second organic insulating layer 105 may include a single layer or multiple layers. However, various modifications may be made.

[0103] In addition, in an embodiment, an additional conductive layer and an additional insulating layer may be provided between the conductive layer and the pixel electrode. In this embodiment, the additional conductive layer may include the same material as that of the conductive layer and have a layered structure identical to that of the conductive layer. The additional insulating layer may include the same material as that of the organic insulating layer and have a layered structure identical to that of the organic insulating layer.

[0104] The pixel electrode layer 150 may be provided on the second organic insulating layer 105 (e.g., directly provided on the second organic insulating layer 105 in the z direction). In an embodiment, the pixel electrode layer 150 may be connected to the second conductive layer 140 through a contact hole formed in the second organic insulating layer 105. The display element may include the pixel electrode layer 150. A light-emitting diode OLED may be used as the display element. For example, the light-emitting diode OLED may be provided on the second organic insulating layer 105. In an embodiment, the pixel electrode layer 150 may include a light-transmissive conductive layer and a reflective layer, where the light-transmissive conductive layer includes a light-transmissive conductive oxide (such as indium tin oxide (ITO), indium oxide (In2O3), or indium zinc oxide (IZO)), and the reflective layer includes a metal (such as aluminum (Al) or silver (Ag)). As an example, the pixel electrode layer 150 may have a three-layer structure of ITO / Ag / ITO.

[0105] For ease of description, although the pixel electrode layer 150 is shown as a pixel electrode corresponding to one pixel in Figure 6 , the pixel electrode layer 150 may represent a configuration including pixel electrodes arranged for each pixel. As an example, the pixel electrode layer 150 may be used as a term including the first pixel electrode and the second pixel electrode described below.

[0106] The pixel defining layer 106 may be provided on the second organic insulating layer 105 and arranged to cover the edge of the pixel electrode layer 150. The pixel defining layer 106 may cover the edge of the pixel electrode layer 150. The pixel defining layer 106 has an opening corresponding to the pixel PX ( Figure 1 ), and the opening may be formed to expose at least the central portion of the pixel electrode layer 150. In an embodiment, the pixel defining layer 106 may include an organic material (such as polyimide or HMDSO). In addition, a spacer 80 (see Figure 14 ) may be provided on the pixel defining layer 106.

[0107] The intermediate layer 160 and the counter electrode layer 170 may be disposed in the opening of the pixel defining layer 106. In an embodiment, the intermediate layer 160 may include a low molecular weight material or a polymeric material. In an embodiment where the intermediate layer 160 includes a low molecular weight material, the intermediate layer 160 may include a hole injection layer, a hole transport layer, an electron transport layer, and / or an electron injection layer. In an embodiment where the intermediate layer 160 includes a polymeric material, the intermediate layer 160 generally may have a structure including a hole transport layer and an emission layer.

[0108] The counter electrode layer 170 may include a transparent conductive layer including a transparent conductive oxide (such as ITO, In2O3, or IZO). The pixel electrode layer 150 serves as an anode, and the counter electrode layer 170 serves as a cathode. The polarities of the electrodes may be applied conversely.

[0109] The structure of the intermediate layer 160 is not necessarily limited to Figure 6 the embodiment shown, and may have various different structures. As an example, at least one of the layers constituting the intermediate layer 160 may be integrally formed like the counter electrode layer 170. In some embodiments, the intermediate layer 160 may include a layer patterned to correspond to each of the plurality of pixel electrode layers 150.

[0110] The counter electrode layer 170 may be disposed in the upper portion of the display area DA and disposed over the entire surface of the display area DA. For example, the counter electrode layer 170 may be integrally formed to cover a plurality of pixels. In an embodiment, the counter electrode layer 170 may be in electrical contact with a common power line (not shown) disposed in the peripheral area PA.

[0111] The thin film encapsulation layer 300 may be disposed on the counter electrode layer 170. The thin film encapsulation layer 300 may be a layer for encapsulating the organic light emitting element. In an embodiment, the thin film encapsulation layer 300 may include only a plurality of inorganic material layers.

[0112] In an embodiment, a capping layer 107 or a filling material (not shown) may be disposed between the thin film encapsulation layer 300 and the counter electrode layer 170, or between the thin film encapsulation layer 300 and another element. As an example, the capping layer 107 may be formed to cover the counter electrode layer 170. In an embodiment, the capping layer 107 may include an organic material (such as N,N'-bis(naphthalen-1-yl)-N,N'-bis(phenyl)-2,2”-dimethylbenzidine (α-NPD), N,N'-di(naphthalen-1-yl)-N,N'-diphenylbenzidine (NPB), N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine (TPD), 4,4',4”-tris(3-methylphenyl)phenylamino]triphenylamine (m-MTDATA), tris(8-hydroxyquinolinato)aluminum (Alq3) or CuPc), and helps to effectively emit the light generated from the light emitting diode OLED, as well as protect the light emitting diode OLED.

[0113] As an example, the filling material (not shown) may fill the space between the thin film encapsulation layer 300 and the counter electrode layer 170. As an example, the filling material may include materials such as epoxy-based materials and acrylate-based materials (for example, epoxy acrylate-based materials).

[0114] As Figure 6 shown, the semiconductor layer 110, the first gate layer 120a and the second gate layer 120b may form a thin film transistor portion TFT. The thin film transistor portion TFT may be used as any one of the thin film transistors included in the pixel circuit PC described Figure 4 above.

[0115] In the present disclosure, the pixel circuit layer PCL may be defined as an element including layers disposed between the substrate 100 and the pixel electrode layer 150. As an example, the pixel circuit layer PCL may include the thin film transistor portion TFT.

[0116] The light emitting diode OLED may be disposed on the pixel circuit layer PCL. The light emitting diode OLED may be an element including the pixel electrode layer 150, the intermediate layer 160 and the counter electrode layer 170. As an example, in an embodiment, the light emitting diode OLED may be an organic light emitting diode or the like.

[0117] Figure 7 For Figure 5 a schematic cross-sectional view of the thin film encapsulation layer 300.

[0118] As a reference, in the description of the thin film encapsulation layer 300 in Figure 7 the above, for the sake of simplicity of description, the same or repeated content as the above may be omitted.

[0119] As Figure 7As shown, in an embodiment, the thin film encapsulation layer 300 may include, for example, a first inorganic material layer 310, a second inorganic material layer 320, and a third inorganic material layer 330 that are continuously stacked in the z direction. Different from the thin film encapsulation member according to the prior art, the thin film encapsulation layer 300 may not include an organic material layer. For example, the thin film encapsulation layer 300 may only include a plurality of layers containing inorganic materials. Although Figure 7 the embodiment in

[0120] shows that the thin film encapsulation layer 300 includes three inorganic material layers, the embodiments of the present disclosure are not necessarily limited thereto, and the number of the plurality of inorganic material layers having different densities in the thin film encapsulation layer may vary.

[0121] In an embodiment, the first inorganic material layer 310 may have a first density. The first inorganic material layer 310 may include at least one inorganic material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic material layer 310 may have a shape corresponding to the upper surface of the first region and have a structure covering the light emitting diode OLED formed in a preset portion. In an embodiment, the first inorganic material layer 310 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0122] The second inorganic material layer 320 may have a second density. In an embodiment, the second inorganic material layer 320 may include at least one inorganic material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The second inorganic material layer 320 may have a structure covering the first inorganic material layer 310. In an embodiment, the second inorganic material layer 320 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0123] The first inorganic material layer 310 to the third inorganic material layer 330 may have a barrier property against the penetration of impurities (such as oxygen and moisture, etc.).

[0124] According to an embodiment of the present disclosure, since the thin film encapsulation layer 300 does not include an organic material layer and the thin film encapsulation layer 300 is formed only using inorganic material layers having a density difference from each other, a thickness smaller than that of a thin film encapsulation member including an organic material layer according to the prior art can be achieved. In addition, according to an embodiment of the present disclosure, by using the pattern layer PL as a mask to form the first inorganic material layer 310 to the third inorganic material layer 330, the thin film encapsulation layer 300 can be formed only at desired positions.

[0125] The process of forming the thin film encapsulation layer 300 according to an embodiment of the present disclosure may be a process of depositing an inorganic material on the entire upper surface of the pixel circuit layer PCL, as in a thin film encapsulation member according to the prior art. In a thin film encapsulation member according to the prior art, it is difficult to form the thin film encapsulation member only at desired positions by depositing an inorganic material on the entire upper surface of the pixel circuit layer PCL. In contrast, according to an embodiment of the present disclosure, since the thin film encapsulation layer 300 is deposited using the pattern layer PL, the thin film encapsulation layer 300 can be formed in a region corresponding to the pattern formed in the pattern layer PL. Accordingly, the thin film encapsulation layer 300 can be deposited only in a desired region according to the pattern of the pattern layer PL.

[0126] As an example, the second density of the second inorganic material layer 320 may have the highest density among the first density to the third density. The second density of the second inorganic material layer 320 may be greater than the first density of the first inorganic material layer 310. The second density of the second inorganic material layer 320 may be greater than the third density of the third inorganic material layer 330. The first density of the first inorganic material layer 310 may be the lowest density among the first density to the third density.

[0127] Since the deposition rate of the deposition process for forming the second inorganic material layer 320 having the highest density is lower than the deposition rates of the deposition processes for forming the first inorganic material layer 310 and the third inorganic material layer 330, there may be a problem with process efficiency.

[0128] In an embodiment, to solve the process efficiency problem, the thickness h2 of the second inorganic material layer 320 having the highest density can be reduced. As an example, the thickness h2 of the second inorganic material layer 320 can be less than the thickness h1 of the first inorganic material layer 310 and the thickness h3 of the third inorganic material layer 330. As an example, in an embodiment, the thickness h2 of the second inorganic material layer 320 can be in the range of about 10% to about 20% of the thickness h3 of the third inorganic material layer 330. As an example, among the thicknesses h1, h2, and h3 of the first inorganic material layer 310 to the third inorganic material layer 330, the thickness h2 of the second inorganic material layer 320 having the highest density can be the smallest. As an example, among the thicknesses h1, h2, and h3 of the first inorganic material layer 310 to the third inorganic material layer 330, the thickness h1 of the first inorganic material layer 310 having the lowest density can be the largest.

[0129] As described above, in an embodiment of the present disclosure, the speed of the entire deposition process can be increased by reducing the thickness h2 of the second inorganic material layer 320 having the highest density. However, the thickness h2 of the second inorganic material layer 320 described above can still be sufficient to maintain the barrier property against the penetration of impurities (such as oxygen and moisture).

[0130] As an example, the lower surface of the second inorganic material layer 320 can be in direct contact with the upper surface of the first inorganic material layer 310. The upper surface of the second inorganic material layer 320 can be in direct contact with the lower surface of the third inorganic material layer 330.

[0131] Generally, an inorganic layer has the property of blocking the penetration of moisture and air, but due to the nature of the material, it may include particles (e.g., small dust). Due to the particles included due to the nature of the material, pores called pinholes may be generated. Accordingly, the thin film encapsulation member includes a monomer layer having a relatively thick thickness between the inorganic layers, rather than using a single inorganic layer.

[0132] To replace the role of the monomer layer according to the prior art, the thin film encapsulation layer 300 according to an embodiment of the present disclosure can include a second inorganic material layer 320 between the first inorganic material layer 310 and the third inorganic material layer 330. The density difference between the first inorganic material layer 310 and the third inorganic material layer 330 can prevent particles from affecting the image quality.

[0133] Accordingly, the second inorganic material layer 320 having a high density can surround the particles of the first inorganic material layer 310, flatten the particles, and prevent damage caused by the particles. As a result, the second inorganic material layer 320 and the third inorganic material layer 330 can be protected from damage caused by the particles.

[0134] Figure 8 For along Figure 5Schematic cross-sectional view of an example of a display device taken along line II-II'.

[0135] For reference, in Figure 8 the description, for the sake of brevity of description, content that is the same as or repetitive of the above may be omitted. Additionally, for ease of explanation and description, a part of the cross-sectional view of the non-covered area NCA in Figure 8 may be omitted.

[0136] As shown in Figure 8 , the pattern layer PL may be disposed in the non-covered area NCA, on the capping layer 107 (e.g., directly disposed in the non-covered area NCA, on the capping layer 107 in the z direction). The pattern layer PL may not be disposed in the covered area CA, on the capping layer 107. As an example, in an embodiment, the pattern layer PL may first be disposed on the capping layer 107 to completely cover the covered area CA and the non-covered area NCA. Then, an etching process using a mask having a preset shape of a pattern may be applied to the pattern layer PL. During the etching process, a part of the pattern layer PL corresponding to the covered area CA may be removed to form at least one opening OP. As a result, a part of the upper surface of the capping layer 107 may be exposed upward through the area where a part of the pattern layer PL corresponding to the covered area CA has been removed.

[0137] The first inorganic material layer 310 may be disposed in the area where a part of the pattern layer PL corresponding to the covered area CA has been removed. The first inorganic material layer 310 may be in direct contact with a part of the upper surface of the capping layer 107, and this part of the upper surface of the capping layer 107 is exposed upward through the area where a part of the pattern layer PL corresponding to the covered area CA has been removed.

[0138] The second inorganic material layer 320 may be disposed on the first inorganic material layer 310 (e.g., directly disposed on the first inorganic material layer 310). As an example, the second inorganic material layer 320 may cover the upper surface of the first inorganic material layer 310. The second inorganic material layer 320 may not only cover the upper surface of the first inorganic material layer 310, but also cover the side surface of the first inorganic material layer 310.

[0139] The third inorganic material layer 330 may be disposed on the second inorganic material layer 320 (e.g., directly disposed on the second inorganic material layer 320). As an example, the third inorganic material layer 330 may cover the upper surface of the second inorganic material layer 320. The third inorganic material layer 330 may not only cover the upper surface of the second inorganic material layer 320, but also cover the side surface of the second inorganic material layer 320.

[0140] The adsorption force between the pattern layer PL and the thin film encapsulation layer 300 may be a first adsorption force. Additionally, the adsorption force between the capping layer 107 and the thin film encapsulation layer 300 may be a second adsorption force. In an embodiment, the first adsorption force may be less than the second adsorption force.

[0141] In an embodiment where the inorganic material in which the thin film encapsulation layer 300 is formed is deposited on the entire surface of the pattern layer PL disposed on the pixel circuit layer PCL, since the first adsorption force is less than the second adsorption force, the material for forming the thin film encapsulation layer 300 may be deposited according to the shape of the first region formed therein.

[0142] In an embodiment, the pattern layer PL may include a metal oxide material to have a reduced adsorption force. As an example, in an embodiment, the metal oxide material included in the pattern layer PL may include alumina (Al2O3) or the like.

[0143] In an embodiment, the pattern layer PL may include an oxide of at least one metal among aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0144] As Figure 8 shown, the pattern layer PL may include an opening OP. The opening OP may be formed to correspond to the covering area CA. In an embodiment, when an etching process is performed in a preset area of the pattern layer PL, the opening OP of the pattern layer PL may be formed. In a plan view (e.g., in the z direction), the opening OP of the pattern layer PL may overlap with the light emitting diode OLED. The opening OP of the pattern layer PL may be covered by the thin film encapsulation layer 300. In a plan view, the opening OP of the pattern layer PL may overlap with the thin film encapsulation layer 300.

[0145] Figures 9 to 13 A cross-sectional view for sequentially showing a manufacturing method of a display device according to an embodiment of the present disclosure.

[0146] As a reference, in the Figure 9 and Figure 13 description, for the sake of simplicity of description, the same or repeated content as the above may be omitted. Additionally, for ease of description, some elements of the display device according to Figures 9 to 13 may be omitted or schematically shown.

[0147] As Figure 9 shown, a manufacturing method of a display device according to an embodiment (hereinafter, referred to as a manufacturing method) may include forming a pixel circuit layer PCL on a substrate 100.

[0148] In an embodiment, forming the pixel circuit layer PCL on the substrate 100 may include forming a pixel circuit layer PCL including at least one thin film transistor portion TFT on the substrate 100.

[0149] Reference Figure 8 and Figure 9 , for example, in an embodiment, forming the pixel circuit layer PCL on the substrate 100 may include forming a buffer layer 101 on the substrate 100, forming a semiconductor layer 110 on the buffer layer 101, forming a gate insulating layer 102 on the semiconductor layer 110, forming a first gate layer 120a on the gate insulating layer 102, forming a first interlayer insulating layer 103a on the first gate layer 120a, forming a second gate layer 120b on the first interlayer insulating layer 103a, forming a second interlayer insulating layer 103b on the second gate layer 120b, forming a first conductive layer 130 on the second interlayer insulating layer 103b, forming a first organic insulating layer 104 on the first conductive layer 130, forming a second conductive layer 140 on the first organic insulating layer 104, and forming a second organic insulating layer 105 on the second conductive layer 140.

[0150] In an embodiment, the formation of the semiconductor layer 110, the formation of the first gate layer 120a, and the formation of the second gate layer 120b may be performed by a photolithography process using a shadow mask or the like. The semiconductor layer 110, the first gate layer 120a, and the second gate layer 120b may be formed into patterns corresponding to preset shapes respectively formed in the shadow mask. The etching process for forming the semiconductor layer 110, the first gate layer 120a, and the second gate layer 120b may be a dry etching process or a wet etching process.

[0151] Similarly, in an embodiment, the formation of the first conductive layer 130 and the formation of the second conductive layer 140 may also be performed by a photolithography process using a shadow mask or the like. The first conductive layer 130 and the second conductive layer 140 may be formed into patterns corresponding to preset shapes respectively formed in the shadow mask. The etching process for forming the first conductive layer 130 and the second conductive layer 140 may be a dry etching process or a wet etching process.

[0152] In an embodiment, the gate insulating layer 102, the first interlayer insulating layer 103a, the second interlayer insulating layer 103b, the first organic insulating layer 104, and the second organic insulating layer 105 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0153] For ease of explanation, although only the thin film transistor portion TFT and the pixel circuit layer PCL are shown in Figure 9 without showing all the corresponding layers, its specific content is the same as or overlaps with the content described in reference Figures 1 to 8 . Accordingly, for the sake of simplicity of description, its content may be omitted.

[0154] As shown in Figure 10 Figure 10 , the manufacturing method according to the embodiment may further include forming a pattern layer PL on the pixel circuit layer PCL.

[0155] As described above, the pattern layer PL may include a metal oxide material (such as alumina). The adsorption force between the pattern layer PL and the thin film encapsulation layer 300 is van der Waals force and may be less than the adsorption force between another layer (such as the capping layer 107) and the thin film encapsulation layer 300.

[0156] As an example, the first adsorption force between the upper surface of the pattern layer PL and the thin film encapsulation layer 300 may be less than the adsorption force between the upper surface of the capping layer 107 and the thin film encapsulation layer 300. As an example, the first adsorption force between the upper surface of the pattern layer PL and the thin film encapsulation layer 300 may be less than the adsorption force between the upper surface of the capping layer 107 and the thin film encapsulation layer 300.

[0157] As an example, forming the pattern layer PL on the pixel circuit layer PCL may include forming the capping layer 107 on the pixel circuit layer PCL and forming the pattern layer PL on the capping layer 107.

[0158] In an embodiment, the formation of the capping layer 107 and the formation of the pattern layer PL on the capping layer 107 may be performed using CVD or ALD.

[0159] In an embodiment, the formation of the pattern layer PL may be performed by a lithography process using a shadow mask or the like. The pattern layer PL may be formed into a pattern corresponding to a preset shape formed in each shadow mask. The etching process for forming the pattern layer PL may be a dry etching process or a wet etching process.

[0160] As shown in Figure 10 Figure 10 , the manufacturing method according to the embodiment may further include forming an opening OP corresponding to a pattern of a preset shape in the pattern layer PL.

[0161] In an embodiment, the formation of the opening OP may be performed by a lithography process using a shadow mask or the like. The opening OP of the pattern layer PL may be formed into a pattern corresponding to a preset shape formed in each shadow mask. The etching process for forming the opening OP of the pattern layer PL may be a dry etching process or a wet etching process. Alternatively, depending on the situation, the formation of the opening OP may be performed by a laser process or the like.

[0162] As shown in Figure 11 Figure 11 , the manufacturing method according to the embodiment may further include forming a first inorganic material layer 310 covering the opening OP and having a first density.

[0163] In an embodiment, the formation of the first inorganic material layer 310 can be carried out by a deposition process such as CVD using an inorganic material in a chamber. In this embodiment, the inorganic material used to form the first inorganic material layer 310 may include at least one inorganic material such as alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0164] In a plan view, the first inorganic material layer 310 formed in the opening OP can cover the opening OP. As an example, in an embodiment where the light-emitting diode OLED is disposed in the opening OP, the first inorganic material layer 310 can cover the opening OP and together cover the light-emitting diode OLED. As a result, the opening OP and the light-emitting diode OLED can be sealed by the first inorganic material layer 310. In an embodiment where other elements are disposed in the opening OP, the other elements can also be covered and sealed by the first inorganic material layer 310.

[0165] The deposition rate for forming the first inorganic material layer 310 having a first density (the first density is the lowest density among the first density to the third density) can be faster than the deposition rate for forming the second inorganic material layer 320 described later. As a result, the formation of the first inorganic material layer 310 can be configured to form the first inorganic material layer 310 having a greater thickness compared to the thickness of the second inorganic material layer 320.

[0166] As Figure 12 shown, the manufacturing method according to an embodiment may further include forming a second inorganic material layer 320 disposed on the first inorganic material layer 310 (e.g., directly disposed on the first inorganic material layer 310) and having a second density greater than the first density.

[0167] In an embodiment, the formation of the second inorganic material layer 320 can be carried out in the same chamber as the chamber used for the formation of the first inorganic material layer 310.

[0168] In an embodiment, the formation of the second inorganic material layer 320 can be carried out by a deposition process such as CVD using an inorganic material in a chamber. In this embodiment, the inorganic material used to form the second inorganic material layer 320 may include at least one inorganic material such as alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0169] In a plan view, the second inorganic material layer 320 formed on the first inorganic material layer 310 can cover the upper surface of the first inorganic material layer 310. Additionally, the second inorganic material layer 320 can cover the side surface of the first inorganic material layer 310. Additionally, in a plan view, the second inorganic material layer 320 can cover the opening OP.

[0170] As an example, in a plan view, in an embodiment in which a light-emitting diode OLED is disposed in an opening OP, the first inorganic material layer 310 and the second inorganic material layer 320 may cover the opening OP and together cover the light-emitting diode OLED. As a result, the opening OP and the light-emitting diode OLED may be sealed by the first inorganic material layer 310 and the second inorganic material layer 320. In an embodiment in which other elements are disposed in the opening OP, the other elements may also be covered and sealed by the first inorganic material layer 310 and the second inorganic material layer 320.

[0171] The deposition rate of forming the second inorganic material layer 320 having a second density (the second density is the highest density among the first density to the third density) may be slower than the deposition rate of forming the first inorganic material layer 310 having a first density. In addition, the deposition rate of forming the second inorganic material layer 320 may be slower than the deposition rate of forming the third inorganic material layer 330 having a third density. As a result, forming the second inorganic material layer 320 may be configured to form the second inorganic material layer 320 having a minimum thickness, and forming the second inorganic material layer 320 having a small thickness may have the effect of increasing the overall process efficiency.

[0172] As Figure 13 shown, the manufacturing method according to an embodiment may further include forming a third inorganic material layer 330 disposed on the second inorganic material layer 320 (e.g., directly disposed on the second inorganic material layer 320) and having a third density less than the second density.

[0173] In an embodiment, the formation of the third inorganic material layer 330 may be performed in the same chamber as the chamber used for the formation of the first inorganic material layer 310. As a result, the first inorganic material layer 310 to the third inorganic material layer 330 may be formed in the same chamber. Since the thin film encapsulation layer 300 is formed in the same chamber, the time and cost consumed for completely forming the thin film encapsulation layer 300 may be significantly reduced.

[0174] In an embodiment, the formation of the third inorganic material layer 330 may be performed by a deposition process such as CVD using an inorganic material in a chamber. In this embodiment, the inorganic material used for forming the third inorganic material layer 330 may include at least one inorganic material such as alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0175] In a plan view, the third inorganic material layer 330 formed on the second inorganic material layer 320 may cover the upper surface of the second inorganic material layer 320. In addition, the third inorganic material layer 330 may cover the side surface of the second inorganic material layer 320. In addition, in a plan view, the third inorganic material layer 330 may cover the opening OP. Finally, the coverage area CA may be defined by the third inorganic material layer 330.

[0176] As an example, in a plan view, in an embodiment in which an organic light-emitting diode (OLED) is disposed in an opening (OP), the first inorganic material layer 310 to the third inorganic material layer 330 may cover the opening OP and together cover the organic light-emitting diode (OLED). As a result, the opening OP and the organic light-emitting diode (OLED) may be sealed by the first inorganic material layer 310 to the third inorganic material layer 330. In an embodiment in which other elements are disposed in the opening OP, the other elements may also be covered and sealed by the first inorganic material layer 310 to the third inorganic material layer 330.

[0177] The deposition rate of forming the third inorganic material layer 330 may be faster than the deposition rate of forming the second inorganic material layer 320. As a result, forming the third inorganic material layer 330 may be configured to form the third inorganic material layer 330 having a greater thickness ratio to the thickness of the second inorganic material layer 320, and forming the third inorganic material layer 330 having a greater thickness may have an effect of increasing the overall process efficiency.

[0178] As an example, in an embodiment, the thickness (e.g., the length in the z direction) of the second inorganic material layer 320 formed by a manufacturing method may be less than the thickness of the first inorganic material layer 310 and less than the thickness of the third inorganic material layer 330. As an example, in an embodiment, the thickness of the second inorganic material layer 320 may be in the range of about 10% to about 20% of the thickness of the third inorganic material layer 330. In an embodiment in which the thickness of the second inorganic material layer 320 is less than about 10% of the thickness of the third inorganic material layer 330, the probability that the second inorganic material layer 320 is pierced or damaged by particles is significantly increased. In an embodiment in which the thickness of the second inorganic material layer 320 exceeds about 20% of the thickness of the third inorganic material layer 330, the time period for forming the second inorganic material layer 320 is too long, and the overall process efficiency may be reduced. In an embodiment, the thickness of the first inorganic material layer 310 and the thickness of the third inorganic material layer 330 may be substantially equal to each other. However, the embodiments of the present disclosure are not limited thereto.

[0179] Figure 14 A schematic cross-sectional view is an example of a part of a display device according to a comparative example.

[0180] As a reference, in Figure 14 the description, for the sake of brevity of description, the same or repeated content as the above may be omitted.

[0181] As Figure 14 shown in , a display device according to a comparative example (also referred to as a "comparative embodiment") may include a thin film encapsulation member (TFE). The thin film encapsulation member (TFE) may completely cover a display area (DA) and extend to a peripheral area (PA) to cover at least a part of the peripheral area (PA).

[0182] In a comparative embodiment, the thin film encapsulation member TFE may extend outside the common power supply line. The thin film encapsulation member TFE may include a first inorganic encapsulation layer 301, a second inorganic encapsulation layer 303, and an organic encapsulation layer 302 therebetween. The first inorganic encapsulation layer 301 and the second inorganic encapsulation layer 303 may include at least one inorganic material such as alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0183] The first inorganic encapsulation layer 301 and the second inorganic encapsulation layer 303 may include a single layer or multiple layers containing the above materials. The first inorganic encapsulation layer 301 and the second inorganic encapsulation layer 303 may include the same material or different materials from each other. The thickness of the first inorganic encapsulation layer 301 (e.g., the length in the z direction) may be different from the thickness of the second inorganic encapsulation layer 303 (e.g., the length in the z direction). For example, the thickness of the first inorganic encapsulation layer 301 may be greater than the thickness of the second inorganic encapsulation layer 303. Alternatively, the thickness of the second inorganic encapsulation layer 303 may be greater than the thickness of the first inorganic encapsulation layer 301, or the thickness of the first inorganic encapsulation layer 301 may be the same as the thickness of the second inorganic encapsulation layer 303.

[0184] The organic encapsulation layer 302 may include monomeric materials and / or polymeric materials. The polymeric materials may include acrylic resins, epoxy resins, polyimides, and polyethylene. In a comparative embodiment, the organic encapsulation layer 302 may include acrylate.

[0185] The barrier wall 200 may be disposed in the outer peripheral region PA of the substrate 100. In a comparative embodiment, although the barrier wall 200 may include a part of the first organic insulating layer 104, a part 230 of the second organic insulating layer 105, a part 220 of the pixel defining layer 106, and a part 210 of the spacer 80, the comparative embodiment is not limited thereto.

[0186] According to a comparative embodiment, the barrier wall 200 may include only a part 230 of the second organic insulating layer 105 and a part 220 of the pixel defining layer 106. The barrier wall 200 is arranged to surround the display area DA and may prevent the organic encapsulation layer 302 of the thin film encapsulation member TFE from overflowing to the outside of the substrate 100. Accordingly, the organic encapsulation layer 302 may be in direct contact with the inner surface of the barrier wall 200 facing the display area DA. In this case, when the organic encapsulation layer 302 is in direct contact with the inner surface of the barrier wall 200, it can be understood that the first inorganic encapsulation layer 301 is located between the organic encapsulation layer 302 and the barrier wall 200, and the organic encapsulation layer 302 is in direct contact with the first inorganic encapsulation layer 301.

[0187] The first inorganic encapsulation layer 301 and the second inorganic encapsulation layer 303 may be disposed on the barrier wall 200 and may extend toward the edge of the substrate 100. However, according to a comparative embodiment, the barrier wall 200 may be provided as a plurality of.

[0188] As Figure 14 shown, the thin film encapsulation member TFE requires a barrier wall to prevent the overflow of the organic encapsulation layer. This structure has a problem that it is difficult to apply to newly developed display devices (such as stretchable display devices, foldable display devices, and flexible display devices).

[0189] As an example, in a comparative embodiment having a stretchable display device or the like, performing a stretching operation may affect the safety and reliability of the thin film encapsulation member TFE. While performing a stretching operation or the like, moisture or oxygen may penetrate between the first inorganic encapsulation layer 301 and the second inorganic encapsulation layer 303 covering the outer portion of the barrier wall 200 along arrow number ①, moisture or oxygen may penetrate around the groove GR formed by the barrier wall 200 along arrow number ②, moisture or oxygen may penetrate around the spacer 80 along arrow number ③, and moisture or oxygen may penetrate along arrow number ④.

[0190] In addition, in a comparative embodiment having a thin film encapsulation member TFE including an organic encapsulation layer 302, inorganic materials and organic materials should be alternately deposited on the entire surface of the display panel. As a result, the thin film encapsulation member TFE is always formed to cover the entire surface of the display panel 10. Accordingly, in the thin film encapsulation member TFE according to the prior art, it is impossible to use the thin film encapsulation member TFE to cover or encapsulate an object only in a desired region. Additionally, in a comparative embodiment of the thin film encapsulation member TFE according to the prior art, it is also impossible to form the thin film encapsulation member TFE in a pattern of a preset shape.

[0191] According to an embodiment having the above configuration, a display device including a thin film encapsulation layer formed only in a desired region and a method of manufacturing the display device can be realized. However, the scope of the present disclosure is not limited by this effect.

[0192] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of the features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the drawings, those of ordinary skill in the art will understand that various changes in form and detail can be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, comprising: a substrate; a pixel circuit layer disposed on the substrate; a pattern layer disposed on the pixel circuit layer, the pattern layer including a first region and a second region excluding the first region, the first region being defined by an opening; and a thin film encapsulation layer disposed only in the first region and above the pixel circuit layer, the thin film encapsulation layer including a plurality of inorganic material layers having different densities from each other, wherein the thin film encapsulation layer includes: a first inorganic material layer disposed in the first region and having a first density; a second inorganic material layer disposed on the first inorganic material layer and having a second density greater than the first density; and a third inorganic material layer disposed on the second inorganic material layer and having a third density less than the second density.

2. The display device according to claim 1, wherein a lower surface of the second inorganic material layer is in direct contact with an upper surface of the first inorganic material layer.

3. The display device according to claim 2, wherein an upper surface of the second inorganic material layer is in direct contact with a lower surface of the third inorganic material layer.

4. The display device according to claim 1, further comprising a light emitting diode disposed in the first region and between the pixel circuit layer and the first inorganic material layer.

5. The display device according to claim 1, further comprising a capping layer disposed between the pixel circuit layer and the pattern layer.

6. The display device according to claim 1, wherein a thickness of the second inorganic material layer is less than a thickness of the first inorganic material layer.

7. The display device according to claim 6, wherein the thickness of the second inorganic material layer is less than a thickness of the third inorganic material layer.

8. The display device according to claim 1, wherein the thickness of the second inorganic material layer is in a range of 10% to 20% of a thickness of the third inorganic material layer.

9. The display device according to claim 1, wherein the first density is the lowest density among the first density to the third density.

10. The display device according to claim 5, wherein: a first adsorption force between an upper surface of the pattern layer and the thin film encapsulation layer is less than a second adsorption force between an upper surface of the capping layer and the thin film encapsulation layer.

11. The display device according to claim 1, wherein the pattern layer includes a metal oxide material.

12. The display device according to claim 11, wherein the pattern layer includes aluminum oxide.

13. A method for manufacturing a display device, the method comprising: forming a pixel circuit layer on a substrate; forming a pattern layer on the pixel circuit layer; forming an opening in the pattern layer, wherein the opening corresponds to a pattern of a preset shape; forming a first inorganic material layer covering the opening and having a first density; forming a second inorganic material layer on the first inorganic material layer and having a second density greater than the first density; and forming a third inorganic material layer on the second inorganic material layer and having a third density less than the second density.

14. The method according to claim 13, wherein a lower surface of the second inorganic material layer is in direct contact with an upper surface of the first inorganic material layer.

15. The method according to claim 14, wherein an upper surface of the second inorganic material layer is in direct contact with a lower surface of the third inorganic material layer.

16. The method according to claim 13, wherein a thickness of the second inorganic material layer is less than a thickness of the first inorganic material layer.

17. The method according to claim 16, wherein the thickness of the second inorganic material layer is less than a thickness of the third inorganic material layer.

18. The method according to claim 13, wherein: the thickness of the second inorganic material layer is in a range of 10% to 20% of the thickness of the third inorganic material layer.

19. The method according to claim 13, wherein forming the pattern layer on the pixel circuit layer includes: forming a capping layer on the pixel circuit layer; and forming the pattern layer on the capping layer.

20. The method according to claim 19, wherein: the first inorganic material layer to the third inorganic material layer form a thin film encapsulation layer; and a first adsorption force between an upper surface of the pattern layer and the thin film encapsulation layer is less than a second adsorption force between an upper surface of the capping layer and the thin film encapsulation layer.

21. A display device, comprising: a substrate including a covered area and an uncovered area, the covered area being arranged in a pattern of a preset shape; a pixel circuit layer disposed on the substrate; a light emitting diode disposed on the pixel circuit layer; a pattern layer covering the pixel circuit layer in the uncovered area and having an opening in the covered area; a thin film encapsulation layer disposed only in the opening of the pattern layer in the covered area, wherein the thin film encapsulation layer is arranged in the pattern of the preset shape and encapsulates the light emitting diode; and the thin film encapsulation layer includes a plurality of inorganic material layers having different densities from each other.

22. The display device according to claim 21, wherein the thin film encapsulation layer includes: a first inorganic material layer; a second inorganic material layer directly disposed on the first inorganic material layer and having a density greater than that of the first inorganic material layer; and a third inorganic material layer disposed on the second inorganic material layer and having a density less than that of the second inorganic material layer.

23. The display device according to claim 22, wherein a thickness of the second inorganic material layer is less than a thickness of the first inorganic material layer and a thickness of the third inorganic material layer.

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