Display device

Abstract

There is provided a display device including a plurality of pixels disposed in a display area, each of the plurality of pixels including: a plurality of pixel electrodes spaced apart from each other; a first light blocking layer disposed in the display area and including a plurality of holes overlapping the plurality of pixel electrodes; and a plurality of color filters disposed on the first light blocking layer and respectively corresponding to the plurality of holes. Some of the plurality of pixels further includes a second light blocking layer disposed on the color filters of some of the plurality of pixels and corresponding to the pixel electrodes of some of the plurality of pixels. The second light blocking layer surrounds corresponding pixel electrodes of some of the plurality of pixels in a plan view, and includes a plurality of light blocking patterns having a constant width.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2024-0005983, filed with the Korean Intellectual Property Office on January 15, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Embodiments of the present disclosure relate to a display device. Background Art

[0003] With the development of an information society, various increased demands are made on display devices for displaying images. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. Among flat panel display devices, in a self-emitting display device, since each of the pixels of the display panel includes a light emitting element capable of emitting light by itself, an image can be displayed without a backlight unit supplying light to the display panel. Summary of the Invention

[0004] Embodiments of the present disclosure provide a display device including a plurality of light blocking layers provided in different layers.

[0005] Embodiments of the present disclosure also provide a display device capable of providing a privacy protection mode by including a light blocking layer provided on some pixels.

[0006] According to an embodiment, a display device includes a plurality of pixels provided in a display area, each of the plurality of pixels including: a plurality of pixel electrodes spaced apart from each other; a first light blocking layer provided in the display area and including a plurality of holes overlapping the plurality of pixel electrodes; and a plurality of color filters provided on the first light blocking layer and corresponding to the plurality of holes, respectively. Some of the plurality of pixels further include: a second light blocking layer provided on the color filters of some of the plurality of pixels and corresponding to the pixel electrodes of some of the plurality of pixels. The second light blocking layer surrounds the corresponding pixel electrodes of some of the plurality of pixels in a plan view and includes a plurality of light blocking patterns having a constant width.

[0007] According to an embodiment, a display device includes a first pixel and a second pixel disposed on a substrate. Each of the first pixel and the second pixel includes: a plurality of pixel electrodes; an encapsulation layer disposed on the plurality of pixel electrodes; a first light blocking layer disposed on the encapsulation layer and including a plurality of holes respectively corresponding to the plurality of pixel electrodes; a plurality of color filters disposed on the first light blocking layer and respectively corresponding to the plurality of pixel electrodes; a passivation layer disposed on the plurality of color filters and the first light blocking layer; and a coating layer disposed on the first light blocking layer. The second pixel further includes: a second light blocking layer disposed between the passivation layer and the coating layer in the second pixel, and including a plurality of light blocking patterns forming a plurality of transmission portions respectively corresponding to the pixel electrodes of the second pixel. The diameter of each of the plurality of transmission portions of the second light blocking layer is larger than the diameter of the corresponding hole of the plurality of holes of the first light blocking layer.

[0008] According to an embodiment, a display device includes a plurality of light blocking layers, and the light blocking layers have a shape corresponding to and surrounding the pixel electrodes. The display device adjusts the shape of the light blocking patterns of the light blocking layers and the distance from the pixel electrodes. Accordingly, a display screen can be visually recognized only by a user viewing from the front surface of the display area, and the screen cannot be visually recognized by a user viewing at a specific viewing angle or from the side. The display device can provide a privacy protection mode to the user. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings, in which: Figure 1 is a schematic perspective view of an electronic device according to an embodiment; Figure 2 is a perspective view showing a display device included in an electronic device according to an embodiment; Figure 3 is a side view of Figure 2 the display device; Figure 4 is a plan view showing the arrangement of pixel electrodes in a display area of a display device according to an embodiment; Figure 5 is a plan view showing the arrangement of pixel electrodes, a first light blocking layer, and color filters in a display area of a display device according to an embodiment; Figure 6 is a plan view showing the arrangement of pixel electrodes and a second light blocking layer in a display area of a display device according to an embodiment; Figure 7 is a schematic view showing a light-emitting pixel according to an emission mode of a display device according to an embodiment; Figure 8 is along Figure 5 andFigure 6 A cross-sectional view taken along line X1-X1' of; Figure 9 is along Figure 5 and Figure 6 A cross-sectional view taken along line X2-X2'; Figure 10 is along Figure 6 A cross-sectional view taken along line X3-X3' and line X4-X4'; Figure 11 is a view showing the relative arrangement of the second light blocking layer and the pixel electrode disposed in one pixel of the display device according to an embodiment; Figure 12 is a view showing the relative arrangement of the second light blocking layer and the pixel electrode disposed in one pixel of the display device according to an embodiment; and Figure 13 and Figure 14 is a view showing the second light blocking layer of the display device according to an embodiment. DETAILED DESCRIPTION

[0010] Hereinafter, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0011] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a "first" element in an embodiment may be described as a "second" element in another embodiment.

[0012] It should be understood that, unless the context clearly indicates otherwise, the description of features or aspects within each embodiment is generally considered applicable to other similar features or aspects in other embodiments.

[0013] As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms.

[0014] For ease of description, spatially relative terms such as "below", "beneath", "lower", "under", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. It will be understood that, in addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of the device during use or operation. For example, if the device in the figures is flipped, an element described as "below", "beneath", or "under" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "under" can encompass both an upper and a lower orientation.

[0015] It will be understood that when a component such as a film, region, layer, etc. is referred to as being "on", "connected to", "bonded to", or "adjacent to" another component, the component can be directly on, directly connected to, directly bonded to, or directly adjacent to the other component, or there can be intervening components. It will also be understood that when a component is referred to as being "between" two components, the component can be the only component between the two components, or there can also be one or more intervening components. It will also be understood that when a component is referred to as "covering" another component, the component can be the only component covering the other component, or one or more intervening components can also cover the other component. Other words used to describe the relationship between components should be interpreted in the same manner.

[0016] In this document, when two or more elements or values are described as being substantially the same or approximately equal to each other, it should be understood that the elements or values are the same as each other, the elements or values are equal to each other within the measurement error, or if measurably unequal, then as would be understood by a person of ordinary skill in the art, the values are close enough to be functionally equal to each other. For example, the term "about" as used herein includes the stated value and means within an acceptable deviation range of the particular value as determined by a person of ordinary skill in the art, taking into account the measurements being discussed and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system). For example, as would be understood by a person of ordinary skill in the art, "about" can mean within one or more standard deviations. Additionally, it should be understood that although a parameter may be described herein as having "about" a certain value, according to an embodiment, as would be understood by a person of ordinary skill in the art, the parameter can be an exact certain value or an approximate certain value within the measurement error. These terms and similar terms for other uses in describing the relationship between components should be interpreted in the same manner.

[0017] It will also be understood that when a layer is referred to as being “on” another layer or substrate, the layer can be directly on the other layer or substrate, or an intermediate layer can also be present. Throughout the specification, the same reference numerals denote the same components.

[0018] It will be understood that although terms such as “first” and “second” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the present invention, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element.

[0019] Figure 1 is a schematic perspective view of an electronic device according to an embodiment.

[0020] Referring to Figure 1 , the electronic device 1 displays a moving image (e.g., video) or a still image. The electronic device 1 can refer to any electronic device including a display screen that provides visual information to a user. Examples of the electronic device 1 can include a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smartphone, a tablet personal computer (PC), an electronic watch, a smartwatch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, a gaming console, a digital camera, and a portable video camera, etc.

[0021] As Figure 2 shown, the electronic device 1 can include a display device 10 including a display screen. Examples of the display device can include an inorganic light-emitting diode display device, an organic light-emitting display device, a quantum dot light-emitting display device, a plasma display device, and a field emission display device. In the following description, the case of applying an organic light-emitting diode display device as the display device will be exemplified, but the present disclosure is not limited thereto, and other display devices can be applied according to the embodiments of the present disclosure.

[0022] The shape of the electronic device 1 can be variously modified. For example, the electronic device 1 can have a shape such as a rectangular shape extended in the horizontal direction, a rectangular shape extended in the vertical direction, a square shape, a quadrilateral shape with rounded corners (vertices), other polygonal shapes, and a circular shape. The shape of the display area DA of the electronic device 1 can also be similar to the overall shape of the electronic device 1. Figure 1 An electronic device 1 having a rectangular shape extended in the second direction DR2 is shown.

[0023] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where the display screen can provide visual data, and the non-display area NDA is an area where no image data is displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may substantially occupy the center of the electronic device 1.

[0024] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 are areas provided for components that add various functions to the electronic device 1. For example, the second display area DA2 and the third display area DA3 may correspond to component areas.

[0025] Figure 2 is a perspective view showing a display device included in an electronic device according to an embodiment.

[0026] Referring to Figure 2 , the electronic device 1 according to an embodiment may include a display device 10. The display device 10 may provide an image displayed by the electronic device 1. The display device 10 may have a planar shape similar to the shape of the electronic device 1. For example, the display device 10 may have a shape similar to a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2. The edges where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a curvature, but are not limited thereto and may be formed as right angles. The planar shape of the display device 10 is not limited to a quadrilateral shape and may be formed as a shape similar to another polygon shape, a circular shape, or an elliptical shape.

[0027] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

[0028] The display panel 100 may include a main area MA and a sub-area SBA.

[0029] The main area MA may include a display area DA and a non-display area NDA provided around the display area DA. The display area DA includes pixels PX1, PX2, PX3, and PX4 that display an image (see Figure 4 ). The display area DA may be provided at the center of the main area MA, and the non-display area NDA may surround the display area DA. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer that defines an emission area or an opening area, and a self-emitting element.

[0030] For example, the self-emitting element may include at least one of an organic light-emitting diode (LED) including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0031] The non-display area NDA may be an area provided outside the display area DA. The non-display area NDA may be defined as an edge area of the main area MA of the display panel 100. The non-display area NDA may include a gate driver that supplies a gate signal to the gate line and a fan-out line that connects the display driver 200 to the display area DA.

[0032] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (third direction DR3). The sub-area SBA may include the display driver 200 and a pad (or referred to as "bond pad" or "landing pad") portion connected to the circuit board 300. In an embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0033] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply a data voltage to the data line. The display driver 200 may supply a power voltage to the power line and may supply a gate control signal to the gate driver. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 by, for example, a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. In an embodiment, the display driver 200 may be provided in the sub-area SBA and may overlap with the main area MA in the thickness direction by bending the sub-area SBA. In an embodiment, the display driver 200 may be mounted on the circuit board 300.

[0034] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). The leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be, for example, a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0035] The touch driver 400 can be mounted on the circuit board 300. The touch driver 400 can be connected to the touch sensing unit of the display panel 100. The touch driver 400 can supply touch driving signals to a plurality of touch electrodes of the touch sensing unit, and can sense the change amount of the capacitance between the plurality of touch electrodes. For example, the touch driving signal can be a pulse signal having a predetermined frequency. The touch driver 400 can calculate whether an input and the input coordinates are made based on the change amount of the capacitance between the plurality of touch electrodes. The touch driver 400 can be formed as an integrated circuit (IC).

[0036] Figure 3 is a cross-sectional view of the display device viewed from the side Figure 2 . Figure 3 shows the Figure 2 sub-region SBA of the display panel 100 in the display device 10 in the folded state.

[0037] Referring to Figure 3 , the display panel 100 can include a display layer DU, a touch sensing layer TSU, a color filter layer CFL, and a light blocking member layer PML. The display layer DU can include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and a package layer TFEL.

[0038] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB can include a polymer resin such as polyimide (PI), but is not limited thereto. In an embodiment, the substrate SUB can include a glass material or a metal material.

[0039] The thin film transistor layer TFTL can be disposed on the substrate SUB. The thin film transistor layer TFTL can include a plurality of thin film transistors constituting the pixel circuits of the pixels. The thin film transistor layer TFTL can further include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver 200 to the data lines, and leads connecting the display driver 200 to the pad portions. Each of the thin film transistors can include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the gate driver is formed on one side of the non-display region NDA of the display panel 100, the gate driver can include thin film transistors.

[0040] The thin film transistor layer TFTL can be disposed in the display region DA, the non-display region NDA, and the sub-region SBA. The thin film transistors, gate lines, data lines, and power lines of the thin film transistor layer TFTL can be disposed in the display region DA. The gate control lines and fan-out lines of the thin film transistor layer TFTL can be disposed in the non-display region NDA. The leads of the thin film transistor layer TFTL can be disposed in the sub-region SBA.

[0041] The light-emitting element layer EML may be disposed on the thin-film transistor layer TFTL. The light-emitting element layer EML may include a plurality of light-emitting elements and a pixel defining layer that defines pixels, and each light-emitting element includes a first electrode, a second electrode, and a light-emitting layer that emits light. The plurality of light-emitting elements of the light-emitting element layer EML may be disposed in the display area DA.

[0042] In an embodiment, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin-film transistor of the thin-film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may be respectively transported to the organic light-emitting layer through the hole transport layer and the electron transport layer, and may be recombined with each other to emit light in the organic light-emitting layer.

[0043] In an embodiment, the light-emitting element may include a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, or a micro light-emitting diode.

[0044] The encapsulation layer TFEL may cover the top surface and the side surfaces of the light-emitting element layer EML, and may protect the light-emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer that encapsulate the light-emitting element layer EML.

[0045] The touch sensing layer TSU may be disposed on the encapsulation layer TFEL. The touch sensing layer TSU may include a plurality of touch electrodes that capacitively sense a user's touch and touch lines that connect the plurality of touch electrodes to the touch driver 400. For example, the touch sensing layer TSU may sense a user's touch by using a mutual capacitance method or a self-capacitance method.

[0046] In an embodiment, the touch sensing layer TSU may be disposed on a separate substrate, and the substrate is disposed on the display layer DU. In this case, the substrate that supports the touch sensing layer TSU may be a base member that encapsulates the display layer DU.

[0047] The plurality of touch electrodes of the touch sensing layer TSU may be disposed in a touch sensor area that overlaps with the display area DA. The touch lines of the touch sensing layer TSU may be disposed in a touch peripheral area that overlaps with the non-display area NDA.

[0048] The color filter layer CFL may be disposed on the touch sensing layer TSU. The color filter layer CFL may include a plurality of color filters respectively corresponding to a plurality of emission regions. Each of the color filters may selectively transmit light of a specific wavelength, and may block or absorb light of different wavelengths. The color filter layer CFL may absorb a part of the light from the outside of the display device 10 to reduce the reflected light caused by the external light. Therefore, the color filter layer CFL may prevent color distortion caused by the reflection of the external light.

[0049] Since the color filter layer CFL is directly disposed on the touch sensing layer TSU, the display device 10 may not use a separate substrate for the color filter layer CFL. Accordingly, the thickness of the display device 10 may be relatively small.

[0050] The light blocking member layer PML may be disposed on the color filter layer CFL. The light blocking member layer PML may include a light blocking pattern that is disposed to correspond to specific pixels of the display layer DU. The display device 10 may also include a light blocking member layer to control visibility at a specific viewing angle and to provide a privacy protection mode to the user.

[0051] In some embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be disposed in the second display area DA2 or the third display area DA3. The optical device 500 may emit or receive light in the infrared band, the ultraviolet band, and the visible light band. For example, the optical device 500 may be an optical sensor or an image sensor such as a proximity sensor, an illuminance sensor, and a camera sensor that detects light incident on the display device 10.

[0052] Figure 4 is a plan view of the arrangement of pixel electrodes in the display area of a display device according to an embodiment. Figure 5 is a plan view showing the arrangement of pixel electrodes, a first light blocking layer, and a color filter in the display area of a display device according to an embodiment.

[0053] Referring to Figure 4 and Figure 5 and Figure 4 , the display device 10 may include a plurality of pixels PX1, PX2, PX3, and PX4 disposed in the display area DA. The plurality of pixels PX1, PX2, PX3, and PX4 may be arranged in a fourth direction DR4 and a fifth direction DR5, which are diagonal directions between the first direction DR1 and the second direction DR2. The first pixel PX1 and the second pixel PX2 may be disposed adjacent to each other in the fifth direction DR5, the second pixel PX2 and the third pixel PX3 may be disposed adjacent to each other in the fourth direction DR4. The third pixel PX3 and the fourth pixel PX4 may be disposed adjacent to each other in the fifth direction DR5. The plurality of pixels PX1, PX2, PX3, and PX4 may be repeatedly arranged across the entire display area DA in a

[0054] Each of the plurality of pixels PX1, PX2, PX3, and PX4 may include a plurality of pixel electrodes AE1, AE2, and AE3. For example, each of the plurality of pixels PX1, PX2, PX3, and PX4 may include a first pixel electrode AE1, a second pixel electrode AE2, and a third pixel electrode AE3. One pixel PX1, PX2, PX3, PX4 may include one first pixel electrode AE1, two second pixel electrodes AE2, and one third pixel electrode AE3. However, the present disclosure is not limited thereto. For example, the number of pixel electrodes AE1, AE2, and AE3 provided in pixels PX1, PX2, PX3, and PX4 may be modified differently.

[0055] One of the pixel electrodes AE1, AE2, AE3 may be an anode electrode of a light-emitting element included in each of the pixels PX1, PX2, PX3, and PX4. One pixel PX1, PX2, PX3, PX4 may include one or more light-emitting elements ED (see Figure 8 ), and the light-emitting elements may be light-emitting elements that emit light of different colors. For example, the light-emitting element including the first pixel electrode AE1 may emit first light of red color. The light-emitting element including the second pixel electrode AE2 may emit second light of green color, and the light-emitting element including the third pixel electrode AE3 may emit third light of blue color. However, the present disclosure is not limited thereto. One first pixel electrode AE1, two second pixel electrodes AE2, and one third pixel electrode AE3 may form one pixel PX1, PX2, PX3, PX4, and may emit different colors and exhibit white gray scale. However, the present disclosure is not limited thereto, and the combination of pixel electrodes AE1, AE2, and AE3 constituting one pixel PX1, PX2, PX3, PX4 may be modified in various ways according to the arrangement of pixel electrodes AE1, AE2, and AE3, the colors of light emitted by pixel electrodes AE1, AE2, and AE3, etc.

[0056] Each of the pixel electrodes AE1, AE2, and AE3 may form an emission region in each of the pixels PX1, PX2, PX3, and PX4. For example, the first pixel electrode AE1 may form a first emission region that emits light of a first color, the second pixel electrode AE2 may form a second emission region that emits light of a second color, and the third pixel electrode AE3 may form a third emission region that emits light of a third color. In an embodiment, the emission region of the display device 10 may be a region overlapping with the pixel electrodes AE1, AE2, and AE3, and for example, in Figure 8 the opening of the pixel defining layer PDL (see Figure 8 ) shown may correspond to the emission region. For example, each of the emission regions may be formed by the pixel defining layer PDL (see Figure 8It is defined by a plurality of openings in (), which will be described in further detail below. The first emission region may be defined by a first opening in the pixel defining layer that overlaps with the first pixel electrode AE1, the second emission region may be defined by a second opening in the pixel defining layer that overlaps with the second pixel electrode AE2, and the third emission region may be defined by a third opening in the pixel defining layer that overlaps with the third pixel electrode AE3.

[0057] A plurality of pixel electrodes AE1, AE2, and AE3 may be in PenTile ® type (e.g., diamond PenTile ® type) arrangement. For example, the first pixel electrode AE1 and the third pixel electrode AE3 may be spaced apart from each other in the second direction DR2, and may be alternately arranged in the first direction DR1 and the second direction DR2. The second pixel electrode AE2 may be spaced apart from another adjacent second pixel electrode AE2 in the first direction DR1 and the second direction DR2, and may be spaced apart from the adjacent first pixel electrode AE1 and the adjacent third pixel electrode AE3 in the fourth direction DR4 or the fifth direction DR5. A plurality of second pixel electrodes AE2 may be repeatedly arranged along the first direction DR1 and the second direction DR2, and the second pixel electrode AE2 and the first pixel electrode AE1 or the second pixel electrode AE2 and the third pixel electrode AE3 may be alternately arranged along the fourth direction DR4 or the fifth direction DR5.

[0058] In an embodiment, the areas or sizes of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be different from each other. In accordance with Figure 4 the embodiment, the area of the third pixel electrode AE3 may be larger than the areas of the first pixel electrode AE1 and the second pixel electrode AE2, and the area of the first pixel electrode AE1 may be larger than the area of the second pixel electrode AE2. The intensity of the light to be emitted may vary according to the area of the emission region that overlaps with the pixel electrodes AE1, AE2, and AE3, and the area of the emission region may be adjusted to control the color of the screen displayed on the display device 10 or the electronic device 1. In accordance with Figure 4 the embodiment, the third pixel electrode AE3 has the largest area, but is not limited thereto. The sizes of the pixel electrodes AE1, AE2, and AE3 and the area of the emission region may be freely adjusted according to the color of the screen for the display device 10 and the electronic device 1. Additionally, the areas of the pixel electrodes AE1, AE2, and AE3 may be related to the light efficiency and lifespan of the light-emitting element ED, and may have a balanced relationship with the reflection of external light. The areas of the pixel electrodes AE1, AE2, and AE3 may be adjusted considering the above factors.

[0059] The display device 10 may include a first light-blocking layer BM1 and a plurality of color filters CF1, CF2, and CF3 disposed on pixel electrodes AE1, AE2, and AE3.

[0060] The first light-blocking layer BM1 may be disposed over the entire display area DA. The first light-blocking layer BM1 may include a plurality of holes OPT1, OPT2, and OPT3 respectively disposed corresponding to the plurality of pixel electrodes AE1, AE2, and AE3. Optionally, each of the holes OPT1, OPT2, and OPT3 of the first light-blocking layer BM1 may be disposed corresponding to the openings of the pixel defining layer PDL (see Figure 8 ). The first light-blocking layer BM1 may cover the display area DA except for the areas where the holes OPT1, OPT2, and OPT3 are disposed in the display area DA. The holes OPT1, OPT2, and OPT3 of the first light-blocking layer BM1 may be areas for emitting light emitted from light-emitting elements including the pixel electrodes AE1, AE2, and AE3. The plurality of holes OPT1, OPT2, and OPT3 may include a first hole OPT1 superposed on the first pixel electrode AE1, a second hole OPT2 superposed on the second pixel electrode AE2, and a third hole OPT3 superposed on the third pixel electrode AE3. One first hole OPT1, two second holes OPT2, and one third hole OPT3 may be formed in the first light-blocking layer BM1 within the area occupied by one pixel PX1, PX2, PX3, or PX4.

[0061] The area of each of the plurality of holes OPT1, OPT2, and OPT3 in a plan view may be larger than the area of each of the pixel electrodes AE1, AE2, and AE3 in the plan view. For example, the first hole OPT1 may have an area larger than that of the first pixel electrode AE1 in the plan view. The second hole OPT2 and the third hole OPT3 may also respectively have areas larger than those of the second pixel electrode AE2 and the third pixel electrode AE3 in the plan view. In addition, each of the holes OPT1, OPT2, and OPT3 of the first light-blocking layer BM1 may have a different area in the plan view. As described above, the areas of the plurality of pixel electrodes AE1, AE2, and AE3 may be different from each other, and correspondingly, the sizes of the holes OPT1, OPT2, and OPT3 in the first light-blocking layer BM1 may also be different from each other. For example, the diameter or size of the third hole OPT3 may be larger than the diameter or size of the first hole OPT1 and the second hole OPT2, and the diameter or size of the first hole OPT1 may be larger than the diameter or size of the second hole OPT2. However, the present disclosure is not limited thereto.

[0062] In some embodiments, regardless of the types of the pixel electrodes AE1, AE2, and AE3 or the holes OPT1, OPT2, and OPT3, the difference between the diameters of the pixel electrodes AE1, AE2, and AE3 and the diameters of the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 or the spacing distance between the outside of the pixel electrodes AE1, AE2, and AE3 and the inside of the holes OPT1, OPT2, and OPT3 may be uniform. For example, the spacing distance between the first pixel electrode AE1 and the first hole OPT1 or the difference between the diameter of the first pixel electrode AE1 and the diameter of the first hole OPT1 may be approximately equal to the spacing distance between the second pixel electrode AE2 and the second hole OPT2 or the difference between the diameter of the second pixel electrode AE2 and the diameter of the second hole OPT2. This may also be approximately equal to the spacing distance between the third pixel electrode AE3 and the third hole OPT3 or the difference between the diameter of the third pixel electrode AE3 and the diameter of the third hole OPT3. However, the present disclosure is not limited thereto, and the spacing distances between the pixel electrodes AE1, AE2, and AE3 and the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may be different according to the types of the pixel electrodes AE1, AE2, and AE3.

[0063] According to an embodiment, the display device 10 may include pixels PX1, PX2, PX3, and PX4 having different spacing distances between pixel electrodes AE1, AE2, and AE3 and holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1. For example, in the first pixel PX1 and the third pixel PX3, the spacing distances between the pixel electrodes AE1, AE2, and AE3 and the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may be approximately equal to each other. Similarly, in the second pixel PX2 and the fourth pixel PX4, the spacing distances between the pixel electrodes AE1, AE2, and AE3 and the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may be approximately equal to each other. However, in the first pixel PX1 and the second pixel PX2, the spacing distances between the pixel electrodes AE1, AE2, and AE3 and the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may be different from each other. In an embodiment, the spacing distances between the pixel electrodes AE1, AE2, and AE3 and the holes OPT1, OPT2, and OPT3 in the first pixel PX1 and the third pixel PX3 may be larger than the spacing distances between the pixel electrodes AE1, AE2, and AE3 and the holes OPT1, OPT2, and OPT3 in the second pixel PX2 and the fourth pixel PX4. In the second pixel PX2 and the fourth pixel PX4, the diameter differences between the pixel electrodes AE1, AE2, and AE3 and the holes OPT1, OPT2, and OPT3 may be small, and the outer sides of the pixel electrodes AE1, AE2, and AE3 and the inner sides of the holes OPT1, OPT2, and OPT3 may be positioned adjacent to each other in a plan view.

[0064] The display device 10 may include first type pixels such as the first pixel PX1 and the third pixel PX3 and second type pixels such as the second pixel PX2 and the fourth pixel PX4. The first type pixels and the second type pixels may be distinguished not only by the spacing distances between the pixel electrodes AE1, AE2, and AE3 and the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1, but also by whether the second light blocking layer BM2 described further below is provided. For example, in an embodiment, the second light blocking layer BM2 is not provided in the first pixel PX1 and the third pixel PX3, and the second light blocking layer BM2 is provided in the second pixel PX2 and the fourth pixel PX4. The second light blocking layer BM2 may surround the corresponding pixel electrodes AE1, AE2, and AE3 in some of the pixels (e.g., PX2 and PX4 in the above example), but not surround the corresponding pixel electrodes AE1, AE2, and AE3 in all pixels (e.g., PX1 and PX3 in the above example). The second light blocking layer BM2 will be described in further detail below.

[0065] Multiple color filters CF1, CF2, and CF3 can be respectively set to correspond to pixel electrodes AE1, AE2, and AE3. For example, color filters CF1, CF2, and CF3 can be disposed on a first light-blocking layer BM1 and can be set to correspond to multiple holes OPT1, OPT2, and OPT3 in the first light-blocking layer BM1. The holes OPT1, OPT2, OPT3 of the first light-blocking layer BM1 can be formed to overlap with the openings of a pixel defining layer PDL (see Figure 8 ), and can form a light-emitting area through which the light emitted from the emission area is emitted. Each of the color filters CF1, CF2, and CF3 can have an area larger than the holes OPT1, OPT2, OPT3 of the first light-blocking layer BM1, and each of the color filters CF1, CF2, and CF3 can completely cover the light-emitting area formed by the holes OPT1, OPT2, OPT3. Each of the color filters CF1, CF2, and CF3 can completely cover the holes OPT1, OPT2, OPT3 of the first light-blocking layer BM1, and a part of the color filters CF1, CF2, and CF3 can be directly disposed on the first light-blocking layer BM1.

[0066] The color filters CF1, CF2, and CF3 can include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are respectively set to correspond to different pixel electrodes AE1, AE2, and AE3. The color filters CF1, CF2, and CF3 can include colorants such as dyes or pigments that absorb light in a band different from that of light in a specific band, and can be set to correspond to the colors of the light emitted by light-emitting elements including the pixel electrodes AE1, AE2, and AE3. For example, the first color filter CF1 can be a red color filter that is set to overlap with the first pixel electrode AE1 and only transmits the first red light. The second color filter CF2 can be a green color filter that is set to overlap with the second pixel electrode AE2 and only transmits the second green light, and the third color filter CF3 can be a blue color filter that is set to overlap with the third pixel electrode AE3 and only transmits the third blue light.

[0067] Similar to the setting of the pixel electrodes AE1, AE2, and AE3, the color filters CF1, CF2, and CF3 can be in the PenTile ® type (e.g., Diamond PenTile ®Type) setting. For example, the first color filter CF1 and the third color filter CF3 may be alternately arranged in the first direction DR1 and the second direction DR2. The second color filter CF2 and another adjacent second color filter CF2 may be arranged in the first direction DR1 and the second direction DR2, and the second color filter CF2 and the adjacent first color filter CF1 and the adjacent third color filter CF3 may be arranged in the fourth direction DR4 or the fifth direction DR5. A plurality of second color filters CF2 may be repeatedly arranged along the first direction DR1 and the second direction DR2, and the second color filter CF2 and the first color filter CF1, or the second color filter CF2 and the third color filter CF3 may be alternately arranged along the fourth direction DR4 or the fifth direction DR5.

[0068] According to an embodiment, the plurality of color filters CF1, CF2, and CF3 may have different areas in a plan view. As described above, the areas of the plurality of pixel electrodes AE1, AE2, and AE3 may be different from each other, and accordingly, the sizes of the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 and the areas of the color filters CF1, CF2, and CF3 in the plan view may also be different from each other. For example, the area of the first color filter CF1, which is a red color filter, may be larger than the area of the second color filter CF2, which is a green color filter, and the area of the third color filter CF3, which is a blue color filter. Additionally, the area of the third color filter CF3 may be larger than the area of the second color filter CF2. The shapes of the color filters CF1, CF2, and CF3 in the plan view may be circular shapes similar to the shapes of the pixel electrodes AE1, AE2, and AE3. However, the present disclosure is not limited thereto, and the color filters CF1, CF2, and CF3 may have a rectangular shape or a rhombus shape in the plan view. The display device 10 according to an embodiment may be designed such that the planar shapes and areas of the color filters CF1, CF2, and CF3 allow the external light of the display device 10 to have a specific color.

[0069] In an embodiment, the planar area ratio of the first color filter CF1 and the second color filter CF2 may be in the range of about 1:0.3 to about 1:0.7, and the area ratio of the first color filter CF1 and the third color filter CF3 may be in the range of about 1:0.4 to about 1:1. For example, the area ratio of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be about 1:0.59:0.52 or about 1:0.59:1. However, the area ratio of the color filters CF1, CF2, and CF3 is not limited to the above ratios, and the planar areas of the color filters CF1, CF2, and CF3 may be designed differently such that the reflected light in the display device 10 and the electronic device 1 has desired color coordinates.

[0070] The display device 10 may include color filters CF1, CF2, and CF3 disposed on the display layer DU, and the color filters CF1, CF2, and CF3 may reduce the intensity of reflected light caused by external light. In addition, the color of the reflected light caused by external light may be controlled by adjusting the arrangement, shape, and area of the color filters CF1, CF2, and CF3 in the plan view. A detailed description thereof will be provided below.

[0071] The touch electrode TL may be disposed between the pixel electrodes AE1, AE2, and AE3. The touch electrode TL may be arranged to extend in the fourth direction DR4 and the fifth direction DR5, and may be spaced apart from the pixel electrodes AE1, AE2, and AE3. The touch electrode TL may be arranged to overlap with the pixel defining layer PDL (see Figure 8 ). The touch electrode TL may include a touch driving electrode and a sensing electrode.

[0072] Figure 6 is a plan view showing the arrangement of pixel electrodes and the second light blocking layer in the display area of the display device according to an embodiment. Figure 7 is a schematic diagram showing a light emitting pixel according to the emission mode of the display device according to an embodiment. Figure 7 Schematically shows a light emitting pixel in an emission mode with limited lateral visibility among the emission modes of the display device 10.

[0073] Refer to Figure 6 and Figure 7 , the display device 10 according to an embodiment may include a second light blocking layer BM2. The second light blocking layer BM2 may be disposed only on some of the plurality of pixels in the display area DA. For example, the second light blocking layer BM2 may be disposed in the second type of pixels (e.g., the second pixel PX2 and the fourth pixel PX4) among the plurality of pixels PX1, PX2, PX3, and PX4. As described above, the plurality of pixels PX1, PX2, PX3, and PX4 may include two types of pixels having different spacing distances between the pixel electrodes AE1, AE2, and AE3 and the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1, and the second light blocking layer BM2 may be disposed only in the second type of pixels.

[0074] The second light blocking layer BM2 may include a plurality of light blocking patterns BMP1, BMP2, and BMP3 (see Figure 11), and the light-blocking pattern can be set to correspond to the plurality of pixel electrodes AE1, AE2, and AE3, respectively. For example, the light-blocking pattern can have a uniform / constant width and surround the pixel electrodes AE1, AE2, and AE3 in a plan view, but can be set not to overlap with the pixel electrodes AE1, AE2, and AE3. The light-blocking pattern does not cover the pixel electrodes AE1, AE2, and AE3 in a plan view and can have an annular shape surrounding them. Similar to the holes OPT1, OPT2, and OPT3 of the first light-blocking layer BM1, the inner side of the light-blocking pattern can be spaced apart from the outer sides of the pixel electrodes AE1, AE2, and AE3 in a plan view.

[0075] In the display device 10 according to the embodiment, the plurality of pixels PX1, PX2, PX3, and PX4 include first-type pixels in which the second light-blocking layer BM2 is not provided and second-type pixels in which the second light-blocking layer BM2 is provided. Therefore, the lateral visibility can be adjusted according to the emission mode. According to the viewing angle of the display device 10, the light-blocking pattern of the second light-blocking layer BM2 can partially cover the pixel electrodes AE1, AE2, and AE3 and block the emission of light at a specific viewing angle.

[0076] For example, in the first emission mode of the display device 10, in a state where the lateral visibility is not restricted, both the first-type pixels and the second-type pixels can emit light. For example, as Figure 6 shown, when all the first pixels PX1, second pixels PX2, third pixels PX3, and fourth pixels PX4 emit light in the first emission mode, the light emitted from at least both the first pixel PX1 and the third pixel PX3 can be visually recognized by the user regardless of the viewing direction of the display device 10.

[0077] On the other hand, in the second emission mode of the display device 10, in a state where the lateral visibility is restricted, only the second-type pixels can emit light. For example, as Figure 7 shown, when only the second pixels PX2 and the fourth pixels PX4 emit light in the second emission mode, the light emitted from the holes OPT1, OPT2, and OPT3 of the first light-blocking layer BM1 can be blocked by the second light-blocking layer BM2 at a specific viewing angle. In the embodiment, in the second emission mode, since the first pixels PX1 and the third pixels PX3 do not emit light, the display screen of the display device 10 can be visually recognized only by the user viewing from the front surface of the display area DA, and the display screen is not visually recognized by the user viewing at a specific viewing angle or from the side. For example, the display device 10 can provide a privacy protection mode to the user.

[0078] In the second emission mode of the display device 10, light leakage of the emitted light may occur according to the degree to which the pixel electrodes AE1, AE2, and AE3 of the second pixel PX2 and the fourth pixel PX4 are blocked by the second light blocking layer BM2. However, in the display device 10 according to an embodiment, the light blocking pattern of the second light blocking layer BM2 may be set to correspond to the shapes of the pixel electrodes AE1, AE2, and AE3 and surround the pixel electrodes AE1, AE2, and AE3 with a uniform / constant width. In the second emission mode, the degrees to which the pixel electrodes AE1, AE2, and AE3 of the second type of pixel are blocked are uniform at all viewing angles of the display device 10. Therefore, the embodiment can prevent light leakage of the light emitted from the light emitting elements including the specific pixel electrodes AE1, AE2, and AE3.

[0079] In addition, in the display device 10, since the light blocking member of the second light blocking layer BM2 is set to correspond to the pixel electrodes AE1, AE2, and AE3 of the second type of pixel, the light blocking member can be set not to intrude into another adjacent pixel (e.g., the first type of pixel), and thus the pixel electrodes of the first type of pixel can be not blocked in the first emission mode. That is, in the display device 10, although a high-resolution display device is implemented, the setting of the pixel structure can be freely designed.

[0080] Figure 8 is a cross-sectional view taken along the Figure 5 and Figure 6 line X1-X1'. Figure 9 is a cross-sectional view taken along the Figure 5 and Figure 6 line X2-X2'. Figure 10 is a cross-sectional view taken along the Figure 6 line X3-X3' and X4-X4'.

[0081] Figure 8 shows a cross-section passing through the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 in the first pixel PX1 which is the first type of pixel, Figure 9 shows a cross-section passing through the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 in the second pixel PX2 which is the second type of pixel. Figure 10 shows a cross-section passing through the first pixel electrode AE1 of the first type of pixel and the first pixel electrode AE1 of the second type of pixel.

[0082] will be described with reference to Figures 8 to 10 the cross-sectional structure of the display device 10. The display panel 100 of the display device 10 (see Figure 3 ) may include a display layer DU (see Figure 3),(touch sensing layer TSU, first light blocking layer BM1, color filter layer CFL, and second light blocking layer BM2. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and a packaging layer TFEL. The first light blocking layer BM1 may be disposed on the touch sensing layer TSU of the display panel 100, and color filters CF1, CF2, and CF3 of the color filter layer CFL may be disposed on the first light blocking layer BM1. The second light blocking layer BM2 may be disposed on the passivation layer PSV, the passivation layer PSV is disposed on the color filter layer CFL, and a coating layer OC may be disposed on the second light blocking layer BM2.

[0083] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. Again, for example, the substrate SUB may include a glass material or a metal material.

[0084] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0085] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing air or water from permeating. For example, the first buffer layer BF1 may include a plurality of inorganic layers stacked alternately.

[0086] The lower metal layer BML may be disposed on the first buffer layer BF1. For example, the lower metal layer BML may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0087] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing air or water from permeating. For example, the second buffer layer BF2 may include a plurality of inorganic layers stacked alternately.

[0088] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of each of a plurality of pixels. For example, the thin film transistor TFT may be a switching transistor or a driving transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0089] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may be stacked with the lower metal layer BML and the gate electrode GE in the thickness direction, and may be insulated from the gate electrode GE through the gate insulating layer GI. In a part of the semiconductor layer ACT, the material of the semiconductor layer ACT may be made into a conductor to form the source electrode SE and the drain electrode DE.

[0090] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may be stacked with the semiconductor layer ACT, and the gate insulating layer GI is interposed between the gate electrode GE and the semiconductor layer ACT.

[0091] The gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 to insulate the gate electrode GE from the semiconductor layer ACT. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0092] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0093] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may be stacked with the gate electrode GE in the thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitance.

[0094] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0095] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into the contact holes provided in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0096] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include contact holes through which the second connection electrode CNE2 passes.

[0097] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrodes AE1, AE2, or AE3 of the light emitting element ED. The second connection electrode CNE2 may be inserted into the contact holes formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0098] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrode AE of the light emitting element ED passes.

[0099] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include the light emitting element ED and the pixel defining layer PDL. The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, a light emitting layer EL, and a common electrode CE.

[0100] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. Each of the different pixel electrodes AE1, AE2, and AE3 may be disposed to overlap with one of the different openings of the pixel defining layer PDL. The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0101] The light emitting layer EL may be disposed on the pixel electrodes AE1, AE2, and AE3. For example, the light emitting layer EL may be an organic light emitting layer made of an organic material, but is not limited thereto. In the case where an organic light emitting layer is used as the light emitting layer EL, the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED, and if the common electrode CE of the light emitting element ED receives a common voltage or a cathode voltage, holes and electrons may move to the light emitting layer EL through the hole transport layer and the electron transport layer and combine to generate light to be emitted by the light emitting layer EL.

[0102] In an embodiment, the light-emitting layers EL provided on different pixel electrodes AE1, AE2, and AE3 may emit lights of different colors. For example, the light-emitting layer provided on the first pixel electrode AE1 may emit red light of a first color, the light-emitting layer provided on the second pixel electrode AE2 may emit green light of a second color, and the light-emitting layer provided on the third pixel electrode AE3 may emit blue light of a third color. However, the present disclosure is not limited thereto. In an embodiment, the light-emitting layer EL may be provided as a common layer on different pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL, or the light-emitting layers EL provided on different pixel electrodes AE1, AE2, and AE3 may emit lights of the same color. In this case, the display device 10 may further include a color adjustment layer provided on the light-emitting element ED.

[0103] The common electrode CE may be disposed on the light-emitting layer EL. For example, the common electrode CE may be formed in the form of an electrode shared by all pixels instead of in the form of an electrode specific to each pixel. The common electrode CE may be provided on the light-emitting layer EL on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, and may be provided on the pixel defining layer PDL in an area other than the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3.

[0104] The common electrode CE may receive a common voltage or a low-potential voltage. When the pixel electrode AE receives a voltage corresponding to the data voltage and the common electrode CE receives a low-potential voltage, a potential difference is formed between the pixel electrodes AE1, AE2, and AE3 and the common electrode CE, so that the light-emitting layer EL can emit light.

[0105] The pixel defining layer PDL may include a plurality of openings and may be provided on a part of the pixel electrodes AE1, AE2, and AE3 and the second passivation layer PAS2. Each opening of the pixel defining layer PDL may expose a part of the pixel electrodes AE1, AE2, and AE3. As described above, the corresponding openings of the pixel defining layer PDL may define the first emission region to the third emission region, and the area or size of the corresponding openings may be different from each other. The pixel defining layer PDL may separate and insulate the pixel electrodes AE1, AE2, and AE3 of each of the plurality of light-emitting elements ED. The pixel defining layer PDL may include a light-absorbing material that can prevent light reflection. For example, the pixel defining layer PDL may include a polyimide (PI)-based adhesive and pigments mixed with red, green, and blue therein. Optionally, the pixel defining layer PDL may include a cardo-based adhesive resin and a mixture of an ε-caprolactam black pigment and a blue pigment. Optionally, the pixel defining layer PDL may include carbon black.

[0106] The encapsulation layer TFEL can be disposed on the common electrode CE to cover a plurality of light-emitting elements ED. The encapsulation layer TFEL can include at least one inorganic layer that can prevent oxygen or moisture from penetrating into the light-emitting element layer EML. The encapsulation layer TFEL can include at least one organic layer that can protect the light-emitting element layer EML from foreign substances such as dust.

[0107] In an embodiment, the encapsulation layer TFEL can include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 can be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed between the first encapsulation layer TFE1 and the third encapsulation layer TFE3 can be an organic encapsulation layer.

[0108] Each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 can include one or more inorganic insulating materials. The inorganic insulating materials can include, for example, alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0109] The second encapsulation layer TFE2 can include polymer-based materials. Examples of polymer-based materials can include acrylic resins, epoxy resins, polyimides, and polyethylene, etc. For example, the organic encapsulation layer can include an acrylic resin, for example, polymethyl methacrylate or polyacrylic acid, etc. The second encapsulation layer TFE2 can be formed by curing monomers or applying polymers.

[0110] The touch sensing layer TSU can be disposed on the encapsulation layer TFEL. The touch sensing layer TSU can include a first touch insulating layer SIL1, a second touch insulating layer SIL2, a touch electrode TL, and a third touch insulating layer SIL3.

[0111] The first touch insulating layer SIL1 can be disposed on the encapsulation layer TFEL. The first touch insulating layer SIL1 can have insulating and optical functions. The first touch insulating layer SIL1 can include at least one inorganic layer. In an embodiment, the first touch insulating layer SIL1 can be omitted.

[0112] The second touch insulating layer SIL2 can cover the first touch insulating layer SIL1. In an embodiment, a touch electrode of another layer can be further disposed on the first touch insulating layer SIL1, and the second touch insulating layer SIL2 can cover the touch electrode TL. The second touch insulating layer SIL2 can have insulating and optical functions. For example, the second touch insulating layer SIL2 can be an inorganic layer including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an alumina layer.

[0113] A part of the touch electrode TL may be disposed on the second touch insulating layer SIL2. In an embodiment, the touch electrode TL does not overlap with the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The touch electrode TL may be formed of a single layer including, for example, molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be formed to have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0114] The touch electrode TL of the touch sensing layer TSU may have a constant line width and may be disposed to overlap with the first light blocking layer BM1, which will be further described below. The first light blocking layer BM1 may have a width sufficient to completely cover the touch electrode TL and may define a gap between the edge of the first light blocking layer BM1 and the touch electrode TL. In an embodiment, the line width of the touch electrode TL may be in the range of about 4 μm to about 6 μm, and the gap between the edge of the touch electrode TL and the first light blocking layer BM1 may be in the range of about 5 μm to about 7 μm. The touch electrode TL may be disposed such that its center is substantially parallel to the center of the first light blocking layer BM1, and the gaps from both sides of the touch electrode TL to the edge of the first light blocking layer BM1 may be approximately constant.

[0115] The third touch insulating layer SIL3 may cover the touch electrode TL and the second touch insulating layer SIL2. The third touch insulating layer SIL3 may have insulating and optical functions. The third touch insulating layer SIL3 may be made of the same material as exemplified for the second touch insulating layer SIL2.

[0116] The first light blocking layer BM1 may be disposed on the third touch insulating layer SIL3 of the touch sensing layer TSU. The first light blocking layer BM1 may be disposed to cover the conductive line of the touch electrode TL and include a plurality of holes OPT1, OPT2, and OPT3 that overlap with the pixel electrodes AE1, AE2, and AE3. For example, the first hole OPT1 may be disposed to overlap with the first pixel electrode AE1, the second hole OPT2 may be disposed to overlap with the second pixel electrode AE2, and the third hole OPT3 may be disposed to overlap with the third pixel electrode AE3. The area or size of the holes OPT1, OPT2, and OPT3 may be larger than the area or size of the pixel electrodes AE1, AE2, and AE3. In addition, the area or size of each of the holes OPT1, OPT2, and OPT3 may be formed to be larger than the opening of the pixel defining layer PDL, and the light emitted from the light emitting element ED can be visually recognized by the user not only from the front of the display device 10 but also from the side of the display device 10.

[0117] The first light blocking layer BM1 may include a light absorbing material. For example, the first light blocking layer BM1 may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of, for example, lactam black, perylene black, and aniline black, but the embodiments are not limited thereto. The first light blocking layer BM1 may prevent visible light penetration and color mixing between the holes OPT1, OPT2, and OPT3, which may improve the color reproducibility of the display device 10. In an embodiment, the first light blocking layer BM1 may have a thickness of about 1 μm to about 3 μm, and in an embodiment, may have a thickness of about 1.5 μm.

[0118] In an embodiment, the sizes of the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 disposed to overlap with the first type of pixels may be larger than the sizes of the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 disposed to overlap with the second type of pixels. As Figure 10 shown, the size of the first hole OPT1 that overlaps with the first pixel electrode AE1 of the first type of pixels (or the third pixel PX3) may be larger than the size of the first hole OPT1 that overlaps with the first pixel electrode AE1 of the second type of pixels (or the fourth pixel PX4). As described above, in an embodiment, in the second emission mode of the display device 10, the first type of pixels do not emit light, and only the second type of pixels may emit light. When the second type of pixels emit light, the sizes of the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may be relatively small, which may block light from exiting at a specific viewing angle. In addition, since the second light blocking layer BM2 is disposed in the second type of pixels, the second emission mode of the display device 10 may control the lateral visibility of the light emitted from the second type of pixels.

[0119] The color filters CF1, CF2, and CF3 of the color filter layer CFL may be disposed on the first light blocking layer BM1. The different color filters CF1, CF2, and CF3 may be set to correspond to different pixel electrodes AE1, AE2, and AE3 and different holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1, respectively. For example, the first color filter CF1 may be set to correspond to the first pixel electrode AE1, the second color filter CF2 may be set to correspond to the second pixel electrode AE2, and the third color filter CF3 may be set to correspond to the third pixel electrode AE3. The first color filter CF1 may be disposed in the first hole OPT1 of the first light blocking layer BM1, the second color filter CF2 may be disposed in the second hole OPT2 of the first light blocking layer BM1, and the third color filter CF3 may be disposed in the third hole OPT3 of the first light blocking layer BM1. Each of the color filters CF1, CF2, and CF3 may be set to have an area larger than the holes OPT1, OPT2, OPT3 of the first light blocking layer BM1 in a plan view, and a part of each of the color filters CF1, CF2, and CF3 may be directly disposed on the first light blocking layer BM1.

[0120] The passivation layer PSV may be disposed on the first light blocking layer BM1 and the color filter layer CFL. The passivation layer PSV may be disposed to cover the entire display area DA, and may flatten the top surface of the display panel 100. The passivation layer PSV may be a colorless light transmissive layer having no color in the visible light band. For example, the passivation layer PSV may include a colorless light transmissive organic material such as an acrylic resin.

[0121] The second light blocking layer BM2 may be disposed on the passivation layer PSV. In an embodiment, the second light blocking layer BM2 is not disposed in the first type of pixel (or the third pixel PX3), but may be disposed only in the second type of pixel (or the fourth pixel PX4). The second light blocking layer BM2 may be disposed to correspond to the peripheries of the pixel electrodes AE1, AE2, and AE3 of the second type of pixel, and may form transmissive portions OPB1, OPB2, and OPB3, which are formed to overlap with the pixel electrodes AE1, AE2, and AE3. For example, the second light blocking layer BM2 may include a first transmissive portion OPB1 that overlaps with the first pixel electrode AE1, a second transmissive portion OPB2 that overlaps with the second pixel electrode AE2, and a third transmissive portion OPB3 that overlaps with the third pixel electrode AE3. The transmissive portions OPB1, OPB2, and OPB3 may overlap with the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1, respectively.

[0122] In an embodiment, the diameters or areas in a plan view of the transmissive portions OPB1, OPB2, and OPB3 of the second light-blocking layer BM2 may be larger than the diameters or areas in a plan view of the holes OPT1, OPT2, and OPT3 of the first light-blocking layer BM1 and the pixel electrodes AE1, AE2, and AE3. Light emitted from the light-emitting elements ED including the pixel electrodes AE1, AE2, and AE3 may be emitted through the holes OPT1, OPT2, and OPT3 of the first light-blocking layer BM1 and the transmissive portions OPB1, OPB2, and OPB3 of the second light-blocking layer BM2. Light emitted from the second-type pixels is finally emitted after passing through the transmissive portions OPB1, OPB2, and OPB3, and a large amount of light can be visually recognized at least when the display device 10 is viewed from the front.

[0123] However, when the display device 10 is viewed from the side, although the light passes through the holes OPT1, OPT2, and OPT3 of the first light-blocking layer BM1, the light emitted from the second-type pixels may be blocked by the second light-blocking layer BM2. That is, the display device 10 can control the visibility at a specific viewing angle and provide a privacy protection mode by making only the second-type pixels (or the fourth pixels PX4) provided with the second light-blocking layer BM2 emit light in the second emission mode.

[0124] The second light-blocking layer BM2 may include a light-absorbing material. For example, the second light-blocking layer BM2 may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of, for example, lactam black, perylene black, and aniline black, but the embodiment is not limited thereto. In an embodiment, the second light-blocking layer BM2 may have a thickness of about 1 μm to about 3 μm, and in an embodiment, may have a thickness of about 1.5 μm.

[0125] The coating layer OC may be provided on the second light-blocking layer BM2 and the passivation layer PSV. The coating layer OC may be provided to cover the entire display area DA and may flatten the top surface of the display panel 100. The coating layer OC may be a colorless light-transmissive layer that does not have a color in the visible light band. For example, the coating layer OC may include a colorless light-transmissive organic material such as an acrylic resin.

[0126] Hereinafter, the second light-blocking layer BM2 of the display device 10 and the pixel electrodes AE1, AE2, and AE3 will be described in more detail.

[0127] Figure 11 It is a diagram showing a relative arrangement of a second light-blocking layer and a pixel electrode provided in one pixel of a display device according to an embodiment. Figure 11 An example of a second-type pixel (or a second pixel PX2) provided with the second light-blocking layer BM2 is shown.

[0128] Reference Figure 11 In the display device 10, the diameters PR1, PR2, and PR3 of different pixel electrodes AE1, AE2, and AE3 may be different from each other. For example, the diameter PR3 of the third pixel electrode AE3 may be larger than the diameter PR1 of the first pixel electrode AE1 and the diameter PR2 of the second pixel electrode AE2. The diameter PR1 of the first pixel electrode AE1 may be larger than the diameter PR2 of the second pixel electrode AE2. For example, the areas of the pixel electrodes AE1, AE2, and AE3 may be designed in consideration of the wavelength of light emitted from the light-emitting elements ED respectively including the pixel electrodes AE1, AE2, and AE3, the lifetime of the light-emitting elements ED, and the like.

[0129] The second light-blocking layer BM2 may include light-blocking patterns BMP1, BMP2, and BMP3 corresponding to the pixel electrodes AE1, AE2, and AE3 respectively and surrounding the pixel electrodes AE1, AE2, and AE3 in a plan view. For example, the second light-blocking layer BM2 may include a first light-blocking pattern BMP1 surrounding the first pixel electrode AE1, a second light-blocking pattern BMP2 surrounding the second pixel electrode AE2, and a third light-blocking pattern BMP3 surrounding the third pixel electrode AE3. In the same manner as the number and arrangement of the pixel electrodes AE1, AE2, and AE3 included in one pixel PX1, PX2, or PX3, one pixel PX1, PX2, or PX3 may include one first light-blocking pattern BMP1, two second light-blocking patterns BMP2, and one third light-blocking pattern BMP3 that may be spaced apart from each other in a diagonal direction. However, the present disclosure is not limited thereto.

[0130] The plurality of light-blocking patterns BMP1, BMP2, and BMP3 of the second light-blocking layer BM2 may have the same width and may be provided to surround the pixel electrodes AE1, AE2, and AE3. The light-blocking patterns BMP1, BMP2, and BMP3 may form transmission portions OPB1, OPB2, and OPB3 (see Figure 9 ) that overlap with the pixel electrodes AE1, AE2, and AE3. The light-blocking patterns BMP1, BMP2, and BMP3 may have an annular shape and may have inner diameters IR1, IR2, and IR3 and outer diameters OR1, OR2, and OR3 measured from the centers of the pixel electrodes AE1, AE2, and AE3.

[0131] According to an embodiment, among the plurality of light-blocking patterns BMP1, BMP2, and BMP3 of the second light-blocking layer BM2, the difference or the interval distance between the inner diameters IR1, IR2, and IR3 and the diameters PR1, PR2, and PR3 of the pixel electrodes AE1, AE2, and AE3 may be uniform. For example, the difference between the inner diameter IR1 of the first light-blocking pattern BMP1 and the diameter PR1 of the first pixel electrode AE1 may be approximately the same as the difference between the inner diameter IR2 of the second light-blocking pattern BMP2 and the diameter PR2 of the second pixel electrode AE2, and the difference between the inner diameter IR3 of the third light-blocking pattern BMP3 and the diameter PR3 of the third pixel electrode AE3. Regardless of the types of the light-blocking patterns BMP1, BMP2, and BMP3 of the second light-blocking layer BM2, they may be disposed at a uniform interval distance from the pixel electrodes AE1, AE2, and AE3. In an embodiment, the interval distance between the light-blocking patterns BMP1, BMP2, and BMP3 of the second light-blocking layer BM2 and the pixel electrodes AE1, AE2, and AE3 may be in the range of about 1 μm to about 3 μm, and in an embodiment, it may be about 1.2 μm.

[0132] Although the diameters PR1, PR2, and PR3 of the pixel electrodes AE1, AE2, and AE3 are different from each other, since the interval distances from the pixel electrodes AE1, AE2, and AE3 are uniform, the inner diameters IR1, IR2, and IR3 and the outer diameters OR1, OR2, and OR3 of the light-blocking patterns BMP1, BMP2, and BMP3 may be different from each other. For example, the inner diameter IR3 of the third light-blocking pattern BMP3 may be larger than the inner diameter IR1 of the first light-blocking pattern BMP1 and the inner diameter IR2 of the second light-blocking pattern BMP2, and the inner diameter IR1 of the first light-blocking pattern BMP1 may be larger than the inner diameter IR2 of the second light-blocking pattern BMP2. Additionally, the outer diameter OR3 of the third light-blocking pattern BMP3 may be larger than the outer diameter OR1 of the first light-blocking pattern BMP1 and the outer diameter OR2 of the second light-blocking pattern BMP2, and the outer diameter OR1 of the first light-blocking pattern BMP1 may be larger than the outer diameter OR2 of the second light-blocking pattern BMP2. The sizes of the light-blocking patterns BMP1, BMP2, and BMP3 may be adjusted in various ways according to the diameters of the pixel electrodes AE1, AE2, and AE3 and the interval distances from the pixel electrodes AE1, AE2, and AE3.

[0133] Figure 12 It is a diagram showing the relative arrangement of the second light-blocking layer and the pixel electrode provided in one pixel of a display device according to an embodiment.

[0134] Refer to Figure 12, in the display device 10 according to the embodiment, the diameters PR1, PR2, and PR3 of the different pixel electrodes AE1, AE2, and AE3 may be different from each other. The plurality of light blocking patterns BMP1, BMP2, and BMP3 of the second light blocking layer BM2 may have approximately the same width and may be arranged to surround the pixel electrodes AE1, AE2, and AE3. However, different from the embodiment according to Figure 11 , in the plurality of light blocking patterns BMP1, BMP2, and BMP3 of the second light blocking layer BM2, the difference or the interval distance between the inner diameters IR1, IR2, and IR3 and the diameters PR1, PR2, and PR3 of the pixel electrodes AE1, AE2, and AE3 may be different from each other. For example, the difference between the inner diameter IR3 of the third light blocking pattern BMP3 and the diameter PR3 of the third pixel electrode AE3 may be smaller than the difference between the inner diameter IR1 of the first light blocking pattern BMP1 and the diameter PR1 of the first pixel electrode AE1 and the difference between the inner diameter IR2 of the second light blocking pattern BMP2 and the diameter PR2 of the second pixel electrode AE2. The difference between the inner diameter IR1 of the first light blocking pattern BMP1 and the diameter PR1 of the first pixel electrode AE1 may be smaller than the difference between the inner diameter IR2 of the second light blocking pattern BMP2 and the diameter PR2 of the second pixel electrode AE2. The interval distances between the pixel electrodes AE1, AE2, and AE3 and the light blocking patterns BMP1, BMP2, and BMP3 may be opposite to the order of the diameters PR1, PR2, and PR3 of the pixel electrodes AE1, AE2, and AE3.

[0135] Although the diameters PR1, PR2, and PR3 of the pixel electrodes AE1, AE2, and AE3 are different from each other and the interval distances between the light blocking patterns BMP1, BMP2, and BMP3 and the pixel electrodes AE1, AE2, and AE3 are also different, the inner diameters IR1, IR2, and IR3 and the outer diameters OR1, OR2, and OR3 of the light blocking patterns BMP1, BMP2, and BMP3 may be uniform. For example, the inner diameter IR1 of the first light blocking pattern BMP1 may be approximately the same as the inner diameter IR2 of the second light blocking pattern BMP2 and the inner diameter IR3 of the third light blocking pattern BMP3. In addition, the outer diameter OR1 of the first light blocking pattern BMP1 may be approximately the same as the outer diameter OR2 of the second light blocking pattern BMP2 and the outer diameter OR3 of the third light blocking pattern BMP3.

[0136] The degree to which the pixel electrodes AE1, AE2, and AE3 are blocked by the light-blocking patterns BMP1, BMP2, and BMP3 at a specific viewing angle when viewing the display device 10 may be related to the spacing distance between the pixel electrodes AE1, AE2, and AE3 and the light-blocking patterns BMP1, BMP2, and BMP3. In order for light not to be visually recognized when viewing the display device 10 from a specific viewing angle in the second emission mode, all of the pixel electrodes AE1, AE2, and AE3 are blocked regardless of the type of the pixel electrodes AE1, AE2, and AE3 at the corresponding viewing angle. When the diameters of the pixel electrodes AE1, AE2, and AE3 are different but the spacing distances from the light-blocking patterns BMP1, BMP2, and BMP3 are uniform, any one of the pixel electrodes AE1, AE2, and AE3 may be completely blocked at a specific viewing angle while the other pixel electrodes AE1, AE2, and AE3 may not be blocked, such that light can be visually recognized.

[0137] For example, in an embodiment, the second type of pixel (hereinafter referred to as the second pixel PX2) is not visually recognized at a viewing angle at which the pixel electrodes AE1, AE2, and AE3 are respectively blocked by the light-blocking patterns BMP1, BMP2, and BMP3. However, in a state where the other pixel electrodes AE1, AE3 are blocked by the light-blocking patterns BMP1, BMP2, and BMP3 at a specific viewing angle, the second pixel electrode AE2 having a relatively small diameter is not covered by the light-blocking patterns BMP1, BMP2, and BMP3. In this case, the light emitted from the light-emitting layer provided on the second pixel electrode AE2 of the second pixel PX2 may be visually recognized at the corresponding viewing angle. When the light-emitting layer provided on the second pixel electrode AE2 emits green light, a green phenomenon in which the display screen has a completely green color may occur at the corresponding viewing angle.

[0138] In addition, at a specific viewing angle, the second pixel electrode AE2 having a relatively smaller diameter than the other pixel electrodes may be blocked to a relatively large extent by the light-blocking patterns BMP1, BMP2, and BMP3. In this case, a relatively small amount of light emitted from the light-emitting layer provided on the second pixel electrode AE2 of the second pixel PX2 may be visually recognized at the corresponding viewing angle. When the light-emitting layer provided on the second pixel electrode AE2 emits green light, a magenta phenomenon in which the display screen has a full purple color may occur at the corresponding viewing angle due to the lack of green light.

[0139] In view of the above, in a perspective where pixel electrodes with a large diameter may be blocked by a light blocking pattern, in order to also block pixel electrodes with a small diameter by the light blocking pattern in a similar proportion, the spacing distance between them can be adjusted. In an embodiment, the spacing distances between pixel electrodes AE1, AE2, and AE3 and light blocking patterns BMP1, BMP2, and BMP3 can be different from each other, and the difference relationship can be opposite to the diameter difference relationship of pixel electrodes AE1, AE2, and AE3.

[0140] Figure 13 and Figure 14 is a view showing a second light blocking layer of a display device according to an embodiment.

[0141] Referring to Figure 13 , in a second light blocking layer BM2 according to an embodiment, light blocking patterns BMP1, BMP2, and BMP3 respectively provided to correspond to pixel electrodes AE1, AE2, and AE3 and surrounding pixel electrodes AE1, AE2, and AE3 can be integrated with each other. Different from the embodiment according to Figure 12 , in the embodiment according to Figure 13 , the light blocking patterns BMP1, BMP2, and BMP3 are integrated.

[0142] The second light blocking layer BM2 can be formed through a patterning process using a mask. In an embodiment, in terms of the process, a large pattern integrated with each other can be formed instead of forming a plurality of patterns spaced apart from each other. Therefore, the display device 10 can include a single light blocking pattern BMP provided to correspond to each second type of pixel (or second pixel PX2), but can have a shape in which the light blocking pattern BMP does not cover pixel electrodes AE1, AE2, and AE3 and includes transmissive portions OPB1, OPB2, and OPB3 superimposed on pixel electrodes AE1, AE2, and AE3.

[0143] Referring to Figure 14 , in a second light blocking layer BM2 according to an embodiment, light blocking patterns BMP1, BMP2, and BMP3 respectively provided to correspond to pixel electrodes AE1, AE2, and AE3 and surrounding pixel electrodes AE1, AE2, and AE3 can be connected to each other (i.e., they can be directly connected). The embodiment according to Figure 14 can be different from the embodiment according to Figure 12 in that the light blocking patterns BMP1, BMP2, and BMP3 are connected through a connecting portion BMC. Optionally, the embodiment according to Figure 14 can be different from the embodiment according to Figure 13The embodiments may differ in that the center of the light-blocking pattern BMP is removed. As described above, in the mask process for forming the second light-blocking layer BM2, the embodiments may form one large pattern instead of forming a plurality of patterns spaced apart from each other. Additionally, the embodiments may reduce the area where the second light-blocking layer BM2 is provided, which may improve color adjustment. The display device 10 may include a shape in which a plurality of light-blocking patterns BMP1, BMP2, and BMP3 respectively provided to correspond to the pixel electrodes AE1, AE2, and AE3 of the second type of pixel (or second pixel PX2) are connected to other adjacent patterns through connection portions BMC.

[0144] Although the present disclosure has been specifically shown and described with reference to embodiments thereof, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the claims.

Claims

1. A display device, the display device comprising: A plurality of pixels disposed in a display area, wherein each of the plurality of pixels includes: a plurality of pixel electrodes spaced apart from each other; a first light-blocking layer disposed in the display area and including a plurality of holes overlapping with the plurality of pixel electrodes; and a plurality of color filters disposed on the first light-blocking layer and corresponding to the plurality of holes respectively, wherein some of the plurality of pixels further include: a second light-blocking layer disposed on the color filters of some of the plurality of pixels and corresponding to the pixel electrodes of some of the plurality of pixels, wherein the second light-blocking layer surrounds the corresponding pixel electrodes of some of the plurality of pixels in a plan view and includes a plurality of light-blocking patterns having a constant width.

2. The display device according to claim 1, wherein, The plurality of pixel electrodes include a first pixel electrode and a second pixel electrode having a diameter larger than that of the first pixel electrode, the second light-blocking layer includes a first light-blocking pattern corresponding to the first pixel electrode and a second light-blocking pattern corresponding to the second pixel electrode, and the spacing distance between the outer side of the first pixel electrode and the inner side of the first light-blocking pattern is equal to the spacing distance between the outer side of the second pixel electrode and the inner side of the second light-blocking pattern.

3. The display device according to claim 2, wherein The spacing distance between the outer side of the first pixel electrode and the inner side of the first light-blocking pattern is in the range of 1 μm to 3 μm.

4. The display device according to claim 2, wherein, The first light-blocking pattern and the second light-blocking pattern have the same width, and the inner diameter from the center of the first pixel electrode to the inner side of the first light-blocking pattern is larger than the inner diameter from the center of the second pixel electrode to the inner side of the second light-blocking pattern.

5. The display device according to claim 4, wherein, The outer diameter from the center of the first pixel electrode to the outer side of the first light-blocking pattern is larger than the outer diameter from the center of the second pixel electrode to the outer side of the second light-blocking pattern.

6. The display device according to claim 1, wherein, The plurality of pixel electrodes include a first pixel electrode and a second pixel electrode having a diameter larger than that of the first pixel electrode, the second light-blocking layer includes a first light-blocking pattern corresponding to the first pixel electrode and a second light-blocking pattern corresponding to the second pixel electrode, and the spacing distance between the outer side of the first pixel electrode and the inner side of the first light-blocking pattern is different from the spacing distance between the outer side of the second pixel electrode and the inner side of the second light-blocking pattern.

7. The display device according to claim 6, wherein, The spacing distance between the outer side of the first pixel electrode and the inner side of the first light-blocking pattern is smaller than the spacing distance between the outer side of the second pixel electrode and the inner side of the second light-blocking pattern.

8. The display device according to claim 7, wherein, The first light-blocking pattern and the second light-blocking pattern have the same width, the inner diameter from the center of the first pixel electrode to the inner side of the first light-blocking pattern is equal to the inner diameter from the center of the second pixel electrode to the inner side of the second light-blocking pattern, and The outer diameter from the center of the first pixel electrode to the outside of the first light-blocking pattern is equal to the outer diameter from the center of the second pixel electrode to the outside of the second light-blocking pattern.

9. The display device according to claim 1, wherein, The plurality of light-blocking patterns are directly connected to each other.

10. The display device according to claim 1, wherein, The second light-blocking layer includes a transmissive portion that overlaps with the corresponding pixel electrodes of some of the plurality of pixels, and The transmissive portion of the second light-blocking layer overlaps with the holes of the first light-blocking layer.

11. The display device according to claim 10, wherein, The diameter of the transmissive portion of the second light-blocking layer is larger than the diameter of the corresponding hole in the holes of the first light-blocking layer.

12. The display device according to claim 1, wherein, The plurality of pixels include a first pixel and a second pixel. The second light-blocking layer is not provided in the first pixel, and the light-blocking patterns are respectively provided in the second pixel and correspond to the corresponding pixel electrodes.

13. The display device according to claim 12, wherein, The diameter of one of the holes in the first light-blocking layer in the first pixel is larger than the diameter of one of the holes in the first light-blocking layer in the second pixel.

14. The display device according to claim 13, wherein, The difference between the diameter of one of the pixel electrodes in the first pixel and the diameter of one of the holes in the first light-blocking layer in the first pixel is larger than the difference between the diameter of one of the pixel electrodes in the second pixel and the diameter of one of the holes in the first light-blocking layer in the second pixel.

15. The display device according to claim 1, wherein, The thickness of each of the first light-blocking layer and the second light-blocking layer is in the range of 1 μm to 3 μm.

16. A display device, the display device includes: A first pixel and a second pixel, disposed on a substrate, wherein each of the first pixel and the second pixel includes: a plurality of pixel electrodes; an encapsulation layer disposed on the plurality of pixel electrodes; a first light-blocking layer disposed on the encapsulation layer and including a plurality of holes corresponding to the plurality of pixel electrodes respectively; a plurality of color filters disposed on the first light-blocking layer and corresponding to the plurality of pixel electrodes respectively; a passivation layer disposed on the plurality of color filters and the first light-blocking layer; and a coating layer disposed on the first light-blocking layer, wherein the second pixel further includes: a second light-blocking layer disposed between the passivation layer and the coating layer in the second pixel, and including a plurality of light-blocking patterns forming a plurality of transmissive portions corresponding to the pixel electrodes of the second pixel respectively, wherein the diameter of each of the plurality of transmissive portions of the second light-blocking layer is larger than the diameter of the corresponding hole in the plurality of holes of the first light-blocking layer.

17. The display device according to claim 16, wherein, Each of the plurality of holes in the first light-blocking layer overlaps with the corresponding pixel electrode among the pixel electrodes, and The diameter of one of the plurality of holes in the first light-blocking layer in the first pixel is larger than the diameter of one of the plurality of holes in the first light-blocking layer in the second pixel.

18. The display device according to claim 16, wherein, The plurality of pixel electrodes have different diameters, and In the second pixel, the differences between the diameters of different pixel electrodes and the diameters of the transmissive portions of the corresponding light-blocking patterns are equal to each other.

19. The display device according to claim 16, wherein, The plurality of pixel electrodes have different diameters, and In the second pixel, the differences between the diameters of different pixel electrodes and the diameters of the transmissive portions of the corresponding light-blocking patterns are different from each other.

20. The display device according to claim 19, wherein, The second pixel includes a first pixel electrode and a second pixel electrode having a diameter larger than that of the first pixel electrode, The second light-blocking layer includes a first light-blocking pattern forming a first transmissive portion overlapping with the first pixel electrode and a second light-blocking pattern forming a second transmissive portion overlapping with the second pixel electrode, and The difference between the diameter of the first pixel electrode and the diameter of the first transmissive portion is smaller than the difference between the diameter of the second pixel electrode and the diameter of the second transmissive portion.

Images