Serial data communication method, electronic equipment, communication system and storage medium

Abstract

The invention relates to a serial data communication method, electronic equipment, a communication system and a storage medium, the serial data communication method is applied to a slave, the slave is connected with a host through a clock line and a data line, the chip selection signal end of the slave is suspended, the slave comprises a communication module and a timer, the input end of the timer is connected with the clock end of the communication module, and the input end of the timer is connected with the clock end of the communication module. The output end of the timer is connected with the reset end of the communication module; the method comprises: receiving a clock signal sent by a host; detecting a level change of the clock signal based on the timer; under the condition that the timer continuously detects the same type of level, judging that the clock signal is in an idle state, and triggering the timer to count and overflow; and triggering the communication module to reset under the condition that the counting of the timer overflows. On the premise of reducing wire harnesses, the signal interference capability is enhanced, the probability of communication collapse is reduced, and the reliability of half-duplex synchronous communication after chip selection signals are omitted is improved.

Description

Technical Field

[0001] The present application relates to the field of data communication, and particularly to a serial data communication method, an electronic device, a communication system, and a storage medium. Background Art

[0002] The Serial Peripheral Interface (SPI for short) is a high-speed synchronous serial communication bus. Data is transmitted between devices through four lines: clock, receive, transmit, and chip select. Due to its simple and easy-to-use characteristics, many Microcontroller Units (MCUs) or Digital Signal Processors (DSPs) integrate the SPI protocol and are widely used in the communication field, especially for building a network layout of one host and multiple slaves in local boards. In the fields of industrial automation and transportation, SPI is usually used for point-to-point communication, that is, one host is connected to one slave.

[0003] In view of the above scenarios involving long-distance communication and harsh electromagnetic environments, differential drive and twisted pairs are usually adopted to enhance signal integrity. Using the chip select signal and the full-duplex communication mode will result in too many wire harnesses and complex connections. However, if the chip select signal is omitted, although the wire harnesses between devices are reduced, once the clock signal is interfered, the communication will go wrong, resulting in signal transmission failure, and in severe cases, communication breakdown will occur.

[0004] Currently, in view of the problem of weak anti-interference ability of serial data communication in the related technology when the chip select signal is omitted, no effective solution has been proposed. Summary of the Invention

[0005] Based on this, it is necessary to provide a serial data communication method, an electronic device, a communication system, and a storage medium that can enhance the anti-interference ability for the above technical problems.

[0006] In a first aspect, the present application provides a serial data communication method, which is applied to a slave device. The slave device is connected to a master device through a clock line and a data line, and the chip select signal terminal of the slave device is left floating. The slave device includes a communication module and a timer. The input end of the timer is connected to the clock end of the communication module, and the output end of the timer is connected to the reset end of the communication module. The method includes:

[0007] Receiving the clock signal sent by the master device;

[0008] Detecting the level change of the clock signal based on the timer;

[0009] In the case where the timer continuously detects the same type of level, it is determined that the clock signal is in an idle state, and the timer count overflow is triggered;

[0010] In the case where the timer count overflows, the communication module is triggered to reset.

[0011] In some embodiments, the configured timing overflow value in the timer is greater than the synchronous clock period of the host and less than the data transmission time interval of the host.

[0012] In some embodiments, detecting the clock signal based on the timer detecting the level change of the clock signal further includes:

[0013] In the case where the first edge of the clock signal is detected, the timer count is triggered;

[0014] In the case where the second edge of the clock signal is detected, the count value of the timer is cleared and counting starts again.

[0015] In some embodiments, the method further includes:

[0016] Receiving data sent by the host;

[0017] Determining whether the data contains a first command code;

[0018] In the case where it is determined that the data contains the first command code, the slave enters the first working mode; wherein, in the first working mode, unidirectional data communication is performed between the slave and the host.

[0019] In some embodiments, after the slave enters the first working mode, the method further includes:

[0020] In the case where it is detected that the clock signal is in an idle state, determining whether the idle time of the clock signal is greater than a threshold;

[0021] In the case where it is determined that the idle time of the clock signal is greater than the threshold, the slave is switched from the first working mode to the second working mode; wherein, in the second working mode, two-way time-division communication is performed between the slave and the host.

[0022] In some embodiments, the method further includes: in the case where it is determined that the data does not contain the first command code, the slave enters the second working mode; wherein, in the second working mode, two-way time-division communication is performed between the slave and the host.

[0023] In some of these embodiments, after the slave device enters the second working mode, the method further includes:

[0024] When it is detected that the clock signal is in an idle state, it is determined whether the first command code is received continuously m times, where m is greater than 1;

[0025] When it is determined that the first command code is received continuously m times, the slave device is switched from the second working mode to the first working mode.

[0026] In a second aspect, the present application provides an electronic device, including: a communication module and a timer, an input end of the timer is connected to a clock end of the communication module, an output end of the timer is connected to a reset end of the communication module, and the electronic device is configured to execute the serial data communication method described in the first aspect above.

[0027] In a third aspect, the present application provides a serial data communication system, including: a host device and a slave device, the host device is connected to the slave device through a clock line and a data line, a chip select signal end of the slave device is left floating, and the slave device includes the electronic device described in the second aspect above.

[0028] In some of these embodiments, the first communication module of the slave device includes a first data sending end, a first data receiving end, and a first clock end; the host device includes a second communication module, and the second communication module includes a second data sending end, a second data receiving end, and a second clock end; wherein,

[0029] The first data sending end and the first data receiving end are connected to the second data sending end and the second data receiving end through the data line;

[0030] The first clock end is connected to the second clock end through the clock line.

[0031] In some of these embodiments, the slave device further includes a first RS485 unit and a second RS485 unit, the first communication module further includes a first control end, the host device further includes a third RS485 unit and a fourth RS485 unit, and the second communication module further includes a second control end; wherein,

[0032] The first RS485 unit is connected to the first data sending end, the first data receiving end, and the first control end, and the second RS485 unit is connected to the first clock end;

[0033] The third RS485 unit is connected to the second data sending end, the second data receiving end, and the second control end, and the fourth RS485 unit is connected to the second clock end;

[0034] The first RS485 unit and the third RS485 unit are connected through the data line, and the second RS485 unit and the fourth RS485 unit are connected through the clock line;

[0035] The first control end and the second control end are respectively used to control the data transmission direction.

[0036] In some embodiments, the slave device further includes a first switching unit, and the master device further includes a second switching unit; wherein,

[0037] The first switching unit includes a first static contact, a first moving contact and a first controlled end. The first moving contact is connected to the first data sending end or the first data receiving end, and the first controlled end is connected to the first control end;

[0038] The second switching unit includes a second static contact, a second moving contact and a second controlled end. The second moving contact is connected to the second data sending end or the second data receiving end, and the second controlled end is connected to the second control end;

[0039] The first static contact is connected to the second static contact through the data line;

[0040] The first clock terminal is connected to the second clock terminal through the clock line.

[0041] Fourthly, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in the first aspect above are implemented.

[0042] In the above serial data communication method, electronic device, communication system and storage medium, the slave device omits the chip select signal and detects the clock signal sent by the master device based on an external timer. When it detects that the clock signal is in an idle state, it triggers the communication module to automatically reset. With such a setting, even if the current frame data is affected by clock interference and the master / slave data is out of sync, it will only cause an error in the current frame data and will not affect the reception of the next data frame, reducing the influence range of clock interference. Therefore, on the premise of reducing the wiring harness, the signal interference resistance is enhanced, the probability of communication breakdown is reduced, and the reliability of half-duplex synchronous communication after omitting the chip select signal is improved. Description of the Drawings

[0043] Figure 1 is a schematic structural diagram of a serial data communication system in an embodiment;

[0044] Figure 2 is a schematic structural diagram of an electronic device in an embodiment;

[0045] Figure 3Schematic flowchart of a serial data communication method in an embodiment;

[0046] Figure 4 Schematic diagram of the signal waveform received by the slave in an embodiment Figure 1 ;

[0047] Figure 5 Schematic diagram of the signal waveform received by the slave in an embodiment Figure 2 ;

[0048] Figure 6 Schematic flowchart of a serial data communication method in an embodiment;

[0049] Figure 7 Schematic flowchart of a serial data communication method in an embodiment;

[0050] Figure 8 For Figure 7 Schematic diagram of the signal waveform received by the slave when it is initially powered on and enters the first working mode;

[0051] Figure 9 For Figure 7 Schematic diagram of the signal waveform received by the slave when it switches from the first working mode to the second working mode;

[0052] Figure 10 For Figure 7 Schematic diagram of the signal waveform received by the slave when it is initially powered on and enters the first working mode;

[0053] Figure 11 For Figure 7 Schematic diagram of the signal waveform received by the slave when writing data in the second working mode;

[0054] Figure 12 For Figure 7 Schematic diagram of the signal waveform received by the slave when reading data in the second working mode;

[0055] Figure 13 For Figure 7 Schematic diagram of the signal waveform received by the slave when it switches from the second working mode to the first working mode;

[0056] Figure 14 Schematic diagram of the structure of a serial data communication system in another embodiment;

[0057] Figure 15 Schematic diagram of the structure of a serial data communication system in another embodiment. Detailed implementation

[0058] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0059] Unless otherwise defined, the technical terms or scientific terms involved in the present application shall have the general meanings understood by those with ordinary skills in the technical field to which the present application belongs. In the present application, words such as "a", "one", "a kind of", "the", "these" and the like do not indicate a limitation in quantity, and they can be singular or plural. The terms "including", "comprising", "having" and any variants thereof involved in the present application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device including a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent in these processes, methods, products or devices. The terms "connected", "coupled" and the like involved in the present application are not limited to physical or mechanical connections, but may include electrical connections, whether directly or indirectly. The "plurality" involved in the present application means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" may mean: A exists alone, A and B exist simultaneously, and B exists alone. Usually, the character " / " indicates that the objects associated before and after are in an "or" relationship. The terms "first", "second", "third" and the like involved in the present application are only used to distinguish similar objects and do not represent a specific sorting of the objects.

[0060] If a chip select signal is used between the host and the slave and a full-duplex communication mode is adopted, at least 10 wire harnesses are required. Among them, the host notifies the slave to receive data by pulling down the chip select signal, and notifies the slave that the data transmission is completed by pulling up the chip select signal. In some application scenarios, half-duplex mode is adopted for data transmission and reception, which can save two wire harnesses, but there are still eight wire harnesses. For example, in the position sensor of the hub motor of an electric vehicle, the encoder is installed inside the hub, and the encoder wire harness needs to pass through the motor shaft hole together with the power line. Since the power line has strong interference radiation, the signal line needs to adopt differential twisted pair drive to reduce the noise impact, resulting in an increase in the number of wire harnesses and making it difficult to pass through the shaft hole. Therefore, in such applications, omitting the chip select signal and adopting half-duplex data communication can significantly reduce the number of wire harnesses. However, once the clock is interfered with after the chip select signal is omitted in SPI, it is easy to cause communication errors and ultimately lead to signal transmission failure.

[0061] Based on the analysis of the above situation, in one embodiment, Figure 1A serial data communication system is provided. The system includes a host and a slave. The host and the slave are connected through a clock line and a data line, and the chip select signal terminal of the slave is left floating. Among them, SPI_RX / SPI_TX represents the data receiving / sending terminal, and SPI_SCK represents the clock terminal. In this embodiment, the chip select signal terminal of the slave is left floating, which means the chip select signal is omitted. The host and the slave adopt a half-duplex communication mode, that is, there is only one data transmission direction for communication between the two parties at the same time. When one party sends data, the other party receives. This half-duplex communication mode omits the chip select signal and reduces the wiring harness.

[0062] The related technology provides a circuit that omits the chip select signal. By generating a chip select signal for the peripheral control component of the slave and simulating the input of the chip select signal to the slave, normal communication is achieved. However, the internal structure and control logic of the externally added chip select generation circuit are complex, which instead increases the complexity of synchronous communication and the manufacturing cost.

[0063] To solve this problem, Figure 2 An electronic device is provided. The electronic device includes a first communication module and a first timer (peripheral of the electronic device). Since there are timers both inside and outside the first communication module, for the convenience of distinction, in this embodiment, the external timer of the first communication module is defined as the first timer, and the internal timer of the first communication module is defined as the second timer. This electronic device serves as a slave and forms a serial data communication system with the host. Among them, the first timer is mainly used to monitor when the clock signal sent by the host is idle, and the second timer is mainly used to cooperate to complete other tasks inside the first communication module, such as capturing the pulse width of the host clock signal and calculating the synchronous clock period.

[0064] Continue to refer to Figure 2 , the first communication module includes a first data sending end SPI_TX1, a first data receiving end SPI_RX1, a first clock end SPI_SCK1, and a reset end RST. Among them, the input end TIM_CH of the first timer is connected to the first clock end SPI_SCK1, and the output end TGR of the first timer is connected to the reset end RST. The host includes a second communication module, and the second communication module includes a second data sending end SPI_TX2, a second data receiving end SPI_RX2, and a second clock end SPI_SCK2. Among them, the first data sending end SPI_TX1 and the first data receiving end SPI_RX1 are connected to the second data sending end SPI_TX2 and the second data receiving end SPI_RX2 through a data line; the first clock end SPI_SCK1 is connected to the second clock end SPI_SCK2 through a clock line.

[0065] The slave device can be a magnetic encoder or other servo motors, and the master device can be any electronic device with computing functions. The slave device executes tasks by receiving the command code from the master device and feeds back data to the master device. The first communication module can be any processor with computing functions, such as a Microcontroller Unit (MCU).

[0066] In the half-duplex communication mode of this embodiment, the chip select signal is omitted, reducing the wiring harness. At the same time, to enhance the signal anti-interference ability, Figure 3 A serial data communication method is provided, taking the slave device in Figure 1 or Figure 2 as an example for illustration, including the following steps:

[0067] Step S101, receive the clock signal sent by the master device.

[0068] In synchronous communication, the master device sends a clock signal to the slave device. Each frame of data sent by the master device is accompanied by a string of clock signals, and the clock signal has a fixed time length, defined as the synchronous clock period. During the process of the master device sending data, when a frame of data is sent, there will be a data sending time interval, which is defined as the clock idle period, representing that the clock signal is in an idle state.

[0069] Step S102, detect the level change of the clock signal based on the first timer.

[0070] The clock signal has two level changes, the rising edge (the level jumps from low to high) and the falling edge (the level jumps from high to low). The slave device determines when to read data by detecting the rising edge or falling edge of the clock signal, ensuring that data is collected at the correct time point to achieve the purpose of data synchronization.

[0071] Step S103, when the first timer continuously detects the same type of level, determine that the clock signal is in an idle state and trigger the first timer to count overflow.

[0072] When the clock signal is in an idle state, the clock signal will maintain a low level or a high level for a period of time (which can be set according to the actual situation). When the first timer detects one of the preset situations, it is determined that the master device has finished sending data.

[0073] Among them, the level when the clock is idle depends on the level change, that is, the edge, of the last clock signal sent by the master device for the current frame. If the last clock signal is the rising edge, the clock will maintain a high level for a certain period of time when it is idle. Conversely, if the last clock signal is the falling edge, the clock will maintain a low level for a certain period of time when it is idle.

[0074] Step S104: Trigger the reset of the first communication module when the first timer counts up and overflows.

[0075] During synchronous communication, after the host sends the last clock signal of the current frame, it will stop sending clock signals. At this time, the level of the clock signal will be fixed and maintained for a certain period of time. The first timer will start a new timing when the host stops sending clock signals. It samples the received host clock signals at a certain frequency and detects the level change of the clock signal. If the level of the same type of clock signal is continuously detected, it means that the host has finished sending the current frame and the clock signal is in an idle state. At this time, the first timer will generate a trigger signal, which will be input to the reset terminal of the first communication module to trigger the reset of the first communication module. It should be noted that the reset described in this application is specifically for the communication module of the slave device, rather than for the entire slave device.

[0076] In some embodiments, the configured timing overflow value in the first timer is greater than the synchronous clock cycle of the host and less than the data transmission time interval of the host. Such a setting helps to ensure that the slave device completes the reset after each frame of data is received and before the data transmission time interval of the host ends, without affecting the normal reception of data.

[0077] In this embodiment, when it is determined that the host has finished sending data, the reset of the communication module is triggered once to ensure that it can automatically synchronize with the host when receiving the next frame of data. It should be noted that the interference of the clock signal may have a cumulative effect, that is, if an error occurs in the reception of a certain frame of data, this error may affect the reception of subsequent frames of data and may ultimately lead to communication breakdown. In this embodiment, the slave device automatically resets the first communication module every time it detects that the clock signal is in an idle state. Such a setting, even if the master / slave data is out of sync due to clock interference in the current frame of data, will only cause an error in the current frame of data and will not affect the reception of the next data frame, reducing the influence range of clock interference.

[0078] In this embodiment, an external timer is set for the communication module of the slave device. The timer detects the clock signal sent by the host. The timer only needs to detect the level change of the clock signal and triggers the reset of the first communication module when the preset condition is met (continuously detecting the level of the same type of clock signal). This embodiment adopts the method of real-time monitoring by the timer, eliminating the chip select signal wiring harness, ensuring automatic synchronization in the next communication cycle under interference signals. Compared with the related technology, the external chip select generation circuit is reduced, the circuit design is simplified without increasing the communication complexity, and the manufacturing cost is reduced.

[0079] The synchronous clock period of a general host is constant. That is to say, for each frame of data sent by the host, the edges of the start clock and the end clock are fixed. Then, the first timer only needs to configure the overflow time and the target edge to monitor the host clock signal. Once the target edge of the host clock signal appears, the timing starts. However, during the process of the host sending data, the host clock signal will continuously and repeatedly present rising edge - falling edge - rising edge - falling edge... If the first timer times at this time, it is easy to overflow and wrongly trigger the reset of the first communication module.

[0080] To solve this problem, in one embodiment, the first timer triggers the timer to count when detecting the first edge of the clock signal; and clears the count value of the first timer and starts counting again when detecting the second edge of the clock signal.

[0081] Among them, the clock signal generates two edges within a complete synchronous clock period, either a rising edge - falling edge or a falling edge - rising edge. The first edge refers to the first edge of the clock signal received by the slave within the synchronous clock period; the second edge refers to the second edge of the clock signal received by the slave within the synchronous clock period. When the first edge appears, the second timer starts counting. When the second edge appears, the second timer clears the count value. By continuously counting and clearing in this way, it can play a role in shielding the first timer during the process of the host sending data, and the first timer becomes effective after the host finishes sending data. Therefore, within a complete data frame communication cycle, the second timer will not overflow during the reception of the clock signal, which is beneficial to reducing the situation of wrongly triggering the reset of the first communication module.

[0082] In one embodiment, continuing to refer to Figure 2 , the first timer is configured in an external edge trigger counting and clearing mode, and a timing overflow interrupt trigger output mode. That is, starting from the first edge received by the first timer, it triggers the first timer to start working and count. The second edge clears the count value of the first timer. When the clock signal enters the idle level and remains unchanged, the first timer continuously counts until the set value in the comparison register, overflows and interrupts, thereby outputting a trigger signal to reset the first communication module and stop counting. Then it enters the next working cycle waiting for an external edge trigger. For easy understanding, the specific working principle of the serial data communication system will be introduced below.

[0083] (1) The slave automatically identifies the synchronous clock period

[0084] The slave configures the second timer in pulse width capture mode. Among them, the main clock HCLK inside the first communication module is divided by frequency to obtain the base frequency clock PCLK of the second timer. In the case where the slave receives the clock signal for the first time after initial power-on, based on the second timer, the pulse widths t1, t2,... of the clock signal are recorded q times. After removing the maximum and minimum values and taking the average, the current host synchronization clock period t (t = q × PCLK) is obtained, and the value t is stored.

[0085] (2)Configure the first timer monitoring function

[0086] Configure the first timer in external edge trigger counting and clearing mode, and timer overflow interrupt trigger output mode, that is, in the idle state, the first clock edge triggers, and the second clock edge clears.

[0087] Configure the overflow comparison register time of the first timer, set it to T, and clear the count value cnt. t < T < Tm, where Tm is the data sending time interval of the host (i.e., the clock idle time).

[0088] (3)The working process of the first timer monitoring and resetting

[0089] Figure 4 This is a schematic diagram of the signal waveform received by the slave in this embodiment Figure 1 ,such as Figure 4 As shown, during synchronous communication, when the first timer detects the first edge of the clock signal, the first timer starts counting, and cnt accumulates. When the second edge of the clock signal is detected, the count value of the first timer is cleared, and the count value cnt = 0. Therefore, during the clock reception process within a complete SPI communication cycle, the first timer will not overflow. When the last clock pulse of a frame of data is triggered, the last edge of the clock clears cnt = 0, and then the host stops sending the clock signal, and the clock state remains unchanged. At this time, the first timer still continues to count from zero. When the count reaches T, the first timer overflows to generate an interrupt signal, outputs a trigger signal TGR, and at the same time the first timer stops working and waits for the next external edge to trigger timing. TGR is output to the SPI reset input, causing a reset operation of the slave to ensure that in the next synchronous clock cycle, the slave can continue to maintain clock synchronization with the host.

[0090] Figure 5 This is a schematic diagram of the signal waveform received by the slave in this embodiment Figure 2 ,such as Figure 5As shown, if interference pulses occur during the synchronous communication process or when the clock is idle, through the clock monitoring of the first timer, the first communication module is automatically reset at the end of the clock, ensuring that the slave can automatically synchronize with the master when the next frame of data arrives. Therefore, even if the slave device receives incorrect data, it will only cause an error in one frame of data, rather than leading to a complete communication breakdown. Through this embodiment, the reliability of the half-duplex synchronous communication of the serial data communication system without the chip selection signal is improved.

[0091] For a half-duplex serial data communication system, to implement the data read and write functions, the related technologies mainly adopt a question-and-answer data communication mode. For example, when the master wants to write data to the slave, the master first sends a write command code to the slave. After the slave responds to the write command code and feeds back an acknowledgment signal, the master can officially start sending data to the slave for writing. This read and write operation requires controlling the data transmission direction to achieve two-way time-division communication. In application scenarios with high real-time control requirements, it is often necessary to write parameters from the master to the slave and read the data of the slave in real time. If the data transmission direction is frequently switched, it will result in a long communication time, a high occupancy rate of the master's computing resources, and affect the control performance. If a high-performance master chip is used, it will increase the material cost.

[0092] To solve this problem, in one embodiment, based on Figure 2 the above, Figure 6 another serial data communication method is provided. The method includes the following steps:

[0093] Step S201, receiving the data sent by the master;

[0094] Step S202, determining whether the data contains a first command code; if so, execute Step S203; if not, execute Step S204;

[0095] Step S203, the slave enters the first working mode; wherein, in the first working mode, unidirectional data communication is performed between the slave and the master;

[0096] Step S204, in the case where it is determined that the data does not contain the first command code, the slave enters the second working mode; wherein, in the second working mode, two-way time-division communication is performed between the slave and the master.

[0097] In this embodiment, during synchronous communication, the slave device needs to execute command codes according to the parameters sent by the master device, and also needs to return data to the master device. The returned data can be the execution result or some status bit information. During this process, considering that the real-time requirement for parameter reading and writing is not high, while the real-time requirement for data reading is high, therefore, the slave device will provide different working modes according to the master device's requirements, namely the first working mode and the second working mode. In the first working mode, unidirectional data communication is carried out between the slave device and the master device, that is, the slave device is allowed to directly send data to the master device, no longer following the one-question-one-answer data communication mode, thereby improving the real-time performance of the master device reading data from the slave device and improving the communication efficiency. In the second working mode, two-way time-sharing communication is carried out between the slave device and the master device to meet the parameter writing requirements of the master device.

[0098] In some embodiments, the slave device can be a servo motor encoder. The servo motor encoder uses the first working mode to real-time feedback angle or position data, reducing the occupation of the master device's computing resources and time, and improving the control performance of the master device without increasing the material cost.

[0099] In one embodiment, after the slave device enters the first working mode, the method further includes:

[0100] When it is detected that the clock signal is in an idle state, determine whether the idle time of the clock signal is greater than a threshold; when it is determined that the idle time of the clock signal is greater than the threshold, switch the slave device from the first working mode to the second working mode; wherein, in the second working mode, two-way time-sharing communication is carried out between the slave device and the master device.

[0101] In this embodiment, when the idle time of the master device's clock signal is greater than the threshold Tn, it means that the master device will switch from data reading to parameter writing. After the slave device enters the first working mode, the first timer continues to monitor the master device's clock signal, and when the master device's clock signal meets the preset conditions, it triggers the slave device to switch from the first working mode to the second working mode.

[0102] In one embodiment, after the slave device enters the second working mode, the method further includes:

[0103] When it is detected that the clock signal is in an idle state, determine whether the first command code is received continuously m times, where m is greater than 1; when it is determined that the first command code is received continuously m times, switch the slave device from the second working mode to the first working mode.

[0104] In this embodiment, after the slave device enters the second working mode, it is determined whether to switch the working mode by judging whether the master device's data meets the preset conditions. Among them, determining whether the first command code is received continuously multiple times is to ensure the validity of the received command code and reduce mis-switching.

[0105] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the indications of the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same moment, but can be executed at different moments, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0106] In one embodiment, the slave is a servo motor encoder, and the master is a controller. During servo operation, the encoder angle data needs to be read in real time in each control cycle. To improve the real-time bidirectional communication of half-duplex data reading and writing, Figure 7 A serial data communication method is provided, and this method includes the following steps:

[0107] Step S301, receiving the data sent by the master. After the slave is initially powered on, it starts to receive the data sent by the master.

[0108] Step S302, determining whether the data contains a first command code; if so, proceed to step S303, if not, proceed to step S306. Among them, the first command code can be 0xFFFF or 0x0000.

[0109] Step S303, determining whether the first command code is received continuously for m times; if so, proceed to step S304, if not, return to step S301. Among them, m is greater than 1.

[0110] Step S304, entering the first working mode.

[0111] Step S305, determining whether the idle time of the clock signal is greater than Tn; if so, return to step S301, if not, return to step S304.

[0112] Step S306, determining whether the second command code is received. If so, proceed to step S307, if not, proceed to step S313. Among them, the second command code can be 0x0505.

[0113] Step S307, determining whether the third command code is received. If so, proceed to step S314, if not, proceed to step S308. Among them, the third command code can be 0x55XX or 0x59XX.

[0114] Step S308: Determine whether the fourth command code is received. If yes, proceed to step S315; if no, proceed to step S309. Here, the fourth command code can be 0x58XX.

[0115] Step S309: Determine whether the fifth command code is received. If yes, proceed to step S316; if no, proceed to step S310. Here, the fifth command code can be 0x5A55.

[0116] Step S310: Determine whether the sixth command code is received. If yes, proceed to step S318; if no, proceed to step S313. Here, the sixth command code can be 0x5A10.

[0117] Step S311: Determine whether the seventh command code is received. If yes, proceed to step S307; if no, proceed to step S312. Here, the seventh command code can be 0x5ABB.

[0118] Step S312: Determine whether the eighth command code is received. If yes, proceed to step S321; if no, proceed to step S313. Here, the eighth command code can be 0x5BXX.

[0119] Step S313: Reset the communication module of the slave; after reset, return to step S301.

[0120] Step S314: Transmit system / user data; after data transmission is completed, return to step S301.

[0121] Step S315: Receive system / user data; after data reception is completed, return to step S301.

[0122] Step S316: Determine whether the fifth command code is received continuously K times; if yes, proceed to step S317; if no, return to step S301. Here, K > 1.

[0123] Step S317: Erase the user parameter area; after erasure, return to step S301.

[0124] Step S318: Write single-electrical-angle data; after writing is completed, return to step S301.

[0125] Step S319: Determine whether the seventh command code is received continuously L times; if yes, proceed to step S320; if no, return to step S301. Here, L > 1.

[0126] Step S320: Erase the system parameter area; after erasure, return to step S301.

[0127] Step S321: Write the number of motor pole pairs; after writing is completed, return to step S301.

[0128] In the above steps S301 to S321, after initial power-on, the slave enters the corresponding working mode. During this process, the master / slave respectively switches the data transmission direction to data reception through the MCU port; the idle state of the clock signal is high level. The master sends the clock signal, receives data through the data reception terminal, and sets the data transmission time interval between two adjacent frames (i.e., the clock idle interval) as Tm. Among them, the command codes received by the slave are divided into the following two cases:

[0129] (1) As Figure 8 shown, when the slave receives the data 0xFFFF or 0x0000 continuously for more than two times, it is determined that the first command code is received. At this time, the slave switches the data transmission direction to data transmission through the MCU port, sends valid data, and enters the first working mode.

[0130] As Figure 9 shown, in the clock idle state, the master stops sending the clock signal and continuously maintains the clock signal at high level for a time Tn > a×Tm, where a > 2. The slave monitors the signal level of the first clock terminal through the first timer. When it is detected that the signal level of the first clock terminal continuously maintains high level for a time Tn > a×Tm, the slave configures the data terminal as the data reception mode and enters the command code reception state; the master simultaneously switches the data transmission direction to data transmission and enters the command code transmission state. With such settings, the switching from the first working mode to the second working mode is achieved.

[0131] (2) As Figure 10 shown, when the slave receives other valid command codes, it enters the second working mode.

[0132] As Figure 11 shown, when the master sends the parameter write command code, the command word includes the command code and the written data frame length; the slave prepares to receive the valid parameter data according to the received command code and data frame length. After the master continuously sends all the valid parameter data and the slave receives the parameter data, the slave continues to enter the command code reception state.

[0133] As Figure 12 shown, when the master sends the parameter read command code, the command word includes the command code and the read data frame length; the slave prepares to send the valid parameter data according to the received command code and data frame length; at the same time, the master data signal line enters the reception mode. After the master continuously sends all the clock quantities of the read data frame length and the slave sends all the parameter data; the slave switches to the data reception mode, enters the command code reception state, and at the same time the master enters the data transmission state.

[0134] As Figure 13As shown, in the clock idle state, the master / slave host switches the data transfer direction to data reception; the host sends a clock signal, receives data through the data port, and sets the idle time interval between two adjacent frames as Tm. When the slave receives data 0xFFFF or 0x0000 continuously for more than two times, it is determined that the first command code is received. At this time, the slave switches to the data transmission mode through the MCU port, sends valid data, and enters the data transmission state. With such settings, the switch from the second working mode to the first working mode is achieved.

[0135] It should be noted that the "working mode" mentioned above Figures 8 to 13 refers to the first working mode, and the "parameter mode" refers to the second working mode.

[0136] In this embodiment, by eliminating the chip select signal, only a few wiring harnesses are required to achieve master-slave synchronous communication. An external timer is used on the slave side to monitor the synchronous clock signal, and the synchronization is automatically reset when the clock is idle, improving the anti-interference ability and fault tolerance ability. Two working modes are set according to the communication requirements to achieve high-speed communication in the first working mode and data read / write function in the second working mode, and the switch between the first working mode and the second working mode is achieved through clock monitoring.

[0137] In one embodiment, during master / slave communication, to achieve the switch of the data transfer direction, Figure 14 a serial data communication system is provided, as Figure 14 shown. The slave also includes a first RS485 unit and a second RS485 unit, the first communication module also includes a first control terminal DIR1, the host also includes a third RS485 unit and a fourth RS485 unit, and the second communication module also includes a second control terminal DIR2; wherein, the first RS485 unit is connected to the first data transmission terminal SPI_TX1, the first data reception terminal SPI_RX1, and the first control terminal DIR1, and the second RS485 unit is connected to the first clock terminal SPI_SCK1; the third RS485 unit is connected to the second data transmission terminal SPI_TX2, the second data reception terminal SPI_RX2, and the second control terminal DIR2, and the fourth RS485 unit is connected to the second clock terminal SPI_SCK2; the first RS485 unit and the third RS485 unit are connected through a data line, and the second RS485 unit and the fourth RS485 unit are connected through a clock line; the first control terminal DIR1 and the second control terminal DIR2 are respectively used to control the data transfer direction.

[0138] In this embodiment, the master / slave machines are respectively provided with RS485 units. During synchronous communication, the master / slave machines generate control signals in response to the protocol, and send the control signals to the corresponding RS485 units through their respective control ends, switching the data transceiver directions of the corresponding RS485 units to achieve the function of time-division bidirectional data communication. Among them, the data line and the clock line respectively adopt twisted pairs to transmit signals in a differential drive mode to enhance the anti-interference ability of the signals.

[0139] In one embodiment, during master / slave communication, in order to achieve the switching of the data transmission direction, Figure 15 another serial data communication system is provided, as Figure 15 shown, the slave machine further includes a first switching unit K1, and the master machine further includes a second switching unit K2; among them, the first switching unit K1 includes a first static contact K11, a first moving contact K12 and a first controlled end K13, the first moving contact K12 is connected to the first data sending end SPI_TX1 or the first data receiving end SPI_RX1, and the first controlled end K13 is connected to the first control end DIR1; the second switching unit K2 includes a second static contact K21, a second moving contact K22 and a second controlled end K23, the second moving contact K22 is connected to the second data sending end SPI_TX2 or the second data receiving end SPI_RX2, and the second controlled end K23 is connected to the second control end DIR2; the first static contact K11 is connected to the second static contact K21 through a data line, and the first clock end SPI_SCK1 is connected to the second clock end SPI_SCK2 through a clock line.

[0140] In this embodiment, Figure 15 the shown switching unit is arranged inside the communication module. In some embodiments, the switching unit can also be arranged outside the communication module. During synchronous communication, the master / slave machines generate control signals in response to the protocol, and send the control signals to the controlled ends of the corresponding switching units through their respective control ends, changing the states of the moving contacts of the switching units (conducting the data sending end or the data receiving end), thereby switching the corresponding data transceiver directions to achieve single-line half-duplex communication. Among them, the data line and the clock line respectively adopt single lines. Compared with Figure 14 , since the master / slave machines respectively omit the RS485 units, the wire harness is further reduced, the circuit design is simplified, and the manufacturing cost is reduced.

[0141] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned serial data communication method embodiments are implemented.

[0142] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0143] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in this application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in this application can be general-purpose processors, central processors, graphics processors, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0144] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0145] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A serial data communication method, characterized in that, Applied to a slave device, the slave device is connected to a master device through a clock line and a data line. The chip select signal terminal of the slave device is left floating. The slave device includes a communication module and a timer. The input end of the timer is connected to the clock end of the communication module, and the output end of the timer is connected to the reset end of the communication module. The method includes: Receiving a clock signal sent by the master device; Detecting a level change of the clock signal based on the timer; When the timer continuously detects the same type of level, determining that the clock signal is in an idle state and triggering the timer to count overflow; When the timer counts overflow, triggering the communication module to reset.

2. The serial data communication method according to claim 1, wherein The configured timing overflow value in the timer is greater than the synchronous clock period of the master device and less than the data transmission time interval of the master device.

3. The serial data communication method according to claim 1, characterized in that Detecting the level change of the clock signal based on the timer further includes: When detecting the first edge of the clock signal, triggering the timer to count; When detecting the second edge of the clock signal, clearing the count value of the timer and restarting the count.

4. The serial data communication method according to claim 1, wherein The method further includes: Receiving data sent by the master device; Judging whether the data contains a first command code; When it is judged that the data contains the first command code, the slave device enters a first working mode. Wherein, in the first working mode, unidirectional data communication is performed between the slave device and the master device.

5. The serial data communication method according to claim 4, wherein After the slave device enters the first working mode, the method further includes: When detecting that the clock signal is in an idle state, judging whether the idle time of the clock signal is greater than a threshold value; When it is judged that the idle time of the clock signal is greater than the threshold value, switching the slave device from the first working mode to a second working mode. Wherein, in the second working mode, two-way time-division communication is performed between the slave device and the master device.

6. The serial data communication method according to claim 4, wherein The method further includes: When it is judged that the data does not contain the first command code, the slave device enters a second working mode. Wherein, in the second working mode, two-way time-division communication is performed between the slave device and the master device.

7. The serial data communication method according to claim 5 or 6, characterized in that, After the slave device enters the second working mode, the method further includes: When detecting that the clock signal is in an idle state, judging whether the first command code is received continuously m times, where m is greater than 1; When it is judged that the first command code is received continuously m times, switching the slave device from the second working mode to the first working mode.

8. An electronic device, characterized in that, Includes: A communication module and a timer. The input end of the timer is connected to the clock end of the communication module, and the output end of the timer is connected to the reset end of the communication module. The electronic device is used to execute the serial data communication method according to any one of claims 1 to 7 above.

9. A serial data communication system, characterized in that, Includes: A master device and a slave device. The master device is connected to the slave device through a clock line and a data line. The chip select signal terminal of the slave device is left floating. The slave device includes the electronic device according to claim 8 above.

10. The serial data communication system according to claim 9, wherein The first communication module of the slave device includes a first data sending end, a first data receiving end, and a first clock end; the master device includes a second communication module, and the second communication module includes a second data sending end, a second data receiving end, and a second clock end; wherein, The first data sending end and the first data receiving end are connected to the second data sending end and the second data receiving end through the data line; The first clock end is connected to the second clock end through the clock line.

11. The serial data communication system according to claim 10, wherein, The slave device further includes a first RS485 unit and a second RS485 unit, the first communication module further includes a first control end, the master device further includes a third RS485 unit and a fourth RS485 unit, and the second communication module further includes a second control end; wherein, The first RS485 unit is connected to the first data sending end, the first data receiving end, and the first control end, and the second RS485 unit is connected to the first clock end; The third RS485 unit is connected to the second data sending end, the second data receiving end, and the second control end, and the fourth RS485 unit is connected to the second clock end; The first RS485 unit is connected to the third RS485 unit through the data line, and the second RS485 unit is connected to the fourth RS485 unit through the clock line; The first control end and the second control end are respectively used to control the data transmission direction.

12. The serial data communication system according to claim 11, wherein The slave device further includes a first switching unit, and the master device further includes a second switching unit; wherein, The first switching unit includes a first static contact, a first moving contact, and a first controlled end, the first moving contact is connected to the first data sending end or the first data receiving end, and the first controlled end is connected to the first control end; The second switching unit includes a second static contact, a second moving contact, and a second controlled end, the second moving contact is connected to the second data sending end or the second data receiving end, and the second controlled end is connected to the second control end; The first static contact is connected to the second static contact through the data line; The first clock end is connected to the second clock end through the clock line.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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