Integrated circuit for shared storage dual-frequency tag and control method thereof

Abstract

The invention discloses an integrated circuit for a shared storage double-frequency tag and a control method of the integrated circuit. The integrated circuit comprises an analog radio frequency circuit, a storage circuit and a digital baseband circuit. The method comprises the following steps: acquiring a high-frequency tag signal and an ultrahigh-frequency tag signal and respectively carrying out demodulation processing; decoding the demodulated label signal to obtain a label logic signal; performing data verification on the label logic signal; command analysis preprocessing is carried out according to a label signal verification result; performing data anti-collision processing on a label signal analysis result; and according to the EEPROM operation command, performing read-write operation on the to-be-operated tag signal to obtain a modified high-frequency data signal and a modified ultrahigh-frequency data signal. According to the embodiment of the invention, the circuit area can be effectively reduced, the process from data reading to data sending is accelerated, and the risk of data modification is reduced. The circuit can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to an integrated circuit for a shared storage dual-frequency tag and a control method thereof. Background Art

[0002] As key components in the Internet of Things ecosystem, high-frequency (HF) and ultra-high-frequency (UHF) RFID tag technologies have reached a highly mature state, and they have demonstrated irreplaceable value in their respective application scenarios. The shared storage dual-frequency tag chip combines the two on this basis and exchanges data through a common storage area. Although this method solves the problem of different frequency requirements to a certain extent, the complexity of system integration and the cumbersome data processing flow not only drive up costs, but also the stored data may be maliciously tampered with through another frequency band, resulting in some security risks.

[0003] In summary, the technical problems existing in the related technologies need to be improved. Summary of the Invention

[0004] The main purpose of the embodiments of this application is to propose an integrated circuit for a shared storage dual-frequency tag and a control method thereof, which can effectively reduce the circuit area, speed up the process from data reading to sending, and reduce the risk of data modification.

[0005] To achieve the above object, on the one hand, an embodiment of this application proposes an integrated circuit for a shared storage dual-frequency tag. The circuit includes an analog radio frequency circuit, a storage circuit, and a digital baseband circuit. The output end of the analog radio frequency circuit is connected to the input end of the digital baseband circuit. The digital baseband circuit is electrically connected to the storage circuit. The digital baseband circuit has a superuser mode, where:

[0006] The analog radio frequency circuit is used to obtain a high-frequency tag signal or an ultra-high-frequency tag signal and perform demodulation and modulation processing to obtain a demodulated tag signal;

[0007] The digital baseband circuit is used to decode the demodulated tag signal and perform logical control judgment to obtain a modified high-frequency data signal and a modified ultra-high-frequency data signal;

[0008] The storage circuit is used to store data.

[0009] In some embodiments, the digital baseband circuit includes an encoding / decoding module, a CRC module, a command parsing module, an anti-collision circuit, a main control module, an EEPROM control circuit, a reset module, a counter module, and a data buffer module. The encoding / decoding module is connected to the CRC module. The first output terminal of the CRC module is connected to the input terminal of the command parsing module. The second output terminal of the CRC module is connected to the input terminal of the reset module. The output terminal of the command parsing module is connected to the input terminal of the anti-collision circuit. The output terminal of the anti-collision circuit is connected to the input terminal of the main control module. The main control module is connected to the EEPROM control circuit. The EEPROM control circuit is connected to the data buffer module. The command parsing module, the anti-collision circuit, and the main control module are all connected to the counter module.

[0010] In some embodiments, the CRC module, the main control module, the EEPROM control circuit, the reset module, the counter module, and the data buffer module are all digital common circuit modules for the high-frequency tag signal and the ultra-high-frequency tag signal.

[0011] To achieve the above object, on the other hand, an embodiment of the present application proposes a control method for an integrated circuit for a shared storage dual-frequency tag. The method includes the following steps:

[0012] Obtain a high-frequency tag signal and an ultra-high-frequency tag signal and perform demodulation processing on them respectively to obtain a demodulated high-frequency tag signal and a demodulated ultra-high-frequency tag signal;

[0013] Perform decoding processing on the demodulated high-frequency tag signal and the demodulated ultra-high-frequency tag signal respectively to obtain a high-frequency digital logic signal and an ultra-high-frequency digital logic signal;

[0014] Perform data verification on the high-frequency digital logic signal and the ultra-high-frequency digital logic signal to obtain a high-frequency data verification result and an ultra-high-frequency data verification result;

[0015] Perform command parsing preprocessing according to the high-frequency data verification result and the ultra-high-frequency data verification result to obtain a high-frequency data parsing result and an ultra-high-frequency data parsing result;

[0016] Perform data anti-collision processing on the high-frequency data parsing result and the ultra-high-frequency data parsing result to obtain a high-frequency data signal to be operated and an ultra-high-frequency data signal to be operated;

[0017] According to the EEPROM operation command, perform read / write operations on the high-frequency data signal to be operated and the ultra-high-frequency data signal to be operated to obtain a modified high-frequency data signal and a modified ultra-high-frequency data signal.

[0018] In some embodiments, the decoding process is respectively performed on the demodulated high-frequency tag signal and the demodulated ultra-high-frequency tag signal to obtain a high-frequency digital logic signal and an ultra-high-frequency digital logic signal, including:

[0019] The decoding and CRC check processing are respectively performed on the demodulated high-frequency tag signal and the demodulated ultra-high-frequency tag signal to obtain the data length of the high-frequency tag signal and the data length of the ultra-high-frequency tag signal;

[0020] For the demodulated high-frequency tag signal and the demodulated ultra-high-frequency tag signal that pass the CRC check, command parsing is performed in combination with the data length of the high-frequency tag signal and the data length of the ultra-high-frequency tag signal to obtain a high-frequency tag parsing signal and an ultra-high-frequency tag parsing signal;

[0021] Selection is performed on the high-frequency tag parsing signal and the ultra-high-frequency tag parsing signal to obtain a selected high-frequency tag parsing signal and a selected ultra-high-frequency tag parsing signal;

[0022] CRC generation and data merging and sending are performed on the selected high-frequency tag parsing signal and the selected ultra-high-frequency tag parsing signal to obtain the high-frequency digital logic signal and the ultra-high-frequency digital logic signal.

[0023] In some embodiments, both the selected high-frequency tag parsing signal and the selected ultra-high-frequency tag parsing signal include the read data of the EEPROM, the reply data of the protocol content, and the UID data or EPC data replied during card selection.

[0024] In some embodiments, the data check is performed on the high-frequency digital logic signal and the ultra-high-frequency digital logic signal to obtain a high-frequency data check result and an ultra-high-frequency data check result, including:

[0025] The data check is performed on the high-frequency digital logic signal and the ultra-high-frequency digital logic signal;

[0026] If the data check result fails, a reset process is performed to re-obtain the high-frequency tag signal and the ultra-high-frequency tag signal;

[0027] If the data check result passes, the high-frequency data check result and the ultra-high-frequency data check result are output.

[0028] In some embodiments, the command parsing preprocessing is performed according to the high-frequency data check result and the ultra-high-frequency data check result to obtain a high-frequency data parsing result and an ultra-high-frequency data parsing result, including:

[0029] Command parsing is performed on the high-frequency data verification result and the ultra-high-frequency data verification result to obtain high-frequency parsed data and ultra-high-frequency parsed data. Both the high-frequency parsed data and the ultra-high-frequency parsed data include data parameters, operation behaviors, and address parameters;

[0030] Based on the address parameter, determine the read / write area permissions of the high-frequency parsed data and the ultra-high-frequency parsed data for the operation behavior;

[0031] If the read / write area permissions do not meet the requirements, a mismatch signal is fed back;

[0032] If the read / write area permissions meet the requirements, generate the high-frequency data parsing result and the ultra-high-frequency data parsing result.

[0033] In some embodiments, it further includes cross-band data modification between the high-frequency parsed data and the ultra-high-frequency parsed data. If the superuser mode is enabled, a corresponding password needs to be input through an instruction. When the password passes, all read / write area permissions are unlocked.

[0034] In some embodiments, it further includes, for the digital common circuit of the high-frequency tag signal and the ultra-high-frequency tag signal, when performing frequency band switching, first perform a reset through a reset signal, and then perform enabling and clock input through an enabling signal and a clock signal after the reset is completed, where:

[0035] The enabling signals of the high-frequency tag signal and the ultra-high-frequency tag signal cannot be high at the same time;

[0036] If the frequency band is in the ultra-high-frequency state or the high-frequency state, the reset signal of the digital common circuit is 1. If the frequency band is in the intermediate transition state during the ultra-high-frequency and high-frequency switching, the reset signal of the digital common circuit is 0;

[0037] Perform clock switching on the high-frequency tag and the ultra-high-frequency tag through a glitch-free clock switching circuit.

[0038] The embodiments of the present application at least include the following beneficial effects: The present application provides an integrated circuit and its control method for a shared storage dual-frequency tag. This solution obtains a high-frequency tag signal or an ultra-high-frequency tag signal and performs demodulation processing, transmits the demodulated data to the digital baseband circuit, and then decodes and performs logic control judgment on the demodulated tag signal to conform to the two protocols of the dual-frequency tag. The high-frequency and ultra-high-frequency use a common part of the digital baseband, effectively reducing the circuit area and achieving the effect of cost savings. For the data storage and communication process, a pipeline method is used to speed up the process from data reading to sending, and a superuser mode is adopted. Only when the password and the command steps are correct can data modification be performed on the encrypted area. Description of the Drawings

[0039] Figure 1 It is a flowchart of an integrated circuit for a shared storage dual - frequency tag provided by an embodiment of the present application;

[0040] Figure 2 It is a schematic structural diagram of a control method for an integrated circuit for a shared storage dual - frequency tag provided by an embodiment of the present application;

[0041] Figure 3 It is a schematic diagram of a digital baseband control circuit provided by an embodiment of the present application;

[0042] Figure 4 It is a schematic framework diagram of digital baseband common module processing provided by an embodiment of the present application;

[0043] Figure 5 It is a schematic diagram of an encoding and decoding processing circuit provided by an embodiment of the present application;

[0044] Figure 6 It is a schematic diagram of the basic state transition of high - frequency band communication provided by an embodiment of the present application;

[0045] Figure 7 It is a schematic diagram of ultra - high - frequency basic communication provided by an embodiment of the present application. Detailed implementation manners

[0046] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of systems and methods that are consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0047] It can be understood that the terms "first", "second", etc. used in the present application can be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the words "if", "when" as used herein can be interpreted as "when...", "while...", or "in response to determining".

[0048] As used in this application, the terms "at least one", "a plurality", "each", "any one", etc. The "at least one" includes one, two or more than two, the "a plurality" includes two or more than two, "each" refers to each one of the corresponding plurality, and "any one" refers to any one of the plurality.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0050] In the prior art, there are the following deficiencies:

[0051] 1) When reading and writing the same storage space for two frequency bands, there is mutual interference, and the permissions for different access areas cannot be made universal.

[0052] 2) The requirement to support both HF and UHF communication frequency bands inevitably increases the complexity and physical size of the chip, and it is difficult to effectively utilize the limited chip space.

[0053] Based on this, in the embodiment of the present invention, first, a high-frequency or ultra-high-frequency reader / writer issues a command, and the tag receives the command through the antenna and demodulates it through the analog radio frequency circuit, and transmits the demodulated data to the digital baseband circuit. Immediately afterwards, the digital baseband circuit decodes the signal to obtain a digital logic signal and transmits it to the CRC module for data verification. If the verification fails, the decoding module is reset to wait for a new command to arrive. If the verification passes, it is transmitted to the command parsing module for command parsing. If a collision occurs, that is, multiple tags are present in the field at the same time, the anti-collision circuit processes the collision process. After the anti-collision is completed, all basic interactions with the reader / writer are processed by the main control module. The main control module makes some state jumps or some basic replies according to the basic protocol. When an operation command regarding the EEPROM is received, the relevant control signals and data, etc. are transmitted to the EEPROM control circuit. The EEPROM control circuit judges the permission according to the address and operation, and after success, generates a driving signal for the EEPROM to perform read and write operations on the EEPROM. Since the storage speed of the EEPROM is generally relatively slow, the tag caches the data through the general-purpose register, which is beneficial to the normal reading and writing of the data. In addition, to reduce the chip area, all operations that require timing or counting in the entire process will be performed by the general-purpose counter module for timing and counting

[0054] Refer to Figure 1 , Figure 1 is a schematic structural diagram of an integrated circuit for a shared storage dual-frequency tag provided by an embodiment of the present invention. Refer to Figure 1, the circuit includes an analog radio frequency circuit, a storage circuit, and a digital baseband circuit. The output end of the analog radio frequency circuit is connected to the input end of the digital baseband circuit, and the digital baseband circuit is electrically connected to the storage circuit. The digital baseband circuit operates in the mode of a superuser, where:

[0055] The analog radio frequency circuit is used to obtain a high-frequency tag signal or a ultra-high-frequency tag signal and perform demodulation and modulation processing to obtain a demodulated tag signal;

[0056] The digital baseband circuit is used to decode the demodulated tag signal and perform logical control judgment to obtain a modified high-frequency data signal and a modified ultra-high-frequency data signal;

[0057] Specifically, the digital baseband circuit includes an encoding / decoding module, a CRC module, a command parsing module, an anti-collision circuit, a main control module, an EEPROM control circuit, a reset module, a counter module, and a data buffer module. The encoding / decoding module is connected to the CRC module. The first output end of the CRC module is connected to the input end of the command parsing module, and the second output end of the CRC module is connected to the input end of the reset module. The output end of the command parsing module is connected to the input end of the anti-collision circuit, and the output end of the anti-collision circuit is connected to the input end of the main control module. The main control module is connected to the EEPROM control circuit, and the EEPROM control circuit is connected to the data buffer module. The command parsing module, the anti-collision circuit, and the main control module are all connected to the counter module. Among them, the CRC module, the main control module, the EEPROM control circuit, the reset module, the counter module, and the data buffer module are all digital common circuit modules for high-frequency tag signals and ultra-high-frequency tag signals.

[0058] The storage circuit is used to store data.

[0059] In this embodiment, the first part of the circuit of the present invention is an analog radio frequency circuit, which is mainly responsible for signal modulation / demodulation, power supply, and other processing. The second part is a storage circuit, which uses EEPROM as a storage medium to store data for the tag. The third part is a digital baseband circuit, which is used for logical judgment and control to conform to the two protocols of the dual-frequency tag. Among them, to save chip area, the high-frequency and ultra-high-frequency use a common digital baseband part, such as Figure 1 The red part. The yellow part is the ordinary digital baseband circuit, which are the logical circuits of the high-frequency and ultra-high-frequency themselves respectively and cannot be shared.

[0060] The basic process of its communication processing is as follows. First, a high-frequency or ultra-high-frequency reader / writer issues a command. The tag receives the command through the antenna and demodulates it through the analog radio frequency circuit, and transmits the demodulated data to the digital baseband circuit. Immediately afterwards, the digital baseband circuit decodes the signal to obtain a digital logic signal and transmits it to the CRC module for data verification. If the verification fails, the decoding module is reset to wait for a new command to arrive. If the verification passes, it is transmitted to the command parsing module for command parsing. If a collision occurs, that is, multiple tags are present in the field at the same time, the anti-collision circuit processes the collision process. After the anti-collision is completed, the basic interaction with the reader / writer is processed through the main control module. The main control module makes some state jumps or some basic responses according to the basic protocol. When an operation command regarding the EEPROM is received, the relevant control signals and data are transmitted to the EEPROM control circuit. The EEPROM control circuit determines the permission according to the address and operation, and after success, generates a driving signal for the EEPROM to perform read / write operations on the EEPROM.

[0061] Since the storage speed of the EEPROM is generally relatively slow, the tag caches the data through the general-purpose register, which is beneficial to the normal reading and writing of the data. In addition, to reduce the chip area, all operations that require timing or counting in the entire process will be performed through the general-purpose counter module for timing and counting.

[0062] Please refer to Figure 2 , the embodiment of the present application also provides a control method for an integrated circuit for a shared storage dual-frequency tag, which can implement the above-mentioned integrated circuit for a shared storage dual-frequency tag. The method includes the following steps:

[0063] S100. Obtain a high-frequency tag signal and an ultra-high-frequency tag signal and perform demodulation processing on them respectively to obtain a demodulated high-frequency tag signal and a demodulated ultra-high-frequency tag signal;

[0064] S200. Perform decoding processing on the demodulated high-frequency tag signal and the demodulated ultra-high-frequency tag signal respectively to obtain a high-frequency digital logic signal and an ultra-high-frequency digital logic signal;

[0065] It should be noted that, in some embodiments, step S200 may include: S210, decoding and CRC check processing are respectively performed on the demodulated high-frequency tag signal and the demodulated ultra-high-frequency tag signal to obtain the data length of the high-frequency tag signal and the data length of the ultra-high-frequency tag signal; S220, for the demodulated high-frequency tag signal and the demodulated ultra-high-frequency tag signal that pass the CRC check, command parsing is performed in combination with the data length of the high-frequency tag signal and the data length of the ultra-high-frequency tag signal to obtain a high-frequency tag parsing signal and an ultra-high-frequency tag parsing signal; S230, selecting the high-frequency tag parsing signal and the ultra-high-frequency tag parsing signal to obtain a selected high-frequency tag parsing signal and a selected ultra-high-frequency tag parsing signal; S240, performing CRC generation and data merging and sending on the selected high-frequency tag parsing signal and the selected ultra-high-frequency tag parsing signal to obtain a high-frequency digital logic signal and an ultra-high-frequency digital logic signal.

[0066] In some specific embodiments, the encoding and decoding data flow is an important part of tag processing. In particular, the processing of variable-length commands for ultra-high-frequency tags is the key point of encoding and decoding. The block diagram of its encoding and decoding data stream processing is as Figure 5 shown, which is mainly divided into two parts: encoding and decoding. CRC check and generation can be divided into parallel CRC and serial CRC according to the operation mode. Since the ultra-high-frequency command is of variable length, serial CRC is selected as the tag scheme. When the tag decodes, the data is input into the CRC in a serial manner for check, and all the decoded data is input into the command parsing module for parsing, and finally given to the total control module unit. Regarding the encoding of the tag, the key point is that a CRC check code needs to be added after some commands when sending data. Since the generation of serial CRC takes a long time, this tag adopts a pipeline method. First, the data to be sent is selected according to the command and the current tag state, generally divided into three aspects. The first is the data read from the EEPROM, the second is some basic fixed data replied according to the content of the high-frequency or ultra-high-frequency protocol, and the third is information such as UID or EPC replied when selecting a card. Secondly, the data is input into the CRC check in a serial manner, and at the same time, the encoding module is started to perform synchronous encoding on the data. The encoding module encodes in units of 8 bits. When encoding to the 7th bit, a ready signal is sent to request an update of the encoded data. Since the encoding rate is much lower than the CRC generation rate, a 16-bit check code has been generated by the CRC at the last stage of encoding. At this time, the check code is sent to the encoding module to complete all data encoding.

[0067] S300, performing data check on the high-frequency digital logic signal and the ultra-high-frequency digital logic signal to obtain a high-frequency data check result and an ultra-high-frequency data check result;

[0068] It should be noted that in some embodiments, step S300 may include: S310, performing data verification on the high-frequency digital logic signal and the ultra-high-frequency digital logic signal; S320, if the data verification result fails, performing a reset process and re-acquiring the high-frequency tag signal and the ultra-high-frequency tag signal; S330, if the data verification result passes, outputting the high-frequency data verification result and the ultra-high-frequency data verification result.

[0069] In this embodiment, the communication process between the tag and the reader is half-duplex communication, that is, only the process of one receiving and one transmitting can be realized at the same time. When the tag sends data, generally the main controller controls the content to be sent, then it becomes the corresponding format after passing through the encoding module, and then the data is modulated by the analog front end and sent. When receiving, the data received by the analog front end is demodulated and then parsed into commands and data by the decoding module. CRC is added because some commands or data need to determine whether they are correct, so a CRC check code is added after the data or command.

[0070] S400, performing command parsing preprocessing according to the high-frequency data verification result and the ultra-high-frequency data verification result to obtain the high-frequency data parsing result and the ultra-high-frequency data parsing result;

[0071] It should be noted that in some embodiments, step S400 may include: S410, performing command parsing on the high-frequency data verification result and the ultra-high-frequency data verification result to obtain high-frequency parsed data and ultra-high-frequency parsed data, and both the high-frequency parsed data and the ultra-high-frequency parsed data include data parameters, operation behaviors, and address parameters; S420, judging the read / write area permissions of the high-frequency parsed data and the ultra-high-frequency parsed data according to the address parameters; S430, if the read / write area permissions do not meet the requirements, feedbacking a mismatch signal; S440, if the read / write area permissions meet the requirements, generating the high-frequency data parsing result and the ultra-high-frequency data parsing result.

[0072] In some specific embodiments, for the purpose of realizing a shared storage space, the embodiment of the present invention adopts EEPROM as the medium for shared storage, and its storage division is shown in Table 1.

[0073] Table 1 Storage Planning Table

[0074]

[0075]

[0076] The digital baseband control module of the EEPROM is as Figure 3As shown, the main control module gives the received command to the command parsing unit. The command parsing unit converts it into relevant controls for the EEPROM according to the current state and command content, which are mainly divided into three aspects: data, address, and read / write operations. Since the read / write area permissions for high frequency and ultra-high frequency are different, it is necessary to comprehensively determine the read / write access permissions according to the address, read / write operation, and frequency band. If the permissions are met, the read / write drive signal unit is enabled to perform relevant operations on the EEPROM. If the access permissions are not met, the main control module is feedback with the reason for the mismatch.

[0077] In addition, to ensure that all storage areas can be read and written when the tag leaves the factory. Secondly, for data modification across frequency bands. This tag has enabled the superuser mode. When the superuser mode is started, relevant passwords need to be input through instructions. When the password passes, all permissions are unlocked, and the user can operate on all areas at this time.

[0078] Since the EEPROM has a slow read / write speed, general registers are added to cache the data. There are mainly two cases. The first case is ordinary data reading. After the data is cached in the register, it waits for the EEPROM to be completely read before data output. The second case is to quickly respond to the card search of the reader / writer. When the tag is powered on, the UID or EPC in the EEPROM is read out immediately and fed back to the main control unit for the tag to perform encoding and reply.

[0079] S500. Perform data anti-collision processing on the high-frequency data parsing result and the ultra-high-frequency data parsing result to obtain the high-frequency data signal to be operated and the ultra-high-frequency data signal to be operated;

[0080] S600. According to the EEPROM operation command, perform read / write operations on the high-frequency data signal to be operated and the ultra-high-frequency data signal to be operated to obtain the modified high-frequency data signal and the modified ultra-high-frequency data signal;

[0081] In some specific embodiments, it also includes a digital common circuit for high-frequency tag signals and ultra-high-frequency tag signals. When switching frequency bands, first perform a reset through a reset signal. After the reset is completed, then perform enabling and clock input through an enabling signal and a clock signal. Among them, the enabling signals of the high-frequency tag signal and the ultra-high-frequency tag signal cannot be high at the same time; if the frequency band is in the ultra-high-frequency state or the high-frequency state, the reset signal of the digital common circuit is 1. If the frequency band is in the intermediate transition state during the ultra-high-frequency and high-frequency switching, the reset signal of the digital common circuit is 0; a glitch-free clock switching circuit is used to switch the clocks of the high-frequency tag and the ultra-high-frequency tag.

[0082] More specifically, to save chip area, the digital baseband circuit adopts a form of shared module circuit. Modules such as general cache registers and reusable timing counters need to be processed to ensure the normal operation of the circuit. For this reason, a shared module control circuit is specifically designed, and its circuit diagram is as shown in Figure 4 Shown. This module mainly processes the enable signal, reset signal, and clock signal. First, when each shared module switches frequency bands, it must be reset. After the reset is completed, the enable and relevant clock inputs are carried out to ensure that the module can work normally.

[0083] Regarding the processing of the enable signal, to ensure the normal operation of the shared module, the enable signals HF_EN and UHF_EN cannot be high at the same time. Therefore, in the shared module processing circuit, relevant processing is done on the two to ensure that at most only one of them is high level in each state, ensuring the normal operation of the circuit. Secondly, to ensure the normal operation of the module, when the asynchronous reset signal RST is high, it is decided whether to pull up HF_EN or UHF_EN.

[0084] Regarding the processing of the reset signal, as shown in Figure 4 Shown, RST is the reset signal of the shared module. When switching frequency bands, the level needs to be pulled low for a period of time and then pulled high to reset the registers in the shared module. For this reason, a state machine is designed. UHF indicates that the frequency band is in the ultra-high frequency state, and at this time RST = 1; HF indicates that the frequency band is in the high frequency state, and at this time RST = 1; the IDLE state is the intermediate transition state when switching between the two frequency bands, and at this time RST = 0, performing a reset operation on the shared module. When switching frequency bands, the state will switch to the IDLE state, and at this time RST = 0. There is a timer in this state. When the timing reaches a certain time, the IDLE state will switch to the HF or UHF state, and at this time RST becomes 1 again, ensuring that the shared module has a stable reset signal.

[0085] Regarding the processing of the clock signal, first, a glitch-free clock switching circuit is used to switch the clock for high-frequency and ultra-high-frequency tags, and the state machine jumps using the switched clock CLK. The shared module also uses this clock. To ensure the stability of the shared module and reduce power consumption, clock gating is added. Only when RST = 1, that is, when the state machine is in the HF or UHF state and the relevant shared module needs to be used, the gated clock is turned on. As shown in Figure 4 Shown, it is a schematic diagram of clock gating. It can be seen from the figure that the clock also goes through two levels of synchronization before entering the gating unit. The purpose of doing this is to delay the clock by two cycles before turning it off when the module enable is turned off, so that some modules using the enable for synchronous reset can have a clock trigger for reset operation.

[0086] Finally, as shown in Figure 6As shown below, the basic communication process in the high-frequency band of the embodiments of the present invention is described:

[0087] 1) The reader sends a card search command. If the tag is within the communication field, it replies with ATQA to indicate its current state.

[0088] 2) After receiving the ATQA, the reader sends the SEL+NVB command to select the card. After receiving the card selection signal, the tag sends the first-level cascaded UID in reply.

[0089] 3) After receiving the UID, the reader determines whether a collision occurs. If there is a collision, it continues to send SEL+NVB + the previous segment of the collision bit of the received UID. After receiving it, the tag determines whether it is its own UID. If so, the tag continues to send the remaining UID. If not, it does not respond.

[0090] 4) After receiving the UID, the reader continues to send the SEL+NVB command. At this time, it selects the second-level cascaded UID, and the tag continues to return the second-level cascaded UID. If a collision occurs, repeat step 3).

[0091] 5) When the reader sends the SEL+NVB command twice and still receives the same UID without any additional UID segments, it indicates successful selection. At this time, the tag enters the ACTIVE state and can communicate normally with the reader.

[0092] 6) When the tag is in the ACTIVE state, the reader can send read / write commands to modify and save the stored content of the tag. If the tag is to be powered off, the reader can send the HALT command.

[0093] As Figure 7 shown below, the basic communication process in the ultra-high-frequency band of the embodiments of the present invention is described:

[0094] 1) The reader selects a specific tag group through the Select command and enters the inventory waiting state.

[0095] 2) The selected tags change their inventory states.

[0096] 3) The reader sends the Query instruction to start inventory.

[0097] 4) The tag generates a random number C, and the range of this random number is determined by the Q parameter in the Query command.

[0098] 5) The reader sends the QueryRep command to continue the inventory operation.

[0099] 6) The tag receives the QueryRep command, and the random number C of the tag is decremented by 1. If C ≠ 0, it continues to return to step 5 to continue the inventory operation. If C = 0, the tag sends the random number RN16 and jumps to step 7).

[0100] 7) After receiving RN16, the reader sends an ACK of the same RN16 for confirmation.

[0101] 8) If the tag receives a valid ACK, it returns PC + EPC + CRC16. If the ACK is invalid, it re-enters step 5).

[0102] 9) The reader continues to inventory other tags.

[0103] 10) The inventoried tags enter the confirmation state. For the tags that enter the confirmation state, the reader can send read / write commands to modify and save the stored content of the tags.

[0104] In summary, in the embodiment of the present invention, the digital baseband design reasonably plans the functional modules of each module for the two protocols of dual frequency, and makes relevant processing for the shared storage. The pipeline method is adopted for the data storage and communication process to speed up the process from data reading to sending. Secondly, the scheme adopts the design of sharing the digital baseband circuit, effectively reducing the circuit area and achieving the effect of cost saving. Finally, the digital baseband sets a super user mode for setting data in different storage areas for security issues.

[0105] It can be understood that the content in the above method embodiments is applicable to the system embodiments of the present application. The functions specifically implemented by the system embodiments of the present application are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0106] The preferred embodiments of the embodiments of the present application are described above with reference to the accompanying drawings, and thus do not limit the scope of rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of rights of the embodiments of the present application.

Claims

1. An integrated circuit for a shared storage dual-frequency tag, characterized in that, The circuit includes an analog radio frequency circuit, a storage circuit, and a digital baseband circuit. The output end of the analog radio frequency circuit is connected to the input end of the digital baseband circuit. The digital baseband circuit is electrically connected to the storage circuit. The digital baseband circuit has a superuser mode, where: The analog radio frequency circuit is used to obtain a high-frequency tag signal or a ultra-high-frequency tag signal and perform demodulation and modulation processing to obtain a demodulated tag signal; The digital baseband circuit is used to decode the demodulated tag signal and perform logical control judgment to obtain a modified high-frequency data signal and a modified ultra-high-frequency data signal; The storage circuit is used to store data.

2. The circuit according to claim 1, wherein The digital baseband circuit includes a codec module, a CRC module, a command parsing module, an anti-collision circuit, a main control module, an EEPROM control circuit, a reset module, a counter module, and a data buffer module. The codec module is connected to the CRC module. The first output end of the CRC module is connected to the input end of the command parsing module. The second output end of the CRC module is connected to the input end of the reset module. The output end of the command parsing module is connected to the input end of the anti-collision circuit. The output end of the anti-collision circuit is connected to the input end of the main control module. The main control module is connected to the EEPROM control circuit. The EEPROM control circuit is connected to the data buffer module. The command parsing module, the anti-collision circuit, and the main control module are all connected to the counter module.

3. The circuit according to claim 2, wherein The CRC module, the main control module, the EEPROM control circuit, the reset module, the counter module, and the data buffer module are all digital common circuit modules for the high-frequency tag signal and the ultra-high-frequency tag signal.

4. A control method for an integrated circuit of a shared storage dual-frequency tag, characterized in that, The method includes the following steps: Obtain a high-frequency tag signal and a ultra-high-frequency tag signal and perform demodulation processing on each to obtain a demodulated high-frequency tag signal and a demodulated ultra-high-frequency tag signal; Perform decoding processing on the demodulated high-frequency tag signal and the demodulated ultra-high-frequency tag signal respectively to obtain a high-frequency digital logic signal and a ultra-high-frequency digital logic signal; Perform data verification on the high-frequency digital logic signal and the ultra-high-frequency digital logic signal to obtain a high-frequency data verification result and a ultra-high-frequency data verification result; Perform command parsing preprocessing according to the high-frequency data verification result and the ultra-high-frequency data verification result to obtain a high-frequency data parsing result and a ultra-high-frequency data parsing result; Perform data anti-collision processing on the high-frequency data parsing result and the ultra-high-frequency data parsing result to obtain a high-frequency data signal to be operated and a ultra-high-frequency data signal to be operated; According to the EEPROM operation command, perform read and write operations on the high-frequency data signal to be operated and the ultra-high-frequency data signal to be operated to obtain a modified high-frequency data signal and a modified ultra-high-frequency data signal.

5. The method according to claim 4, wherein The performing decoding processing on the demodulated high-frequency tag signal and the demodulated ultra-high-frequency tag signal respectively to obtain a high-frequency digital logic signal and a ultra-high-frequency digital logic signal includes: Perform decoding and CRC check processing on the demodulated high-frequency tag signal and the demodulated ultra-high-frequency tag signal respectively to obtain the data length of the high-frequency tag signal and the data length of the ultra-high-frequency tag signal; For the demodulated high-frequency tag signal and the demodulated ultra-high-frequency tag signal that pass the CRC check, perform command parsing in combination with the data length of the high-frequency tag signal and the data length of the ultra-high-frequency tag signal to obtain a high-frequency tag parsing signal and an ultra-high-frequency tag parsing signal; Select the high-frequency tag parsing signal and the ultra-high-frequency tag parsing signal to obtain a selected high-frequency tag parsing signal and a selected ultra-high-frequency tag parsing signal; Perform CRC generation and data merging and sending on the selected high-frequency tag parsing signal and the selected ultra-high-frequency tag parsing signal to obtain the high-frequency digital logic signal and the ultra-high-frequency digital logic signal.

6. The method according to claim 5, wherein Both the selected high-frequency tag parsing signal and the selected ultra-high-frequency tag parsing signal include the read data of the EEPROM, the reply data of the protocol content, and the UID data or EPC data replied during card selection.

7. The method according to claim 4, characterized in that The data check on the high-frequency digital logic signal and the ultra-high-frequency digital logic signal to obtain a high-frequency data check result and an ultra-high-frequency data check result includes: Perform data check on the high-frequency digital logic signal and the ultra-high-frequency digital logic signal; If the data check result fails, perform a reset process and re-obtain the high-frequency tag signal and the ultra-high-frequency tag signal; If the data check result passes, output the high-frequency data check result and the ultra-high-frequency data check result.

8. The method according to claim 4, characterized in that The command parsing preprocessing based on the high-frequency data check result and the ultra-high-frequency data check result to obtain a high-frequency data parsing result and an ultra-high-frequency data parsing result includes: Perform command parsing on the high-frequency data check result and the ultra-high-frequency data check result to obtain high-frequency parsed data and ultra-high-frequency parsed data. Both the high-frequency parsed data and the ultra-high-frequency parsed data include data parameters, operation behaviors, and address parameters; Judge the read / write area permissions of the high-frequency parsed data and the ultra-high-frequency parsed data according to the operation behavior based on the address parameter; If the read / write area permission does not meet the requirements, feedback a mismatch signal; If the read / write area permission meets the requirements, generate the high-frequency data parsing result and the ultra-high-frequency data parsing result.

9. The method according to claim 8, wherein It also includes cross-band data modification between the high-frequency parsed data and the ultra-high-frequency parsed data. If the superuser mode is enabled, the corresponding password needs to be input through an instruction, and all read / write area permissions are unlocked when the password passes.

10. The method according to claim 4, characterized in that, It also includes that for the digital common circuit of the high-frequency tag signal and the ultra-high-frequency tag signal, when performing frequency band switching, first perform a reset through a reset signal, and then perform enabling and clock input through an enabling signal and a clock signal, where: The enabling signals of the high-frequency tag signal and the ultra-high-frequency tag signal cannot be high at the same time; If the frequency band is in the ultra-high frequency state or the high frequency state, the reset signal of the digital common circuit is 1. If the frequency band is in the intermediate transition state during the ultra-high frequency and high frequency switching, the reset signal of the digital common circuit is 0; The clock of the high-frequency tag and the ultra-high frequency tag is switched by the glitch-free clock switching circuit.

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