Shifting register, driving circuit, driving method and display device

Abstract

The invention provides a shift register, a driving circuit, a driving method and a display device, and relates to the technical field of display. The shift register comprises a first control circuit which controls a first node by using a first input signal under the control of a first clock signal, and controls a second node by using a second power supply voltage and a second clock signal under the control of the first input signal, the first clock signal and a first power supply voltage; the second control circuit is used for controlling a third node by utilizing the potential of the second node and a second power supply voltage under the control of a first clock signal, a first input signal, a second input signal and a third clock signal; the first output circuit outputs a first output signal based on the first power supply voltage and the second power supply voltage under the potential control of the first node and the second node; and the second output circuit outputs a second output signal based on the first power supply voltage and the second power supply voltage under the control of the first input signal, the potential of the third node, the third input signal and the fourth input signal.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a shift register, a driving circuit, a driving method, and a display device. Background Art

[0002] In some display devices, pixel circuits are driven to emit light by multiple driving signals. Therefore, it is usually necessary for multiple gate driver on array (GOA) circuits to respectively provide multiple driving signals, which will increase the area occupied by the GOA and is not conducive to narrowing the border of the display device. Summary of the Invention

[0003] To solve the above problems, the present disclosure provides a shift register, a driving circuit, a driving method, and a display device.

[0004] According to a first aspect, the present disclosure provides a shift register, including: a first control circuit configured to control the potential of a first node by using a first input signal from a first input terminal under the control of a first clock signal from a first clock terminal, and to control the potential of a second node by using a second power supply voltage of a second power supply and a second clock signal from a second clock terminal under the control of the first input signal, the first clock signal, and a first power supply voltage of a first power supply; a second control circuit configured to control the potential of a third node by using the potential of the second node and the second power supply voltage under the control of the first clock signal, the first input signal, a second input signal from a second input terminal, and a third clock signal from a third clock terminal; a first output circuit configured to output a first output signal via a first output terminal based on the first power supply voltage and the second power supply voltage under the control of the potential of the first node and the potential of the second node; and a second output circuit configured to output a second output signal via a second output terminal based on the first power supply voltage and the second power supply voltage under the control of the first input signal, the potential of the third node, a third input signal from a third input terminal, and a fourth input signal from a fourth input terminal; wherein, the moment when the second output signal switches from a first level to a second level is related to the levels of the second input signal and the fourth input signal, and the moment when the second output signal switches from the second level to the first level is related to the levels of the third input signal and the fourth input signal.

[0005] According to a second aspect, the present disclosure provides a driving circuit, including M cascaded shift registers provided in the embodiments of the present disclosure, where M is an integer greater than 1.

[0006] According to a third aspect, the present disclosure provides a display device, including the driving circuit provided in the embodiments of the present disclosure.

[0007] According to a fourth aspect, the present disclosure provides a driving method, which is applied to the shift register provided in the embodiments of the present disclosure, and includes: controlling the potential of a first node by using a first input signal from a first input terminal under the control of a first clock signal from a first clock terminal, and controlling the potential of a second node by using a second power supply voltage of a second power supply and a second clock signal from a second clock terminal under the control of the first input signal, the first clock signal, and a first power supply voltage of a first power supply; controlling the potential of a third node by using the potential of the second node and the second power supply voltage under the control of the first clock signal, the first input signal, a second input signal from a second output terminal, and a third clock signal from a third clock terminal; outputting a first output signal via a first output terminal based on the first power supply voltage and the second power supply voltage under the control of the potential of the first node and the potential of the second node; and outputting a second output signal via a second output terminal based on the first power supply voltage and the second power supply voltage under the control of the first input signal, the potential of the third node, a third input signal from a third input terminal, and a fourth input signal from a fourth input terminal. Description of the Drawings

[0008] Figure 1 Shows a schematic structural diagram of a shift register according to an embodiment of the present disclosure;

[0009] Figure 2 Shows a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0010] Figure 3 Shows a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0011] Figure 4 Shows a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0012] Figure 5 Shows Figure 4 The signal timing diagram of the shift register in

[0013] Figure 6 Shows a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0014] Figure 7 Shows Figure 6 The signal timing diagram of the shift register in

[0015] Figure 8 Shows a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0016] Figure 9 Shows a schematic structural diagram of a driving circuit according to another embodiment of the present disclosure;

[0017] Figure 10 shows Figure 9 the signal timing diagram of the driving circuit in

[0018] Figure 11 shows the structural schematic diagram of the driving circuit according to another embodiment of the present disclosure;

[0019] Figure 12 shows Figure 11 the signal timing diagram of the driving circuit in

[0020] Figure 13 shows the structural schematic diagram of the display device according to the embodiment of the present disclosure;

[0021] Figure 14 shows the schematic flowchart of the driving method according to the embodiment of the present disclosure. Detailed Embodiments

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are for illustrative purposes only and should not be construed as any limitation to the present disclosure, but merely examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual sizes and proportions, but only illustrate the content of the embodiments of the present disclosure.

[0023] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings understood by those skilled in the art. The "first", "second", and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components.

[0024] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may mean that two components are directly connected, or may mean that two components are connected via one or more other components. In addition, these two components may be connected or coupled by wired or wireless means.

[0025] In the embodiments of the present disclosure, the source and drain of the switching transistor used are symmetric, so the source and drain can be interchanged. In the embodiments of the present disclosure, according to its function, the gate can be referred to as the control electrode, one of the source and drain can be referred to as the first electrode, and the other of the source and drain can be referred to as the second electrode.

[0026] In addition, in the description of the embodiments of the present disclosure, the terms "first power supply voltage" and "second power supply voltage" are only used to distinguish the different amplitudes of the two power supply voltages. For example, in the following, the "first power supply voltage" is taken as a relatively low voltage and the "second power supply voltage" is taken as a relatively high voltage for description. Those skilled in the art can understand that the present disclosure is not limited thereto.

[0027] It should be noted that in the description of the embodiments of the present disclosure, INPUT can represent both the input signal terminal and the input signal provided by the input terminal, and can also represent the level of the input signal. Similarly, the symbol CLA can represent both the first clock terminal and the first clock signal provided by the first clock terminal, and can also represent the level of the first clock signal. OUT1 can represent both the first output terminal and the first output signal output by the first output terminal, and can also represent the level of the first output signal. VGH and VGL can represent both the power supply terminal and the power supply voltage provided by the power supply terminal. For example, the second power supply VGH can provide a high-level voltage, and the first power supply VGL can provide a low-level voltage. The same applies to the following embodiments and will not be repeated.

[0028] Figure 1 A schematic structural diagram of a shift register according to an embodiment of the present disclosure is shown.

[0029] As Figure 1 shown, the shift register 100 includes a first control circuit 110, a second control circuit 120, a first output circuit 130, and a second output circuit 140.

[0030] In the embodiments of the present disclosure, the first control circuit 110 is electrically connected to the first clock terminal CLA, the second clock terminal CLB, the first input terminal INPUT1, the first power supply VGL, and the second power supply VGH. Under the control of the first clock signal CLA from the first clock terminal CLA, the first control circuit 110 controls the potential of the first node N1 by using the first input signal INPUT1 from the first input terminal INPUT1, and under the control of the first input signal INPUT1, the first clock signal CLA, and the first power supply voltage VGL of the first power supply VGL, the first control circuit 110 controls the potential of the second node N2 by using the second power supply voltage VGH of the second power supply VGH and the second clock signal CLB from the second clock terminal CLB.

[0031] For example, the first control circuit 110 can control the connection or disconnection between the first input signal INPUT1 and the first node N1. Under the control of the first clock signal CLA, when the first control circuit 110 controls the connection between the first input signal INPUT1 and the first node N1, the first input signal INPUT1 can be provided to the first node N1 at this time to control the potential of the first node N1. Under the control of the first clock signal CLA, when the first control circuit 110 controls the disconnection between the first input signal INPUT1 and the first node N1, the potential of the first node N1 can maintain the state of the previous stage at this time.

[0032] For example, the first control circuit 110 can control the connection or disconnection between the second power supply voltage VGH and the second node N2. Under the control of the first input signal INPUT1, when the first control circuit 110 controls the connection between the second power supply voltage VGH and the second node N2, the second power supply voltage VGH can be provided to the second node N2 at this time, and the second node N2 is a high-level signal. Under the control of the first input signal INPUT1, when the first control circuit 110 controls the disconnection between the second power supply voltage VGH and the second node N2, the potential of the second node N2 can maintain the state of the previous stage at this time.

[0033] For example, the first control circuit 110 can control the connection or disconnection between the second clock signal CLB and the second node N2. Under the control of the first clock signal CLA, the first power supply voltage VGL, and the second clock signal CLB, when the first control circuit 110 controls the connection between the second clock signal CLB and the second node N2, the second clock signal CLB can be provided to the second node N2 at this time to control the potential of the second node N2. Under the control of the first clock signal CLA, the first power supply voltage VGL, and the second clock signal CLB, when the first control circuit 110 controls the disconnection between the second clock signal CLB and the second node N2, the potential of the second node N2 can maintain the state of the previous stage at this time.

[0034] In the embodiment of the present disclosure, the first output circuit 120 is electrically connected to the first power supply VGL and the second power supply VGH. Under the control of the potential of the first node N1 and the potential of the second node N2, the first output circuit 120 outputs the first output signal OUT1 via the first output terminal OUT1 based on the first power supply voltage VGL and the second power supply voltage VGH.

[0035] For example, the first output circuit 120 can control the connection or disconnection between the first power supply voltage VGL and the first output terminal OUT1. Under the control of the potential of the first node N1, when the first control circuit 110 controls the connection between the first power supply voltage VGL and the first output terminal OUT1, the first power supply voltage VGL can be provided to the first output terminal OUT1 at this time, and the first output terminal OUT1 outputs a low-level signal. Under the control of the potential of the first node N1, when the first control circuit 110 controls the disconnection between the first power supply voltage VGL and the first output terminal OUT1, the potential of the first output terminal OUT1 can maintain the state of the previous stage at this time.

[0036] For example, the first output circuit 120 can control the connection or disconnection between the second power supply voltage VGH and the first output terminal OUT1. Under the control of the potential of the second node N2, when the first control circuit 110 controls the connection between the second power supply voltage VGH and the first output terminal OUT1, the second power supply voltage VGH can be provided to the first output terminal OUT1 at this time, and the first output terminal OUT1 outputs a high-level signal. Under the control of the potential of the second node N2, when the first control circuit 110 controls the disconnection between the second power supply voltage VGH and the first output terminal OUT1, the potential of the first output terminal OUT1 can maintain the state of the previous stage at this time.

[0037] In the embodiment of the present disclosure, the second control circuit 130 is electrically connected to the first input terminal INPUT1, the second input terminal INPUT2, the first clock terminal CLA, the third clock terminal CLC, and the second power supply VGH. Under the control of the first clock signal CLA, the first input signal INPUT1, the second input signal INPUT2 from the second input terminal INPUT2, and the third clock signal CLC from the third clock terminal CLC, the second control circuit 130 controls the potential of the third node N3 by using the potential of the second node N2 and the second power supply voltage VGH.

[0038] For example, the second control circuit 130 can control the connection or disconnection between the second power supply voltage VGH and the third node N3. Under the control of the first input signal INPUT1, when the second control circuit 130 controls the connection between the second power supply voltage VGH and the third node N3, the second power supply voltage VGH can be provided to the third node N3 at this time, and the potential of the third node N3 is high level. Under the control of the first input signal INPUT1, when the second control circuit 130 controls the disconnection between the second power supply voltage VGH and the third node N3, the potential of the third node N3 can maintain the state of the previous stage at this time.

[0039] For example, the second control circuit 130 can control the connection or disconnection between the second node N2 and the third node N3. Under the control of the first clock signal CLA, the second input signal INPUT2, and the third clock signal CLC, when the second control circuit 130 controls the connection between the second node N2 and the third node N3, the potential of the second node N2 can be provided to the third node N3 to control the potential of the third node N3. Under the control of the first clock signal CLA, the second input signal INPUT2, and the third clock signal CLC, when the second control circuit 130 controls the disconnection between the second node N2 and the third node N3, the potential of the third node N3 can maintain the state of the previous stage.

[0040] In the embodiment of the present disclosure, the second output circuit 140 is electrically connected to the first power supply VGL, the second power supply VGH, the first input terminal INPUT1, the third input terminal INPUT3, and the fourth input terminal INPUT4. Under the control of the first input signal INPUT1, the potential of the third node N3, the third input signal INPUT3 from the third input terminal INPUT3, and the fourth input signal INPUT4 from the fourth input terminal INPUT4, the second output circuit 140 outputs the second output signal OUT2 via the second output terminal OUT2 based on the first power supply voltage VGL and the second power supply voltage VGH.

[0041] For example, the second output circuit 140 can control the connection or disconnection between the first power supply voltage VGL and the second output terminal OUT2. Under the control of the third input signal INPUT3, when the second output circuit 140 controls the connection between the first power supply voltage VGL and the second output terminal OUT2, the first power supply voltage VGL can be provided to the second output terminal OUT2, and the second output terminal OUT2 outputs a low-level signal. Under the control of the third input signal INPUT3, when the second output circuit 140 controls the disconnection between the first power supply voltage VGL and the second output terminal OUT2, the potential of the second output signal OUT2 can maintain the state of the previous stage.

[0042] For example, the second output circuit 140 can control the connection or disconnection between the first power supply voltage VGL and the second output terminal OUT2. When the second output circuit 140 controls the connection between the first power supply voltage VGL and the second output terminal OUT2 under the control of the first input signal INPUT1 and the fourth input signal INPUT4, the first power supply voltage VGL can be provided to the second output terminal OUT2 at this time, and the second output terminal OUT2 outputs a low-level signal. When the second output circuit 140 controls the disconnection between the first power supply voltage VGL and the second output terminal OUT2 under the control of the first input signal INPUT1 and the fourth input signal INPUT4, the potential of the second output signal OUT2 can maintain the state of the previous stage at this time.

[0043] For example, the second output circuit 140 can control the connection or disconnection between the second power supply voltage VGH and the second output terminal OUT2. When the second output circuit 140 controls the connection between the second power supply voltage VGH and the second output terminal OUT2 under the control of the potential of the third node N3 and the fourth input signal INPUT4, the second power supply voltage VGH can be provided to the second output terminal OUT2 at this time, and the second output terminal OUT2 outputs a high-level signal. When the second output circuit 140 controls the disconnection between the second power supply voltage VGH and the second output terminal OUT2 under the control of the potential of the third node N3 and the fourth input signal INPUT4, the potential of the second output signal OUT2 can maintain the state of the previous stage at this time.

[0044] In the embodiments of the present disclosure, the moment when the second output signal OUT2 switches from the first level to the second level is related to the levels of the second input signal INPUT2 and the fourth input signal INPUT4, and the moment when the second output signal OUT2 switches from the second level to the first level is related to the levels of the third input signal INPUT3 and the fourth input signal INPUT4.

[0045] In the embodiments of the present disclosure, the first level can be a low level, the second level can be a high level, the moment when the level of the second output signal OUT2 switches from low to high is related to the levels of the second input signal INPUT2 and the fourth input signal INPUT4, and the moment when the level of the second output signal OUT2 switches from high to low is related to the levels of the third input signal INPUT3 and the fourth input signal INPUT4.

[0046] For example, the level switching moment of the third input signal INPUT3 can affect the moment when the first power supply voltage VGL is connected to and disconnected from the second output terminal OUT2, thereby affecting the moment when the second output terminal OUT2 outputs a low-level signal. The level switching moments of the second input signal INPUT2 and the fourth input signal INPUT4 can affect the moment when the second power supply voltage VGH is connected to and disconnected from the second output terminal OUT2, thereby affecting the moment when the second output terminal OUT2 outputs a high-level signal.

[0047] In the embodiments of the present disclosure, by setting the level switching moments of the second input signal INPUT2, the third input signal INPUT3, and the fourth input signal INPUT4, the moment of high-level and low-level switching of the second output signal OUT2 can be controlled, the level width of the second output signal OUT2 can be controlled, and the phase difference between the second output signal OUT2 and the first output signal OUT1 can be controlled.

[0048] In the embodiments of the present disclosure, the first input signal INPUT1, the first clock signal CLA, and the second clock signal CLB are used to control the first output terminal OUT1 to output a high-level signal or a low-level signal. The first input signal INPUT1, the second input signal INPUT2, the third input signal INPUT3, the fourth input signal INPUT4, the first clock signal CLA, the second clock signal CLB, and the third clock signal CLC are used to control the second output terminal OUT2 to output a high-level signal or a low-level signal. The level widths of the first output signal OUT1 and the second output signal OUT2 can be different or the same, and thus can be used as different driving signals respectively. The first output signal OUT1 and the second output signal OUT2 output by a single shift register can be provided to the pixel circuit as different driving signals to meet the different driving signals required by the pixel circuit, thereby reducing the number of GOAs and the number of thin-film transistors (TFTs), and effectively narrowing the border of the display product.

[0049] In addition, the first output signal OUT1 and the second output signal OUT2 share the first clock signal CLA, the second clock signal CLB, and the third clock signal CLC, which can reduce the number of clock signals required to output the two output signals. Figure 2 A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown.

[0050] As Figure 2 shown, the shift register 200 includes a first control circuit 210, a second control circuit 220, a first output circuit 230, a second output circuit 240, a third control circuit 250, and a third output circuit 260.

[0051] In the embodiments of the present disclosure, the first control circuit 210, the second control circuit 220, the first output circuit 230, and the second output circuit 240 may refer to the first control circuit 110, the second control circuit 120, the first output circuit 130, and the second output circuit 140 described above, and the similar parts will not be described in detail.

[0052] In the embodiments of the present disclosure, the third control circuit 250 is electrically connected to the fifth input terminal INPUT5, the second output terminal OUT2, the second power supply VGH, and the fourth clock terminal CLD. Under the control of the second output signal OUT2, the second power supply voltage VGH, and the fourth clock signal CLD from the fourth clock terminal CLD, the third control circuit 250 controls the potential of the fourth node N4 by using the second power supply voltage VGH and the fifth input signal INPUT5 from the fifth input terminal INPUT5.

[0053] For example, the third control circuit 250 can control the connection state or disconnection state between the second power supply voltage VGH and the fourth node N4. Under the control of the fourth clock signal CLD, when the third control circuit 250 controls the connection state between the second power supply voltage VGH and the fourth node N4, the second power supply voltage VGH can be provided to the fourth node N4 at this time, and the potential of the fourth node N4 is at a high level. Under the control of the fourth clock signal CLD, when the third control circuit 250 controls the disconnection state between the second power supply voltage VGH and the fourth node N4, the potential of the fourth node N4 can maintain the state of the previous stage at this time.

[0054] For example, the third control circuit 250 can control the connection state or disconnection state between the fifth input signal INPUT5 and the fourth node N4. Under the control of the second output signal OUT2 and the second power supply voltage VGH, when the third control circuit 250 controls the connection state between the fifth input signal INPUT5 and the fourth node N4, the fifth input signal INPUT5 can be provided to the fourth node N4 at this time to control the potential of the fourth node N4. Under the control of the second output signal OUT2 and the second power supply voltage VGH, when the third control circuit 250 controls the disconnection state between the fifth input signal INPUT5 and the fourth node N4, the potential of the fourth node N4 can maintain the state of the previous stage at this time.

[0055] In the embodiments of the present disclosure, the third output circuit 260 is electrically connected to the fourth node N4, the second output terminal OUT2, the second clock terminal CLB, and the second power supply voltage VGH. Under the control of the potential of the fourth node N4 and the second output signal OUT2, the third output circuit 260 outputs the third output signal OUT3 via the third output terminal OUT3 based on the second power supply voltage VGH and the second clock signal CLB.

[0056] For example, the third output circuit 260 can control the connection or disconnection between the second power supply voltage VGH and the third output terminal OUT3. When the third output circuit 260 controls the connection between the second power supply voltage VGH and the third output terminal OUT3 under the control of the second output signal OUT2, the second power supply voltage VGH can be provided to the third output terminal OUT3 at this time, and the third output terminal OUT3 outputs a high-level signal. When the third output circuit 260 controls the disconnection between the second power supply voltage VGH and the third output terminal OUT3 under the control of the second output signal OUT2, the potential of the third output terminal OUT3 can maintain the state of the previous stage at this time.

[0057] For example, the third output circuit 260 can control the connection or disconnection between the second clock terminal CLB and the third output terminal OUT3. When the third output circuit 260 controls the connection between the second clock terminal CLB and the third output terminal OUT3 under the control of the potential of the fourth node N4, the second clock signal CLB can be provided to the third output terminal OUT3 at this time to control the potential of the third output terminal OUT3. When the third output circuit 260 controls the disconnection between the second clock terminal CLB and the third output terminal OUT3 under the control of the potential of the fourth node N4, the potential of the third output terminal OUT3 can maintain the state of the previous stage at this time.

[0058] In the embodiments of the present disclosure, the moment when the third output signal OUT3 switches from the second level to the first level is related to the levels of the fifth input signal INPUT5 and the second output signal OUT2, and the moment when the third output signal OUT3 switches from the first level to the second level is related to the levels of the second output signal OUT2 and the fourth clock signal CLD.

[0059] In the embodiments of the present disclosure, the first level can be a low level, the second level can be a high level, the moment when the second output signal OUT2 switches from high to low is related to the levels of the fifth input signal INPUT5 and the second output signal OUT2, and the moment when the third output signal OUT3 switches from low to high is related to the levels of the second output signal OUT2 and the fourth clock signal CLD. By controlling the moment of the high and low level switching of the third output signal OUT3 through the fifth input signal INPUT5, the second output signal OUT2, and the fourth clock signal CLD, the level width of the third output signal OUT3 can be controlled, the phase difference between the third output signal OUT3 and the second output signal OUT2 can be controlled, and the phase difference between the third output signal OUT3 and the first output signal OUT1 can be controlled.

[0060] In the embodiments of the present disclosure, the second output signal OUT2, the fourth clock signal CLD, and the fifth input signal INPUT5 can control the potential of the fourth node N4. Based on the potential of the fourth node N4, the second output signal OUT2 and the second clock signal CLB can control the third output terminal OUT3 to output a high-level signal or a low-level signal.

[0061] In the embodiments of the present disclosure, the second output signal OUT2, the fourth clock signal CLD, the fifth input signal INPUT5, and the second clock signal CLB are used to control the third output terminal OUT3 to output a high-level signal or a low-level signal. The level widths of the first output signal OUT1, the second output signal OUT2, and the third output signal OUT3 can be different, so that they can be used as different driving signals respectively. The first output signal OUT1, the second output signal OUT2, and the third output signal OUT3 output by a single shift register can be provided to the pixel circuit as different driving signals to meet the different driving signals required by the pixel circuit, thereby reducing the number of GOAs and the number of TFTs, and effectively narrowing the border of the display product.

[0062] In addition, the first output signal OUT1, the second output signal OUT2, and the third output signal OUT3 share a set of clock signals (the first clock signal CLA, the second clock signal CLB, the third clock signal CLC, and the fourth clock signal CLD), which can reduce the number of clock signals required to output the three output signals.

[0063] In the embodiments of the present disclosure, the first output signal OUT1 can be a light emission control signal output to the pixel circuit, and the second output signal OUT2 can be a scanning signal output to the pixel circuit to control, for example, the N-type transistor in the pixel circuit. The third output signal OUT3 can be a reset signal output to the pixel circuit.

[0064] Figure 3 FIG. shows a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0065] As Figure 3 shown, the shift register 300 includes a first control circuit 310, a first output circuit 320, a second control circuit 330, a second output circuit 340, a third control circuit 350, and a third output circuit 360.

[0066] In the embodiments of the present disclosure, the first output circuit 330 and the third output circuit 360 can refer to the first output circuit 230 and the third output circuit 260 described above, and similar parts will not be described in detail.

[0067] In the embodiments of the present disclosure, the first control circuit 310 includes a first control unit 311 and a second control unit 312.

[0068] In an embodiment of the present disclosure, the first control unit 311 is electrically connected to the first input terminal INPUT1, the first clock terminal CLA, and the second clock terminal CLB. Under the control of the first clock signal CLA, the first control unit 311 provides the first input signal INPUT1 to the first node N1 and the sixth node N6, and under the control of the second clock signal CLB and the potential of the sixth node N6, provides the potential of the sixth node N6 to the first node N1.

[0069] For example, the first clock signal CLA can control the connection state or disconnection state between the first input signal INPUT1 and the first node N1. When the first control unit 311 controls the connection state between the first input signal INPUT1 and the first node N1 under the control of the first clock signal CLA, the first input signal INPUT1 can be provided to the first node N1 at this time to control the potential of the first node N1. When the first control unit 311 controls the disconnection state between the first input signal INPUT1 and the first node N1 under the control of the first clock signal CLA, the potential of the first node N1 can maintain the state of the previous stage at this time.

[0070] For example, the first clock signal CLA can control the connection or disconnection state between the first input signal INPUT1 and the sixth node N6. When the first control unit 311 controls the connection state between the first input signal INPUT1 and the sixth node N6 under the control of the first clock signal CLA, the first input signal INPUT1 can be provided to the sixth node N6 at this time to control the potential of the sixth node N6. When the first control unit 311 controls the disconnection state between the first input signal INPUT1 and the sixth node N6 under the control of the first clock signal CLA, the potential of the sixth node N6 can maintain the state of the previous stage at this time. For example, the second clock signal CLB and the potential of the sixth node N6 can control the connection or disconnection state between the sixth node N6 and the first node N1. When the second control unit 312 controls the connection state between the sixth node N6 and the first node N1 under the control of the second clock signal CLB and the potential of the sixth node N6, the potential of the sixth node N6 can be provided to the first node N1 at this time to control the potential of the first node N1. When the second control unit 312 controls the disconnection state between the sixth node N6 and the first node N1 under the control of the second clock signal CLB and the potential of the sixth node N6, the potential of the first node N1 can maintain the state of the previous stage at this time. The potential of the first node N1 can be stably controlled at a low potential through the second clock signal CLB and the sixth node N6. In the embodiment of the present disclosure, the second control unit 312 is electrically connected to the first input terminal INPUT1, the first clock terminal CLA, the second clock terminal CLB, the first power supply VGL, and the second power supply VGH. Under the control of the first power supply voltage VGL and the first clock signal CLA, the second control unit 312 provides the second clock signal CLB to the seventh node N7, and under the control of the first input signal INPUT1 and the second clock signal CLB, provides the second power supply voltage VGH or the potential of the seventh node N7 to the second node N2.

[0071] For example, the first input signal INPUT1 can control the connection or disconnection state between the second power supply VGH and the second node N2. When the second control unit 312 controls the connection state between the second power supply VGH and the second node N2 under the control of the first input signal INPUT1, the second power supply voltage VGH can be provided to the second node N2 at this time, and the potential of the second node N2 is at a high level. When the second control unit 312 controls the disconnection state between the second power supply VGH and the second node N2 under the control of the first input signal INPUT1, the potential of the second node N2 can maintain the state of the previous stage at this time.

[0072] When the first input signal INPUT1 is at a low level, N2 between the first power supply voltage VGL and the second node conducts, thereby maintaining the potential of the second node N2 at a high level. The first output circuit 320 stably controls the disconnection between the second power supply VGH and the first output terminal OUT1 to avoid the misoutput of the second power supply voltage VGH.

[0073] For example, the second clock signal CLB can control the connection state or disconnection state between the seventh node N7 and the second node N2. Under the control of the second clock signal CLB, when the second control unit 312 controls the connection state between the seventh node N7 and the second node N2, the potential of the seventh node N7 can be provided to the second node N2 at this time to control the potential of the second node N2. Under the control of the second clock signal CLB, when the second control unit 312 controls the disconnection state between the seventh node N7 and the second node N2, the potential of the second node N2 can maintain the state of the previous stage at this time.

[0074] For example, the first power supply voltage VGL and the first clock signal CLA can control the connection state or disconnection state between the second clock terminal CLB and the seventh node N7. Under the control of the first power supply voltage VGL and the first clock signal CLA, when the second control unit 312 controls the connection state between the second clock terminal CLB and the seventh node N7, the second clock signal CLB can be provided to the seventh node N7 at this time to control the potential of the seventh node N7. Under the control of the first power supply voltage VGL and the first clock signal CLA, when the second control unit 312 controls the disconnection state between the second clock terminal CLB and the seventh node N7, the potential of the seventh node N7 can maintain the state of the previous stage at this time.

[0075] In the embodiment of the present disclosure, the second control circuit 330 includes a third control unit 331 and a fourth control unit 332.

[0076] In the embodiment of the present disclosure, the third control unit 331 is electrically connected to the second input terminal INPUT2, the first clock terminal CLA, and the third clock terminal CLC. The third control unit 331 provides the second input signal INPUT2 to the eighth node N8 under the control of the third clock signal CLC, and controls the potential of the eighth node N8 by using the first clock signal CLA under the control of the potential of the eighth node N8.

[0077] For example, the third clock signal CLC can control the connection or disconnection between the second input terminal INPUT2 and the eighth node N8. When the third control unit 331 controls the connection between the second input terminal INPUT2 and the eighth node N8 under the control of the third clock signal CLC, the second input signal INPUT2 can be provided to the eighth node N8 at this time to control the potential of the eighth node N8. When the third control unit 331 controls the disconnection between the second input terminal INPUT2 and the eighth node N8 under the control of the third clock signal CLC, the potential of the eighth node N8 can maintain the state of the previous stage. In the embodiment of the present disclosure, the fourth control unit 332 is electrically connected to the first input terminal INPUT1, the second power supply VGH, the second node N2, and the eighth node N8. Under the control of the potential of the eighth node N8, the fourth control unit 332 provides the potential of the second node N2 to the third node N3, and under the control of the first input signal INPUT1, provides the second power supply voltage VGH to the third node N3.

[0078] For example, the potential of the eighth node N8 can control the connection or disconnection between the second node N2 and the third node N3. When the fourth control unit 332 controls the connection between the second node N2 and the third node N3 under the control of the potential of the eighth node N8, the potential of the second node N2 can be provided to the third node N3 at this time to control the potential of the third node N3. When the fourth control unit 332 controls the disconnection between the second node N2 and the third node N3 under the control of the potential of the eighth node N8, the potential of the third node N3 can maintain the state of the previous stage.

[0079] For example, the first input signal INPUT1 can control the connection or disconnection between the second power supply VGH and the third node N3. When the fourth control unit 332 controls the connection between the second power supply VGH and the third node N3 under the control of the first input signal INPUT1, the second power supply voltage VGH can be provided to the third node N3 at this time, and the potential of the third node N3 is at a high level. When the fourth control unit 332 controls the disconnection between the second power supply VGH and the third node N3 under the control of the first input signal INPUT1, the potential of the third node N3 can maintain the state of the previous stage.

[0080] In the embodiment of the present disclosure, the second output circuit 340 includes a pull - down unit 341 and an output unit 342.

[0081] In the embodiment of the present disclosure, the pull - down unit 341 is electrically connected to the first input terminal INPUT1 and the first power supply VGL. The pull - down unit 341 provides the first power supply voltage VGL to the fifth node N5 under the control of the first input signal INPUT1.

[0082] For example, the first input signal INPUT1 can control the connection or disconnection between the first power supply VGL and the fifth node N5. When the pull-down unit 341 controls the connection between the first power supply VGL and the fifth node N5 under the control of the first input signal INPUT1, the first power supply voltage VGL can be provided to the fifth node N5 at this time, and the potential of the fifth node N5 is at a low level. When the pull-down unit 341 controls the disconnection between the first power supply VGL and the fifth node N5 under the control of the first input signal INPUT1, the potential of the fifth node N5 can maintain the state of the previous stage at this time.

[0083] In the embodiment of the present disclosure, the output unit 342 is electrically connected to the second output terminal OUT2, the fifth node N5, and the fourth input terminal INPUT4. Under the control of the fourth input signal INPUT4, the output unit 342 provides the potential of the fifth node N5 to the second output terminal OUT2.

[0084] For example, the fourth input signal INPUT4 can control the connection or disconnection between the fifth node N5 and the second output terminal OUT2. When the output unit 342 controls the connection between the fifth node N5 and the second output terminal OUT2 under the control of the fourth input signal INPUT4, the potential of the fifth node N5 can be provided to the second output terminal OUT2 at this time to control the potential of the second output terminal OUT2. When the output unit 342 controls the disconnection between the fifth node N5 and the second output terminal OUT2 under the control of the fourth input signal INPUT4, the potential of the second output terminal OUT2 can maintain the state of the previous stage at this time.

[0085] In the embodiment of the present disclosure, the output unit 342 is electrically connected to the third node N3, the fifth node N5, and the second power supply VGH. Under the control of the potential of the third node N3, the output unit 342 provides the potential of the second power supply VGH to the fifth node N5.

[0086] For example, the potential of the third node N3 can control the connection or disconnection between the second power supply VGH and the fifth node N5. When the output unit 342 controls the connection between the second power supply VGH and the fifth node N5 under the control of the potential of the third node N3, the potential of the second power supply VGH can be provided to the fifth node N5 at this time, and the fifth node N5 is at a high potential. When the output unit 342 controls the disconnection between the second power supply VGH and the fifth node N5 under the control of the potential of the third node N3, the potential of the fifth node N5 can maintain the state of the previous stage at this time.

[0087] The second input terminal INPUT2 controls the conduction relationship between the second node N2 and the third node N3 by controlling the potential of the eighth node N8, and pulls down the potential of the third node N3, so that the second power supply VGH and the fifth node N5 can be controlled to be in a connected state, and the potential of the fifth node N5 is pulled up. When the fifth node N5 and the second output terminal OUT2 are in a connected state, the potential of the fifth node N5 can be provided to the second output terminal OUT2. Therefore, the second input terminal INPUT2 can control the potential of the second output terminal OUT2 to switch from a low potential to a high potential.

[0088] In the embodiment of the present disclosure, in the case where the second output signal OUT2 with a low level needs to be output from the second output terminal OUT2, as can be seen from the foregoing content, the first power supply voltage VGL can be provided to the second output terminal OUT2 under the control of the third input signal INPUT3. At this time, the pull-down unit 341 can control the first power supply VGL and the fifth node N5 to be in a connected state through the first input signal INPUT1, so that the first power supply voltage VGL is provided to the fifth node N5, and the potential of the fifth node N5 is maintained at a low level. In the case where the fifth node N5 and the second output terminal OUT2 are accidentally in a connected state, the low-level signal of the fifth node N5 can control the second output terminal OUT2 to be at a low level, which can prevent the second output terminal OUT2 from being pulled up and improve the stability of the signal output from the second output terminal OUT2.

[0089] In the embodiment of the present disclosure, the third control circuit 350 includes a fifth control unit 351 and a sixth control unit 352.

[0090] In the embodiment of the present disclosure, the fifth control unit 351 is electrically connected to the second output terminal OUT2, the fifth input terminal INPUT5, and the second power supply VGH. The fifth control unit 351 provides the fifth input signal INPUT5 to the fourth node N4 under the control of the second output signal OUT2 and the second power supply voltage VGH.

[0091] For example, the second output signal OUT2 and the second power supply voltage VGH can control the connection state or disconnection state between the fifth input terminal INPUT5 and the fourth node N4. When the fifth control unit 351 controls the fifth input terminal INPUT5 and the fourth node N4 to be in a connected state under the control of the second output signal OUT2 and the second power supply voltage VGH, the fifth input signal INPUT5 can be provided to the fourth node N4 at this time to control the potential of the fourth node N4. When the fifth control unit 351 controls the fifth input terminal INPUT5 and the fourth node N4 to be in a disconnected state under the control of the second output signal OUT2 and the second power supply voltage VGH, the potential of the fourth node N4 can maintain the state of the previous stage at this time.

[0092] In an embodiment of the present disclosure, the sixth control unit 352 is electrically connected to the fourth clock terminal CLD and the second power supply VGH. Under the control of the fourth clock signal CLD, the sixth control unit 352 supplies the second power supply voltage VGH to the fourth node N4.

[0093] For example, the fourth clock signal CLD can control the connection state or disconnection state between the second power supply VGH and the fourth node N4. When the sixth control unit 352 controls the connection state between the second power supply VGH and the fourth node N4 under the control of the fourth clock signal CLD, the second power supply voltage VGH can be supplied to the fourth node N4 at this time, and the potential of the fourth node N4 is at a high level. When the sixth control unit 352 controls the disconnection state between the second power supply VGH and the fourth node N4 under the control of the fourth clock signal CLD, the potential of the fourth node N4 can maintain the state of the previous stage at this time.

[0094] The second output signal OUT2 controls the writing time of the fifth input signal INPUT5, controls the pull-down time of the fourth node N4, and thus controls the time when the third output terminal OUT3 outputs the second clock signal CLB. The second output signal OUT2 can control the time when the third output signal OUT3 switches from a high potential to a low potential.

[0095] Figure 4 The structural schematic diagram of a shift register according to another embodiment of the present disclosure is shown.

[0096] As Figure 4 shown, the shift register 400 includes a first control circuit 410, a first output circuit 420, a second control circuit 430, and a second output circuit 440. In an embodiment of the present disclosure, the first control circuit 410 includes a first control unit 411 and a second control unit 412. The first control unit 411 includes transistors T1, T6, T3, T7, and capacitor C2, and the second control unit 412 includes transistors T2, T8, T4, T5, T9, and capacitor C1.

[0097] The control electrode of transistor T1 is electrically connected to the first clock terminal CLA, the first pole of transistor T1 is electrically connected to the first input terminal INPUT1, and the second pole of transistor T1 is electrically connected to the first node N1.

[0098] The control electrode of transistor T6 is electrically connected to the first clock terminal CLA, the first pole of transistor T6 is electrically connected to the first input terminal INPUT1, and the second pole of transistor T6 is electrically connected to the sixth node N6.

[0099] The control electrode of transistor T3 is electrically connected to the sixth node N6, the first electrode of transistor T3 is electrically connected to the eleventh node N11, and the second electrode of transistor T3 is electrically connected to the second clock terminal CLB.

[0100] The control electrode of transistor T7 is electrically connected to the sixth node N6, the first electrode of transistor T7 is electrically connected to the first node N1, and the second electrode of transistor T7 is electrically connected to the sixth node N6.

[0101] The first terminal of capacitor C2 is electrically connected to the eleventh node N11, and the second terminal of capacitor C2 is electrically connected to the sixth node N6.

[0102] The control electrode of transistor T2 is electrically connected to the first clock terminal CLA, the first electrode of transistor T2 is electrically connected to the first power supply VGL, and the second electrode of transistor T2 is electrically connected to the tenth node N10.

[0103] The control electrode of transistor T8 is electrically connected to the first input terminal INPUT1, the first electrode of transistor T8 is electrically connected to the tenth node N10, and the second electrode of transistor T8 is electrically connected to the first clock terminal CLA.

[0104] The control electrode of transistor T4 is electrically connected to the tenth node N10, the first electrode of transistor T4 is electrically connected to the second clock terminal CLB, and the second electrode of transistor T4 is electrically connected to the seventh node N7.

[0105] The control electrode of transistor T5 is electrically connected to the second clock terminal CLB, the first electrode of transistor T5 is electrically connected to the seventh node N7, and the second electrode of transistor T5 is electrically connected to the second node N2.

[0106] The control electrode of transistor T9 is electrically connected to the first input terminal INPUT1, the first electrode of transistor T9 is electrically connected to the second node N2, and the second electrode of transistor T9 is electrically connected to the second power supply VGH.

[0107] The first terminal of capacitor C1 is electrically connected to the tenth node N10, and the second terminal of capacitor C1 is electrically connected to the seventh node N7.

[0108] In the embodiment of the present disclosure, the first output circuit 420 includes transistor T10, transistor T11, and capacitor C3.

[0109] The control electrode of transistor T10 is electrically connected to the second node N2, the first electrode of transistor T10 is electrically connected to the second power supply VGH, and the second electrode of transistor T10 is electrically connected to the first output terminal OUT1.

[0110] The control electrode of transistor T11 is electrically connected to the first node N1, the first electrode of transistor T11 is electrically connected to the first output terminal OUT1, and the second electrode of transistor T11 is electrically connected to the first power supply VGL.

[0111] The first terminal of capacitor C3 is electrically connected to the second node N2, and the second terminal of capacitor C3 is electrically connected to the first pole of transistor T10.

[0112] In an embodiment of the present disclosure, the second control circuit 430 includes a third control unit 431 and a fourth control unit 432. The third control unit 431 includes transistor T13 (the first transistor), transistor T14 (the second transistor), and capacitor C4 (the first capacitor), and the fourth control unit 432 includes transistor T12 (the third transistor) and transistor T18 (the fourth transistor).

[0113] The control pole of transistor T13 is electrically connected to the third clock terminal CLC, the first pole of transistor T13 is electrically connected to the second input terminal INPUT2, and the second pole of transistor T13 is electrically connected to the eighth node N8.

[0114] The first terminal of capacitor C4 is electrically connected to the eighth node N8, and the second terminal of capacitor C4 (the first capacitor) is electrically connected to the first pole of transistor T14.

[0115] The control pole of transistor T14 is electrically connected to the eighth node N8, and the second pole of transistor T14 is electrically connected to the first clock terminal CLA.

[0116] The control pole of transistor T12 is electrically connected to the eighth node N8, the first pole of transistor T12 is electrically connected to the second node N2, and the second pole of transistor T12 is electrically connected to the third node N3.

[0117] The control pole of transistor T18 is electrically connected to the first input terminal INPUT1, the first pole of transistor T18 is electrically connected to the second power supply VGH, and the second pole of transistor T18 is electrically connected to the third node N3.

[0118] In an embodiment of the present disclosure, the second output circuit 440 includes a pull - down unit 441 and an output unit 442. The pull - down unit 441 includes transistor T19 (the fifth transistor), and the output unit 442 includes transistor T15 (the sixth transistor), transistor T16 (the seventh transistor), and transistor T17 (the eighth transistor).

[0119] The control pole of transistor T19 is electrically connected to the first input terminal INPUT1, the first pole of transistor T19 is electrically connected to the fifth node N5, and the second pole of transistor T19 is electrically connected to the first power supply.

[0120] The control pole of transistor T15 is electrically connected to the third node N3, the first pole of transistor T15 is electrically connected to the second power supply VGH, and the second pole of transistor T15 is electrically connected to the fifth node N5.

[0121] The control electrode of transistor T16 is electrically connected to the fourth input terminal INPUT4, the first electrode of transistor T16 is electrically connected to the fifth node N5, and the second electrode of transistor T16 is electrically connected to the second output terminal OUT2.

[0122] The control electrode of transistor T17 is electrically connected to the third input terminal INPUT3, the first electrode of transistor T17 is electrically connected to the second output terminal OUT2, and the second electrode of transistor T17 is electrically connected to the first power supply.

[0123] In the embodiments of the present disclosure, transistors T1 to T19 are all P-type TFT transistors. For example, thin-film transistors with an active layer of low-temperature doped polysilicon (LTPS). Those skilled in the art can understand that transistors T1 to T19 in the present disclosure can also be N-type TFT transistors, such as thin-film transistors with an active layer of indium gallium zinc oxide (IGZO), and the level of the gate conduction signal of each transistor can be changed accordingly.

[0124] In addition, those skilled in the art can understand that capacitors can be respectively implemented as a single capacitor or multiple capacitive units connected in parallel or in series, as long as their corresponding functions can be achieved.

[0125] In the description of the embodiments of the present disclosure, a node does not represent an actually existing component, but represents a convergence point of relevant circuit connections in a circuit diagram.

[0126] Figure 5 Shows Figure 4 The signal timing diagram of the shift register in Figure 5 Shows that the shift register 400 outputs a first output signal OUT1 and a second output signal OUT2 for driving the pixel circuit.

[0127] Next, taking Figure 4 The structure of the shift register 400 shown as an example, combined with Figure 5 The signal timing diagram shown, the working process of the shift register provided by the embodiments of the present disclosure will be described.

[0128] Figure 5 The first clock signal CLA and the second clock signal CLB shown are not both at the effective level at the same time, and the period of the first clock signal CLA is the same as the period of the second clock signal CLB. For example, the first clock signal CLA and the second clock signal CLB can be inverted clock signals. For example, when the first clock signal CLA is at a low level, the second clock signal CLB is at a high level. When the second clock signal CLB is at a low level, the first clock signal CLA is at a high level.

[0129] In the embodiments of the present disclosure, the period of the first clock signal CLA is the sum of the duration of a high-level signal of the first clock signal CLA and the duration of a low-level signal of the first clock signal CLA. The period of the second clock signal CLB is the sum of the duration of a high-level signal of the second clock signal CLB and the duration of a low-level signal of the second clock signal CLB. For example, within one period, the first clock signal CLA has one high level and one low level.

[0130] In the embodiments of the present disclosure, the third clock signal CLC and the fourth clock signal CLD are not both at the active level at the same time, and the period of the third clock signal CLC is the same as the period of the fourth clock signal CLD. For example, when the third clock signal CLC is at a low level, the fourth clock signal CLD is at a high level. When the fourth clock signal CLD is at a low level, the third clock signal CLC is at a high level.

[0131] In the embodiments of the present disclosure, the period of the third clock signal CLC is twice the period of the first clock signal CLA. In this case, within the duration of the low level of the third clock signal CLC, the first clock signal CLA has a low level and a high level. Therefore, the first clock signal CLA and the third clock signal CLC can be both at a low level at the same time, or the first clock signal CLA can be at a certain level when CLC is at a low level. The third clock signal CLC and the first clock signal CLA can jointly control the potential of a node, or can separately control the potential of a node. For example, the low level of the third clock signal CLC and the low level of the first clock signal CLA can jointly pull down the potential of the eighth node N8, or when the low level of the third clock signal CLC controls the potential of the eighth node N8, the influence of the first clock signal CLA on the potential of the eighth node N8 can be avoided.

[0132] In the embodiments of the present disclosure, within the duration of the first level (low level) of the fourth input signal INPUT4, the level change of the second input signal INPUT2 is consistent with the level change of the first clock signal CLA. The duration of the second level (high level) of the third input signal INPUT3 is greater than the duration of the second level of the first input signal INPUT1. The duration of the first level of the fourth input signal INPUT4 is less than the duration of the second level of the first input signal INPUT1.

[0133] In an embodiment of the present disclosure, during the period when the shift register scans a row of pixel circuits in the display panel, the moment when the third input signal INPUT3 switches from the first level to the second level is earlier than the moment when the first input signal INPUT1 switches from the first level to the second level, and the moment when the third input signal INPUT3 switches from the second level to the first level is earlier than the moment when the first input signal INPUT1 switches from the second level to the first level.

[0134] In an embodiment of the present disclosure, during the period when the shift register scans a row of pixel circuits in the display panel, the moment when the third input signal INPUT3 switches from the first level to the second level is earlier than the moment when the fourth input signal INPUT4 switches from the second level to the first level, and the moment when the third input signal INPUT3 switches from the second level to the first level is later than the moment when the fourth input signal INPUT4 switches from the first level to the second level.

[0135] In an embodiment of the present disclosure, during the period when the shift register scans a row of pixel circuits in the display panel, the moment when the fourth input signal INPUT4 switches from the second level to the first level is earlier than the moment when the first input signal INPUT1 switches from the first level to the second level, and the moment when the fourth input signal INPUT4 switches from the first level to the second level is earlier than the moment when the first input signal INPUT1 switches from the second level to the first level.

[0136] In an embodiment of the present disclosure, the duration of the second level of the third input signal INPUT3 is the same as the duration of the second level (high level) of the first node N1. The duration of the first level of the fourth input signal INPUT4 is the same as the duration of the second level of the second node N2.

[0137] As Figure 5 shown, the process of the shift register 400 outputting the first output signal OUT1 and the second output signal OUT2 may include stages 1 to 16.

[0138] The following analyzes the change process of the output level of the first output signal OUT1. In stage 4, the first input signal INPUT1 is at a low level, the first clock signal CLA is at a low level, and the second clock signal CLB is at a high level. The transistor T1 and the transistor T6 are turned on. The first input signal INPUT1 is written to the first node N1 through the transistor T1, and the potential of the first node N1 is at a low level. The first input signal INPUT1 is written to the sixth node N6 through the transistor T6, and the potential of the sixth node N6 is at a low level. The transistor T11 and the transistor T7 are turned on. The first power supply voltage VGL is written to the first output terminal OUT1 through the transistor T11. The transistor T3 is turned on, and the second clock signal CLB is written to the first end of the capacitor C2 through the transistor T3. The transistor T2 and the transistor T8 are turned on. The first power supply voltage VGL is written to the tenth node N10 through the transistor T2, and the potential of the tenth node N10 is at a low level. The capacitor C1 stores the first power supply voltage VGL. The transistor T4 is turned on, and the second clock signal CLB is written to the seventh node N7 through the transistor T4. The potential of the seventh node N7 is at a high level, and the transistor T5 is turned off. The transistor T9 is turned on, and the second power supply voltage VGH is written to the second node N2 through the transistor T9. The potential of the second node N2 is at a high level, and the transistor T10 is turned off. At this time, the first output signal OUT1 outputs a low-level signal.

[0139] In stage 5, the first input signal INPUT1 is at a low level, the first clock signal CLA is at a high level, and the second clock signal CLB is at a low level. The transistor T8 is turned on, and the first clock signal CLA is written to the tenth node N10 through the transistor T8. The potential of the tenth node N10 is pulled up, and the transistor T4 is turned off. The transistor T9 is turned on, and the second power supply voltage VGH is written to the second node N2 through the transistor T9. The potential of the second node N2 is at a high level, and the transistor T10 is turned off. The transistor T1 and the transistor T6 are turned off. The second clock signal CLB switches from the high level in stage 4 to the low level in stage 5, and the potential of the first end of the capacitor C2 decreases. Due to the bootstrap effect of the capacitor C2, the potential of the second end of the capacitor C2 decreases, and the potential of the sixth node N6 is further pulled down. The transistor T7 is turned on. The potential of the first node N1 is pulled down through the transistor T7, the transistor T11 is turned on, and the first power supply voltage VGL is written to the first output terminal OUT1. At this time, the first output signal OUT1 maintains a low-level output.

[0140] The working process of the shift register 400 in stages 1, 2, and 3 is similar to the working process of the shift register 400 in stages 4 to 5, and will not be elaborated here.

[0141] In stage 6, the first input signal INPUT1 is at a high level, the first clock signal CLA is at a low level, and the second clock signal CLB is at a high level. Transistors T1 and T6 are turned on. The first input signal INPUT1 is written to the first node N1 through transistor T1, and the potential of the first node N1 is at a high level. The first input signal INPUT1 is written to the sixth node N6 through transistor T6, and the potential of the sixth node N6 is at a high level. Transistors T3, T11, and T7 are turned off. Transistor T2 is turned on. The first power supply voltage VGL is written to the tenth node N10 through transistor T2, and the potential of the tenth node N10 is at a low level. The first end of the capacitor C1 is written with a low potential. Transistor T4 is turned on. The second clock signal CLB is written to the seventh node N7 through transistor T4, and the potential of the seventh node N7 is at a high level. Transistor T5 is turned off. Transistors T8 and T9 are turned off. The second node N2 is maintained at the high potential in stage 5, and transistor T10 is turned off. At this time, the first output signal OUT1 maintains a low-level output.

[0142] In stage 7, the first input signal INPUT1 is at a high level, the first clock signal CLA is at a high level, and the second clock signal CLB is at a low level. Transistors T1, T6, T8, T9, and T2 are turned off. The second clock signal CLB switches from the high level in stage 5 to the low level in stage 6, and the capacitor C1 maintains the low level of the tenth node N10. Transistor T4 is turned on. The second clock signal CLB is written to the seventh node N7 through transistor T4, and the potential of the seventh node N7 is at a low level. Transistor T5 is turned on. The low-level signal of the seventh node N7 is written to the second node N2 through transistor T5, and the potential of the second node N2 is at a low level. Transistor T10 is turned on. The second power supply voltage VGH is written to the first output terminal OUT1 through transistor T10. At this time, the first output signal OUT1 outputs a high-level signal.

[0143] In stage 8, the first input signal INPUT1 is at a high level, the first clock signal CLA is at a low level, and the second clock signal CLB is at a high level. The transistor T1 and the transistor T6 are turned on. The first input signal INPUT1 is written to the first node N1 through the transistor T1, and the potential of the first node N1 is at a high level. The first input signal INPUT1 is written to the sixth node N6 through the transistor T6, and the potential of the sixth node N6 is at a high level. The transistors T3, T7, and T11 are turned off. The transistor T2 is turned on, and the first power supply voltage VGL is written to the tenth node N10 through the transistor T2, and the potential of the tenth node N10 is at a low level. The transistor T4 is turned on, and the second clock signal CLB is written to the seventh node N7 through the transistor T4, and the potential of the seventh node N7 is at a high level. The transistor T5 is turned off, and the second node N2 remains at the low potential in stage 7. The transistor T10 is turned on, and the second power supply voltage VGH is written to the first output terminal OUT1 through the transistor T10. At this time, the first output signal OUT1 outputs a high-level signal.

[0144] The operation process of the shift register 400 in stage 9 is similar to that of the shift register 400 in stage 7. The operation processes of the shift register 400 in stages 10 and 11 are similar to those of the shift register 400 in stages 8 to 9. The operation process of the shift register 400 in stage 12 is similar to that of the shift register 400 in stage 8, and will not be elaborated here.

[0145] In stage 13, the first input signal INPUT1 is at a low level, the first clock signal CLA is at a high level, and the second clock signal CLB is at a low level. The transistors T1, T6, and T2 are turned off. The potentials of the first node N1 and the sixth node N6 are maintained at the high levels in stage 12, and the transistor T11 is turned off. The transistors T8 and T9 are turned on, and the first clock signal CLA is written to the tenth node N10 through the transistor T8, and the potential of the tenth node N10 is at a high level. The transistor T4 is turned off. The second power supply voltage VGH is written to the second node N2 through the transistor T9, and the potential of the second node N2 is at a high level. The transistor T10 is turned off. At this time, the first output signal OUT1 is maintained at the high-level output in stage 12.

[0146] In stage 14, the first input signal INPUT1 is at a low level, the first clock signal CLA is at a low level, and the second clock signal CLB is at a high level. The transistor T1 and the transistor T6 are turned on. The first input signal INPUT1 is written to the first node N1 through the transistor T1, and the potential of the first node N1 switches from a high potential to a low potential. The first input signal INPUT1 is written to the sixth node N6 through the transistor T6, and the potential of the sixth node N6 switches from a high potential to a low potential. The transistor T11 is turned on, and the first power supply voltage VGL is written to the first output terminal OUT1 through the transistor T11, and the first output signal OUT1 outputs a low-level signal. The transistors T2, T8, and T9 are turned on, and the first power supply voltage VGL is written to the tenth node N10 through the transistor T2, and the potential of the tenth node N10 is at a low level. The transistor T4 is turned on, and the second clock signal CLB is written to the seventh node N7 through the transistor T4, and the potential of the seventh node N7 is at a high level, and the transistor T5 is turned off. The second power supply voltage VGH is written to the second node N2 through the transistor T9, and the potential of the second node N2 is at a high level, and the transistor T10 is turned off. At this time, the first output signal OUT1 outputs a low-level signal.

[0147] The operation process of the shift register 400 in stage 15 is similar to the operation process of the shift register 400 in stage 5 in the previous text. The operation process of the shift register 400 in stage 16 is similar to the operation process of the shift register 400 in stages 4 to 5, which will not be elaborated here.

[0148] Next, the change process of the output level of the first output signal OUT2 will be analyzed.

[0149] In stage 1, the first input signal INPUT1 is at a low level, the third input signal INPUT3 is at a low level, the fourth input signal INPUT4 is at a high level, and the third clock signal CLC is at a high level. The transistor T13 is turned off, and the high level stored in the capacitor C4 keeps the potential of the eighth node N8 at a high level. The transistors T12 and T14 are turned off. The transistor T18 is turned on, and the second power supply voltage VGH is written to the third node N3 through the transistor T18, and the potential of the third node N3 is at a high level. The transistor T15 is turned off. The transistor T19 is turned on, and the first power supply voltage VGL is written to the fifth node N5 through the transistor T19, and the potential of the fifth node N5 is at a low level. The transistor T16 is turned off, the transistor T17 is turned on, and the first power supply voltage VGL is written to the second output terminal OUT2. At this time, the second output signal OUT2 outputs a low-level signal.

[0150] In stage 2, the first input signal INPUT1 is at a low level, the second input signal INPUT2 is at a high level, the third input signal INPUT3 is at a low level, the fourth input signal INPUT4 is at a high level, and the third clock signal CLC is at a low level. Transistor T13 is turned on, and the second input signal INPUT2 is written to the eighth node N8 through transistor T13, and the potential of the eighth node N8 is at a high level. Transistor C4 stores a high level, and transistors T12 and T14 are turned off. Transistor T18 is turned on, and the second power supply voltage VGH is written to the third node N3 through transistor T18, and the potential of the third node N3 is at a high level, and transistor T15 is turned off. Transistor T19 is turned on, and the first power supply voltage VGL is written to the fifth node N5 through transistor T19, and the potential of the fifth node N5 is at a low level. Transistor T16 is turned off, transistor T17 is turned on, and the first power supply voltage VGL is written to the second output terminal OUT2 through transistor T17. At this time, the second output signal OUT2 maintains a low-level output.

[0151] In stage 3, the first input signal INPUT1 is at a low level, the third input signal INPUT3 is at a high level, the potential of the fourth input signal INPUT4 is at a high level, and the third clock signal CLC is at a high level. Transistor T13 is turned off, and the potential of the eighth node N8 remains at the high level in stage 2, and transistors T12 and T14 are turned off. Transistor T18 is turned on, and the second power supply voltage VGH is written to the third node N3 through transistor T18, and the potential of the third node N3 is at a high level, and transistor T15 is turned off. Transistor T19 is turned on, and the first power supply voltage VGL is written to the fifth node N5 through transistor T19, and the potential of the fifth node N5 is at a low level. Transistor T17 is turned off. Transistor T16 is turned off. At this time, the second output signal OUT2 maintains the low-level output in stage 2. The potential of the fourth input signal INPUT4 switches from a high level to a low level, transistor T16 is turned on, and the potential of the fifth node N5 is written to the second output terminal OUT2 through transistor T16. At this time, the second output signal OUT2 outputs a low level.

[0152] In stage 4, the first input signal INPUT1 is at a low level, the second input signal INPUT2 is at a low level, the third input signal INPUT3 is at a high level, the fourth input signal INPUT4 is at a low level, and the third clock signal CLC is at a low level. Transistor T13 is turned on, and the second input signal INPUT2 is written to the eighth node N8 through transistor T13, and the potential of the eighth node N8 is at a low level. Transistors T12 and T18 are turned on, and the second power supply voltage VGH is written to the third node N3 through transistor T18, and the potential of the third node N3 is at a high level. Transistor T15 is turned off, transistor T19 is turned on, and the first power supply voltage VGL is written to the fifth node N5 through transistor T19, and the potential of the fifth node N5 is at a low level. Transistor T17 is turned off, transistor T16 is turned on, and the potential of the fifth node N5 is written to the second output terminal OUT2 through transistor T16. At this time, the second output signal OUT2 maintains a low-level output.

[0153] In stage 5, the first input signal INPUT1 is at a low level, the second input signal INPUT2 is at a high level, the third input signal INPUT3 is at a high level, the fourth input signal INPUT4 is at a low level, and the third clock signal CLC is at a low level. Transistor T13 is turned on, and the second input signal INPUT2 is written to the eighth node N8 through transistor T13, and the potential of the eighth node N8 is at a high level, and transistor T12 is turned off. Transistor T18 is turned on, and the second power supply voltage VGH is written to the third node N3 through transistor T18, and the potential of the third node N3 is at a high level. Transistor T19 is turned on, and the first power supply voltage VGL is written to the fifth node N5 through transistor T19, and the potential of the fifth node N5 is at a low level. Transistor T17 is turned off, transistor T16 is turned on, and the potential of the fifth node N5 is written to the second output terminal OUT2 through transistor T16. At this time, the second output signal OUT2 maintains a low-level output.

[0154] In stages 6 to 7, the first input signal INPUT1 is at a high level, the third input signal INPUT3 is at a high level, the fourth input signal INPUT4 is at a low level, and the third clock signal CLC is at a high level. Transistor T13 is turned off, and the potential of the eighth node N8 remains at the high level in stage 5, and transistor T12 is turned off. Transistors T18, T19, and T17 are turned off, and transistor T16 is turned on. The potential of the third node N3 remains at the high level in stage 5, and transistor T15 is turned off. The potential of the fifth node N5 remains at the low level in stage 5, and the potential of the fifth node N5 is written to the second output terminal OUT2 through transistor T16. At this time, the second output signal OUT2 maintains a low-level output.

[0155] In stage 8 to stage 9, the first input signal INPUT1 is at a high level, the second input signal INPUT2 is at a low level, the third input signal INPUT3 is at a high level, the fourth input signal INPUT4 is at a low level, and the third clock signal CLC is at a low level. Transistor T13 is turned on, and the second input signal INPUT2 is written to the eighth node N8 through transistor T13. The potential of the eighth node N8 is at a low level. Transistor T12 is turned on, and the low-level signal of the second node N2 is written to the third node N3 through transistor T12. Transistor T15 is turned on. The second power supply voltage VGH is written to the fifth node N5 through transistor T15, and the potential of the fifth node N5 is at a high level. Transistors T19 and T17 are turned off, and transistor T16 is turned on. The potential of the fifth node N5 is written to the second output terminal OUT2 through transistor T16, and the second output terminal OUT2 outputs a high level. The second input signal INPUT2 switches from a low level to a high level, the potential of the eighth node N8 is pulled up, and transistor T12 is turned off. The third node N3 maintains a low potential, transistor T15 is turned on, and at this time, the second output terminal OUT2 maintains a high-level output.

[0156] In stage 10, the first input signal INPUT1 is at a high level, the third input signal INPUT3 is at a high level, the fourth input signal INPUT4 is at a low level, and the third clock signal CLC is at a high level. Transistor T13 is turned off, and the potential of the eighth node N8 is maintained at a high level. Transistor T12 is turned off. The potential of the third node N3 maintains the low level of the previous stage. Transistor T15 is turned on, and the second power supply voltage VGH is written to the fifth node N5 through transistor T15. The potential of the fifth node N5 is at a high level. Transistor T17 is turned off. Transistor T16 is turned on, and the high level of the fifth node N5 is written to the second output terminal OUT2 through transistor T16. The second output terminal OUT2 outputs a high level. The fourth input signal INPUT4 switches from a low level to a high level, transistor T16 is turned off, and the second output terminal OUT2 maintains a high-level output.

[0157] In stage 11, the first input signal INPUT1 is at a high level, the second input signal INPUT2 is at a high level, the third input signal INPUT3 is at a low level, the fourth input signal INPUT4 is at a high level, and the third clock signal CLC is at a low level. Transistor T13 is turned on, and the second input signal INPUT2 is written to the eighth node N8 through transistor T13. The potential of the eighth node N8 is at a high level, and transistor T12 is turned off. The potential of the third node N3 maintains the low level of the previous stage, and transistor T15 is turned on. The second power supply voltage VGH is written to the fifth node N5 through transistor T15. The potential of the fifth node N5 is at a high level. Transistors T16 and T19 are turned off, and transistor T17 is turned on. The first power supply voltage VGL is written to the second output terminal OUT2 through transistor T17, and the second output terminal OUT2 outputs a low level.

[0158] In stages 12 to 13, the third input signal INPUT3 is at a low level, the fourth input signal INPUT4 is at a high level, and the third clock signal CLC is at a high level. Transistor T16 is turned off, and transistor T17 is turned on. The first power supply voltage VGL is written to the second output terminal OUT2 through transistor T17, and the second output terminal OUT2 maintains a low level output.

[0159] In stages 14 to 15, the first input signal INPUT1 is at a low level, the second input signal INPUT2 is at a high level, the third input signal INPUT3 is at a low level, the fourth input signal INPUT4 is at a high level, and the third clock signal CLC is at a low level. Transistor T13 is turned on, and the second input signal INPUT2 is written to the eighth node N8 through transistor T13. The potential of the eighth node N8 is at a high level, and transistor T12 is turned off. Transistor T18 is turned on, and the second power supply voltage VGH is written to the third node N3 through transistor T18. The potential of the third node N3 is at a high level, and transistor T15 is turned off. Transistor T19 is turned on, and the first power supply voltage VGL is written to the fifth node N5 through transistor T19. The potential of the fifth node N5 is at a low level. Transistors T16 is turned off, and transistor T17 is turned on. The first power supply voltage VGL is written to the second output terminal OUT2 through transistor T17, and the second output terminal OUT2 maintains a low level output.

[0160] In stage 16, the first input signal INPUT1 is at a low level, the second input signal INPUT2 is at a high level, the third input signal INPUT3 is at a low level, the fourth input signal INPUT4 is at a high level, and the third clock signal CLC is at a high level. Transistor T18 is turned on, and the second power supply voltage VGH is written to the third node N3 through transistor T18, and the potential of the third node N3 is at a high level. Transistor T19 is turned on, and the first power supply voltage VGL is written to the fifth node N5 through transistor T19, and the potential of the fifth node N5 is at a low level. Transistor T16 is turned off, and transistor T17 is turned on. The first power supply voltage VGL is written to the second output terminal OUT2 through transistor T17, and the second output terminal OUT2 maintains a low-level output.

[0161] Figure 6 FIG. shows a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0162] As Figure 6 shown, the shift register 600 includes a first control circuit 610, a first output circuit 620, a second control circuit 630, a second output circuit 640, a third control circuit 650, and a third output circuit 660.

[0163] In the embodiments of the present disclosure, the first control circuit 610, the first output circuit 620, the second control circuit 630, and the second output circuit 640 may refer to Figure 4 the relevant descriptions of the first control circuit 410, the first output circuit 420, the second control circuit 430, and the second output circuit 440 in

[0164] In the embodiments of the present disclosure, the third control circuit 650 includes a fifth control unit 651 and a sixth control unit 652. The fifth control unit 651 includes a transistor T20 (ninth transistor), a transistor T21 (tenth transistor), and a capacitor C5 (second capacitor), and the sixth control unit 652 includes a transistor T22 (eleventh transistor).

[0165] The control electrode of transistor T20 is electrically connected to the ninth node N9, the first electrode of transistor T20 is electrically connected to the fifth input terminal INPUT5, and the second electrode of transistor T20 is electrically connected to the fourth node N4.

[0166] The control electrode of transistor T21 is electrically connected to the second output terminal OUT2, the first electrode of transistor T21 is electrically connected to the ninth node N9, and the second electrode of transistor T21 is electrically connected to the second power supply VGH.

[0167] The first end of capacitor C5 is electrically connected to the fifth input terminal INPUT5, and the second end of capacitor C5 is electrically connected to the ninth node N9.

[0168] The control electrode of transistor T22 is electrically connected to the fourth clock terminal CLD, the first electrode of transistor T22 is electrically connected to the fourth node N4, and the second electrode of transistor T22 is electrically connected to the second power supply VGH.

[0169] In the embodiment of the present disclosure, the third output circuit 660 includes a transistor T23, a transistor T24, and a capacitor C6.

[0170] The control electrode of transistor T23 is electrically connected to the fourth node N4, the first electrode of transistor T23 is electrically connected to the second clock terminal CLB, and the second electrode of transistor T23 is electrically connected to the third output terminal OUT3.

[0171] The control electrode of transistor T24 is electrically connected to the second output terminal OUT2, the first electrode of transistor T24 is electrically connected to the third output terminal OUT3, and the second electrode of transistor T24 is electrically connected to the second power supply VGH.

[0172] The first end of capacitor C6 is electrically connected to the fourth node N4, and the second end of capacitor C6 is electrically connected to the third output terminal OUT3.

[0173] In the embodiment of the present disclosure, transistors T1 to T24 are all P-type TFT transistors. For example, thin-film transistors with an active layer of low-temperature doped polysilicon (LTPS). Those skilled in the art can understand that transistors T1 to T24 in the present disclosure can also be N-type TFT transistors, such as thin-film transistors with an active layer of indium gallium zinc oxide (IGZO), and the level of the gate conduction signal of each transistor can be changed accordingly.

[0174] Figure 7 shows Figure 6 the signal timing diagram of the shift register in Figure 7 shows that the shift register 600 outputs a first output signal OUT1, a second output signal OUT2, and a third output signal OUT3 for driving the pixel circuit.

[0175] In the embodiment of the present disclosure, the timing changes of the first input signal INPUT1 to the fourth input signal INPUT4 can be referred to Figure 5 , and similar parts will not be described in detail.

[0176] During the duration of the first level (low level) of the fourth input signal INPUT4, the level change of the fifth input signal INPUT5 is consistent with the level change of the second clock signal CLB. Therefore, during the low-level duration of the fourth input signal INPUT4, the fifth input signal INPUT5 is inverted with respect to the second input signal INPUT2.

[0177] Next, taking Figure 6Taking the structure of the shift register 400 shown as an example, the working process of the shift register provided by the embodiments of the present disclosure will be described in combination with Figure 7 the signal timing diagram shown.

[0178] As Figure 7 shown, the process of the shift register 600 outputting the first output signal OUT1, the second output signal OUT2, and the third output signal OUT3 may include stages 1 to 16.

[0179] In the embodiments of the present disclosure, the change process of the output levels of the first output signal OUT1 and the second output signal OUT2 may refer to Figure 5 the relevant description, which will not be elaborated here.

[0180] Next, the change process of the output level of the third output signal OUT3 will be analyzed.

[0181] In stage 3, the first input signal INPUT1 is at a low level, the fourth clock signal CLD is at a low level, and the second output signal OUT2 is at a low level. The transistor T21 is turned on, and the second power supply voltage VGH is written to the ninth node N9 through the transistor T21. The potential of the ninth node N9 is at a high level, and the transistor T20 is turned off. The transistor T22 is turned on, and the second power supply voltage VGH is written to the fourth node N4 through the transistor T22. The potential of the fourth node N4 is at a high level, and the transistor T23 is turned off. The transistor T24 is turned on, and the second power supply voltage VGH is written to the third output terminal OUT3. At this time, the third output signal OUT3 outputs a high level.

[0182] In stages 4 to 5, the first input signal INPUT1 is at a low level, the fourth clock signal CLD is at a high level, and the second output signal OUT2 is at a low level. The transistor T21 is turned on, and the second power supply voltage VGH is written to the ninth node N9 through the transistor T21. The potential of the ninth node N9 is at a high level, and the transistor T20 is turned off. The transistor T22 is turned off, and the fourth node N4 maintains the high level of the previous stage, and the transistor T23 is turned off. The transistor T24 is turned on, and the second power supply voltage VGH is written to the third output terminal OUT3. At this time, the third output signal OUT3 maintains a high level output.

[0183] In stage 6 to stage 7, the first input signal INPUT1 is at a high level, the fourth clock signal CLD is at a low level, and the second output signal OUT2 is at a low level. The transistor T21 is turned on, and the second power supply voltage VGH is written to the ninth node N9 through the transistor T21. The potential of the ninth node N9 is at a high level, and the transistor T20 is turned off. The transistor T22 is turned on, and the second power supply voltage VGH is written to the fourth node N4 through the transistor T22. The potential of the fourth node N4 is at a high level, and the transistor T23 is turned off. The transistor T24 is turned on, and the second power supply voltage VGH is written to the third output terminal OUT3. At this time, the third output signal OUT3 maintains a high-level output.

[0184] In stage 8, the first input signal INPUT1 is at a high level, the fifth input signal INPUT5 is at a high level, the fourth clock signal CLD is at a high level, and the second output signal OUT2 is at a high level. The transistor T21 is turned off, and the potential of the ninth node N9 is maintained at a high level, and the transistor T20 is turned off. The transistor T22 is turned off, and the potential of the fourth node N4 is maintained at a high level, and the transistor T23 is turned off. The transistor T24 is turned off. At this time, the third output signal OUT3 maintains a high-level output.

[0185] In stage 9, the fourth clock signal CLD is at a high level, the fifth input signal INPUT5 changes from a high level to a low level, and the transistor T21 remains turned off. At this time, under the bootstrap action of the capacitor C5, the potential of the ninth node N9 is pulled down. The transistor T22 is turned off, the transistor T20 is turned on, and the fifth input signal INPUT5 is written to the fourth node N4 through the transistor T20. The potential of the fourth node N4 is at a low level, the transistor T23 is turned on, and the transistor T24 is turned off. The low level of the second clock signal CLB is written to the third output terminal OUT3 through the transistor T23. At this time, the potential of the second clock signal CLB has a process of changing from a low potential to a high potential. Therefore, the potential of the third output signal OUT3 changes from a low potential to a high potential.

[0186] In stage 10, the first input signal INPUT1 is at a high level, the fourth clock signal CLD is at a low level, the second output signal OUT2 is at a high level, and the transistors T21 and T24 are turned off. The potential of the ninth node N9 is maintained at a high level, and the transistor T20 is turned off. The transistor T22 is turned on, and the second power supply voltage VGH is written to the fourth node N4 through the transistor T22. The potential of the fourth node N4 is at a high level, and the transistor T23 is turned off. At this time, the third output signal OUT3 maintains a high-level output.

[0187] In stage 11, the first input signal INPUT1 is at a high level, the fourth clock signal CLD is at a high level, the second output signal OUT2 is at a low level, and transistors T21 and T24 are turned on. The second power supply voltage VGH is written to the ninth node N9 through transistor T21, the potential of the ninth node N9 is at a high level, and transistor T20 is turned off. Transistor T22 is turned off, the potential of the fourth node N4 is maintained at a high level, and transistor T23 is turned off. The second power supply voltage VGH is written to the third output terminal OUT3 through transistor T24, and at this time, the third output signal OUT3 maintains a high-level output.

[0188] In stages 12 to 13, the first input signal INPUT1 switches from a high level to a low level, the fourth clock signal CLD is at a low level, the second output signal OUT2 is at a low level, and transistors T21 and T24 are turned on. The second power supply voltage VGH is written to the ninth node N9 through transistor T21, the potential of the ninth node N9 is at a high level, and transistor T20 is turned off. Transistor T22 is turned on, the second power supply voltage VGH is written to the fourth node N4 through transistor T22, the potential of the fourth node N4 is at a high level, and transistor T23 is turned off. The second power supply voltage VGH is written to the third output terminal OUT3 through transistor T24, and at this time, the third output signal OUT3 maintains a high-level output.

[0189] In stages 14 to 15, the first input signal INPUT1 is at a low level, the fourth clock signal CLD is at a high level, and the second output signal OUT2 is at a low level. Transistor T21 is turned on, the second power supply voltage VGH is written to the ninth node N9 through transistor T21, the potential of the ninth node N9 is at a high level, and transistor T20 is turned off. Transistor T22 is turned off, the fourth node N4 maintains the high level of the previous stage, and transistor T23 is turned off. Transistor T24 is turned on, the second power supply voltage VGH is written to the third output terminal OUT3 through transistor T24, and at this time, the third output signal OUT3 maintains a high-level output.

[0190] In stage 16, the first input signal INPUT1 is at a low level, the fourth clock signal CLD is at a low level, and the second output signal OUT2 is at a low level. Transistor T21 is turned on, the second power supply voltage VGH is written to the ninth node N9 through transistor T21, the potential of the ninth node N9 is at a high level, and transistor T20 is turned off. Transistor T22 is turned on, the second power supply voltage VGH is written to the fourth node N4 through transistor T22, the potential of the fourth node N4 is at a high level, and transistor T23 is turned off. Transistor T24 is turned on, the second power supply voltage VGH is written to the third output terminal OUT3. At this time, the third output signal OUT3 outputs a high level.

[0191] Figure 8The structural schematic diagram of a driving circuit according to an embodiment of the present disclosure is shown.

[0192] As Figure 8 shown, the driving circuit 800 includes M cascaded shift registers, where M is a positive integer greater than 1. The M shift registers include the first-stage shift register GOA(1), …, the m-th stage shift register GOA(m), …, the M-th stage shift register GOA(M).

[0193] In the embodiment of the present disclosure, the shift register GOA(1) can be any one of the shift registers 100, 200, 300, 400, and 600 described above. For example, all M shift registers are shift register 200. For example, all M shift registers are shift register 600. Details are not described herein again.

[0194] In the embodiment of the present disclosure, among the M cascaded shift registers, the input signal INPUT1 of the input terminal INPUT1 of the first-stage shift register GOA(1) is a start signal STV, such as a vertical start signal (StartVertical, STV).

[0195] In the embodiment of the present disclosure, the first input terminal INPUT1 of the m-th stage shift register is electrically connected to the first output terminal OUT1 of the (m - a)-th stage shift register, where 1 ≤ a < m ≤ M, and a and m are integers. For example, a = 1, OUT(1) of the first-stage shift register GOA(1) is electrically connected to INPUT(1) of the second-stage shift register GOA(2), and OUT(2) of the second-stage shift register GOA(2) is electrically connected to INPUT(3) of the third-stage shift register GOA(3). For example, a = 2, OUT(1) of the first-stage shift register GOA(1) is electrically connected to INPUT(3) of the third-stage shift register GOA(3), and OUT(2) of the second-stage shift register GOA(2) is electrically connected to INPUT(4) of the fourth-stage shift register GOA(4).

[0196] Figure 9 The structural schematic diagram of a driving circuit according to another embodiment of the present disclosure is shown.

[0197] In the embodiment of the present disclosure, the driving circuit 900 includes M cascaded shift registers. The cascading relationship between the M shift registers included in the driving circuit 900 can refer to the cascading relationship between the M shift registers included in the driving circuit 800, and similar parts are not described herein again.

[0198] In the embodiment of the present disclosure, the second input terminal INPUT2 of the m-th stage shift register is electrically connected to the seventh node N7 of the (m - b)-th stage shift register, the third input terminal INPUT3 of the m-th stage shift register is electrically connected to the first node N1 of the (m - b - 1)-th stage shift register, and the fourth input terminal INPUT4 of the m-th stage shift register is electrically connected to the second node N2 of the (m - b - 1)-th stage shift register, where 1 ≤ b < m ≤ M, and y and m are integers.

[0199] As can be seen from the above content, the potential of the first node N1 can be stabilized at a low potential. Since the third input terminal INPUT3 of the m-th stage shift register is electrically connected to the first node N1 of the (m - b - 1)-th stage shift register, the potential of the third input terminal INPUT3 can be stabilized at a low potential. Since the level switching moment of the third input signal INPUT3 can affect the moment when the first power supply voltage VGL and the second output terminal OUT2 are connected and disconnected, thereby affecting the moment when the second output terminal OUT2 outputs a low-level signal, the third input signal INPUT3 stabilized at a low potential can ensure that the second output terminal OUT2 outputs the second output signal OUT2 without an output step. As Figure 9 shown, the cascading relationship of the driving circuit 900 is schematically illustrated with b = 3. For example, the second input terminal INPUT2 of the fifth-stage shift register GOA(5) is electrically connected to the seventh node N7 of the second-stage shift register GOA(2), the third input terminal INPUT3 of the fifth-stage shift register GOA(5) is electrically connected to the first node N1 of the first-stage shift register GOA(1), and the fourth input terminal INPUT4 of the fifth-stage shift register GOA(5) is electrically connected to the second node N2 of the first-stage shift register GOA(1).

[0200] In the embodiment of the present disclosure, the driving circuit 900 may further include a dummy shift register. The dummy shift register is used to connect to the second input terminal INPUT2, the third input terminal INPUT3, and the fourth input terminal INPUT4 of the first-stage shift register GOA(1) to the fourth-stage shift register GOA(4) to meet the required second input signal INPUT2, third input signal INPUT3, and fourth input signal INPUT4 of the first-stage shift register GOA(1) to the fourth-stage shift register GOA(4). The number of preposed Dummies can be determined according to the number of stages of the shift register cascaded with the second input terminal INPUT2, the third input terminal INPUT3, and the fourth input terminal INPUT4 of the m-th stage shift register.

[0201] In the embodiments of the present disclosure, by controlling the number of cascaded shift registers connected to the second input terminal INPUT2, the third input terminal INPUT3, and the fourth input terminal INPUT4 of the m-th stage shift register, the phase difference between the second output signal OUT2 and the first output signal OUT1 can be controlled.

[0202] For example, by controlling the number of stages of the (m - b)-th stage shift register, the moment of level switching of the second input signal INPUT2 received by the m-th stage shift register can be controlled, thereby controlling the duration of the valid level in the second output signal OUT2 and the phase difference from the first output signal OUT1.

[0203] By controlling the number of stages of the (m - b - 1)-th stage shift register, the moment of level switching of the third input signal INPUT3 received by the m-th stage shift register can be controlled, thereby controlling the duration of the valid level in the second output signal OUT2 and the phase difference from the first output signal OUT1.

[0204] By controlling the number of stages of the (m - b - 1)-th stage shift register, the moment of level switching of the fourth input signal INPUT4 received by the m-th stage shift register can also be controlled, thereby controlling the duration of the valid level in the second output signal OUT2 and the phase difference from the first output signal OUT1.

[0205] In the embodiments of the present disclosure, the fewer the number of stages that the (m - b)-th stage shift register advances relative to the m-th stage shift register, the greater the phase difference between the second output signal OUT2 and the first output signal OUT1, and the wider the output level of the second output signal OUT2.

[0206] In the embodiments of the present disclosure, the driving circuit 900 further includes a first clock signal line cla, a second clock signal line clb, a third clock signal line clc, and a fourth clock signal line cld.

[0207] In the embodiments of the present disclosure, the connection relationship between the m-th stage shift register GOA(m) and the first clock signal line cla, the second clock signal line clb, the third clock signal line clc, and the fourth clock signal line cld is the same as the connection relationship between the (m + 4)-th stage shift register GOA(m + 4) and the first clock signal line cla, the second clock signal line clb, the third clock signal line clc, and the fourth clock signal line cld, where m is an integer greater than or equal to 1.

[0208] For example, the clock terminal CLA of the first-stage shift register GOA(1) is electrically connected to the first clock signal line cla, the clock terminal CLB of the first-stage shift register GOA(1) is electrically connected to the second clock signal line clb, and the clock terminal CLC of the first-stage shift register GOA(1) is electrically connected to the third clock signal line clc.

[0209] For example, the clock terminal CLA of the second-stage shift register GOA(2) is electrically connected to the second clock signal line clb, the clock terminal CLB of the second-stage shift register GOA(2) is electrically connected to the first clock signal line cla, and the clock terminal CLC of the second-stage shift register GOA(2) is electrically connected to the third clock signal line clc.

[0210] For example, the clock terminal CLA of the third-stage shift register GOA(3) is electrically connected to the first clock signal line cla, the clock terminal CLB of the third-stage shift register GOA(3) is electrically connected to the second clock signal line clb, and the clock terminal CLC of the third-stage shift register GOA(3) is electrically connected to the fourth clock signal line cld.

[0211] For example, the clock terminal CLA of the fourth-stage shift register GOA(4) is electrically connected to the first clock signal line cla, the clock terminal CLB of the fourth-stage shift register GOA(4) is electrically connected to the second clock signal line clb, and the clock terminal CLC of the fourth-stage shift register GOA(4) is electrically connected to the fourth clock signal line cld.

[0212] For example, the connection relationship between the first-stage shift register GOA(1) and the first clock signal line cla, the second clock signal line clb, the third clock signal line clc, and the fourth clock signal line cld is the same as the connection relationship between the fifth-stage shift register GOA(5) and the first clock signal line cla, the second clock signal line clb, the third clock signal line clc, and the fourth clock signal line cld. Figure 10 shows Figure 9 the signal timing diagram of the driving circuit in

[0213] In the embodiment of the present disclosure, by sharing the first clock signal line cla, the second clock signal line clb, the third clock signal line clc, and the fourth clock signal line cld, two different output signals can be output, reducing the number of clock signal lines. By controlling the timing changes of the first input signal INPUT1 to the fourth input signal INPUT4, the driving circuit 500 can output output signals with different level widths. In addition, by setting a pseudo shift register, each stage of the shift register can be provided with the first input signal INPUT1 to the fourth input signal INPUT4 by the previous-stage shift register, realizing the internal multiplexing of the first input signal INPUT1 to the fourth input signal INPUT4, thereby reducing the connection traces between the driving circuit 900 and the external signal source. The driving circuit 900 only needs the start signal line STV, the first clock signal line cla, the second clock signal line clb, the third clock signal line clc, and the fourth clock signal line cld to output two output signals with different level widths, namely the first output signal OUT1 and the second output signal OUT2.

[0214] Figure 10 shows Figure 9 the signal timing diagram of the driving circuit in Figure 10 shows that under the action of the start signal STV, the first clock signal cla, the second clock signal clb, the third clock signal clc, and the fourth clock signal cld as shown in Figure 10 the first output signal OUT1 output from the first output terminal OUT1 of the first-stage shift register GOA(1) to the eighth-stage shift register GOA(8) and the second output signal OUT2 output from the second output terminal OUT2. The eight-stage first output signal OUT1 is sequentially shifted and output, and the eight-stage second output signal OUT2 is sequentially shifted and output.

[0215] In the embodiment of the present disclosure, Figure 10 the shown start signal STV is consistent with Figure 9 the signal output from the shown start signal line STV. The timing change of the first clock signal CLA is consistent with the signal output from the first clock signal line cla. The timing change of the second clock signal CLB is consistent with the signal output from the second clock signal line clb. The timing change of the third clock signal CLC is consistent with the signal output from the third clock signal line clc. The timing change of the fourth clock signal CLD is consistent with the signal output from the fourth clock signal line cld.

[0216] Figure 11 shows a schematic structural diagram of the driving circuit according to another embodiment of the present disclosure.

[0217] In the embodiment of the present disclosure, the driving circuit 1100 includes M cascaded shift registers. The cascading relationship between the M shift registers included in the driving circuit 1100 can refer to the cascading relationship between the M shift registers included in the driving circuit 900, and similar parts will not be described in detail.

[0218] In the embodiment of the present disclosure, the fifth input terminal INPUT5 of the mth-stage shift register is electrically connected to the seventh node N7 of the (m - c)th-stage shift register, where 1 ≤ c < m ≤ M, and c and m are integers.

[0219] For example, as shown in Figure 11 taking c = 4 as an example to schematically illustrate the cascading relationship of the driving circuit 1100. The fifth input terminal INPUT5 of the fifth-stage shift register GOA(5) is electrically connected to the seventh node N7 of the first-stage shift register GOA(1), and the fifth input terminal INPUT5 of the sixth-stage shift register GOA(6) is electrically connected to the seventh node N7 of the second-stage shift register GOA(2).

[0220] In an embodiment of the present disclosure, the pseudo shift register included in the driving circuit 1100 can also be used to connect to the fifth input terminal INPUT5 of the first-stage shift register GOA(1) to the fourth-stage shift register GOA(4), so as to satisfy the fifth input signal INPUT5 required by the first-stage shift register GOA(1) to the fourth-stage shift register GOA(4). The number of pre-stage Dummies can be determined according to the number of stages of the shift register cascaded with the second input terminal INPUT2, the third input terminal INPUT3, and the fourth input terminal INPUT4 of the m-th stage shift register. For example, by controlling the number of stages of the m-c stage shift register, the moment of the level switching of the fifth input signal INPUT5 received by the m-th stage shift register can be controlled, so as to control the duration of the effective level in the third output signal OUT3 and the phase difference from the first output signal OUT1.

[0221] In an embodiment of the present disclosure, the connection relationship between the m-th stage shift register GOA(m) and the first clock signal line cla, the second clock signal line clb, the third clock signal line clc, and the fourth clock signal line cld is the same as the connection relationship between the (m + 4)-th stage shift register GOA(m + 4) and the first clock signal line cla, the second clock signal line clb, the third clock signal line clc, and the fourth clock signal line cld, where m is an integer greater than or equal to 1.

[0222] For example, the clock terminal CLA of the first-stage shift register GOA(1) is electrically connected to the first clock signal line cla, the clock terminal CLB of the first-stage shift register GOA(1) is electrically connected to the second clock signal line clb, the clock terminal CLC of the first-stage shift register GOA(1) is electrically connected to the third clock signal line clc, and the clock terminal CLD of the first-stage shift register GOA(1) is electrically connected to the fourth clock signal line cld.

[0223] For example, the clock terminal CLA of the second-stage shift register GOA(2) is electrically connected to the second clock signal line clb, the clock terminal CLB of the second-stage shift register GOA(2) is electrically connected to the first clock signal line cla, the clock terminal CLC of the second-stage shift register GOA(2) is electrically connected to the third clock signal line clc, and the clock terminal CLD of the first-stage shift register GOA(1) is electrically connected to the third clock signal line clc.

[0224] For example, the clock terminal CLA of the third-stage shift register GOA(3) is electrically connected to the first clock signal line cla, the clock terminal CLB of the third-stage shift register GOA(3) is electrically connected to the second clock signal line clb, the clock terminal CLC of the third-stage shift register GOA(3) is electrically connected to the fourth clock signal line cld, and the clock terminal CLD of the third-stage shift register GOA(3) is electrically connected to the third clock signal line clc.

[0225] For example, the clock terminal CLA of the fourth-stage shift register GOA(4) is electrically connected to the second clock signal line clb, the clock terminal CLB of the fourth-stage shift register GOA(4) is electrically connected to the first clock signal line cla, the clock terminal CLC of the fourth-stage shift register GOA(4) is electrically connected to the fourth clock signal line cld, and the clock terminal CLD of the fourth-stage shift register GOA(4) is electrically connected to the fourth clock signal line cld.

[0226] For example, the connection relationship between the first-stage shift register GOA(1) and the first clock signal line cla, the second clock signal line clb, the third clock signal line clc, and the fourth clock signal line cld is the same as the connection relationship between the fifth-stage shift register GOA(5) and the first clock signal line cla, the second clock signal line clb, the third clock signal line clc, and the fourth clock signal line cld. Figure 10 Shows Figure 9 the signal timing diagram of the driving circuit in

[0227] In the embodiment of the present disclosure, three different output signals can be output by sharing the first clock signal line cla, the second clock signal line clb, the third clock signal line clc, and the fourth clock signal line cld, reducing the number of clock signal lines. By controlling the timing changes of the first input signal INPUT1 to the fifth input signal INPUT5, the driving circuit 1100 can output output signals with different level widths. In addition, by setting the pseudo shift register, each stage of the shift register can be provided with the first input signal INPUT1 to the fifth input signal INPUT5 by the previous-stage shift register, realizing the internal multiplexing of the first input signal INPUT1 to the fifth input signal INPUT5, thereby reducing the connection traces between the driving circuit 1100 and the external signal source. The driving circuit 1100 only needs the start signal line STV, the first clock signal line cla, the second clock signal line clb, the third clock signal line clc, and the fourth clock signal line cld to output three output signals with different level widths, namely the first output signal OUT1, the second output signal OUT2, and the third output signal OUT3.

[0228] Figure 12 Shows Figure 11 the signal timing diagram of the driving circuit in

[0229] Figure 12 shows that under the action of the start signal STV, the first clock signal cla, the second clock signal clb, the third clock signal clc, and the fourth clock signal cld as shown in Figure 12 The first output signal OUT1 output from the first output terminal OUT1 of the first-stage shift register GOA(1) to the eighth-stage shift register GOA(8), the second output signal OUT2 output from the second output terminal OUT2, and the third output signal OUT3 output from the third output terminal OUT3. The eight-stage first output signal OUT1 is sequentially shifted and output, the eight-stage second output signal OUT2 is sequentially shifted and output, and the eight-stage third output signal OUT3 is sequentially shifted and output.

[0230] Figure 13 shows a schematic structural diagram of the display device according to an embodiment of the present disclosure.

[0231] As Figure 13 shown, the display device 1300 may include a driving circuit 1310.

[0232] In the embodiment of the present disclosure, the driving circuit 1310 may be any one of the driving circuits 800, 900, and 1100 described above, and will not be elaborated here.

[0233] Figure 14 shows a schematic flowchart of the driving method according to an embodiment of the present disclosure.

[0234] As Figure 14 shown, the driving method may include operations S1410 to S1440.

[0235] In operation S1410, under the control of the first clock signal from the first clock terminal, the potential of the first node is controlled by using the first input signal from the first input terminal, and under the control of the first input signal, the first clock signal, and the first power supply voltage of the first power supply, the potential of the second node is controlled by using the second power supply voltage of the second power supply and the second clock signal from the second clock terminal.

[0236] In operation S1420, under the control of the first clock signal, the first input signal, the second input signal from the second output terminal, and the third clock signal from the third clock terminal, the potential of the third node is controlled by using the potential of the second node and the second power supply voltage.

[0237] In operation S1430, based on the first power supply voltage and the second power supply voltage, a first output signal is output via the first output terminal under the control of the potential of the first node and the potential of the second node.

[0238] At operation S1440, under the control of the first input signal, the potential of the third node, the third input signal from the third input terminal, and the fourth input signal from the fourth input terminal, a second output signal is output via the second output terminal based on the first power supply voltage and the second power supply voltage.

[0239] In the embodiments of the present disclosure, operations S1410 to S1440 are similar to the operations performed by the shift register 100 described above, and will not be described in detail here.

[0240] In the embodiments of the present disclosure, the driving method further includes controlling the potential of the fourth node using the second power supply voltage and the fifth input signal from the fifth input terminal under the control of the second output signal, the second power supply voltage, and the fourth clock signal from the fourth clock terminal. Under the control of the potential of the fourth node and the second output signal, a third output signal is output via the third output terminal based on the second power supply voltage and the second clock signal.

[0241] In the embodiments of the present disclosure, the driving method further includes supplying the first power supply voltage to the fifth node under the control of the first input signal. Under the control of the fourth input signal, the potential of the fifth node is supplied to the second output terminal.

[0242] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, as well as the combination of blocks in the block diagram or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0243] Those skilled in the art can understand that the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly recited in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0244] The embodiments of the present disclosure have been described above. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A shift register, comprising: A first control circuit configured to control the potential of a first node by using a first input signal from a first input terminal under the control of a first clock signal from a first clock terminal, and to control the potential of a second node by using a second power supply voltage of a second power supply and a second clock signal from a second clock terminal under the control of the first input signal, the first clock signal, and a first power supply voltage of a first power supply; A second control circuit configured to control the potential of a third node by using the potential of the second node and the second power supply voltage under the control of the first clock signal, the first input signal, a second input signal from a second input terminal, and a third clock signal from a third clock terminal; A first output circuit configured to output a first output signal via a first output terminal based on the first power supply voltage and the second power supply voltage under the control of the potential of the first node and the potential of the second node; And A second output circuit configured to output a second output signal via a second output terminal based on the first power supply voltage and the second power supply voltage under the control of the first input signal, the potential of the third node, a third input signal from a third input terminal, and a fourth input signal from a fourth input terminal.

2. The shift register according to claim 1, further comprising: A third control circuit electrically connected to a fifth input terminal, the second output terminal, the second power supply, and a fourth clock terminal, the third control circuit being configured to control the potential of a fourth node by using the second power supply voltage and a fifth input signal from the fifth input terminal under the control of the second output signal, the second power supply voltage, and a fourth clock signal from the fourth clock terminal; A third output circuit electrically connected to the fourth node, the second output terminal, the second clock terminal, and the second power supply voltage, the third output circuit being configured to output a third output signal via a third output terminal based on the second power supply voltage and the second clock signal under the control of the potential of the fourth node and the second output signal.

3. The shift register according to claim 1, wherein, The second output circuit includes: A pull - down unit electrically connected to the first input terminal and the first power supply, the pull - down unit being configured to provide the first power supply voltage to a fifth node under the control of the first input signal; and An output unit electrically connected to the second output terminal, the fifth node, and the fourth input terminal, the output unit being configured to provide the potential of the fifth node to the second output terminal under the control of the fourth input signal.

4. The shift register according to claim 1, wherein, The first control circuit includes: A first control unit electrically connected to the first input terminal, the first clock terminal, and the second clock terminal, the first control unit being configured to provide the first input signal to the first node and a sixth node under the control of the first clock signal, and to provide the potential of the sixth node to the first node under the control of the second clock signal and the potential of the sixth node; and A second control unit, electrically connected to the first input terminal, the first clock terminal, the second clock terminal, the first power supply, and the second power supply, is configured to provide the second clock signal to the seventh node under the control of the first power supply voltage and the first clock signal, and provide the second power supply voltage or the potential of the seventh node to the second node under the control of the first input signal and the second clock signal.

5. The shift register according to claim 1, wherein, The second control circuit includes: A third control unit, electrically connected to the second input terminal, the first clock terminal, and the third clock terminal, is configured to provide the second input signal to the eighth node under the control of the third clock signal, and control the potential of the eighth node by using the first clock signal under the control of the potential of the eighth node; A fourth control unit, electrically connected to the first input terminal, the second power supply, the second node, and the eighth node, is configured to provide the potential of the second node to the third node under the control of the potential of the eighth node, and provide the second power supply voltage to the third node under the control of the first input signal.

6. The shift register according to claim 2, wherein, The third control circuit includes: A fifth control unit, electrically connected to the second output terminal, the fifth input terminal, and the second power supply, is configured to provide the fifth input signal to the fourth node under the control of the second output signal and the second power supply voltage; and A sixth control unit, electrically connected to the fourth clock terminal and the second power supply, is configured to provide the second power supply voltage to the fourth node under the control of the fourth clock signal.

7. The shift register according to claim 5, wherein The third control unit includes a first transistor, a second transistor, and a first capacitor, and the fourth control unit includes a third transistor and a fourth transistor; Wherein, the control electrode of the first transistor is electrically connected to the third clock terminal, the first pole of the first transistor is electrically connected to the second input terminal, and the second pole of the first transistor is electrically connected to the eighth node; The first end of the first capacitor is electrically connected to the eighth node, and the second end of the first capacitor is electrically connected to the first pole of the second transistor; The control electrode of the second transistor is electrically connected to the eighth node, and the second pole of the second transistor is electrically connected to the first clock terminal; The control electrode of the third transistor is electrically connected to the eighth node, the first pole of the third transistor is electrically connected to the second node, and the second pole of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the first input terminal, the first pole of the fourth transistor is electrically connected to the second power supply, and the second pole of the fourth transistor is electrically connected to the third node.

8. The shift register according to claim 3, wherein, The pull-down unit includes a fifth transistor, and the output unit includes a sixth transistor, a seventh transistor, and an eighth transistor; Wherein, the control electrode of the fifth transistor is electrically connected to the first input terminal, the first pole of the fifth transistor is electrically connected to the fifth node, and the second pole of the fifth transistor is electrically connected to the first power supply; The control electrode of the sixth transistor is electrically connected to the third node, the first pole of the sixth transistor is electrically connected to the second power supply, and the second pole of the sixth transistor is electrically connected to the fifth node; The control electrode of the seventh transistor is electrically connected to the fourth input terminal, the first pole of the seventh transistor is electrically connected to the fifth node, and the second pole of the seventh transistor is electrically connected to the second output terminal; The control electrode of the eighth transistor is electrically connected to the third input terminal, the first pole of the eighth transistor is electrically connected to the second output terminal, and the second pole of the eighth transistor is electrically connected to the first power supply.

9. The shift register according to claim 6, wherein, The fifth control unit includes a ninth transistor, a tenth transistor and a second capacitor, and the sixth control unit includes an eleventh transistor; Wherein, the control electrode of the ninth transistor is electrically connected to the ninth node, the first pole of the ninth transistor is electrically connected to the fifth input terminal, and the second pole of the ninth transistor is electrically connected to the fourth node; The control electrode of the tenth transistor is electrically connected to the second output terminal, the first pole of the tenth transistor is electrically connected to the ninth node, and the second pole of the tenth transistor is electrically connected to the second power supply; The first end of the second capacitor is electrically connected to the fifth input terminal, and the second end of the second capacitor is electrically connected to the ninth node; and The control electrode of the eleventh transistor is electrically connected to the fourth clock terminal, the first pole of the eleventh transistor is electrically connected to the fourth node, and the second pole of the eleventh transistor is electrically connected to the second power supply.

10. The shift register according to any one of claims 2 to 9, wherein, The first clock signal and the second clock signal are not both at an active level at the same time, and the third clock signal and the fourth clock signal are not both at an active level at the same time; Wherein, the period of the first clock signal is the same as the period of the second clock signal, the period of the third clock signal is the same as the period of the fourth clock signal, and the period of the third clock signal is twice the period of the first clock signal.

11. The shift register according to any one of claims 2 to 9, wherein, During the duration of the first level of the fourth input signal, the level change of the second input signal is consistent with the level change of the first clock signal, and the level change of the fifth input signal is consistent with the level change of the second clock signal.

12. The shift register according to any one of claims 1 to 9, wherein, The duration of the second level of the third input signal is the same as the duration of the second level of the first node; The duration of the second level of the third input signal is greater than the duration of the second level of the first input signal; The moment when the third input signal switches from the first level to the second level is earlier than the moment when the first input signal switches from the first level to the second level, and the moment when the third input signal switches from the second level to the first level is earlier than the moment when the first input signal switches from the second level to the first level; The moment when the third input signal switches from the first level to the second level is earlier than the moment when the fourth input signal switches from the second level to the first level, and the moment when the third input signal switches from the second level to the first level is later than the moment when the fourth input signal switches from the first level to the second level.

13. The shift register according to any one of claims 1 to 9, wherein, The duration of the first level of the fourth input signal is the same as the duration of the second level of the second node; The duration of the first level of the fourth input signal is less than the duration of the second level of the first input signal; The moment when the fourth input signal switches from the second level to the first level is earlier than the moment when the first input signal switches from the first level to the second level, and the moment when the fourth input signal switches from the first level to the second level is earlier than the moment when the first input signal switches from the second level to the first level.

14. A driving circuit, comprising M cascaded shift registers according to any one of claims 1 - 10, where M is an integer greater than 1.

15. The driving circuit according to claim 11, wherein, The first input end of the m-th stage shift register is electrically connected to the first output end of the (m - a)-th stage shift register, 1 ≤ a < m ≤ M, and a and m are integers.

16. The driving circuit according to claim 11, wherein, The second input end of the m-th stage shift register is electrically connected to the seventh node of the (m - b)-th stage shift register, the third input end of the m-th stage shift register is electrically connected to the first node of the (m - b - 1)-th stage shift register, the fourth input end of the m-th stage shift register is electrically connected to the second node of the (m - b - 1)-th stage shift register, 1 ≤ b < m ≤ M, and b and m are integers.

17. The driving circuit according to claim 11, wherein, The fifth input end of the m-th stage shift register is electrically connected to the seventh node of the (m - c)-th stage shift register, 1 ≤ c < m ≤ M, and c and m are integers.

18. A display device, comprising: The driving circuit according to any one of claims 14 to 17.

19. A driving method, applied to the shift register according to any one of claims 1 - 13, comprising: Under the control of a first clock signal from a first clock terminal, controlling the potential of a first node by using a first input signal from a first input end, and under the control of the first input signal, the first clock signal, and a first power supply voltage of a first power supply, controlling the potential of a second node by using a second power supply voltage of a second power supply and a second clock signal from a second clock terminal; Under the control of the first clock signal, the first input signal, the second input signal from the second output terminal, and the third clock signal from the third clock terminal, the potential of the third node is controlled by using the potential of the second node and the second power supply voltage; Under the control of the potential of the first node and the potential of the second node, a first output signal is output via the first output terminal based on the first power supply voltage and the second power supply voltage; and Under the control of the first input signal, the potential of the third node, the third input signal from the third input terminal, and the fourth input signal from the fourth input terminal, a second output signal is output via the second output terminal based on the first power supply voltage and the second power supply voltage.

20. The driving method according to claim 19, further comprising: Under the control of the second output signal, the second power supply voltage, and the fourth clock signal from the fourth clock terminal, the potential of the fourth node is controlled by using the second power supply voltage and the fifth input signal from the fifth input terminal; Under the control of the potential of the fourth node and the second output signal, a third output signal is output via the third output terminal based on the second power supply voltage and the second clock signal.

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