Driver and display device

Abstract

The invention relates to a driver and a display device. At least one stage of the driver includes: an input circuit transmitting an input signal to a first node in response to at least one of a clock signal and an inverted clock signal; a holding capacitor holding a voltage of the first node; a first inverter generating a voltage of a second node by inverting the voltage of the first node; a second inverter generating a voltage of a third node by inverting the voltage of the second node; a third inverter generating a carry signal by inverting a voltage of the second node; and an output control circuit selectively outputting a voltage of the third node as an output signal in response to the output enable signal. At least one of the first inverter, the second inverter, the third inverter, and the output control circuit includes a PMOS transistor and an NMOS transistor connected in series.

Description

Technical Field

[0001] Embodiments of the inventive concept relate to a display device, and more particularly, to a driver including complementary metal-oxide semiconductor (CMOS) transistors and a display device including the driver. Background Art

[0002] A driver of a display device (e.g., a gate driver and / or an emission driver) may sequentially provide signals (e.g., a gate signal and / or an emission signal) to pixels of a display panel on a line-by-line basis. To sequentially provide signals on a line-by-line basis, the driver may be implemented in the form of a shift register including a plurality of stages.

[0003] Generally, each stage of the driver may include only a single type of transistor, such as a p-type metal-oxide semiconductor (PMOS) transistor. In the case where each stage includes only PMOS transistors, in order to output an output signal having a low voltage level, a bootstrap operation of reducing the voltage of an internal node of the stage to a voltage level lower than the low voltage level should be performed. Summary of the Invention

[0004] Some embodiments provide a driver in which each stage includes complementary metal-oxide semiconductor (CMOS) transistors.

[0005] Some embodiments provide a display device including a driver in which each stage includes CMOS transistors.

[0006] According to an embodiment, there is provided a driver including a plurality of stages. At least one of the plurality of stages includes: an input circuit configured to transfer an input signal to a first node in response to at least one of a clock signal and an inverted clock signal; a holding capacitor configured to hold a voltage of the first node; a first inverter configured to generate a voltage of a second node by inverting the voltage of the first node; a second inverter configured to generate a voltage of a third node by inverting the voltage of the second node; a third inverter configured to generate a carry signal by inverting the voltage of the second node; and an output control circuit configured to selectively output the voltage of the third node as an output signal in response to an output enable signal. At least one of the first inverter, the second inverter, the third inverter, and the output control circuit includes a p-type metal-oxide semiconductor (PMOS) transistor and an n-type metal-oxide semiconductor (NMOS) transistor connected in series.

[0007] In an embodiment, a first active region of the PMOS transistor may include a material different from a material of a second active region of the NMOS transistor.

[0008] In an embodiment, the first active region of the PMOS transistor may include polysilicon, and the second active region of the NMOS transistor may include an oxide semiconductor, an organic semiconductor, or amorphous silicon.

[0009] In an embodiment, the NMOS transistor may include a top gate located above the second active region and a bottom gate located below the second active region. A low gate voltage may be applied to the terminals of the NMOS transistor, and a second low gate voltage lower than the low gate voltage may be applied to the bottom gate of the NMOS transistor.

[0010] In an embodiment, when the output enable signal has a high level, the output control circuit may output the low gate voltage as an output signal, and when the output enable signal has a low level, the output control circuit may output the voltage of the third node as an output signal.

[0011] In an embodiment, the output control circuit may include: a first PMOS transistor including a gate receiving the output enable signal, a first terminal connected to the third node, and a second terminal connected to the output node for outputting the output signal; and a first NMOS transistor including a gate receiving the output enable signal, a first terminal connected to the line for transmitting the low gate voltage, and a second terminal connected to the output node.

[0012] In an embodiment, the input circuit may include at least one of a second PMOS transistor and a second NMOS transistor. The second PMOS transistor includes a gate receiving an inverted clock signal, a first terminal receiving an input signal, and a second terminal connected to the first node. The second NMOS transistor includes a gate receiving a clock signal, a first terminal receiving an input signal, and a second terminal connected to the first node.

[0013] In an embodiment, the holding capacitor may include a first electrode connected to the line for transmitting the high gate voltage and a second electrode connected to the first node.

[0014] In an embodiment, the first inverter may include: a third PMOS transistor including a gate connected to the first node, a first terminal connected to the line for transmitting the high gate voltage, and a second terminal connected to the second node; and a third NMOS transistor including a gate connected to the first node, a first terminal connected to the line for transmitting the low gate voltage, and a second terminal connected to the second node.

[0015] In an embodiment, the second inverter may include: a fourth PMOS transistor including a gate connected to the second node, a first terminal connected to a line for transmitting a high gate voltage, and a second terminal connected to the third node; and a fourth NMOS transistor including a gate connected to the second node, a first terminal connected to a line for transmitting a low gate voltage, and a second terminal connected to the third node.

[0016] In an embodiment, the third inverter may include: a fifth PMOS transistor including a gate connected to the second node, a first terminal connected to a line for transmitting a high gate voltage, and a second terminal connected to the carry node for outputting a carry signal; and a fifth NMOS transistor including a gate connected to the second node, a first terminal connected to a line for transmitting a low gate voltage, and a second terminal connected to the carry node.

[0017] In an embodiment, at least one stage may further include a sixth PMOS transistor including a gate receiving a global reset signal, a first terminal connected to a line for transmitting a high gate voltage, and a second terminal connected to the first node.

[0018] In an embodiment, at least one stage may further include a PMOS boost buffer, wherein the voltage of the first node is at a low level, and the PMOS boost buffer is configured to output a low gate voltage to the third node.

[0019] In an embodiment, the PMOS boost buffer may include: a boost capacitor including a first electrode connected to the carry node for outputting a carry signal and a second electrode connected to the fourth node; a seventh PMOS transistor including a gate connected to a line for transmitting a low gate voltage, a first terminal connected to the first node, and a second terminal connected to the fourth node; and an eighth PMOS transistor including a gate connected to the fourth node, a first terminal connected to the third node, and a second terminal connected to a line for transmitting a low gate voltage.

[0020] In an embodiment, when the output enable signal is at a high level, the output control circuit may output the voltage of the third node as an output signal, and when the output enable signal is at a low level, the output control circuit may output a low gate voltage as an output signal.

[0021] In an embodiment, the output control circuit may include: a first NMOS transistor including a gate receiving the output enable signal, a first terminal connected to the third node, and a second terminal connected to the output node for outputting the output signal; and a first PMOS transistor including a gate receiving the output enable signal, a first terminal connected to a line for transmitting a low gate voltage, and a second terminal connected to the output node.

[0022] According to an embodiment, a driver including a plurality of stages is provided. At least one of the plurality of stages includes: a first PMOS transistor including a gate receiving an output enable signal, a first terminal connected to a third node, and a second terminal connected to an output node; a first NMOS transistor including a gate receiving an output enable signal, a first terminal connected to a line transmitting a low gate voltage, and a second terminal connected to the output node; a second PMOS transistor including a gate receiving an inverted clock signal, a first terminal receiving an input signal, and a second terminal connected to a first node; a second NMOS transistor including a gate receiving a clock signal, a first terminal receiving an input signal, and a second terminal connected to the first node; a holding capacitor including a first electrode connected to a line transmitting a high gate voltage and a second electrode connected to the first node; a third PMOS transistor including a gate connected to the first node, a first terminal connected to a line transmitting a high gate voltage, and a second terminal connected to a second node; a third NMOS transistor including a gate connected to the first node, a first terminal connected to a line transmitting a low gate voltage, and a second terminal connected to the second node; a fourth PMOS transistor including a gate connected to the second node, a first terminal connected to a line transmitting a high gate voltage, and a second terminal connected to the third node; a fourth NMOS transistor including a gate connected to the second node, a first terminal connected to a line transmitting a low gate voltage, and a second terminal connected to the third node; a fifth PMOS transistor including a gate connected to the second node, a first terminal connected to a line transmitting a high gate voltage, and a second terminal connected to a carry node; a fifth NMOS transistor including a gate connected to the second node, a first terminal connected to a line transmitting a low gate voltage, and a second terminal connected to the carry node; and a sixth PMOS transistor including a gate receiving a global reset signal, a first terminal connected to a line transmitting a high gate voltage, and a second terminal connected to the first node.

[0023] In an embodiment, at least one stage may further include: a boosting capacitor including a first electrode connected to the carry node and a second electrode connected to a fourth node; a seventh PMOS transistor including a gate connected to a line transmitting a low gate voltage, a first terminal connected to the first node, and a second terminal connected to the fourth node; and an eighth PMOS transistor including a gate connected to the fourth node, a first terminal connected to the third node, and a second terminal connected to a line transmitting a low gate voltage.

[0024] According to an embodiment, a display device is provided, which includes: a display panel including a plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; a gate driver configured to provide gate signals to the plurality of pixels; an emission driver configured to provide emission signals to the plurality of pixels; and a controller configured to control the data driver, the gate driver, and the emission driver. At least one of the gate driver and the emission driver includes a plurality of stages. At least one stage of the plurality of stages includes: an input circuit configured to transfer an input signal to a first node in response to at least one of a clock signal and an inverted clock signal; a holding capacitor configured to hold a voltage of the first node; a first inverter configured to generate a voltage of a second node by inverting the voltage of the first node; a second inverter configured to generate a voltage of a third node by inverting the voltage of the second node; a third inverter configured to generate a carry signal by inverting the voltage of the second node; and an output control circuit configured to selectively output the voltage of the third node as an output signal in response to an output enable signal. At least one of the first inverter, the second inverter, the third inverter, and the output control circuit includes a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor connected in series.

[0025] In an embodiment, the display panel may include a first panel area driven at a first driving frequency and a second panel area driven at a second driving frequency lower than the first driving frequency. In a first frame period, the controller may generate an output enable signal having a first level during a first time period allocated to the first panel area within the first frame period and a second time period allocated to the second panel area within the first frame period, such that the plurality of stages output the output signal to both the first panel area and the second panel area. In a second frame period, the controller may generate an output enable signal having a first level during a third time period allocated to the first panel area within the second frame period, and generate an output enable signal having a second level different from the first level during a fourth time period allocated to the second panel area within the second frame period, such that the plurality of stages output the output signal to the first panel area and do not output the output signal to the second panel area.

[0026] As described above, in the driver and the display device according to the embodiment, at least one stage may include an input circuit, a first inverter, a second inverter, a third inverter, and an output control circuit, and at least one of the first inverter, the second inverter, the third inverter, and the output control circuit may include both a PMOS transistor and an NMOS transistor or include a CMOS transistor. Therefore, a bootstrap operation may not be required or performed in this stage, and power consumption of the driver and the display device may be reduced.

[0027] In addition, in the driver and the display device according to the embodiment, the output control circuit may selectively output an output signal in response to an output enable signal. Accordingly, the driver according to the embodiment may be applicable to a display device that performs a multi-frequency driving (MFD) operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Exemplary, non-limiting embodiments will be understood more clearly through the following detailed description in conjunction with the drawings.

[0029] Figure 1 is a block diagram showing a driver according to an embodiment.

[0030] Figure 2 is a block diagram showing a stage of a driver according to an embodiment.

[0031] Figure 3 is a cross-sectional view showing an example of a PMOS transistor and an NMOS transistor included in the Figure 2 stage.

[0032] Figure 4 is a circuit diagram showing a stage of a driver according to an embodiment.

[0033] Figure 5 is a timing diagram for describing an example of the operation of the Figure 4 stage.

[0034] Figure 6 is a circuit diagram for describing an example of the operation of the Figure 4 stage in a first time period when the output enable signal has a low level.

[0035] Figure 7 is a circuit diagram for describing an example of the operation of the Figure 4 stage in a first time period when the output enable signal has a high level.

[0036] Figure 8 is a circuit diagram for describing an example of the operation of the Figure 4 stage in a second time period.

[0037] Figure 9 is a circuit diagram showing a stage of a driver according to an embodiment.

[0038] Figure 10 is a circuit diagram showing a stage of a driver according to an embodiment.

[0039] Figure 11 is for describing Figure 10 the operation of the stage.

[0040] Figure 12 is a circuit diagram showing a stage of a driver according to an embodiment.

[0041] Figure 13 is a block diagram showing a display device according to an embodiment.

[0042] Figure 14A is a diagram showing an example of a display panel in which a plurality of panel regions are driven at different driving frequencies.

[0043] Figure 14B and Figure 14C is a diagram showing an example of a gate signal applied to Figure 14A the display panel.

[0044] Figure 15 is a block diagram showing an electronic device including a display device according to an embodiment. Detailed embodiments

[0045] Embodiments will be described more fully hereinafter with reference to the accompanying drawings. Like or similar reference numerals refer to like or similar elements throughout.

[0046] Figure 1 is a block diagram showing a driver 100 according to an embodiment.

[0047] Referring to Figure 1 , the driver 100 according to an embodiment may include a plurality of stages STG1, STG2, STG3, STG4, etc. The plurality of stages STG1, STG2, STG3, STG4, etc. may sequentially generate carry signals CR1, CR2, CR3, CR4, etc. based on a start signal FLM, a clock signal CLK, and an inverted clock signal CLKB, and may selectively output output signals OUT1, OUT2, OUT3, OUT4, etc. based on an output enable signal OUT_EN. In some embodiments, the driver 100 may be included in a display device and may be formed in a display panel of the display device. For example, the driver 100 may be integrated or formed on a substrate of the display panel, but is not limited thereto. In other embodiments, the driver 100 may be implemented as an integrated circuit.

[0048] The first stage STG1 may receive the start signal FLM as an input signal, and each of the subsequent stages STG2, STG3, STG4, etc. may receive the carry signal of the previous stage as an input signal. For example, the second stage STG2 may receive the first carry signal CR1 of the first stage STG1 as an input signal, the third stage STG3 may receive the second carry signal CR2 of the second stage STG2 as an input signal, and the fourth stage STG4 may receive the third carry signal CR3 of the third stage STG3 as an input signal.

[0049] In some embodiments, when the clock signal CLK is at a high level, each odd-stage STG1, STG3, etc. can start to output carry signals CR1, CR3, etc., and when the inverted clock signal CLKB is at a high level, each even-stage STG2, STG4, etc. can start to output carry signals CR2, CR4, etc. For example, when the clock signal CLK becomes high after the start signal FLM becomes high, the first-stage STG1 can start to output a first carry signal CR1 with a high level. When the inverted clock signal CLKB becomes high after the first carry signal CR1 becomes high, the second-stage STG2 can start to output a second carry signal CR2 with a high level. When the clock signal CLK becomes high after the second carry signal CR2 becomes high, the third-stage STG3 can start to output a third carry signal CR3 with a high level. When the inverted clock signal CLKB becomes high after the third carry signal CR3 becomes high, the fourth-stage STG4 can start to output a fourth carry signal CR4 with a high level. In this way, by delaying or shifting the carry signals CR1, CR2, CR3, CR4, etc. by half a period of the clock signal CLK, multiple stages STG1, STG2, STG3, STG4, etc. can sequentially output the carry signals CR1, CR2, CR3, CR4, etc.

[0050] In addition, each stage STG1, STG2, STG3, STG4, etc. can selectively output its output signal with a high level according to the level of the output enable signal OUT_EN while outputting its carry signal with a high level. For example, when outputting the first carry signal CR1 with a high level, the first-stage STG1 can output a first output signal OUT1 with a high level in response to an output enable signal OUT_EN having a first level (e.g., Figure 5 the low level in the example of Figure 11 or the high level in the example of Figure 5 ), and can output a first output signal OUT1 with a high level in response to an output enable signal OUT_EN having a second level (e.g., Figure 11The output enable signal OUT_EN at a low level (in the example) enables the output without outputting the first output signal OUT1 at a high level. In addition, when outputting the second carry signal CR2 at a high level, the second stage STG2 can output the second output signal OUT2 at a high level in response to the output enable signal OUT_EN at the first level, and can refrain from outputting the second output signal OUT2 at a high level in response to the output enable signal OUT_EN at the second level. Therefore, the corresponding stages STG1, STG2, STG3, STG4, etc. can selectively output the output signals OUT1, OUT2, OUT3, OUT4, etc. according to the output enable signal OUT_EN applied to the plurality of stages STG1, STG2, STG3, STG4, etc. Accordingly, the driver 100 according to the embodiment can provide the output signals OUT1, OUT2, OUT3, OUT4, etc. to a plurality of pixel rows at different driving frequencies, and thus can be applied to a display device performing a multi-frequency driving (MFD) operation.

[0051] Figure 2 is a block diagram showing a stage 200 of a driver according to an embodiment. Figure 3 is shown including Figure 2 an example of a PMOS transistor PT and an NMOS transistor NT included in the stage 200 of

[0052] Refer to Figure 2 , at least one stage 200 of a driver according to an embodiment may include an input circuit INC, a holding capacitor CHOLD, a first inverter INV1, a second inverter INV2, a third inverter INV3, and an output control circuit OCC.

[0053] The input circuit INC can transfer the input signal SIN to the first node N1 in response to at least one of the clock signal CLK and the inverted clock signal CLKB. When the stage 200 is the first stage, the input signal SIN may be the start signal FLM, or when the stage 200 is a subsequent stage, the input signal SIN may be the carry signal PCR of the previous stage. In some embodiments, the input circuit INC may be implemented as but not limited to a complementary metal oxide semiconductor (CMOS) transmission gate including a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor connected in parallel. In other embodiments, the input circuit INC may include only PMOS transistors, or may include only NMOS transistors. The holding capacitor CHOLD can maintain the voltage of the first node N1.

[0054] The first inverter INV1 can generate the voltage of the second node N2 by inverting the voltage of the first node N1. The second inverter INV2 can generate the voltage of the third node N3 by inverting the voltage of the second node N2. The third inverter INV3 can generate the carry signal CR by inverting the voltage of the second node N2. Thus, when the first node N1 has a high gate voltage VGH, the voltage of the third node N3 can be at a high level, and a carry signal CR at a high level can be output.

[0055] The output control circuit OCC can selectively output the voltage of the third node N3 as the output signal OUT in response to the output enable signal OUT_EN. In some embodiments, when the output enable signal OUT_EN is at a high level, the output control circuit OCC can output an output signal OUT at a low level, and when the output enable signal OUT_EN is at a low level, the voltage of the third node N3 can be output as the output signal OUT. In other embodiments, when the output enable signal OUT_EN is at a high level, the output control circuit OCC can output the voltage of the third node N3 as the output signal OUT, and when the output enable signal OUT_EN is at a low level, an output signal OUT at a low level can be output.

[0056] In each stage 200 of the driver according to an embodiment, at least one of the first inverter INV1, the second inverter INV2, the third inverter INV3, and the output control circuit OCC can include a PMOS transistor and an NMOS transistor connected in series. In some embodiments, the first active region of the PMOS transistor can include a material different from that of the second active region of the NMOS transistor. Further, in some embodiments, the NMOS transistor can include a top gate located above the second active region and a bottom gate located below the second active region.

[0057] For example, as Figure 3As shown, a first source / drain region SD1, a first active region ACT1, and a second source / drain region SD2 of the PMOS transistor PT may be formed on a substrate SUB of a display panel. In some embodiments, a buffer layer may also be formed between the substrate SUB and the first active region ACT1 to prevent impurities, but the embodiments are not limited thereto. The first active region ACT1 of the PMOS transistor PT may include polysilicon, such as low-temperature polysilicon (LTPS). In addition, the first source / drain region SD1 and the second source / drain region SD2 may be p+ doped regions and may be used as the source and drain of the PMOS transistor PT, respectively. A first gate insulating layer GI1 may be formed on the first source / drain region SD1, the first active region ACT1, and the second source / drain region SD2. For example, the first gate insulating layer GI1 may include silicon oxide, but is not limited thereto. In addition, a gate GAT1 of the PMOS transistor PT may be formed on the first gate insulating layer GI1. For example, the gate GAT1 of the PMOS transistor PT may include a metal material such as molybdenum, but is not limited thereto. A second gate insulating layer GI2 may be formed on the gate GAT1 of the PMOS transistor PT. For example, the second gate insulating layer GI2 may include silicon nitride, but is not limited thereto.

[0058] In addition, a bottom gate BML of the NMOS transistor NT may be formed on the second gate insulating layer GI2. For example, the bottom gate BML may include a metal material such as molybdenum, but is not limited thereto. In some embodiments, a terminal (e.g., a third source / drain region SD3 or a fourth source / drain region SD4) of the NMOS transistor NT may receive a low gate voltage, which is a low voltage of a clock signal CLK, an inverted clock signal CLKB, a carry signal CR, an output signal OUT, and an input signal SIN, and the bottom gate BML of the NMOS transistor NT may receive a second low gate voltage lower than the low gate voltage. In this case, the threshold voltage of the NMOS transistor NT may be increased, and thus the leakage current passing through the NMOS transistor NT may be reduced. A first interlayer insulating layer ILD1 may be formed on the bottom gate BML. For example, the first interlayer insulating layer ILD1 may include silicon oxide or silicon nitride, but is not limited thereto.

[0059] The third source / drain region SD3, the second active region ACT2, and the fourth source / drain region SD4 of the NMOS transistor NT may be formed on the first interlayer insulating layer ILD1. The second active region ACT2 of the NMOS transistor NT may include a material different from that of the first active region ACT1 of the PMOS transistor PT. For example, the second active region ACT2 of the NMOS transistor NT may include an oxide semiconductor, an organic semiconductor, amorphous silicon, etc. That is, in some embodiments, the first active region ACT1 of the PMOS transistor PT may include polysilicon, while the second active region ACT2 of the NMOS transistor NT may include an oxide semiconductor, an organic semiconductor, or amorphous silicon. In addition, in some embodiments, as Figure 3 shown, the first active region ACT1 of the PMOS transistor PT and the second active region ACT2 of the NMOS transistor NT may be formed in different layers located at different heights from the substrate SUB of the display panel. The third source / drain region SD3 and the fourth source / drain region SD4 may be n+ doped regions and may be used as the source and drain of the NMOS transistor NT, respectively. The third gate insulating layer GI3 may be formed on the third source / drain region SD3, the second active region ACT2, and the fourth source / drain region SD4. For example, the third gate insulating layer GI3 may include silicon nitride, but is not limited thereto. In addition, the top gate GAT2 of the NMOS transistor NT may be formed on the third gate insulating layer GI3. For example, the top gate GAT2 of the NMOS transistor NT may include a metal material such as molybdenum or titanium, but is not limited thereto. The second interlayer insulating layer ILD2 may be formed on the top gate GAT2 of the NMOS transistor NT. For example, the second interlayer insulating layer ILD2 may include silicon oxide or silicon nitride, but is not limited thereto.

[0060] Each stage of a conventional driver may include only a single type of transistor. For example, in the case where each stage includes only PMOS transistors, in order to output an output signal having a low voltage level, a bootstrap operation of reducing the voltage of the internal node of the stage to a voltage level lower than the low voltage level should be performed. In addition, in the case where each stage includes only NMOS transistors, in order to output an output signal having a high voltage level, a bootstrap operation of increasing the voltage of the internal node of the stage to a voltage level higher than the high voltage level should be performed.

[0061] However, as described above, in each stage 200 of the driver according to the embodiment, at least one of the first inverter INV1, the second inverter INV2, the third inverter INV3, and the output control circuit OCC may include both a PMOS transistor PT and an NMOS transistor NT or include a CMOS transistor. In addition, in some embodiments, the PMOS transistor PT may output a high voltage (e.g., a high gate voltage VGH), and the NMOS transistor NT may output a low voltage (e.g., a low gate voltage). Therefore, a bootstrap operation may not be required or performed in the stage 200, and power consumption of the driver and a display device including the driver may be reduced.

[0062] In addition, in the stage 200 of the driver according to the embodiment, the output control circuit OCC may selectively output the output signal OUT in response to an output enable signal OUT_EN. Therefore, the driver according to the embodiment may be applicable to a display device that performs a multi-frequency driving (MFD) operation.

[0063] Figure 4 is a circuit diagram showing a stage 200a of a driver according to an embodiment.

[0064] Reference Figure 4 , the stage 200a of the driver according to the embodiment may include an input circuit INC, a holding capacitor CHOLD, a first inverter INV1, a second inverter INV2, a third inverter INV3, and an output control circuit OCC. In some embodiments, the stage 200a may further include a sixth PMOS transistor PT6.

[0065] The input circuit INC may transmit an input signal SIN to a first node N1 in response to at least one of a clock signal CLK and an inverted clock signal CLKB. In some embodiments, the input circuit INC may include a second PMOS transistor PT2 that transmits the input signal SIN to the first node N1 in response to the inverted clock signal CLKB. In other embodiments, the input circuit INC may include a second NMOS transistor NT2 that transmits the input signal SIN to the first node N1 in response to the clock signal CLK. In still other embodiments, as Figure 4As shown, the input circuit INC may include a second PMOS transistor PT2 and a second NMOS transistor NT2 connected in parallel. That is, the input circuit INC may be implemented as a CMOS gate. In addition, in some embodiments, the second PMOS transistor PT2 may include a gate receiving an inverted clock signal CLKB, a first terminal receiving an input signal SIN, and a second terminal connected to a first node N1. The second NMOS transistor NT2 may include a gate receiving a clock signal CLK, a first terminal receiving an input signal SIN, and a second terminal connected to the first node N1.

[0066] When the second PMOS transistor PT2 and the second NMOS transistor NT2 of the input circuit INC are turned off, the holding capacitor CHOLD may maintain the voltage of the first node N1. In some embodiments, as Figure 4 shown, the holding capacitor CHOLD may be connected between the line transmitting the high gate voltage VGH and the first node N1. That is, the holding capacitor CHOLD may include a first electrode connected to the line transmitting the high gate voltage VGH and a second electrode connected to the first node N1. In other embodiments, the holding capacitor CHOLD may be connected between the line transmitting the low gate voltage VGL and the first node N1.

[0067] The first inverter INV1 may generate the voltage of the second node N2 by inverting the voltage of the first node N1. For example, when the first node N1 has a high gate voltage VGH, the first inverter INV1 may provide a low gate voltage VGL to the second node N2, and when the first node N1 has a low gate voltage VGL, the first inverter INV1 may provide a high gate voltage VGH to the second node N2. In some embodiments, the first inverter INV1 may be implemented as a CMOS inverter that includes a third PMOS transistor PT3 and a third NMOS transistor NT3 connected in series between the line transmitting the high gate voltage VGH and the line transmitting the low gate voltage VGL. In addition, in some embodiments, the third PMOS transistor PT3 may include a gate connected to the first node N1, a first terminal connected to the line transmitting the high gate voltage VGH, and a second terminal connected to the second node N2. The third NMOS transistor NT3 may include a gate connected to the first node N1, a first terminal connected to the line transmitting the low gate voltage VGL, and a second terminal connected to the second node N2.

[0068] The second inverter INV2 can generate the voltage of the third node N3 by inverting the voltage of the second node N2. For example, when the second node N2 has a high gate voltage VGH, the second inverter INV2 can provide a low gate voltage VGL to the third node N3, and when the second node N2 has a low gate voltage VGL, the second inverter INV2 can provide a high gate voltage VGH to the third node N3. In some embodiments, the second inverter INV2 can be implemented as a CMOS inverter that includes a fourth PMOS transistor PT4 and a fourth NMOS transistor NT4 connected in series between a line for transmitting the high gate voltage VGH and a line for transmitting the low gate voltage VGL. Further, in some embodiments, the fourth PMOS transistor PT4 can include a gate connected to the second node N2, a first terminal connected to the line for transmitting the high gate voltage VGH, and a second terminal connected to the third node N3. The fourth NMOS transistor NT4 can include a gate connected to the second node N2, a first terminal connected to the line for transmitting the low gate voltage VGL, and a second terminal connected to the third node N3.

[0069] The third inverter INV3 can generate a carry signal CR by inverting the voltage of the second node N2. For example, when the second node N2 has a high gate voltage VGH, the third inverter INV3 can generate a carry signal CR with a low gate voltage VGL, and when the second node N2 has a low gate voltage VGL, the third inverter INV3 can generate a carry signal CR with a high gate voltage VGH. In some embodiments, the third inverter INV3 can be implemented as a CMOS inverter that includes a fifth PMOS transistor PT5 and a fifth NMOS transistor NT5 connected in series between a line for transmitting the high gate voltage VGH and a line for transmitting the low gate voltage VGL. Further, in some embodiments, the fifth PMOS transistor PT5 can include a gate connected to the second node N2, a first terminal connected to the line for transmitting the high gate voltage VGH, and a second terminal connected to a carry node NC for outputting the carry signal CR. The fifth NMOS transistor NT5 can include a gate connected to the second node N2, a first terminal connected to the line for transmitting the low gate voltage VGL, and a second terminal connected to the carry node NC.

[0070] The sixth PMOS transistor PT6 can transfer a high gate voltage VGH to the first node N1 in response to a global reset signal ESR. In some embodiments, when performing a power-on sequence of a display device, the global reset signal ESR may have a low level and may be provided to multiple stages of the driver simultaneously. Thus, the sixth PMOS transistors PT6 of multiple stages can transfer the high gate voltage VGH to the first node N1 during the power-on sequence, thereby stabilizing the voltages of the nodes N1, N2, N3, NC, and NO of multiple stages. Additionally, in some embodiments, the sixth PMOS transistor PT6 may include a gate that receives the global reset signal ESR, a first terminal connected to the line for transferring the high gate voltage VGH, and a second terminal connected to the first node N1. Although Figure 4 an example is shown in which the sixth PMOS transistor PT6 is connected to the line for transferring the high gate voltage VGH, in other embodiments, the sixth PMOS transistor PT6 may be connected to the line for transferring a low gate voltage VGL. In this case, the sixth PMOS transistor PT6 can transfer the low gate voltage VGL to the first node N1 during the power-on sequence.

[0071] The output control circuit OCC can selectively output the voltage of the third node N3 as an output signal OUT in response to an output enable signal OUT_EN. When the output enable signal OUT_EN has a high level or a high gate voltage VGH, the output control circuit OCC can output a low gate voltage VGL as the output signal OUT regardless of the voltage of the third node N3. However, when the output enable signal OUT_EN has a low level or a low gate voltage VGL, the output control circuit OCC can output the voltage of the third node N3 as the output signal OUT. In some embodiments, the output control circuit OCC may include a first PMOS transistor PT1 for outputting the voltage of the third node N3 as the output signal OUT, and a first NMOS transistor NT1 for outputting a low gate voltage VGL as the output signal OUT. Additionally, in some embodiments, the first PMOS transistor PT1 may include a gate that receives the output enable signal OUT_EN, a first terminal connected to the third node N3, and a second terminal connected to an output node NO for outputting the output signal OUT. The first NMOS transistor NT1 may include a gate that receives the output enable signal OUT_EN, a first terminal connected to the line for transferring the low gate voltage VGL, and a second terminal connected to the output node NO.

[0072] In some embodiments, as Figure 4As shown, each of the first to fifth NMOS transistors NT1 to NT5 may include not only a top gate but also a bottom gate, and the bottom gate may receive a second low gate voltage VGL2 different from the low gate voltage VGL. The second low gate voltage VGL2 applied to the bottom gate may be used as a body bias voltage for each of the first to fifth NMOS transistors NT1 to NT5, and the threshold voltage of each of the first to fifth NMOS transistors NT1 to NT5 may be adjusted by adjusting the second low gate voltage VGL2. For example, a second low gate voltage VGL2 lower than the low gate voltage VGL may be applied to the bottom gate BML (e.g., see Figure 3 ), and thus the threshold voltage of each of the first to fifth NMOS transistors NT1 to NT5 may be increased. In this case, the leakage current through the first to fifth NMOS transistors NT1 to NT5 may be reduced.

[0073] Hereinafter, an example of the operation of stage 200a of Figures 5 to 8 will be described with reference to Figure 4 .

[0074] Figure 5 is a timing diagram for describing an example of the operation of stage 200a of Figure 4 . Figure 6 is a circuit diagram for describing an example of the operation of stage 200a of Figure 4 in the first time period TP1 when the output enable signal OUT_EN has a low level. Figure 7 is a circuit diagram for describing an example of the operation of stage 200a of Figure 4 in the first time period TP1 when the output enable signal OUT_EN has a high level. Figure 8 is a circuit diagram for describing an example of the operation of stage 200a of Figure 4 in the second time period TP2.

[0075] Referring to Figure 4 and Figure 5 , when the clock signal CLK becomes a high gate voltage VGH after the input signal SIN has a high gate voltage VGH, stage 200a may start to output a carry signal CR having a high gate voltage VGH. Further, when outputting the carry signal CR having a high gate voltage VGH, or when the third node N3 has a high gate voltage VGH, stage 200a may selectively output an output signal OUT having a high gate voltage VGH according to the level of the output enable signal OUT_EN.

[0076] In the case where the output enable signal OUT_EN has a low gate voltage VGL, in a first time period TP1 in which the input signal SIN has a high gate voltage VGH and the clock signal CLK has a high gate voltage VGH, the stage 200a can output a carry signal CR having a high gate voltage VGH and an output signal OUT having a high gate voltage VGH.

[0077] For example, in the first time period TP1, as Figure 6 shown, the second NMOS transistor NT2 can be turned on in response to the clock signal CLK having a high gate voltage VGH, the second PMOS transistor PT2 can be turned on in response to the inverted clock signal CLKB having a low gate voltage VGL, and the second NMOS transistor NT2 and the second PMOS transistor PT2 can transfer the input signal SIN having a high gate voltage VGH to the first node N1. Accordingly, the first node N1 can have a high gate voltage VGH. In addition, the hold capacitor CHOLD can maintain the high gate voltage VGH at the first node N1.

[0078] The third PMOS transistor PT3 can be turned off in response to the high gate voltage VGH of the first node N1, the third NMOS transistor NT3 can be turned on in response to the high gate voltage VGH of the first node N1, and the third NMOS transistor NT3 can transfer the low gate voltage VGL to the second node N2. Accordingly, the second node N2 can have a low gate voltage VGL.

[0079] The fourth NMOS transistor NT4 can be turned off in response to the low gate voltage VGL of the second node N2, the fourth PMOS transistor PT4 can be turned on in response to the low gate voltage VGL of the second node N2, and the fourth PMOS transistor PT4 can transfer the high gate voltage VGH to the third node N3. Accordingly, the third node N3 can have a high gate voltage VGH.

[0080] In addition, the fifth NMOS transistor NT5 can be turned off in response to the low gate voltage VGL of the second node N2, the fifth PMOS transistor PT5 can be turned on in response to the low gate voltage VGL of the second node N2, and the fifth PMOS transistor PT5 can transfer the high gate voltage VGH to the carry node NC. Accordingly, a carry signal CR having a high gate voltage VGH can be output at the carry node NC.

[0081] In the case where the output enable signal OUT_EN has a low gate voltage VGL, as Figure 6As shown, the first NMOS transistor NT1 can be turned off in response to an output enable signal OUT_EN having a low gate voltage VGL, the first PMOS transistor PT1 can be turned on in response to an output enable signal OUT_EN having a low gate voltage VGL, and the first PMOS transistor PT1 can transfer the high gate voltage VGH of the third node N3 to the output node NO. Accordingly, an output signal OUT having a high gate voltage VGH can be output at the output node NO.

[0082] In other embodiments, in the case where the output enable signal OUT_EN has a high gate voltage VGH as shown by the dashed line in Figure 5 , in a first time period TP1 in which the input signal SIN has a high gate voltage VGH and the clock signal CLK has a high gate voltage VGH, stage 200a can output a carry signal CR having a high gate voltage VGH, but may not output an output signal OUT having a high gate voltage VGH. That is, stage 200a can output a low gate voltage VGL as the output signal OUT, as shown by the dashed line in Figure 5 .

[0083] For example, in the first time period TP1, as shown in Figure 7 , in the case where the output enable signal OUT_EN has a high gate voltage VGH, the first PMOS transistor PT1 can be turned off in response to the output enable signal OUT_EN having a high gate voltage VGH, the first NMOS transistor NT1 can be turned on in response to the output enable signal OUT_EN having a high gate voltage VGH, and the first NMOS transistor NT1 can transfer the low gate voltage VGL to the output node NO. Accordingly, although the third node N3 has a high gate voltage VGH, an output signal OUT having a high gate voltage VGH may not be output, and an output signal OUT having a low gate voltage VGL can be output at the output node NO.

[0084] As described above, stage 200a can output an output signal OUT having a high gate voltage VGH in response to an output enable signal OUT_EN having a low level (or a low gate voltage VGL), and can refrain from outputting an output signal OUT having a high gate voltage VGH in response to an output enable signal OUT_EN having a high level (or a high gate voltage VGH). Accordingly, a driver including stage 200a can selectively output the output signal OUT during a period in which the output enable signal OUT_EN has a low level, but can refrain from outputting the output signal OUT during a period in which the output enable signal OUT_EN has a high level. Accordingly, a driver including stage 200a can selectively output the output signal OUT to a corresponding panel area of a display panel. Accordingly, a driver including stage 200a can be applied to a display device that performs a multi-frequency driving (MFD) operation, in which the corresponding panel areas are driven at different driving frequencies.

[0085] In a second time period TP2 in which an input signal SIN has a low gate voltage VGL and a clock signal CLK has a high gate voltage VGH, stage 200a can output a carry signal CR having a low gate voltage VGL and an output signal OUT having a low gate voltage VGL.

[0086] For example, in the second time period TP2, as Figure 8 shown, a second NMOS transistor NT2 can be turned on in response to the clock signal CLK having a high gate voltage VGH, a second PMOS transistor PT2 can be turned on in response to an inverted clock signal CLKB having a low gate voltage VGL, and the second NMOS transistor NT2 and the second PMOS transistor PT2 can transfer the input signal SIN having a low gate voltage VGL to a first node N1. Accordingly, the first node N1 can have a low gate voltage VGL. In addition, a holding capacitor CHOLD can maintain the low gate voltage VGL at the first node N1.

[0087] A third NMOS transistor NT3 can be turned off in response to the low gate voltage VGL of the first node N1, a third PMOS transistor PT3 can be turned on in response to the low gate voltage VGL of the first node N1, and the third PMOS transistor PT3 can transfer a high gate voltage VGH to a second node N2. Accordingly, the second node N2 can have a high gate voltage VGH.

[0088] The fourth PMOS transistor PT4 can be turned off in response to the high gate voltage VGH of the second node N2. The fourth NMOS transistor NT4 can be turned on in response to the high gate voltage VGH of the second node N2, and the fourth NMOS transistor NT4 can transfer the low gate voltage VGL to the third node N3. Therefore, the third node N3 can have the low gate voltage VGL.

[0089] In addition, the fifth PMOS transistor PT5 can be turned off in response to the high gate voltage VGH of the second node N2. The fifth NMOS transistor NT5 can be turned on in response to the high gate voltage VGH of the second node N2, and the fifth NMOS transistor NT5 can transfer the low gate voltage VGL to the carry node NC. Therefore, a carry signal CR having the low gate voltage VGL can be output at the carry node NC.

[0090] As Figure 8 shown, when the output enable signal OUT_EN has the low gate voltage VGL, the first NMOS transistor NT1 can be turned off in response to the output enable signal OUT_EN having the low gate voltage VGL. The first PMOS transistor PT1 can be turned on in response to the output enable signal OUT_EN having the low gate voltage VGL, and the first PMOS transistor PT1 can transfer the low gate voltage VGL of the third node N3 to the output node NO. Therefore, an output signal OUT having the low gate voltage VGL can be output at the output node NO. In other embodiments, even when the output enable signal OUT_EN has the high gate voltage VGH, the first PMOS transistor PT1 can be turned off in response to the output enable signal OUT_EN having the high gate voltage VGH. The first NMOS transistor NT1 can be turned on in response to the output enable signal OUT_EN having the high gate voltage VGH. The first NMOS transistor NT1 can transfer the low gate voltage VGL to the output node NO, and thus an output signal OUT having the low gate voltage VGL can be output at the output node NO.

[0091] Figure 9 is a circuit diagram showing stage 200b of a driver according to an embodiment.

[0092] Referring Figure 9 , stage 200b of a driver according to an embodiment can include an input circuit INC, a holding capacitor CHOLD, a first inverter INV1, a second inverter INV2, a third inverter INV3, an output control circuit OCC, a sixth PMOS transistor PT6, and a PMOS boost buffer PBB. Except that stage 200b can further include a PMOS boost buffer PBB, Figure 9 stage 200b ofFigure 4 has substantially the same configuration and substantially the same operation as that of stage 200a.

[0093] When the voltage of the first node N1 is at a low level, the PMOS boost buffer PBB can output a low gate voltage VGL to the third node N3. In some embodiments, the PMOS boost buffer PBB may include: a boost capacitor CBOOST including a first electrode connected to a carry node NC of an output carry signal CR and a second electrode connected to a fourth node N4; a seventh PMOS transistor PT7 including a gate connected to a line for transmitting the low gate voltage VGL, a first terminal connected to the first node N1, and a second terminal connected to the fourth node N4; and an eighth PMOS transistor PT8 including a gate connected to the fourth node N4, a first terminal connected to the third node N3, and a second terminal connected to the line for transmitting the low gate voltage VGL.

[0094] When the voltage of the first node N1 changes from the high gate voltage VGH to the low gate voltage VGL, the seventh PMOS transistor PT7 can transfer the low gate voltage VGL of the first node N1 to the fourth node N4, and the voltage of the fourth node N4 can also change from the high gate voltage VGH to the low gate voltage VGL. When the voltage of the fourth node N4 changes from the high gate voltage VGH to the low gate voltage VGL, the eighth PMOS transistor PT8 can transfer the low gate voltage VGL to the third node N3, and the voltage of the third node N3 can also be reduced from the high gate voltage VGH to the low gate voltage VGL. In addition, when the voltage of the first node N1 changes from the high gate voltage VGH to the low gate voltage VGL while the carry node NC has the high gate voltage VGH, the first inverter INV1 can provide the high gate voltage VGH to the second node N2, the third inverter INV3 can provide the low gate voltage VGL to the carry node NC, and thus the voltage of the carry node NC can be reduced from the high gate voltage VGH to the low gate voltage VGL. When the voltage of the carry node NC connected to the first electrode of the boost capacitor CBOOST decreases, the voltage of the fourth node N4 connected to the second electrode of the boost capacitor CBOOST can also be reduced from the low gate voltage VGL to the boost low gate voltage lower than the low gate voltage VGL. This operation of reducing the voltage of the fourth node N4 to the boost low gate voltage lower than the low gate voltage VGL can be referred to as a boost operation. In other words, when the first node N1 and the third node N3 have the low gate voltage VGL, the voltage of the fourth node N4 can have the boost low gate voltage lower than the low gate voltage VGL. Since the fourth node N4 has the boost low gate voltage, the eighth PMOS transistor PT8 can be fully turned on, and the voltage of the third node N3 can be quickly reduced from the high gate voltage VGH to the low gate voltage VGL. In addition, in the case where the output enable signal OUT_EN has the low gate voltage VGL, the output signal OUT at the output node NO can also be quickly reduced from the high gate voltage VGH to the low gate voltage VGL.

[0095] Figure 10 is a circuit diagram showing stage 200c of a driver according to an embodiment. Figure 11 is for describing Figure 10 an example of the operation of stage 200c.

[0096] Reference Figure 10, the stage 200c of the driver according to the embodiment may include an input circuit INC, a holding capacitor CHOLD, a first inverter INV1, a second inverter INV2, a third inverter INV3, an output control circuit OCC', and a sixth PMOS transistor PT6. Except that the output control circuit OCC' may output the voltage of the third node N3 as an output signal OUT in response to an output enable signal OUT_EN' having a high level, and may output a low gate voltage VGL as an output signal OUT in response to an output enable signal OUT_EN' having a low level, Figure 10 the stage 200c may have substantially the same configuration and substantially the same operation as Figure 4 the stage 200a.

[0097] The output control circuit OCC' may include: a first NMOS transistor NT1', which outputs the voltage of the third node N3 as an output signal OUT when the output enable signal OUT_EN' has a high level; and a first PMOS transistor PT1', which outputs a low gate voltage VGL as an output signal OUT when the output enable signal OUT_EN' has a low level. In some embodiments, the first NMOS transistor NT1' may include a gate receiving the output enable signal OUT_EN', a first terminal connected to the third node N3, and a second terminal connected to an output node NO for outputting the output signal OUT. The first PMOS transistor PT1' may include a gate receiving the output enable signal OUT_EN', a first terminal connected to a line for transmitting the low gate voltage VGL, and a second terminal connected to the output node NO.

[0098] As Figure 11 shown, when a carry signal CR having a high gate voltage VGH is output, or when the third node N3 has a high gate voltage VGH, the stage 200c including the output control circuit OCC' may output an output signal OUT having a high gate voltage VGH in response to an output enable signal OUT_EN' having a high level, and may not output an output signal OUT having a high gate voltage VGH in response to an output enable signal OUT_EN' having a low level. Therefore, even if the third node N3 has a high gate voltage VGH, the stage 200c including the output control circuit OCC' may output a low gate voltage VGL as an output signal OUT in response to an output enable signal OUT_EN' having a low level as shown by the dashed line in Figure 11 Figure 11 ​As shown by the dashed line in [the figure]. Therefore, the driver including stage 200c can output the output signal OUT during the period in which the output enable signal OUT_EN' has a high level, but can refrain from outputting the output signal OUT during the period in which the output enable signal OUT_EN' has a low level. Therefore, the driver including stage 200c can selectively output the output signal OUT to the corresponding panel area of the display panel. Therefore, the driver including stage 200c can be applied to a display device that performs a multi-frequency driving (MFD) operation, in which the multi-frequency driving operation drives the corresponding panel areas at different driving frequencies.

[0099] Figure 12 is a circuit diagram showing stage 200d of a driver according to an embodiment.

[0100] Reference Figure 12 , stage 200d of the driver according to an embodiment may include an input circuit INC, a holding capacitor CHOLD, a first inverter INV1, a second inverter INV2, a third inverter INV3, an output control circuit OCC', a sixth PMOS transistor PT6, and a PMOS boost buffer PBB. Except that stage 200d may further include a PMOS boost buffer PBB, Figure 12 stage 200d of Figure 10 may have substantially the same configuration and substantially the same operation as stage 200c of

[0101] Figure 13 is a block diagram showing a display device 1000 according to an embodiment. Figure 14A is a diagram showing an example of a display panel 1010 in which a plurality of panel areas PR1, PR2, PR3, PR4 are driven at different driving frequencies. Figure 14B and Figure 14C are diagrams showing examples of gate signals applied to Figure 14A the display panel 1010.

[0102] Reference Figure 13 , the display device 1000 according to an embodiment may include: a display panel 1010 including a plurality of pixels PX; a data driver 1030 that provides data signals DS to the plurality of pixels PX; a gate driver 1050 that provides gate signals GS to the plurality of pixels PX; an emission driver 1070 that provides emission signals EM to the plurality of pixels PX; and a controller 1090 that controls the data driver 1030, the gate driver 1050, and the emission driver 1070.

[0103] The display panel 1010 may include data lines, gate lines, emission lines, and a plurality of pixels PX connected to these lines. In some embodiments, each pixel PX may include a light-emitting element, and the display panel 1010 may be a light-emitting display panel. In some embodiments, the light-emitting element may be an organic light-emitting diode (OLED). In other embodiments, the light-emitting element may be a nano light-emitting diode (NED), a quantum dot (QD) light-emitting diode, a micro light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element. In other embodiments, the display panel 1010 may be a liquid crystal display (LCD) panel or any other suitable display panel.

[0104] The data driver 1030 may generate a data signal DS based on the data control signal DCTRL and the output image data ODAT received from the controller 1090, and may provide the data signal DS to the plurality of pixels PX through the data lines. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. In some embodiments, the data driver 1030 and the controller 1090 may be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED) integrated circuit. In other embodiments, the data driver 1030 and the controller 1090 may be implemented as separate integrated circuits.

[0105] The gate driver 1050 may generate a gate signal GS based on the gate control signal GCTRL received from the controller 1090, and may sequentially provide the gate signal GS to the plurality of pixels PX through the gate lines on a line-by-line basis. The gate control signal GCTRL may include, but is not limited to, a gate start signal and a gate clock signal. In some embodiments, the gate control signal GCTRL may further include an output enable signal OUT_EN for selectively outputting the gate signal GS. In addition, in some embodiments, the gate driver 1050 may be Figure 1 including Figure 2 stage 200 of Figure 4 stage 200a of Figure 9 stage 200b of Figure 10 stage 200c of Figure 12 stage 200d of or Figure 13 driver 100 of. In addition, in some embodiments, as

[0106] The emission driver 1070 may generate an emission signal EM based on an emission control signal ECTRL received from the controller 1090, and may sequentially supply the emission signal EM to a plurality of pixels PX through emission lines on a line-by-line basis. The emission control signal ECTRL may include, but is not limited to, an emission start signal and an emission clock signal. In some embodiments, the emission control signal ECTRL may further include an output enable signal OUT_EN for selectively outputting the emission signal EM. Additionally, in some embodiments, the emission driver 1070 may be Figure 1 a driver 100 including Figure 2 stage 200 of Figure 4 stage 200a of Figure 9 stage 200b of Figure 10 stage 200c of or Figure 12 stage 200d of. Additionally, in some embodiments, as shown in Figure 13 , the emission driver 1070 may be integrated or formed in the display panel 1010. In other embodiments, the emission driver 1070 may be implemented as one or more integrated circuits.

[0107] The controller 1090 (e.g., a timing controller (TCON)) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In some embodiments, the input image data IDAT may be RGB image data including red image data, green image data, and blue image data. In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The controller 1090 may generate output image data ODAT, a data control signal DCTRL, a gate control signal GCTRL, and an emission control signal ECTRL based on the input image data IDAT and the control signal CTRL. The controller 1090 may control the operation of the data driver 1030 by providing the output image data ODAT and the data control signal DCTRL to the data driver 1030, may control the operation of the gate driver 1050 by providing the gate control signal GCTRL to the gate driver 1050, and may control the operation of the emission driver 1070 by providing the emission control signal ECTRL to the emission driver 1070.

[0108] The display device 1000 according to an embodiment may perform a multi-frequency driving (MFD) operation that drives a plurality of panel regions of the display panel 1010 at different driving frequencies. Further, in the display device 1000 according to an embodiment, in order to perform the MFD operation, at least one of the gate driver 1050 and the emission driver 1070 may be implemented as Figure 1 driver 100, and may selectively provide output signals (e.g., gate signal GS and / or emission signal EM) to the plurality of panel regions in response to an output enable signal OUT_EN.

[0109] For example, as Figure 14A shown, in the case where the gate driver 1050 is implemented as Figure 1 driver 100, a first panel region PR1 receiving a first gate signal GS1 is driven at a driving frequency of about 1 Hz, a second panel region PR2 receiving a second gate signal GS2 and a third gate signal GS3 is driven at a driving frequency of about 120 Hz, a third panel region PR3 receiving a fourth gate signal GS4 and a fifth gate signal GS5 is driven at a driving frequency of about 60 Hz, and a fourth panel region PR4 receiving a sixth gate signal GS6 is driven at a driving frequency of about 1 Hz. As Figure 14B and Figure 14C shown, the controller 1090 may generate an output enable signal OUT_EN such that the first gate signal GS1 is output in one frame period FP1 among one hundred and twenty frame periods FP1, FP2, FP3..., the second gate signal GS2 and the third gate signal GS3 are output in all one hundred and twenty frame periods FP1, FP2, FP3..., the fourth gate signal GS4 and the fifth gate signal GS5 are output in sixty frame periods FP1, FP3, etc. among one hundred and twenty frame periods FP1, FP2, FP3..., and the sixth gate signal GS6 is output in one frame period FP1 among one hundred and twenty frame periods FP1, FP2, FP3....

[0110] For example, in the case where the gate driver 1050 includes Figure 4 stage 200a of Figure 9 or Figure 14BAs shown, the controller 1090 may generate an output enable signal OUT_EN that is at a low level throughout the first frame period FP1, and the gate driver 1050 may output all gate signals GS1, GS2, GS3, …, GS4, GS5, …, and GS6 to the first panel region PR1 to the fourth panel region PR4 in response to the output enable signal OUT_EN. In the second frame period FP2, the controller 1090 may generate an output enable signal OUT_EN that is at a low level during the time period allocated to the second panel region PR2 within the second frame period FP2 and at a high level during the time periods allocated to the first panel region PR1, the third panel region PR3, and the fourth panel region PR4 within the second frame period FP2. In the second frame period FP2, in response to the output enable signal OUT_EN, the gate driver 1050 may output the gate signals GS2, GS3, … to the second panel region PR2, but may not output the gate signals GS1, GS4, GS5, …, and GS6 to the first panel region PR1, the third panel region PR3, and the fourth panel region PR4. Further, in the third frame period FP3, the controller 1090 may generate an output enable signal OUT_EN that is at a low level during the time periods allocated to the second panel region PR2 and the third panel region PR3 within the third frame period FP3 and at a high level during the time periods allocated to the first panel region PR1 and the fourth panel region PR4 within the third frame period FP3. In the third frame period FP3, in response to the output enable signal OUT_EN, the gate driver 1050 may output the gate signals GS2, GS3, …, GS4, GS5, … to the second panel region PR2 and the third panel region PR3, but may not output the gate signals GS1 and GS6 to the first panel region PR1 and the fourth panel region PR4. Further, in the one-hundred-and-twenty-first frame period FP121, the controller 1090 may again generate an output enable signal OUT_EN that is at a low level throughout the one-hundred-and-twenty-first frame period FP121, and the gate driver 1050 may output all gate signals GS1, GS2, GS3, …, GS4, GS5, …, and GS6 to the first panel region PR1 to the fourth panel region PR4 in response to the output enable signal OUT_EN. In this way, the gate driver 1050 may provide the gate signals GS1, GS2, GS3, …, GS4, GS5, …, and GS6 to the first panel region PR1, the second panel region PR2, the third panel region PR3, and the fourth panel region PR4 at frequencies of approximately 1 Hz, approximately 120 Hz, approximately 60 Hz, and approximately 1 Hz, respectively.

[0111] In another example, where the gate driver 1050 includes Figure 10of level 200c or Figure 12 in the case of level 200d of, as Figure 14C shown in, the controller 1090 may generate an output enable signal OUT_EN' that is high throughout the first frame period FP1, and the gate driver 1050 may output all of the gate signals GS1, GS2, GS3, …, GS4, GS5, …, and GS6 to the first panel region PR1 to the fourth panel region PR4 in response to the output enable signal OUT_EN'. In the second frame period FP2, the controller 1090 may generate an output enable signal OUT_EN' that is high during the time period allocated to the second panel region PR2 within the second frame period FP2 and low during the time periods allocated to the first panel region PR1, the third panel region PR3, and the fourth panel region PR4 within the second frame period FP2. In the second frame period FP2, in response to the output enable signal OUT_EN', the gate driver 1050 may output the gate signals GS2, GS3, … to the second panel region PR2, but may not output the gate signals GS1, GS4, GS5, …, and GS6 to the first panel region PR1, the third panel region PR3, and the fourth panel region PR4. Further, in the third frame period FP3, the controller 1090 may generate an output enable signal OUT_EN' that is high during the time periods allocated to the second panel region PR2 and the third panel region PR3 within the third frame period FP3 and low during the time periods allocated to the first panel region PR1 and the fourth panel region PR4 within the third frame period FP3. In the third frame period FP3, in response to the output enable signal OUT_EN', the gate driver 1050 may output the gate signals GS2, GS3, …, GS4, GS5, … to the second panel region PR2 and the third panel region PR3, but may not output the gate signals GS1 and GS6 to the first panel region PR1 and the fourth panel region PR4. Further, in the one hundred and twenty-first frame period FP121, the controller 1090 may again generate an output enable signal OUT_EN' that is high throughout the one hundred and twenty-first frame period FP121, and the gate driver 1050 may output all of the gate signals GS1, GS2, GS3, …, GS4, GS5, …, and GS6 to the first panel region PR1 to the fourth panel region PR4 in response to the output enable signal OUT_EN'. In this way, the gate driver 1050 may supply the gate signals GS1, GS2, GS3, …, GS4, GS5, …, and GS6 to the first panel region PR1, the second panel region PR2, the third panel region PR3, and the fourth panel region PR4 at frequencies of approximately 1 Hz, approximately 120 Hz, approximately 60 Hz, and approximately 1 Hz, respectively.

[0112] As described above, the gate driver 1050 and / or the emission driver 1070 according to an embodiment may selectively output a gate signal GS and / or an emission signal EM in response to an output enable signal OUT_EN. Accordingly, the gate driver 1050 and / or the emission driver 1070 according to an embodiment may be applicable to a display device 1000 that performs an MFD operation.

[0113] Figure 15 is a block diagram illustrating an electronic device 1100 including a display device 1160 according to an embodiment.

[0114] Reference Figure 15 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0115] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), or the like. The processor 1110 may be connected to other components via an address bus, a control bus, a data bus, and the like. In addition, in some embodiments, the processor 1110 may also be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0116] The memory device 1120 may store data for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device and / or at least one volatile memory device, at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0117] The storage device 1130 can be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 can be an input device such as a keyboard, keypad, mouse, touch screen, etc. and an output device such as a printer, speaker, etc. The power supply 1150 can supply power for the operation of the electronic device 1100. The display device 1160 can be connected to other components through a bus or other communication link.

[0118] In the display device 1160, at least one stage of a driver (e.g., a gate driver and / or an emission driver) can include both a PMOS transistor and an NMOS transistor. Therefore, a bootstrap operation may not be required or performed in this stage, and the power consumption of the driver and the display device 1160 can be reduced. In addition, at least one stage of the driver can selectively output an output signal in response to an output enable signal. Therefore, the driver according to an embodiment can be applied to the display device 1160 that performs a multi-frequency drive (MFD) operation.

[0119] The inventive concept can be applied to any display device 1160 and any electronic device 1100 including the display device 1160. For example, the inventive concept can be applied to a smart phone, a wearable electronic device, a tablet computer, a mobile phone, a television (TV) (e.g., a digital TV, a 3D TV, etc.), a personal computer (PC), a household appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.

[0120] The foregoing description is an example of embodiments and should not be construed as a limitation of the embodiments. Although several embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Accordingly, it will be understood that the foregoing description is an example of various embodiments and should not be construed as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A driver including multiple stages, at least one of the multiple stages including: An input circuit configured to transfer an input signal to a first node in response to at least one of a clock signal and an inverted clock signal; A holding capacitor configured to hold the voltage of the first node; A first inverter configured to generate the voltage of a second node by inverting the voltage of the first node; A second inverter configured to generate the voltage of a third node by inverting the voltage of the second node; A third inverter configured to generate a carry signal by inverting the voltage of the second node; And An output control circuit configured to selectively output the voltage of the third node as an output signal in response to an output enable signal, Wherein at least one of the first inverter, the second inverter, the third inverter, and the output control circuit includes a PMOS transistor and an NMOS transistor connected in series.

2. The driver according to claim 1, wherein A first active region of the PMOS transistor includes a material different from that of a second active region of the NMOS transistor.

3. The driver according to claim 2, wherein The first active region of the PMOS transistor includes polysilicon, and Wherein the second active region of the NMOS transistor includes an oxide semiconductor, an organic semiconductor, or amorphous silicon.

4. The driver according to claim 2, wherein The NMOS transistor includes a top gate located above the second active region and a bottom gate located below the second active region, and Wherein a low gate voltage is applied to a terminal of the NMOS transistor, and a second low gate voltage lower than the low gate voltage is applied to the bottom gate of the NMOS transistor.

5. The driver according to claim 1, wherein, The output control circuit outputs the low gate voltage as the output signal when the output enable signal is at a high level, and outputs the voltage of the third node as the output signal when the output enable signal is at a low level.

6. The driver according to claim 1, wherein The output control circuit includes: A first PMOS transistor including a gate receiving the output enable signal, a first terminal connected to the third node, and a second terminal connected to an output node for outputting the output signal; and A first NMOS transistor including a gate receiving the output enable signal, a first terminal connected to a line for transmitting the low gate voltage, and a second terminal connected to the output node.

7. The driver according to claim 1, wherein, The input circuit includes at least one of a second PMOS transistor and a second NMOS transistor. The second PMOS transistor includes a gate receiving the inverted clock signal, a first terminal receiving the input signal, and a second terminal connected to the first node. The second NMOS transistor includes a gate receiving the clock signal, a first terminal receiving the input signal, and a second terminal connected to the first node.

8. The driver according to claim 1, wherein, The holding capacitor includes a first electrode connected to a line for transmitting a high gate voltage and a second electrode connected to the first node.

9. The driver according to claim 1, wherein, The first inverter includes: A third PMOS transistor, including a gate connected to the first node, a first terminal connected to a line for transmitting a high gate voltage, and a second terminal connected to the second node; and A third NMOS transistor, including a gate connected to the first node, a first terminal connected to a line for transmitting a low gate voltage, and a second terminal connected to the second node.

10. The driver according to claim 1, wherein, The second inverter includes: A fourth PMOS transistor, including a gate connected to the second node, a first terminal connected to a line for transmitting a high gate voltage, and a second terminal connected to the third node; and A fourth NMOS transistor, including a gate connected to the second node, a first terminal connected to a line for transmitting a low gate voltage, and a second terminal connected to the third node.

11. The driver according to claim 1, wherein, The third inverter includes: A fifth PMOS transistor, including a gate connected to the second node, a first terminal connected to a line for transmitting a high gate voltage, and a second terminal connected to a carry node for outputting the carry signal; and A fifth NMOS transistor, including a gate connected to the second node, a first terminal connected to a line for transmitting a low gate voltage, and a second terminal connected to the carry node.

12. The driver according to claim 1, wherein, The at least one stage further includes: A sixth PMOS transistor, including a gate receiving a global reset signal, a first terminal connected to a line for transmitting a high gate voltage, and a second terminal connected to the first node.

13. The driver according to claim 1, wherein, The at least one stage further includes: A PMOS boost buffer, wherein the voltage of the first node has a low level, and the PMOS boost buffer is configured to output a low gate voltage to the third node.

14. The driver according to claim 13, wherein, The PMOS boost buffer includes: A boost capacitor, including a first electrode connected to a carry node for outputting the carry signal and a second electrode connected to a fourth node; A seventh PMOS transistor, including a gate connected to a line for transmitting the low gate voltage, a first terminal connected to the first node, and a second terminal connected to the fourth node; and An eighth PMOS transistor, including a gate connected to the fourth node, a first terminal connected to the third node, and a second terminal connected to the line for transmitting the low gate voltage.

15. The driver according to claim 1, wherein, The output control circuit outputs the voltage of the third node as the output signal when the output enable signal has a high level, and outputs a low gate voltage as the output signal when the output enable signal has a low level.

16. The driver according to claim 1, wherein, The output control circuit includes: A first NMOS transistor, including a gate receiving the output enable signal, a first terminal connected to the third node, and a second terminal connected to an output node for outputting the output signal; and A first PMOS transistor, including a gate receiving the output enable signal, a first terminal connected to a line for transmitting a low gate voltage, and a second terminal connected to the output node.

17. A driver including a plurality of stages, at least one stage of the plurality of stages including: A first PMOS transistor, including a gate for receiving an output enable signal, a first terminal connected to a third node, and a second terminal connected to an output node; A first NMOS transistor, including a gate for receiving the output enable signal, a first terminal connected to a line for transmitting a low gate voltage, and a second terminal connected to the output node; A second PMOS transistor, including a gate for receiving an inverted clock signal, a first terminal for receiving an input signal, and a second terminal connected to a first node; A second NMOS transistor, including a gate for receiving a clock signal, a first terminal for receiving the input signal, and a second terminal connected to the first node; A holding capacitor, including a first electrode connected to a line for transmitting a high gate voltage and a second electrode connected to the first node; A third PMOS transistor, including a gate connected to the first node, a first terminal connected to the line for transmitting the high gate voltage, and a second terminal connected to a second node; A third NMOS transistor, including a gate connected to the first node, a first terminal connected to the line for transmitting the low gate voltage, and a second terminal connected to the second node; A fourth PMOS transistor, including a gate connected to the second node, a first terminal connected to the line for transmitting the high gate voltage, and a second terminal connected to the third node; A fourth NMOS transistor, including a gate connected to the second node, a first terminal connected to the line for transmitting the low gate voltage, and a second terminal connected to the third node; A fifth PMOS transistor, including a gate connected to the second node, a first terminal connected to the line for transmitting the high gate voltage, and a second terminal connected to a carry node; A fifth NMOS transistor, including a gate connected to the second node, a first terminal connected to the line for transmitting the low gate voltage, and a second terminal connected to the carry node; And A sixth PMOS transistor, including a gate for receiving a global reset signal, a first terminal connected to the line for transmitting the high gate voltage, and a second terminal connected to the first node.

18. The driver according to claim 17, wherein, The at least one stage further includes: A boosting capacitor, including a first electrode connected to the carry node and a second electrode connected to a fourth node; A seventh PMOS transistor, including a gate connected to the line for transmitting the low gate voltage, a first terminal connected to the first node, and a second terminal connected to the fourth node; and An eighth PMOS transistor, including a gate connected to the fourth node, a first terminal connected to the third node, and a second terminal connected to the line for transmitting the low gate voltage.

19. A display device, including: A display panel, including a plurality of pixels; A data driver, configured to provide data signals to the plurality of pixels; A gate driver, configured to provide gate signals to the plurality of pixels; A emission driver, configured to provide emission signals to the plurality of pixels; And A controller, configured to control the data driver, the gate driver, and the emission driver, Wherein, at least one of the gate driver and the emission driver includes a plurality of stages, and Wherein, at least one of the plurality of stages includes: An input circuit configured to transmit an input signal to a first node in response to at least one of a clock signal and an inverted clock signal; A holding capacitor configured to hold the voltage of the first node; A first inverter configured to generate the voltage of a second node by inverting the voltage of the first node; A second inverter configured to generate the voltage of a third node by inverting the voltage of the second node; A third inverter configured to generate a carry signal by inverting the voltage of the second node; and An output control circuit configured to selectively output the voltage of the third node as an output signal in response to an output enable signal, Wherein, at least one of the first inverter, the second inverter, the third inverter, and the output control circuit includes a PMOS transistor and an NMOS transistor connected in series.

20. The display device according to claim 19, wherein, The display panel includes a first panel area driven at a first driving frequency and a second panel area driven at a second driving frequency lower than the first driving frequency, Wherein, in a first frame period, the controller generates the output enable signal having a first level during a first time period of the first frame period allocated to the first panel area and during a second time period of the first frame period allocated to the second panel area, such that the plurality of stages output the output signal to both the first panel area and the second panel area, and Wherein, in a second frame period, the controller generates the output enable signal having the first level during a third time period of the second frame period allocated to the first panel area, and generates the output enable signal having a second level different from the first level during a fourth time period of the second frame period allocated to the second panel area, such that the plurality of stages output the output signal to the first panel area and do not output the output signal to the second panel area.

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