Data compression method and logic chip
The characters to be sorted and the frequency of usage in the Hoffman compression algorithm are sorted through the storage module and comparison module in the logic chip to be sorted, and the encoding table is generated, which solves the problem of the Hoffman compression algorithm consumes a lot of resources in electronic devices and achieves more efficient data compression.
Patent Information
- Application Number
- CN202510399161.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-18
AI Technical Summary
The existing Hoffman compression algorithm consumes a lot of resources in electronic devices, making it difficult to efficiently implement data compression.
The storage module and comparison module in the logic chip sort the characters and usage frequency, and generate encoding tables to achieve data compression and release the resources of the software processor.
Improve data compression efficiency, reduce resource consumption of software processors, and improve data processing speed.
Smart Images
Figure CN120342403A_ABST
Abstract
Description
Technical Field
[0001] This specification relates to the field of electronic technologies, and in particular, to a data compression method and a logic chip. Background Art
[0002] With the development of information processing and network technologies, the amount of data in electronic devices is increasing. Electronic devices need to store more data in limited storage space and transmit more data at limited transmission speeds. Therefore, data compression algorithms are applied to electronic devices, and among them, the Huffman compression algorithm has extensive applications.
[0003] In the Huffman compression algorithm, a symbol encoding table is generated by frequency statistics and constructing a tree structure as the basis for data encoding and data decoding. When the above process is implemented based on software, the resource consumption is relatively large. Therefore, how to more efficiently implement data compression efficiency in electronic devices is an urgent problem for those skilled in the art to solve. Summary of the Invention
[0004] To overcome the problems existing in the related art, this specification provides a data compression method and a logic chip.
[0005] According to a first aspect of the embodiments of this specification, a data compression method is provided, which is applied to a logic chip and includes:
[0006] Write the obtained characters to be sorted and the usage frequencies of each character to be sorted into a storage module respectively, where the number of storage modules is not less than the number of characters to be sorted;
[0007] Compare the usage frequencies in two adjacent storage modules through a comparison module, and perform sorting according to the comparison result and a preset sorting rule until the characters to be sorted and the usage frequencies of each character to be sorted are recorded in the order of the storage modules. Each comparison module is connected to two adjacent storage modules one by one in a staggered manner, and the preset sorting rule is to exchange the characters to be sorted and the usage frequencies of the characters to be sorted in the storage module in descending order of usage frequency;
[0008] After the sorting is completed, obtain an encoding table through the characters to be sorted and the usage frequencies recorded by the storage module;
[0009] Implement data compression based on the encoding table.
[0010] Optionally, before writing the obtained characters to be sorted and the usage frequencies of each character to be sorted into the storage module respectively, it further includes:
[0011] Obtain the data to be processed, and record the usage frequencies of the characters to be sorted in the data to be processed through a counting module.
[0012] Optionally, after the sorting is completed, an encoding table is obtained based on the characters to be sorted and their usage frequencies recorded by the storage module, including:
[0013] After the sorting is completed, a tree structure is established based on the characters to be sorted and their usage frequencies recorded by the storage module;
[0014] An encoding table is generated according to the established tree structure.
[0015] Optionally, the N characters to be sorted correspond to N / 2 comparison modules, where N is a positive integer;
[0016] The comparison module includes a comparator and a selector;
[0017] The first pin of the comparator is connected to the output terminal of the selector, the second pin of the comparator is connected to the second storage module among three adjacent storage modules, and the two input terminals of the selector are respectively connected to the first storage module and the third storage module among three adjacent storage modules;
[0018] Through the strobe pin of the selector, the first storage module and the third storage module are switched on to compare the usage frequency stored in the first storage module with the usage frequency stored in the second storage module or compare the usage frequency stored in the second storage module with the usage frequency stored in the third storage module.
[0019] Optionally, the N characters to be sorted correspond to N - 1 comparison modules, and the comparison module is a comparator;
[0020] One comparison module is connected to two adjacent storage modules, and one pin of two adjacent comparison modules is connected to the same storage module.
[0021] According to the second aspect of the embodiments of the present specification, a logic chip is provided, including:
[0022] N storage modules, each storage module is used to store a character to be sorted and the usage frequency of the character to be sorted, where N is a positive integer and N is not less than the number of characters to be sorted;
[0023] M comparison modules are staggeredly connected to two adjacent storage modules, and are used to compare the usage frequencies obtained from two adjacent storage modules, and perform sorting according to the comparison results and a preset sorting rule until the characters to be sorted and the usage frequencies of each character to be sorted are recorded in the order of the storage modules. Each comparison module is staggeredly connected to two adjacent storage modules, and the preset sorting rule is to sequentially exchange the usage frequencies in the storage modules from large to small, where M is a positive integer;
[0024] A recording module, configured to record an encoding table obtained based on characters to be sorted and usage frequencies in a storage module, so as to implement data compression based on the encoding table.
[0025] Optionally, the logic chip further includes:
[0026] A counting module, configured to count the characters in the obtained data to be processed, and generate the usage frequencies of the characters to be sorted.
[0027] Optionally, the logic chip further includes:
[0028] A tree building module, configured to build a tree structure based on the characters to be sorted and the usage frequencies recorded by the storage module;
[0029] An encoding module, configured to generate an encoding table according to the built tree structure.
[0030] Optionally, the N characters to be sorted correspond to N / 2 comparison modules;
[0031] The comparison module includes a comparator and a selector;
[0032] A first pin of the comparator is connected to an output end of the selector, a second pin of the comparator is connected to a second storage module among three adjacent storage modules, and two input ends of the selector are respectively connected to a first storage module and a third storage module among three adjacent storage modules;
[0033] By a strobe pin of the selector, the first storage module and the third storage module are switched on to conduct, so as to compare the usage frequency stored in the first storage module and the usage frequency stored in the second storage module or compare the usage frequency stored in the second storage module and the usage frequency stored in the third storage module.
[0034] Optionally, the N characters to be sorted correspond to N - 1 comparison modules, and the comparison module is a comparator;
[0035] One comparison module is connected to two adjacent storage modules, and one pin of two adjacent comparison modules is connected to the same storage module.
[0036] The technical solutions provided in the embodiments of this specification may include the following beneficial effects:
[0037] In the embodiments of this specification, through the above structure, the sorting process of the characters to be sorted in the Huffman compression algorithm can be implemented by the logic chip of the hardware, the resources of the processor executing the software are released, and the data compression efficiency is improved.
[0038] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this specification. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] The drawings herein are incorporated into and form a part of this specification, showing embodiments in accordance with this specification, and are used together with the specification to explain the principles of this specification.
[0040] Figure 1 It is a schematic structural diagram of a logic chip involved in the present application;
[0041] Figure 2 It is a schematic structural diagram of another logic chip involved in the present application, wherein the comparison module includes a comparator and a selector;
[0042] Figure 3 It is a schematic structural diagram of another logic chip involved in the present application, wherein the comparison module serves as a comparator;
[0043] Figure 4 It is a schematic structural diagram of another logic chip involved in the present application, wherein the logic chip includes a counting module;
[0044] Figure 5 It is a schematic structural diagram of another logic chip involved in the present application, wherein the logic chip includes a tree-building module and an encoding module;
[0045] Figure 6 It is a flowchart of a data compression method involved in the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0046] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. On the contrary, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.
[0047] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. The singular forms "a", "the", and "said" used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0048] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".
[0049] This application provides a logic chip, as Figure 1 shown, including:
[0050] N storage modules, each storage module is used to store a character to be sorted and the usage frequency of the character to be sorted, where N is a positive integer and N is not less than the number of characters to be sorted;
[0051] M comparison modules, which are misaligned and connected to adjacent two storage modules, and are used to compare the usage frequencies obtained from the adjacent two storage modules, and perform sorting according to the comparison results and a preset sorting rule until the characters to be sorted and the usage frequencies of each character to be sorted are recorded in the order of the storage modules. Among them, each comparison module is misaligned and connected to adjacent two storage modules, and the preset sorting rule is to exchange the usage frequencies in the storage modules in descending order of usage frequency, where M is a positive integer;
[0052] A recording module, which is used to record an encoding table based on the characters to be sorted and the usage frequencies in the storage module, so as to implement data compression based on the encoding table.
[0053] The number N of the storage modules can be set according to requirements. For example, if the logic chip needs to compress 10 characters, then 10 storage modules need to be set. The spatial size of the storage module is related to the maximum value of the usage frequency that can be recorded and the length of the character. For example, it can be set that the maximum value of the usage frequency is 2^32, and the length of the character is 16 bits. Then the spatial size of the storage module needs to be set to at least 48-bit storage space for storage. Of course, there may be other information stored in the storage module, and the spatial size of the storage module can be set according to the length of the information that actually needs to be stored.
[0054] The comparison module needs to sort based on the usage frequency of the characters to be sorted in the storage module, so that characters with higher usage frequencies can have shorter lengths in the encoding table, and characters with lower usage frequencies can have longer lengths, thereby reducing the space occupied by high-usage-frequency characters and achieving the purpose of data compression. To achieve sorting at the hardware level, a comparison module needs to be connected to at least two adjacent storage modules, and different numbers of comparison modules can be set according to different comparison methods. A comparison module can also include a selector with a routing function, etc. After the comparison, the comparison module can send a swap signal to the two connected storage modules to prompt the two compared storage modules to swap the characters to be sorted and the corresponding usage frequencies of the characters to be sorted through the connected pins.
[0055] The preset sorting rule can be to sort in descending order of the identifiers of the storage modules or in ascending order of the identifiers of the storage modules, which can be set according to actual needs without limitation.
[0056] Due to the misaligned connection of two adjacent comparison modules, the misaligned connection means that one pin of each of the two adjacent comparison modules is connected to the same storage module, and the other pin of the two adjacent comparison modules is connected to different storage modules. This misaligned connection can enable the logic chip to compare the usage frequencies in N / 2 adjacent storage modules within one clock signal and achieve the interchange of characters and usage frequencies, so that the sorting of the characters to be sorted can be completed after at most N interchanges.
[0057] The preset sorting rule can affect the comparison method of the comparison module and the method of triggering the storage module to perform a swap. For example, when sorting in ascending order of the identifiers of the storage modules, during the sorting process, the character to be sorted with a higher usage frequency will be swapped to the side with a smaller identifier of the storage module. After the sorting is completed, the storage module with the smallest identifier records the character with the highest usage frequency. When sorting in descending order of the identifiers of the storage modules, during the sorting process, the character to be sorted with a higher usage frequency will be swapped to the side with a larger identifier of the storage module. After the sorting is completed, the storage module with the largest identifier records the character with the highest usage frequency. The specific setting can be based on actual needs without limitation.
[0058] After the sorting is achieved, the logic chip can implement data compression based on the encoding table by itself, or enable the processor to implement data compression based on the encoding table through interaction with the processor, which can be set according to actual needs. In the case where the logic chip needs to implement compression, a compression module can also be formed in the logic chip to compress the subsequent received data by obtaining the encoding table.
[0059] Regarding the implementation of the comparison module, in one possible implementation, such as Figure 2As shown, the N characters to be sorted correspond to N / 2 comparison modules. That is to say, M = N / 2. Since M needs to be a positive integer, when N is odd, M = floor(N / 2); when N is even, M = N / 2.
[0060] The comparison module includes a comparator and a selector.
[0061] The first pin (pin1) of the comparator is connected to the output terminal (out) of the selector. The second pin (pin2) of the comparator is connected to the second storage module among three adjacent storage modules. The two input terminals (in1, in2) of the selector are respectively connected to the first storage module and the third storage module among three adjacent storage modules.
[0062] Through the strobe pin (sel) of the selector, the first storage module and the third storage module are switched on to compare the usage frequency stored in the first storage module and the usage frequency stored in the second storage module, or to compare the usage frequency stored in the second storage module and the usage frequency stored in the third storage module.
[0063] In this implementation manner, the misaligned connection of adjacent comparison modules to the storage modules is realized through the selector. For two adjacent comparison modules, for example, the first pin of comparison module 1 is connected to storage module 1 and storage module 3 through selector 1, the first pin of comparison module 2 is connected to storage module 3 through selector 2, comparison module 1 is separately connected to storage module 2, and comparison module 2 is separately connected to storage module 4.
[0064] For the implementation of the comparison module, in another possible implementation manner, as Figure 3 shown, the N characters to be sorted correspond to N - 1 comparison modules. The comparison module is a comparator, and M = N - 1. Only the case where the number of characters to be sorted is odd is shown in the figure as an example, and it does not limit the solution.
[0065] One comparison module is connected to two adjacent storage modules, and one pin of two adjacent comparison modules is connected to the same storage module.
[0066] In this implementation manner, the misaligned connection of adjacent comparison modules to the storage modules is directly realized through the comparison module. Compared with the previous implementation manner, more comparison modules are set. For example, comparison module 1 is respectively connected to storage module 1 and storage module 2, comparison module 2 is respectively connected to storage module 2 and storage module 3, and comparison module 3 is respectively connected to storage module 3 and storage module 4.
[0067] When making comparisons, the single comparison module can make comparisons separately on one clock signal, and the double comparison module can make comparisons separately on the next clock signal to achieve interleaved comparison of the storage module and data exchange in the storage module.
[0068] The implementation in the logic chip can be achieved according to different requirements without limitation.
[0069] Optionally, the logic chip, as Figure 4 shown, further includes:
[0070] A counting module, used to count the characters in the acquired data to be processed and generate the usage frequency of the characters to be sorted.
[0071] In the implementation manner as Figure 1 shown, the logic chip can receive the characters to be sorted and their usage frequencies from the processor for comparison and sorting.
[0072] In the implementation manner as Figure 4 shown, the logic chip can count the characters based on the data to be processed received by itself, and output the recorded characters to be sorted and their usage frequencies to the storage module for recording, for the logic chip to perform sorting.
[0073] Optionally, the logic chip, as Figure 5 shown, further includes:
[0074] A tree-building module, used to build a tree structure through the characters to be sorted and their usage frequencies recorded by the storage module;
[0075] An encoding module, used to generate an encoding table according to the built tree structure.
[0076] In this implementation manner, the logic chip can also implement the establishment of the tree structure of the Huffman tree and the generation of the encoding table through hardware. After the logic chip completes sorting, it can send an enable signal to the tree-building module to trigger the tree-building module to obtain the characters to be sorted and their usage frequencies from N storage modules to construct the Huffman tree, and transmit the built tree structure to the encoding module to generate the encoding table for the logic chip to perform data compression or for the processor to implement data compression.
[0077] The above processes of counting, tree-building, and encoding can also be implemented by the processor and transmitted to the logic chip for use. Moreover, the above counting module, tree-building module, and encoding module can be wholly or partially included in the logic chip, and can be set according to actual requirements without limitation.
[0078] Correspondingly, the present application also provides a data compression method, as Figure 6 shown, applied to the logic chip, including:
[0079] S100. Write the obtained characters to be sorted and the usage frequencies of each character to be sorted into the storage module respectively.
[0080] Among them, the number of the storage modules is not less than the number of the characters to be sorted. That is to say, the number of the storage modules created in the logic chip needs to be set according to the requirements of the characters to be sorted.
[0081] The characters to be sorted and their usage frequencies can be formed by the self - counting of the logic chip or obtained from the processor connected to the logic chip, without limitation.
[0082] S101. Compare the usage frequencies in two adjacent storage modules through a comparison module, and perform sorting according to the comparison result and the preset sorting rule until the characters to be sorted and the usage frequencies of each character to be sorted are recorded in the order of the storage modules.
[0083] Among them, each comparison module is connected to two adjacent storage modules one by one in a staggered manner, and the preset sorting rule is to exchange the characters to be sorted and the usage frequencies of the characters to be sorted in the storage module in descending order of usage frequency.
[0084] S102. After completing the sorting, obtain a coding table through the characters to be sorted and the usage frequencies recorded by the storage module, so as to realize data compression based on the coding table.
[0085] After realizing the sorting, the logic chip can generate the coding table by itself, or enable the processor to generate the coding table through interaction with the processor.
[0086] In addition, the logic chip can perform data compression based on the coding table by itself, or enable the processor to perform data compression based on the coding table through interaction with the processor, which can be set according to actual needs.
[0087] Optionally, before step S100. Write the obtained characters to be sorted and the usage frequencies of each character to be sorted into the storage module respectively, it further includes:
[0088] S103. Obtain the data to be processed, and record the usage frequencies of the characters to be sorted in the data to be processed through a counting module.
[0089] That is, process and count the data to be processed through the logic chip.
[0090] Optionally, step S102. After completing the sorting, obtain a coding table through the characters to be sorted and the usage frequencies recorded by the storage module, includes:
[0091] S102A. After completing the sorting, establish a tree structure through the characters to be sorted and the usage frequencies recorded by the storage module;
[0092] S102B. Generate a coding table according to the established tree structure.
[0093] That is, the tree structure of the Huffman tree is established through a logic chip, and a coding table is generated based on the tree structure.
[0094] Optionally, the N characters to be sorted correspond to N / 2 comparison modules, where N is a positive integer.
[0095] The comparison module includes a comparator and a selector.
[0096] The first pin of the comparator is connected to the output end of the selector, the second pin of the comparator is connected to the second storage module among three adjacent storage modules, and the two input ends of the selector are respectively connected to the first storage module and the third storage module among three adjacent storage modules.
[0097] Through the strobe pin of the selector, the first storage module and the third storage module are switched on to conduct, so as to compare the usage frequency stored in the first storage module with the usage frequency stored in the second storage module or compare the usage frequency stored in the second storage module with the usage frequency stored in the third storage module.
[0098] Optionally, the N characters to be sorted correspond to N-1 comparison modules, and the comparison module is a comparator.
[0099] One comparison module is connected to two adjacent storage modules, and one pin of two adjacent comparison modules is connected to the same storage module.
[0100] The technical solution provided by the embodiments of this specification may include the following beneficial effects:
[0101] In the embodiments of this specification, through the above structure, the sorting process of the characters to be sorted in the Huffman compression algorithm can be realized through the logic chip of the hardware, releasing the resources of the processor executing the software and improving the data compression efficiency.
[0102] That is, on the one hand, the logic chip of the hardware takes over the processor to sort the characters, thereby releasing the processing resources of the processor and improving the efficiency of the processor in the electronic device. On the other hand, due to the structure of the logic chip, the sorting process has a higher speed. Whether the data compression is realized through the processor or through the logic chip subsequently, it can have a higher compression efficiency compared with the software implementation of the processor.
[0103] For the implementation processes of the functions and effects of each module in the above device, please refer to the implementation processes of the corresponding steps in the above method for details, and will not be elaborated here.
[0104] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to the descriptions in the method embodiments. The device embodiments described above are only illustrative. The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the objectives of the solutions in this specification. Those of ordinary skill in the art can understand and implement it without creative efforts.
[0105] The above describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0106] Those skilled in the art will readily conceive of other embodiments of this specification after considering the specification and practicing the invention herein. This specification is intended to cover any variations, uses, or adaptations of this specification, which follow the general principles of this specification and include the common general knowledge or conventional technical means in the technical field not claimed in this application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of this specification are pointed out by the following claims.
[0107] It should be understood that this specification is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of this specification is only limited by the appended claims.
[0108] The above are only the preferred embodiments of this specification and are not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification shall be included within the scope of protection of this specification.
Claims
1. A data compression method, characterized in that, Applied to a logic chip, including: Writing the obtained characters to be sorted and the usage frequencies of each character to be sorted into a storage module respectively, where the number of the storage modules is not less than the number of the characters to be sorted; Comparing the usage frequencies in two adjacent storage modules through a comparison module, and sorting according to the comparison result and a preset sorting rule until the characters to be sorted and the usage frequencies of each character to be sorted are recorded in the order of the storage modules. Each comparison module is connected to two adjacent storage modules in a staggered manner. The preset sorting rule is to exchange the characters to be sorted and the usage frequencies of the characters to be sorted in the storage module in descending order of usage frequency; After completion of sorting, obtaining a coding table based on the characters to be sorted and the usage frequencies recorded by the storage module; Implementing data compression based on the coding table.
2. The method according to claim 1, characterized in that, Before writing the obtained characters to be sorted and the usage frequencies of each character to be sorted into the storage module respectively, it further includes: Obtaining data to be processed, and recording the usage frequencies of the characters to be sorted in the data to be processed through a counting module.
3. The method according to claim 1, characterized in that The step of obtaining a coding table based on the characters to be sorted and the usage frequencies recorded by the storage module after completion of sorting includes: After completion of sorting, establishing a tree structure based on the characters to be sorted and the usage frequencies recorded by the storage module; Generating a coding table according to the established tree structure.
4. The method according to claim 1, wherein The N characters to be sorted correspond to N / 2 comparison modules, where N is a positive integer; The comparison module includes a comparator and a selector; A first pin of the comparator is connected to an output end of the selector, a second pin of the comparator is connected to a second storage module among three adjacent storage modules, and two input ends of the selector are respectively connected to a first storage module and a third storage module among the three adjacent storage modules; Through a strobe pin of the selector, switching to conduct the first storage module and the third storage module to compare the usage frequency stored in the first storage module and the usage frequency stored in the second storage module or compare the usage frequency stored in the second storage module and the usage frequency stored in the third storage module.
5. The method according to claim 1, wherein The N characters to be sorted correspond to N - 1 comparison modules, and the comparison module is a comparator; One comparison module is connected to two adjacent storage modules, and one pin of two adjacent comparison modules is connected to the same storage module.
6. A logic chip, characterized in that, Including: N storage modules, each storage module is used to store a character to be sorted and the usage frequency of the character to be sorted, where N is a positive integer and N is not less than the number of the characters to be sorted; M comparison modules, which are connected to two adjacent storage modules in a staggered manner, and are used to compare the usage frequencies obtained from two adjacent storage modules, and sort according to the comparison result and a preset sorting rule until the characters to be sorted and the usage frequencies of each character to be sorted are recorded in the order of the storage modules. Each comparison module is connected to two adjacent storage modules in a staggered manner. The preset sorting rule is to exchange the usage frequencies in the storage module in descending order of usage frequency, where M is a positive integer; A recording module, configured to record an encoding table obtained based on the characters to be sorted and their usage frequencies in a storage module, so as to implement data compression based on the encoding table.
7. The logic chip according to claim 6, characterized in that It further includes: A counting module, configured to count the characters in the data to be processed obtained, and generate the usage frequencies of the characters to be sorted.
8. The logic chip according to claim 6, wherein It further includes: A tree-building module, configured to build a tree structure based on the characters to be sorted and their usage frequencies recorded by the storage module; An encoding module, configured to generate an encoding table according to the built tree structure.
9. The logic chip according to claim 6, wherein The N characters to be sorted correspond to N / 2 comparison modules; The comparison module includes a comparator and a selector; A first pin of the comparator is connected to an output end of the selector, a second pin of the comparator is connected to a second storage module among three adjacent storage modules, and two input ends of the selector are respectively connected to a first storage module and a third storage module among three adjacent storage modules; Through a strobe pin of the selector, the first storage module and the third storage module are switched on to conduct, so as to compare the usage frequency stored in the first storage module with the usage frequency stored in the second storage module or compare the usage frequency stored in the second storage module with the usage frequency stored in the third storage module.
10. The logic chip according to claim 6, wherein The N characters to be sorted correspond to N-1 comparison modules, and the comparison module is a comparator; One comparison module is connected to two adjacent storage modules, and one pin of two adjacent comparison modules is connected to the same storage module.