Display device including separation portion on anode

Abstract

A display device including a separation portion on an anode is provided. The display device includes an emission region, a non-emission region surrounding the emission region, anodes spaced apart from each other, and separation portions respectively on the anodes and overlapping the non-emission region. Each of the anodes overlaps a corresponding one of the emission regions and the non-emission region.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0004183, filed with the Korean Intellectual Property Office on January 10, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a display device, and more particularly, to a display device including a separation part located on an anode. Background art

[0004] With the development of information technology, display devices are increasingly used as devices for transmitting information to users. Such display devices include display panels such as liquid crystal displays (LCDs) or organic light - emitting diode (OLED) displays. Summary of the invention

[0005] The display device includes an emission area, a non - emission area adjacent to the emission area, anodes spaced apart from each other, and separation parts respectively disposed on the anodes and overlapping the non - emission area. Each of the anodes overlaps a corresponding one in the emission area and the non - emission area.

[0006] Each of the separation parts can surround at least one surface of a corresponding one in the emission area.

[0007] Each of the separation parts can be adjacent to three surfaces of a corresponding one in the emission area.

[0008] The display device may further include a pixel - defining layer disposed on the anode and the separation part and surrounding the remaining one surface of each of the emission areas; a light - emitting structure disposed on the anode, the separation part, and the pixel - defining layer; and a cathode disposed on the light - emitting structure.

[0009] The separation part can have a conical structure.

[0010] The angle of the conical structure with respect to the plane of the anode can be at least 50°.

[0011] The thickness of the conical structure can be greater than the thickness of the light - emitting structure.

[0012] The separation part can have an inverted conical structure that becomes thicker as it is farther from the plurality of anodes.

[0013] The thickness of the inverted conical structure can be greater than the thickness of the light - emitting structure.

[0014] The light - emitting structure and / or the cathode can be separated by the separation part.

[0015] Each of the separation parts can surround four surfaces of a corresponding one in the emission area.

[0016] The display device may further include a pixel defining layer disposed on the anode and the separation part and surrounding the separation part; a light-emitting structure disposed on the anode, the separation part, and the pixel defining layer; and a cathode disposed on the light-emitting structure.

[0017] The separation part may have a conical structure.

[0018] The angle of the conical structure with respect to the plane of the plurality of anodes may be at least 50°.

[0019] The thickness of the conical structure may be greater than the thickness of the light-emitting structure.

[0020] The separation part may have an inverted conical structure that becomes thicker as it is farther from the plurality of anodes.

[0021] The thickness of the inverted conical structure may be greater than the thickness of the light-emitting structure.

[0022] The light-emitting structure and / or the cathode may be separated by the separation part.

[0023] The separation part may include an inorganic material.

[0024] The display device includes an emission region. A non-emission region is adjacent to the emission region. The anode overlaps both the emission region and the non-emission region. The light-emitting structure is disposed on the anode within the emission region. The separation part is disposed on the anode and separates the emission region from the non-emission region. The separation part has a shape that becomes wider as it is farther from the anode. The separation part is disposed at a discontinuity of the cathode and / or the light-emitting structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other features of the present disclosure will become more apparent by referring to the drawings in which embodiments of the present disclosure are described in detail, in which:

[0026] Figure 1 is a block diagram showing a display device according to an embodiment;

[0027] Figure 2 is a block diagram showing any one of the sub-pixels according to an embodiment Figure 1 of;

[0028] Figure 3 is a circuit diagram showing a sub-pixel according to an embodiment Figure 2 of;

[0029] Figure 4 is a plan view showing a display panel according to an embodiment Figure 1 of;

[0030] Figure 5 is an exploded perspective view showing a part of a display panel according to an embodiment Figure 4 of;

[0031] Figure 6 is a cross-sectional view showing a light-emitting structure according to an embodiment;

[0032] Figure 7 is a cross-sectional view showing a light-emitting structure according to an embodiment;

[0033] Figure 8 is a plan view showing a pixel according to an embodiment;

[0034] Figure 9 is a cross-sectional view taken along line I-I' of Figure 8 ;

[0035] Figure 10 is a cross-sectional view taken along line I-I' of Figure 8 ;

[0036] Figure 11 is a plan view showing an embodiment of a pixel;

[0037] Figure 12 is a cross-sectional view taken along line II-II' of Figure 11 ;

[0038] Figure 13 is a block diagram showing a display system according to an embodiment;

[0039] Figure 14 is a perspective view showing an application example of a display system of Figure 13 ; and

[0040] Figure 15 is a view showing a head-mounted display device worn by a user of Figure 14 ; DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] Hereinafter, various embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, parts necessary for understanding the operation according to the present disclosure are described, and descriptions of other parts may be omitted so as not to obscure the subject matter of the present disclosure. In addition, the present disclosure may be implemented in other forms and is not necessarily limited to the embodiments described herein. However, the embodiments described herein are provided to describe in sufficient detail so that those skilled in the art to which the present disclosure pertains can easily implement the technical spirit of the present disclosure.

[0042] Throughout the specification, where a part is "connected" to another part, such a situation includes not only the case where the part is "directly connected", but also the case where the part is "indirectly connected" with another element intervening therebetween. The terms used herein are for describing particular embodiments and are not necessarily intended to limit the present disclosure. Throughout the specification, unless otherwise stated, where a part "includes" something, it means that the part may also include another component without excluding the other component. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, and YZ). Here, "and / or" includes all combinations of one or more of the corresponding configurations.

[0043] Here, terms such as first and second may be used to describe various components, but these components are not necessarily limited by these terms. These terms are used to distinguish one component from another. Thus, without departing from the scope disclosed herein, the first component may be referred to as the second component within the scope.

[0044] Spatial relative terms, such as "below", "above", etc., may be used for descriptive purposes to describe the relationship between one element or feature and another (some) element or feature as shown in the drawings. In addition to the orientation depicted in the drawings, spatial relative terms are also intended to include different directions during use, operation, and / or manufacturing. For example, when the device shown in the drawings is turned upside down, the element depicted as being "below" other elements or features is positioned in the direction of being "above" other elements or features. Thus, in an embodiment, the term "below" may include both upward and downward directions. In addition, the device may face other directions (e.g., rotated 90 degrees or in other directions), and thus the spatial relative terms used herein are interpreted accordingly.

[0045] Various embodiments are described with reference to the drawings that schematically illustrate ideal embodiments. Therefore, it will be expected that the shape may change, for example, according to tolerances and / or manufacturing techniques. Thus, the embodiments disclosed herein are not necessarily to be construed as limited to the specific shapes shown, but should be construed as including, for example, shape changes that occur due to manufacturing. Although each drawing may represent one or more specific embodiments of the present disclosure, drawn to scale so that relative lengths, thicknesses, and angles can be inferred therefrom, it should be understood that the present invention is not necessarily limited to the relative lengths, widths, and angles shown. These values can be changed within the spirit and scope of the present disclosure, for example, to account for manufacturing limitations, etc.

[0046] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0047] Figure 1 is a block diagram showing a display device according to an embodiment.

[0048] Referring to Figure 1 , the display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0049] The display panel 110 includes sub-pixels SP. The sub-pixels SP may be electrically connected to the gate driver 120 through the first gate line GL1 to the m-th gate line GLm. The sub-pixels SP may be electrically connected to the data driver 130 through the first data line DL1 to the n-th data line DLn. Here, each of m and n is a natural number greater than 0.

[0050] Each of the sub-pixels SP may include at least one light-emitting element configured to generate light. Accordingly, each of the sub-pixels SP may generate light of a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more of the sub-pixels SP may configure one pixel PXL. For example, as Figure 1 shown, three sub-pixels SP may configure one pixel PXL.

[0051] The gate driver 120 is electrically connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with the timing of applying a data signal, and the like.

[0052] In an embodiment, first emission control lines EL1 to the m-th emission control lines ELm electrically connected to the sub-pixels SP in the row direction may also be provided. In this case, the gate driver 120 may include an emission control driver configured to control the first emission control lines EL1 to the m-th emission control lines ELm, and the emission control driver may operate under the control of the controller 150.

[0053] The gate driver 120 may be disposed on one side of the display panel 110. However, the embodiment is not necessarily limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically divided drivers, and these drivers may be disposed on one side of the display panel 110 and on the other side of the display panel 110 opposite to that side. As described above, the gate driver 120 may be disposed close to the display panel 110 and may have various shapes according to the embodiment.

[0054] The data driver 130 is electrically connected to sub-pixels SP arranged in the column direction through first data lines DL1 to nth data lines DLn. The data driver 130 receives image data DATA and a data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0055] The data driver 130 may apply data signals having gray-scale voltages corresponding to the image data DATA to the first data lines DL1 to nth data lines DLn using voltages from the voltage generator 140. When a gate signal is applied to each of the first gate lines GL1 to mth gate lines GLm, the data signals corresponding to the image data DATA may be applied to the first data lines DL1 to nth data lines DLn. Accordingly, the corresponding sub-pixels SP may generate light corresponding to the data signals. Accordingly, an image is displayed on the display panel 110.

[0056] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0057] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and supply the generated voltages to components of the display device 100. For example, the voltage generator 140 may generate a plurality of voltages by receiving an input voltage from an external source, adjusting the received voltage, and stabilizing the adjusted voltage.

[0058] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS, and may supply the generated first power supply voltage VDD and second power supply voltage VSS to the sub-pixels SP. The first power supply voltage VDD may have a relatively high voltage level, and the second power supply voltage VSS may have a voltage level lower than that of the first power supply voltage VDD. In other embodiments, the first power supply voltage VDD or the second power supply voltage VSS may be provided by an external device of the display device 100.

[0059] In addition, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixels SP. For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels SP, a predetermined reference voltage may be applied to the first data lines DL1 to nth data lines DLn, and the voltage generator 140 may generate such a reference voltage.

[0060] The controller 150 controls the overall operation of the display device 100. The controller 150 receives input image data IMG and a control signal CTRL for controlling display of the input image data IMG from an external source. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0061] The controller 150 may convert the input image data IMG so that the input image data IMG is suitable for the display device 100 or the display panel 110, and output the image data DATA. In an embodiment, the controller 150 may output the image data DATA by aligning the input image data IMG so that the input image data IMG is suitable for the sub-pixels SP of the row unit.

[0062] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted in one integrated circuit. Figure 1 As shown in , the data driver 130, the voltage generator 140 and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140 and the controller 150 may be functionally divided components in one driver integrated circuit DIC. In other embodiments, the data driver 130, the voltage generator 140 and / or the controller 150 may be provided as components different from the driver integrated circuit DIC.

[0063] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense a temperature near it and generate temperature data TEP indicating the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0064] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In an embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control the data signal and the first power supply voltage VDD and the second power supply voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0065] Figure 2 It is shown that according to the embodiment Figure 1 A block diagram of any one of the sub-pixels. Figure 2 in Figure 1 Among the sub-pixels SP, the sub-pixel SPij arranged in the i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (where j is an integer greater than or equal to 1 and less than or equal to n) is shown as an example.

[0066] Refer to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0067] The light-emitting element LD is electrically connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN. At this time, the first power supply voltage node VDDN is a node for transmitting Figure 1 the first power supply voltage VDD, and the second power supply voltage node VSSN is a node for transmitting Figure 1 the second power supply voltage VSS.

[0068] The anode AE of the light-emitting element LD may be electrically connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC, and the cathode CE of the light-emitting element LD may be electrically connected to the second power supply voltage node VSSN. For example, the anode AE of the light-emitting element LD may be electrically connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0069] The sub-pixel circuit SPC may be electrically connected to Figure 1 the i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm of Figure 1 the first emission control line EL1 to the m-th emission control line ELm of Figure 1 and the j-th data line DLj among the first data line DL1 to the n-th data line DLn of. The sub-pixel circuit SPC is configured to control the light-emitting element LD according to the signals received through these signal lines.

[0070] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In an embodiment, as Figure 2 shown in, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. As described above, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to the gate signals received through the corresponding sub-gate lines.

[0071] The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. In an embodiment, the i-th emission control line ELi may include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to the emission control signals received through the corresponding sub-emission control lines.

[0072] The sub-pixel circuit SPC can receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to a gate signal received through the first sub-gate line SGL1 and / or the second sub-gate line SGL2. The sub-pixel circuit SPC can adjust a current flowing from the first power voltage node VDDN to the second power voltage node VSSN through the light-emitting element LD according to the stored voltage in response to an emission control signal received through the i-th emission control line ELi. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0073] Figure 3 is a circuit diagram showing a sub-pixel according to an embodiment Figure 2 of.

[0074] Referring to Figure 3 , the sub-pixel SPij can include a sub-pixel circuit SPC and a light-emitting element LD.

[0075] The sub-pixel circuit SPC can be electrically connected to the i-th gate line GLi', the i-th emission control line ELi', and the j-th data line DLj. Compared with the i-th gate line GLi Figure 2 of, the i-th gate line GLi' can further include a third sub-gate line SGL3. Compared with the i-th emission control line ELi Figure 2 of, the i-th emission control line ELi' can include a first sub-emission control line SEL1 and a second sub-emission control line SEL2.

[0076] The sub-pixel circuit SPC can include a first transistor T1 to a sixth transistor T6, and a first capacitor C1 and a second capacitor C2.

[0077] The first transistor T1 is electrically connected between the first power voltage node VDDN and the first node N1. The gate of the first transistor T1 can be electrically connected to the second node N2, and thus the first transistor T1 can be turned on according to the voltage level of the second node N2. The first transistor T1 can be referred to as a driving transistor.

[0078] The second transistor T2 is electrically connected between the j-th data line DLj and the second node N2. The gate of the second transistor T2 can be electrically connected to the first sub-gate line SGL1, and thus the second transistor T2 can be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 can be referred to as a switching transistor.

[0079] The third transistor T3 is electrically connected between the first node N1 and the second node N2. The gate of the third transistor T3 can be electrically connected to the second sub-gate line SGL2, and thus the third transistor T3 can be turned on in response to the gate signal of the second sub-gate line SGL2.

[0080] The fourth transistor T4 is electrically connected between the first node N1 and the anode AE of the light-emitting element LD. The gate of the fourth transistor T4 may be electrically connected to the second sub-emission control line SEL2, and thus the fourth transistor T4 may be turned on in response to the emission control signal of the second sub-emission control line SEL2.

[0081] The fifth transistor T5 is electrically connected between the anode AE of the light-emitting element LD and the initialization voltage node VINTN. The initialization voltage node VINTN is configured to transmit an initialization voltage. In an embodiment, the initialization voltage may be provided by Figure 1 the voltage generator 140. In other embodiments, the initialization voltage may be provided by an external device of the display device 100 (refer to Figure 1 ). The gate of the fifth transistor T5 may be electrically connected to the third sub-gate line SGL3, and thus the fifth transistor T5 may be turned on in response to the gate signal of the third sub-gate line SGL3.

[0082] The sixth transistor T6 is electrically connected between the first power supply voltage node VDDN and the first transistor T1. The gate of the sixth transistor T6 may be electrically connected to the first sub-emission control line SEL1, and thus the sixth transistor T6 may be turned on in response to the emission control signal of the first sub-emission control line SEL1.

[0083] The first capacitor C1 is electrically connected between the second transistor T2 and the second node N2. The second capacitor C2 is electrically connected between the first power supply voltage node VDDN and the second node N2.

[0084] As described above, the sub-pixel circuit SPC may include the first transistor T1 to the sixth transistor T6, and the first capacitor C1 and the second capacitor C2. However, the embodiment is not necessarily limited thereto. The sub-pixel circuit SPC may be implemented as any of various types of circuits including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. According to an embodiment of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line Gli' and the number of sub-emission control lines included in the i-th emission control line Eli' may be variable.

[0085] The first transistor T1 to the sixth transistor T6 may be P-type transistors. Each of the first transistor T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). However, the embodiment is not necessarily limited thereto. For example, at least one of the first transistor T1 to the sixth transistor T6 may be replaced with an N-type transistor.

[0086] In an embodiment, the first transistor T1 to the sixth transistor T6 may include amorphous silicon semiconductors, single-crystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, etc.

[0087] The light-emitting element LD may include an anode AE, a cathode CE, and a light-emitting layer. The light-emitting layer may be disposed between the anode AE and the cathode CE. After the data signal transmitted through the j-th data line DLj is reflected in the voltage of the second node N2, when the emission control signals of the first sub-emission control line SEL1 and the second sub-emission control line SEL2 are enabled to be at a low level, the fourth transistor T4 and the sixth transistor T6 may be turned on. In addition, the first transistor T1 may be turned on according to the voltage of the second node N2, and thus current may flow from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light-emitting element LD may emit light according to the amount of the flowing current.

[0088] Figure 4 is a plan view of a Figure 1 display panel according to an embodiment.

[0089] Referring to Figure 4 , Figure 1 an embodiment of the display panel 110 (i.e., the display panel DP) may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA is disposed adjacent to the display area DA.

[0090] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0091] When the display panel DP is used as a display screen of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc., the display panel DP may be positioned very close to the user's eyes. In this case, a relatively high integration degree of the sub-pixels SP is required. In order to improve the integration degree of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on the substrate SUB which is a silicon substrate. The display device 100 (referring to Figure 1 ) including the display panel DP formed on the substrate SUB which is a silicon substrate may be referred to as a silicon-based organic light-emitting diode (OLEDoS) display device.

[0092] The sub-pixels SP are disposed in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix shape along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiment is not necessarily limited thereto. For example, the sub-pixels SP may be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a shape, where is the arrangement of the light-emitting areas manufactured by Samsung Corporation. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0093] Two or more of the plurality of sub-pixels SP can configure one pixel PXL.

[0094] Components for controlling the sub-pixels SP can be arranged in the non-display area NDA on the substrate SUB. For example, lines electrically connected to the sub-pixels SP can be arranged in the non-display area NDA, such as Figure 1 the first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn.

[0095] Figure 1 The gate driver 120, data driver 130, voltage generator 140, controller 150, and / or temperature sensor 160 of can be integrated in the non-display area NDA of the display panel DP. In an embodiment, Figure 1 the gate driver 120 of can be mounted on the display panel DP and can be arranged in the non-display area NDA. In other embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. In an embodiment, the temperature sensor 160 can be arranged in the non-display area NDA to sense the temperature of the display panel DP.

[0096] Pads PD are arranged in the non-display area NDA on the substrate SUB. The pads PD can be electrically connected to the sub-pixels SP through lines. For example, the pads PD can be electrically connected to the sub-pixels SP through the first data line DL1 to the n-th data line DLn.

[0097] The pads PD can interface the display panel DP to other components of the display device 100 (refer to Figure 1 ). In an embodiment, the voltages and signals required for the operation of the components included in the display panel DP can be provided from Figure 1 the driver integrated circuit DIC of through the pads PD. For example, the first data line DL1 to the n-th data line DLn can be electrically connected to the driver integrated circuit DIC through the pads PD. For example, the first power supply voltage VDD and the second power supply voltage VSS can be received from the driver integrated circuit DIC through the pads PD. For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be sent from the driver integrated circuit DIC to the gate driver 120 through the pads PD.

[0098] In an embodiment, the circuit board can be electrically connected to the pads PD using a conductive adhesive member such as an anisotropic conductive film. At this time, the circuit board can be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. The driver integrated circuit DIC can be mounted on the circuit board and can be electrically connected to the pads PD.

[0099] In an embodiment, the display area DA may have various shapes. The display area DA may have a closed-loop shape including straight edges and / or curved edges. For example, the display area DA may have shapes such as polygons, circles, semi-circles, and ellipses.

[0100] In an embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially circular. In an embodiment, the display panel DP may be bendable, foldable, or rollable to at least a noticeable extent without cracking or otherwise being damaged. In these cases, the display panel DP and / or the substrate SUB may include materials having flexible properties.

[0101] Figure 5 is an exploded perspective view showing a part of a Figure 4 display panel according to an embodiment. In Figure 5 , for clarity and concise description, a part of the display panel DP corresponding to Figure 4 two of the pixels PXL1 and PXL2 among the pixels PXL of

[0102] is schematically shown. The part of the display panel DP corresponding to the remaining pixels may be configured similarly. Figure 4 and Figure 5 , each of the first pixel PXL1 and the second pixel PXL2 may include first to third sub-pixels SP1 to SP3. However, the embodiment is not necessarily limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0103] In Figure 5 , when viewed from a third direction DR3 that intersects the first direction DR1 and the second direction DR2, the first to third sub-pixels SP1 to SP3 have a quadrilateral shape and have equal sizes to each other. However, the embodiment is not necessarily limited thereto. The first to third sub-pixels SP1 to SP3 may be modified to have various shapes.

[0104] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a packaging layer TFE, an optical function layer OFL, an outer coating OC, and a cover window CW.

[0105] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like. In other embodiments, the substrate SUB may include a glass substrate. In still other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0106] The pixel circuit layer PCL is disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer PCL may be used as at least a part of circuit elements, wires, etc. The conductive patterns may include copper (Cu), but the embodiments are not necessarily limited thereto.

[0107] The circuit elements may include sub-pixel circuits SPC for each of the first sub-pixel SP1 to the third sub-pixel SP3 (refer to Figure 2 ). The sub-pixel circuit SPC may include transistors and one or more capacitors. Each transistor may include a semiconductor portion including an active region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In an embodiment, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other in a direction perpendicular to the plane defined by the first direction DR1 and the second direction DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3 with an insulating layer therebetween.

[0108] The wires of the pixel circuit layer PCL may include signal wires electrically connected to each of the first sub-pixel SP1 to the third sub-pixel SP3, such as gate wires, emission control wires, data wires, etc. These wires may also include wires electrically connected to Figure 2 the first power voltage node VDDN. In addition, the wires may also include wires electrically connected to Figure 2 the second power voltage node VSSN.

[0109] The light-emitting element layer LDL may include an anode AE, a pixel defining layer PDL, a light-emitting structure EMS, and a cathode CE.

[0110] The anode AE can be disposed on the pixel circuit layer PCL. The anode AE can be in contact with the circuit elements of the pixel circuit layer PCL. The anode AE can include an opaque conductive material capable of reflecting light, but the embodiments are not necessarily limited thereto.

[0111] The pixel defining layer PDL is disposed on the anode AE. The pixel defining layer PDL can include openings OP that expose portions of each of the anodes AE. The openings OP of the pixel defining layer PDL can be understood as corresponding to the emission regions of the first sub-pixel SP1 to the third sub-pixel SP3, respectively.

[0112] In an embodiment, the pixel defining layer PDL can include an inorganic material. In this case, the pixel defining layer PDL can include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL can include silicon oxide (SiO x ) and silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL can include an organic material. However, the material of the pixel defining layer PDL is not necessarily limited thereto.

[0113] The light emitting structure EMS can be disposed on the anode AE exposed by the openings OP of the pixel defining layer PDL. The light emitting structure EMS can include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, a hole transport layer configured to transport holes, and the like.

[0114] In an embodiment, the light emitting structure EMS can fill the openings OP of the pixel defining layer PDL and can be disposed entirely on the pixel defining layer PDL. For example, the light emitting structure EMS can extend across the first sub-pixel SP1 to the third sub-pixel SP3. In this case, at least a portion of the layers in the light emitting structure EMS can be disconnected or bent at the boundaries between the first sub-pixel SP1 to the third sub-pixel SP3. However, the embodiments are not necessarily limited thereto. For example, the portions of the light emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 can be separated from each other, and each of these portions can be disposed in the openings OP of the pixel defining layer PDL.

[0115] The cathode CE can be disposed on the light emitting structure EMS. The cathode CE can extend across the first sub-pixel SP1 to the third sub-pixel SP3. As described above, the cathode CE can be provided as a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3.

[0116] The cathode CE can be a thin metal layer having a thickness sufficient to transmit light emitted from the light-emitting structure EMS. The cathode CE can be formed of a metal material or a transparent conductive material to have a relatively small thickness. In an embodiment, the cathode CE can include various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc oxide tin, and / or gallium tin oxide. In other embodiments, the cathode CE can include silver (Ag), magnesium (Mg), or a mixture thereof. However, the material of the cathode CE is not necessarily limited thereto.

[0117] It can be understood that any one of the anodes AE, an overlapping part of the light-emitting structure EMS therewith, and an overlapping part of the cathode CE therewith configure a light-emitting element LD (refer to Figure 2 ). For example, each of the light-emitting elements in the first sub-pixel SP1 to the third sub-pixel SP3 can include an anode AE, an overlapping part of the light-emitting structure EMS therewith, and an overlapping part of the cathode CE therewith. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode AE and electrons injected from the cathode CE can be transported into the light-emitting layer of the light-emitting structure EMS to recombine and form excitons, and when the excitons transition from the excited state to the ground state, light can be generated. The brightness of the light can be determined according to the amount of current flowing through the light-emitting layer. According to the configuration of the light-emitting layer, the wavelength range of the generated light can be determined.

[0118] The encapsulation layer TFE is disposed on the cathode CE. The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can prevent oxygen, moisture, and / or the like from penetrating into the light-emitting element layer LDL. In an embodiment, the encapsulation layer TFE can include a structure in which one or more inorganic layers and one or more organic layers are alternately stacked. For example, the inorganic layer can include silicon nitride, silicon oxide, silicon oxynitride (SiO x N y ), etc. For example, the organic layer can include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not necessarily limited thereto.

[0119] To improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE can further include a thin film containing aluminum oxide (AlO x ). The thin film including aluminum oxide can be positioned on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0120] A thin film including alumina can be formed by an atomic layer deposition (ALD) method. However, the embodiments are not necessarily limited thereto. The encapsulation layer TFE may also include a thin film formed of various materials suitable for improving the encapsulation efficiency.

[0121] The optical function layer OFL is disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0122] The color filter layer CFL is disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL is configured to filter the light emitted from the light-emitting structure EMS and selectively output light in a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF respectively corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, and each of the color filters CF may allow light in a wavelength range corresponding to the corresponding sub-pixel to pass through. For example, the color filter CF corresponding to the first sub-pixel SP1 may allow red light to pass through, the color filter CF corresponding to the second sub-pixel SP2 may allow green light to pass through, and the color filter CF corresponding to the third sub-pixel SP3 may allow blue light to pass through. At least a part of the plurality of color filters CF may be omitted according to the light emitted from the light-emitting structure EMS of each sub-pixel.

[0123] The lens array LA is disposed on the color filter layer CFL. The lens array LA may include lenses LS respectively corresponding to the first sub-pixel SP1 to the third sub-pixel SP3. Each of the lenses LS can improve the light output efficiency by outputting the light emitted from the light-emitting structure EMS to an intended path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the outer coating OC. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acrylic material. However, the material of the lens LS is not necessarily limited thereto.

[0124] In an embodiment, at least a part of the plurality of color filters CF of the color filter layer CFL and at least a part of the plurality of lenses LS of the lens array LA may be shifted in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2, compared to the opening OP of the pixel defining layer PDL. For example, in the central region of the display area DA, when observed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be aligned or overlapped with the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the central region of the display area DA, the opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In a region of the display area DA adjacent to the non-display area NDA, when observed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be shifted in the plane direction from the center of the corresponding opening OP of the pixel defining layer PDL. For example, in a region of the display area DA adjacent to the non-display area NDA, the opening OP of the pixel defining layer PDL may partially overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, at the center of the display area DA, the light emitted from the light emitting structure EMS can be effectively output in the normal direction of the display surface. At the outer region of the display area DA, the light emitted from the light emitting structure EMS can be effectively output in a direction inclined at a predetermined angle with respect to the normal direction of the display surface.

[0125] The outer coating OC may be disposed on the lens array LA. The outer coating OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The outer coating OC may include various materials suitable for protecting the underlying layers from foreign substances such as dust or moisture. For example, the outer coating OC may include an inorganic insulating layer and / or an organic insulating layer. For example, the outer coating OC may include an epoxy resin, but the embodiment is not necessarily limited thereto. The outer coating OC may have a refractive index lower than that of the lens array LA.

[0126] The cover window CW may be disposed on the outer coating OC. The cover window CW is configured to protect the underlying layers. The cover window CW may have a refractive index higher than that of the outer coating OC. The cover window CW may include glass, but the embodiment is not necessarily limited thereto. For example, the cover window CW may be an encapsulation glass configured to protect the components disposed thereunder. In other embodiments, the cover window CW may be omitted.

[0127] Figure 6 is a cross-sectional view showing a light emitting structure according to an embodiment.

[0128] Referring to Figure 6 , the light emitting structure EMS may have a series structure in which a first light emitting unit EU1 and a second light emitting unit EU2 are stacked.

[0129] Each of the first light-emitting unit EU1 and the second light-emitting unit EU2 may include at least one light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0130] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include a hole injection layer and / or a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. if necessary. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same or different configurations from each other.

[0131] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include an electron injection layer and / or an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. if necessary. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same or different configurations from each other.

[0132] A connection layer in the form of a charge generation layer CGL may be disposed between the first light-emitting unit EU1 and the second light-emitting unit EU2 to connect the first light-emitting unit EU1 and the second light-emitting unit EU2 to each other. In an embodiment, the charge generation layer CGL may have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include p-type dopants such as HAT-CN, TCNQ, and NDP-9, and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the embodiment is not necessarily limited thereto.

[0133] In an embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of different colors. The light emitted from each of the first light-emitting layer EML1 and the second light-emitting layer EML2 may be mixed and observed as white light. For example, the first light-emitting layer EML1 may generate blue light, and the second light-emitting layer EML2 may generate yellow light. In an embodiment, the second light-emitting layer EML2 may include a structure in which a first sub-light-emitting layer configured to generate red light and a second sub-light-emitting layer configured to generate green light are stacked. The red light and the green light may be mixed, and thus yellow light may be provided. In this case, an intermediate layer configured to perform a function of transporting holes and / or blocking electron transport may also be disposed between the first sub-light-emitting layer and the second sub-light-emitting layer.

[0134] In other embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of the same color.

[0135] In an embodiment, the light-emitting structure EMS may be formed by a method such as vacuum deposition, inkjet printing, etc., but the embodiment is not necessarily limited thereto.

[0136] Figure 7 is a cross-sectional view showing a light-emitting structure according to an embodiment.

[0137] Referring to Figure 7 , the light-emitting structure EMS' may have a series structure in which a first light-emitting unit EU1' to a third light-emitting unit EU3' are stacked.

[0138] Each of the first light-emitting unit EU1' to the third light-emitting unit EU3' may include a light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0139] Each of the first hole transport unit HTU1' to the third hole transport unit HTU3' may include a hole injection layer and / or a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. if necessary. The first hole transport unit HTU1' to the third hole transport unit HTU3' may have the same or different configurations from each other.

[0140] Each of the first electron transport unit ETU1' to the third electron transport unit ETU3' may include an electron injection layer and / or an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. if necessary. The first electron transport unit ETU1' to the third electron transport unit ETU3' may have the same or different configurations from each other.

[0141] A first charge generation layer CGL1' is disposed between the first light emitting unit EU1' and the second light emitting unit EU2'. A second charge generation layer CGL2' is disposed between the second light emitting unit EU2' and the third light emitting unit EU3'.

[0142] In an embodiment, the first light emitting layer EML1' to the third light emitting layer EML3' may generate lights of different colors. The lights emitted from each of the first light emitting layer EML1' to the third light emitting layer EML3' may be mixed and observed as white light. For example, the first light emitting layer EML1' may generate blue light, the second light emitting layer EML2' may generate green light, and the third light emitting layer EML3' may generate red light.

[0143] In other embodiments, two or more of the first light emitting layer EML1' to the third light emitting layer EML3' may generate lights of the same color.

[0144] Figure 8 is a plan view showing a pixel according to an embodiment.

[0145] Referring to Figure 8 , the pixel PXL may include a first sub-pixel SP1 to a third sub-pixel SP3 arranged in a first direction DR1.

[0146] The first sub-pixel SP1 may include a first emission area EMA1 and a non-emission area NEA adjacent to the first emission area EMA1. The second sub-pixel SP2 may include a second emission area EMA2 and a non-emission area NEA adjacent to the second emission area EMA2. The third sub-pixel SP3 may include a third emission area EMA3 and a non-emission area NEA adjacent to the third emission area EMA3.

[0147] The first emission area EMA1 may be from a light emitting structure EMS (referring to Figure 5) the region that emits light corresponding to the first sub-pixel SP1. The second emission region EMA2 may be the region that emits light from the portion of the light-emitting structure EMS corresponding to the second sub-pixel SP2. The third emission region EMA3 may be the region that emits light from the portion of the light-emitting structure EMS corresponding to the third sub-pixel SP3.

[0148] The pixel PXL may include a separation part SPR surrounding the corresponding first emission region EMA1 to third emission region EMA3. The separation part SPR may overlap with the non-emission region NEA.

[0149] The separation part SPR may surround at least one surface of each of the first emission region EMA1 to third emission region EMA3. As used herein, the phrase "surrounding at least one surface" means that the first element is close to the second element at one or more of its surfaces. For example, one of the separation parts SPR may surround three surfaces of the first emission region EMA1. Another of the separation parts SPR may surround three surfaces of the second emission region EMA2. Yet another of the separation parts SPR may surround three surfaces of the third emission region EMA3. In this case, one of the four surfaces of each of the first emission region EMA1 to third emission region EMA3 may be exposed. Different from Figure 8 this, three surfaces of the corresponding one of the first emission region EMA1 to third emission region EMA3 surrounded by each of the separation parts SPR may be changed. Similarly, the exposed first surface of the first emission region EMA1 to third emission region EMA3 may also be changed.

[0150] Figure 9 is a cross-sectional view taken along the Figure 8 line I-I'.

[0151] Referring to Figure 9 , a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB are provided.

[0152] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0153] The pixel circuit layer PCL is disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first sub-pixel SP1 to third sub-pixel SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be a sub-pixel circuit SPC of the first sub-pixel SP1 (refer to Figure 2)Any one of the transistors included in the first sub-pixel SP1, the transistor T_SP2 of the second sub-pixel SP2 can be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 can be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. In Figure 7 For clarity and concise description, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted. To the extent that the elements are not described in detail with reference to this figure, it can be understood that the element is at least similar to the corresponding element described elsewhere in the present disclosure.

[0154] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0155] The source region SRA and the drain region DRA may be disposed in the substrate SUB. A well WL formed by an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be spaced apart from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0156] The gate electrode GE may overlap with the channel region between the source region SRA and the drain region DRA, and may be disposed in the pixel circuit layer PCL. The gate electrode GE may be spaced apart from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0157] The plurality of layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers, and these conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA through a drain connection portion DRC passing through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA through a source connection portion SRC passing through one or more insulating layers.

[0158] As the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 are electrically connected to different circuit elements and / or lines, the transistor T_SP1 of the first sub-pixel SP1 can be provided as any one of the transistors of the first sub-pixel SP1.

[0159] Each of the transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 can be configured similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0160] As described above, the substrate SUB and the pixel circuit layer PCL may include the circuit elements of each of the first sub-pixel SP1 to the third sub-pixel SP3.

[0161] A via layer VIAL is disposed on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL and may have an overall flat surface. The via layer VIAL is configured to planarize the steps on the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiO x ), silicon nitride (SiN x ), and / or silicon carbonitride (SiCN), but the embodiments are not necessarily limited thereto.

[0162] A light-emitting element layer LDL is disposed on the via layer VIAL. The light-emitting element layer LDL may include a first reflective electrode RE1 to a third reflective electrode RE3, a planarization layer PLNL, a first anode AE1 to a third anode AE3, a pixel defining layer PDL, a light-emitting structure EMS, and a cathode CE.

[0163] On the via layer VIAL, the first reflective electrode RE1 to the third reflective electrode RE3 are respectively disposed in the first sub-pixel SP1 to the third sub-pixel SP3. Each of the first reflective electrode RE1 to the third reflective electrode RE3 may contact a circuit element disposed in the pixel circuit layer PCL through a via passing through the via layer VIAL.

[0164] The first reflective electrode RE1 to the third reflective electrode RE3 can be used as total reflection mirrors for reflecting the light emitted from the light-emitting structure EMS toward the display surface (or the cover window CW (refer to Figure 5 ). The first reflective electrode RE1 to the third reflective electrode RE3 may include a metal material suitable for reflecting light. The first reflective electrode RE1 to the third reflective electrode RE3 may include aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and / or an alloy of two or more materials selected from them, but the embodiments are not necessarily limited thereto.

[0165] In an embodiment, a connection electrode may be disposed under each of the first reflective electrode RE1 to the third reflective electrode RE3. The connection electrode can increase the electrical connection between the corresponding reflective electrode and the circuit element of the pixel circuit layer PCL. The connection electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiments are not necessarily limited thereto. In an embodiment, the corresponding reflective electrode may be positioned between multiple layers of the connection electrode.

[0166] The first reflective electrode RE1 to the third reflective electrode RE3 can be used as a total reflection mirror (for example, a mirror capable of total reflection), and the cathode CE can be used as a semi-reflective mirror (for example, a mirror capable of semi-reflection and semi-transmission). The light emitted from the light-emitting layer of the light-emitting structure EMS can be amplified by reciprocating at least partially between the corresponding reflective electrode and the cathode CE, and the amplified light can be output through the cathode CE. As described above, the distance between each reflective electrode and the cathode CE can be understood as the resonance distance of the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0167] To planarize the steps between the first reflective electrode RE1 to the third reflective electrode RE3, a planarization layer PLNL can be disposed on the via layer VIAL and the first reflective electrode RE1 to the third reflective electrode RE3. The planarization layer PLNL can generally cover the first reflective electrode RE1 to the third reflective electrode RE3 and the via layer VIAL, and can have a flat surface. In an embodiment, the planarization layer PLNL can be omitted.

[0168] On the planarization layer PLNL, first anodes AE1 to third anodes AE3 that overlap with the first reflective electrode RE1 to the third reflective electrode RE3 respectively are disposed. When observed in the third direction DR3, the first anodes AE1 to third anodes AE3 can have a shape similar to that of Figure 8 the first emission regions EMA1 to third emission regions EMA3. The first anodes AE1 to third anodes AE3 are electrically connected to the first reflective electrode RE1 to the third reflective electrode RE3 respectively. The first anode AE1 can be electrically connected to the first reflective electrode RE1 through a first via VIA1 passing through the planarization layer PLNL. The second anode AE2 can be electrically connected to the second reflective electrode RE2 through a second via VIA2 passing through the planarization layer PLNL. The third anode AE3 can be electrically connected to the third reflective electrode RE3 through a third via VIA3 passing through the planarization layer PLNL.

[0169] In an embodiment, the first anodes AE1 to third anodes AE3 can include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x )), indium gallium zinc oxide (IGZO), and / or indium tin zinc oxide (ITZO). However, the materials of the first anodes AE1 to third anodes AE3 are not necessarily limited thereto. For example, the first anodes AE1 to third anodes AE3 can include titanium nitride.

[0170] The separation part SPR can be arranged on the anode AE. The corresponding separation part SPR can be arranged on the corresponding anode AE overlapping with the non-emitting area NEA. For example, one of the separation parts SPR can be arranged on the first anode AE1 overlapping with the non-emitting area NEA. Another separation part SPR can be arranged on the second anode AE2 overlapping with the non-emitting area NEA. Still another separation part SPR can be arranged on the third anode AE3 overlapping with the non-emitting area NEA. For example, the separation part SPR can be arranged not to overlap with the first emission area EMA1 to the third emission area EMA3 and does not affect the light-emitting area. In addition, the separation part SPR can be easily formed in a desired shape on the anode AE without being affected by the lower structure. For example, the separation part SPR can be formed by chemical vapor deposition (CVD), but the implementation is not necessarily limited to this.

[0171] As described above, the corresponding separation part SPR can be arranged on the anode AE to surround three surfaces of each of the first emission area EMA1 to the third emission area EMA3. In the I-I' cross-section, one separation part SPR can be arranged on each of the anodes AE.

[0172] In an embodiment, the separation part SPR can include an inorganic material. For example, the separation part SPR can include an inorganic material such as SiN x , SiO x or SiON, but the implementation is not necessarily limited to this.

[0173] In an embodiment, the separation part SPR can have a tapered structure. The separation part SPR with a tapered structure can cause the formation of a discontinuous area DSA where the light-emitting structure EMS and / or the cathode CE is disconnected or bent. The cone angle a1 of the separation part SPR with a tapered structure can be at least 50° relative to the surface from which the separation part SPR extends (i.e., the plane of the anode AE). The thickness t1 of the separation part SPR with a tapered structure can be greater than the thickness t2 of the light-emitting structure EMS. When the standard of the separation part SPR with a tapered structure meets the above conditions, the above-mentioned discontinuous area DSA can be effectively formed.

[0174] The pixel defining layer PDL can be arranged on a part of the separation part SPR and a part of the anode AE. In addition, the pixel defining layer PDL can be arranged on the planarization layer PLNL. The pixel defining layer PDL can overlap with the non-emitting area NEA.

[0175] The pixel defining layer PDL can, together with the separation part SPR, define the first emission area EMA1 to the third emission area EMA3 overlapping with the corresponding first anode AE1 to the third anode AE3. In the plane, the pixel defining layer PDL can surround the separation part SPR. In addition, the pixel defining layer PDL can surround Figure 8One surface among the four surfaces of each of the first emission area EMA1 to the third emission area EMA3 shown in [Figure X] that is not surrounded by the separation part SPR.

[0176] The pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x ) and / or silicon nitride (SiN x ). For example, the pixel defining layer PDL may include a first inorganic insulating layer to a third inorganic insulating layer stacked in sequence, and the first inorganic insulating layer to the third inorganic insulating layer may include silicon nitride, silicon oxide, and silicon nitride respectively, but the embodiments are not necessarily limited thereto.

[0177] The light emitting structure EMS may be disposed on the anode AE exposed by the pixel defining layer PDL and the separation part SPR. Although Figure 9 not shown in [Figure X], the light emitting structure EMS may be disposed on the anode AE exposed by the corresponding separation part SPR. The light emitting structure EMS may be disposed entirely across the first sub-pixel SP1 to the third sub-pixel SP3. For example, the light emitting structure EMS may extend along the pixel defining layer PDL and may be disposed on the planarization layer PLNL.

[0178] The light emitting structure EMS may be disconnected or bent on the separation part SPR. For example, the charge generation layer CGL (refer to Figure 6 ) included in the light emitting structure EMS may be disconnected or bent in the discontinuous region DSA caused by the separation part SPR. Therefore, when the display panel DP (refer to Figure 4 ) operates, the current flowing from each of the first sub-pixel SP1 to the third sub-pixel SP3 to the adjacent sub-pixel through the charge generation layer CGL can be reduced.

[0179] The cathode CE may be disposed on the light emitting structure EMS. The cathode CE may be commonly provided to the first sub-pixel SP1 to the third sub-pixel SP3. The cathode CE may be used as a semi-reflective mirror that partially transmits and partially reflects the light emitted from the light emitting structure EMS. According to an embodiment, the cathode CE may be disconnected or bent on the separation part SPR. For example, the cathode CE may be disconnected or bent in the discontinuous region DSA caused by the separation part SPR.

[0180] Figure 10 is another cross-sectional view taken along the line I-I' of Figure 8 . Regarding Figure 10 , the description of the content that is repeated with Figure 9 is simplified or omitted. To the extent that the elements are not described in detail with reference to this figure, it can be understood that the elements are at least similar to the corresponding elements described elsewhere in the present disclosure.

[0181] Refer to Figure 10, in an embodiment, the separation part SPR may have an inverted conical structure. The separation part SPR with an inverted conical structure may cause the formation of a discontinuous area DSA where the light-emitting structure EMS and / or the cathode CE are disconnected or bent. The inverted cone angle a2 of the separation part SPR with an inverted conical structure may be greater than 90°. The thickness t1' of the separation part SPR with an inverted conical structure may be greater than the thickness t2 of the light-emitting structure EMS. The thickness t1' of the separation part SPR with an inverted conical structure may be equal to or different from the thickness t1 of the separation part SPR with a conical structure (refer to Figure 9 ). When the criteria of the separation part SPR with an inverted conical structure meet the above conditions, the above discontinuous area DSA can be effectively formed.

[0182] Figure 11 is a plan view showing another embodiment of a pixel. Regarding Figure 11 , descriptions of content that duplicates with Figure 8 are simplified or omitted. To the extent that elements are not described in detail with reference to this figure, it can be understood that the elements are at least similar to the corresponding elements described elsewhere in the present disclosure.

[0183] Referring to Figure 11 , the pixel PXL may include a separation part SPR' surrounding the corresponding first emission area EMA1 to the third emission area EMA3. The separation part SPR' may overlap with the non-emission area NEA.

[0184] In an embodiment, each of the separation parts SPR' may surround four surfaces (or the entire surface) of each of the first emission area EMA1 to the third emission area EMA3. For example, one of the separation parts SPR' may surround the four surfaces of the first emission area EMA1. Another of the separation parts SPR' may surround the four surfaces of the second emission area EMA2. Still another of the separation parts SPR' may surround the four surfaces of the third emission area EMA3. In this case, the four surfaces of the first emission area EMA1 to the third emission area EMA3 may be completely surrounded by the separation part SPR' and may not be exposed.

[0185] Figure 12 is a cross-sectional view taken along the line II-II' of Figure 11 . Regarding Figure 12 , descriptions of content that duplicates with Figure 9 are simplified or omitted. To the extent that elements are not described in detail with reference to this figure, it can be understood that the elements are at least similar to the corresponding elements described elsewhere in the present disclosure.

[0186] Referring to Figure 12, the separation part SPR' can be arranged on the anode AE. The corresponding separation part SPR' can be arranged on the corresponding anode AE overlapping with the non-emitting region NEA. For example, one of the separation parts SPR' can be arranged on the first anode AE1 overlapping with the non-emitting region NEA. Another one of the separation parts SPR' can be arranged on the second anode AE2 overlapping with the non-emitting region NEA. Still another one of the separation parts SPR' can be arranged on the third anode AE3 overlapping with the non-emitting region NEA. For example, the separation part SPR' can be arranged not to overlap with the first emission region EMA1 to the third emission region EMA3 and can not affect the light-emitting area. In addition, the separation part SPR' can be easily formed in the desired shape on the anode AE without being affected by the lower structure. For example, the separation part SPR' can be formed by chemical vapor deposition (CVD), but the implementation is not necessarily limited to this.

[0187] As described above, the corresponding separation part SPR' can be arranged on the anode AE to surround each of the four surfaces of the first emission region EMA1 to the third emission region EMA3. In the II-II' cross-section, two separation parts SPR' can be arranged on each of the anodes AE.

[0188] In an embodiment, the separation part SPR' can include an inorganic material. For example, the separation part SPR' can include an inorganic material such as SiN x , SiO x or SiON, but the implementation is not necessarily limited to this.

[0189] In an embodiment, the separation part SPR' can have a tapered structure. The separation part SPR' with a tapered structure can cause the formation of a discontinuous region DSA where the light-emitting structure EMS and / or the cathode CE is disconnected or bent. The cone angle a1 of the separation part SPR' with a tapered structure can be at least 50°. The thickness t1 of the separation part SPR' with a tapered structure can be greater than the thickness t2 of the light-emitting structure EMS. When the standard of the separation part SPR' with a tapered structure meets the above conditions, the above-mentioned discontinuous region DSA can be effectively formed. The separation part SPR' can have an inverted tapered structure as shown in Figure 10 .

[0190] The pixel definition layer PDL can be arranged on a part of the separation part SPR' and a part of the anode AE. In addition, the pixel definition layer PDL can be arranged on the planarization layer PLNL. The pixel definition layer PDL can overlap with the non-emitting region NEA. In the plane, the pixel definition layer PDL can completely surround the separation part SPR'.

[0191] The light-emitting structure EMS can be disposed on the anode AE exposed by the corresponding separation part SPR'. In addition, the light-emitting structure EMS can be disposed on the separation part SPR', can extend along the pixel-defining layer PDL, and can be disposed on the planarization layer PLNL.

[0192] The light-emitting structure EMS can be disconnected or bent on the separation part SPR'. For example, the charge generation layer CGL (refer to Figure 6 ) included in the light-emitting structure EMS can be disconnected or bent in the discontinuous region DSA caused by the separation part SPR'. Therefore, when the display panel DP (refer to Figure 4 ) operates, the current flowing from each of the first sub-pixel SP1 to the third sub-pixel SP3 to the adjacent sub-pixel through the charge generation layer CGL can be reduced. In particular, since the separation part SPR' is disposed to surround the four surfaces of each of the first emission region EMA1 to the third emission region EMA3, the possibility of current leakage to the adjacent sub-pixels can be further reduced.

[0193] Figure 13 is a block diagram showing a display system according to an embodiment.

[0194] Refer to Figure 13 , the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220.

[0195] The processor 1100 can perform various tasks and calculations. In an embodiment, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 through a bus system and can control other components.

[0196] In Figure 13 , the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 can be connected to the first display device 1210 through a first channel CH1 and can be connected to the second display device 1220 through a second channel CH2.

[0197] Through the first channel CH1, the processor 1100 can send first image data IMG1 and a first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can be configured similarly to the display device 100 described with reference to Figure 1 . In this case, the first image data IMG1 and the first control signal CTRL1 can be respectively provided as the input image data IMG and the control signal CTRL of Figure 1 .

[0198] Through a second channel CH2, the processor 1100 may send second image data IMG2 and a second control signal CTRL2 to a second display device 1220. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 may be configured similarly to the display device 100 described with reference to Figure 1 . In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as the input image data IMG and the control signal CTRL, respectively, of Figure 1 .

[0199] The display system 1000 may include a computing system providing an image display function, such as a portable computer (e.g., a tablet personal computer (PC) and an ultra-mobile personal computer (UMPC)), a mobile phone, a smart phone, a smart watch, a watch phone, a portable multimedia player (PMP), and a navigation device. In addition, the display system 1000 may include a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and / or an augmented reality (AR) device.

[0200] Figure 14 is a perspective view showing an application example of the display system of Figure 13 .

[0201] With reference to Figure 14 , Figure 13 the display system 1000 may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device wearable on a user's head.

[0202] The head-mounted display device 2000 may include a head-mounted band 2100 and a display device accommodation housing 2200. The head-mounted band 2100 may be connected to the display device accommodation housing 2200. The head-mounted band 2100 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the user's head. The horizontal band may surround the side portion of the user's head, and the vertical band may surround the upper portion of the user's head. However, the embodiments are not necessarily limited thereto. For example, the head-mounted band 2100 may be implemented in the form of a spectacle frame, a helmet form, etc.

[0203] The display device accommodation housing 2200 may accommodate Figure 13 the first display device 1210 and the second display device 1220 of Figure 13 . The display device accommodation housing 2200 may also accommodate

[0204] Figure 15 is a view showing Figure 14 the head-mounted display device worn by the user.

[0205] Reference Figure 15 , in the head-mounted display device 2000, a first display panel DP1 of a first display device 1210 (reference Figure 13 ) and a second display panel DP2 of a second display device 1220 (reference Figure 13 ) are arranged. The head-mounted display device 2000 may further include one or more lenses LLNS and RLNS.

[0206] Within the display device housing 2200, the right-eye lens RLNS may be arranged between the first display panel DP1 and the user's right eye. Within the display device housing 2200, the left-eye lens LLNS may be arranged between the second display panel DP2 and the user's left eye.

[0207] The image output from the first display panel DP1 may be displayed to the user's right eye through the right-eye lens RLNS. The right-eye lens RLNS may refract the light from the first display panel DP1 to direct it towards the user's right eye. The right-eye lens RLNS may perform an optical function for adjusting the viewing distance between the first display panel DP1 and the user's right eye.

[0208] The image output from the second display panel DP2 may be displayed to the user's left eye through the left-eye lens LLNS. The left-eye lens LLNS may refract the light from the second display panel DP2 to direct it towards the user's left eye. The left-eye lens LLNS may perform an optical function for adjusting the viewing distance between the second display panel DP2 and the user's left eye.

[0209] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pie-shaped cross-section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including a plurality of sub-regions having different optical characteristics. In this case, each display panel may output images corresponding to the plurality of sub-regions of the multi-channel lens respectively, and the output images may pass through the corresponding sub-regions and may be viewed by the user.

[0210] Although specific embodiments and application examples are described herein, other embodiments and modifications can be derived from the above description. Therefore, the spirit of the present disclosure is not necessarily limited to these embodiments, but extends to the scope of the following claims, various obvious modifications, and equivalents.

[0211] Although the present disclosure has been specifically described according to the above embodiments, it should be noted that the above embodiments are used to describe the present disclosure, rather than necessarily limiting the scope of the present disclosure. Those of ordinary skill in the art to which the present disclosure pertains will understand that various modifications can be made within the scope of the technical spirit of the present disclosure.

Claims

1. A display device, comprising: a plurality of emission regions; a non-emission region, the non-emission region being adjacent to the plurality of emission regions; a plurality of anodes, the plurality of anodes being spaced apart from each other, wherein each of the plurality of anodes overlaps a corresponding one of the plurality of emission regions and the non-emission region; and a plurality of separation portions, the plurality of separation portions being respectively disposed on the plurality of anodes and overlapping the non-emission region.

2. The display device according to claim 1, wherein, Each of the plurality of separation portions surrounds at least one surface of a corresponding one of the plurality of emission regions.

3. The display device according to claim 2, wherein, Each of the plurality of separation portions is adjacent to three surfaces of a corresponding one of the plurality of emission regions.

4. The display device according to claim 3, further comprising: a pixel defining layer, the pixel defining layer being disposed on the plurality of anodes and the plurality of separation portions and adjacent to a remaining one surface of each of the plurality of emission regions; a light-emitting structure, the light-emitting structure being disposed on the plurality of anodes, the plurality of separation portions and the pixel defining layer; and a cathode, the cathode being disposed on the light-emitting structure.

5. The display device according to claim 4, wherein, Each of the plurality of separation portions has a tapered structure.

6. The display device according to claim 5, wherein, The angle of the tapered structure with respect to the plane of the plurality of anodes is at least 50°.

7. The display device according to claim 5, wherein, The thickness of the tapered structure is greater than the thickness of the light-emitting structure.

8. The display device according to claim 4, wherein, Each of the plurality of separation portions has an inverted tapered structure that becomes thicker as it is farther from the plurality of anodes.

9. The display device according to claim 8, wherein, The thickness of the inverted tapered structure is greater than the thickness of the light-emitting structure.

10. The display device according to claim 4, wherein, The light-emitting structure and / or the cathode are separated by the plurality of separation portions.

11. The display device according to claim 2, wherein, Each of the plurality of separation portions surrounds four surfaces of a corresponding one of the plurality of emission regions.

12. The display device according to claim 11, further comprising: a pixel defining layer, the pixel defining layer being disposed on the plurality of anodes and the plurality of separation portions and surrounding the plurality of separation portions; a light-emitting structure, the light-emitting structure being disposed on the plurality of anodes, the plurality of separation portions and the pixel defining layer; and a cathode, the cathode being disposed on the light-emitting structure.

13. The display device according to claim 12, wherein, Each of the plurality of separation portions has a tapered structure.

14. The display device according to claim 13, wherein, The angle of the tapered structure with respect to the plane of the plurality of anodes is at least 50°.

15. The display device according to claim 13, wherein, The thickness of the tapered structure is greater than the thickness of the light-emitting structure.

16. The display device according to claim 12, wherein, Each of the plurality of separation portions has an inverted tapered structure that becomes thicker as it is farther from the plurality of anodes.

17. The display device according to claim 16, wherein, The thickness of the inverted tapered structure is greater than the thickness of the light-emitting structure.

18. The display device according to claim 12, wherein The light-emitting structure and / or the cathode are separated by the plurality of separation portions.

19. The display device according to claim 1, wherein, Each of the plurality of separation portions includes an inorganic material.

20. A display device, comprising: an emission region; a non-emission region, the non-emission region being adjacent to the emission region; an anode, the anode overlapping both the emission region and the non-emission region; a light-emitting structure, the light-emitting structure being disposed on the anode within the emission region; and a separation portion, the separation portion being disposed on the anode and separating the emission region from the non-emission region, wherein the separation portion has a shape that becomes wider as it is farther from the anode, and Wherein, the separation part is arranged at a discontinuity of the cathode and / or the light-emitting structure.

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